AN2664 NAND01G-B2B NAND02G-B2C NAND04G-B2B NAND08G-B2A NAND02G-B2D NAND04G-B2D

Application note How to migrate from cache program to multiplane page program single level cell NAND Flash memories Introduction

AN2664 AN2664 Application note How to migrate from cache program to multiplane page program single level cell NAND Flash memories Introduction The purpose of this application note is to give guidelines for the migration from cache program to multiplane page program single level cell (SLC) NAND Flash memory devices. In addition, the application note shows the advantages of the multiplane page program over the cache program devices. Section 1 and Section 2 highlight the differences in commands and timings between cache program and multiplane page program single level cell (SLC) NAND Flash memories. Section 3 explains how the differences between the two kinds of devices have an impact (in terms of hardware and software) on customer systems which include SLC NAND Flash memories. November 2007 Rev 1 1/8 www.st.com Commands 1 AN2664 AN2664 Commands Table 1 shows the list of commands which are different for cache program and multiplane page program SLC NAND Flash memories. All other commands not listed in Table 1 are the same for the two types of devices. To make their systems work properly when replacing a cache program with a new multiplane page program device, customers must follow the information given in Table 1. Table 1. Command set Nr. Command Multiplane Cache page program program Remark 1 Cache Read (sequential) Yes - 2 Cache Read (cache program device) Enhanced Cache Read (random) (multiplane page program device) Yes Yes 3 Exit Cache Read 3Fh 34h 4 Multiplane Page Program Yes - 5 Copy Back Program Yes* Yes *with Read EDC Status Register *same A18 6 Cache Program -* Yes *Multiplane page program devices use the Multiplane Page Program command 7 Multiplane Copy Back Program Yes - 8 Multiplane Block Erase Yes - 9 Read Electronic Signature Yes Yes 4 read cycles (cache program device) 5 read cycles (multiplane page program device) 10 Read Status Register Yes Yes SR1 (cache program bit) is Don't care on multiplane page program devices 11 Read Status Enhanced Yes - 12 Read ONFI Signature Yes - 13 Read Parameter Page Yes - 14 Read EDC Status Register Yes - 15 Read Block Lock Status - Yes* *only 4 Gbit cache program devices 16 Block Unlock - Yes* *only 4 Gbit cache program devices 17 Block Lock - Yes* *only 4 Gbit cache program devices 18 Block Lock-down - Yes* *only 4 Gbit cache program devices 2/8 31h 00h - 31h AN2664 AN2664 2 Timings Timings Some AC characteristics and their values, improved in multiplane page program devices, are shown in Table 2. Table 2. Symbol tALLWH AC characteristics Multiplane page program Alt. symbol 4 Gbit, cache program 1/2 Gbit, cache program Unit tALS Min 12 15 15 ns tCLS Min 12 15 15 ns tDVWH tDS Min 12 15 15 ns tELWH tCS Min 20 25 20 ns tWLWH tWP Min 12 15 15 ns tWLWL tWC Min 25(1) 30 30 ns Min 10 15 10 ns Min 10 15 10 ns tALHWH tCLHWH tCLLWH tALLRL1 tALLRL2 tAR tBLBH3 tBERS Max 2 3 3 ms tCLLRL tCLR Min 10 15 10 ns tEHQZ tCHZ Max 30 50 30 ns tRHQZ tRHZ Max 100 50 30 ns tELQV tCEA Max 25 30 25 ns tEHQX tOH(tCOH) Min 15 15 10 ns tRLQX tRLOH 5 - - ns tRLRH tRP 12 15 15 ns 30 30 ns Min (1) tRC Min tCSD Min 10 - - ns tRLQV tREA Max 20 25 20 ns tRHRL2 tCRRH Min - 100 - ns tRHWL tRHW Min 100 - - ns tWHWH tADL Min 70 100 100 ns tRLRL tEHALX tEHCLX 25 1. By upgrading to this timing, the throughput for read and write operations can be improved. To obtain the best performances from SLC NAND Flash memory devices, it is suggested aligning the timings with the values listed in the `multiplane page program' column in Table 2. 3/8 Impact on software/hardware AN2664 AN2664 3 Impact on software/hardware 3.1 Multiplane page program Multiplane page program SLC NAND Flash memories do not feature Cache Program operation, which is replaced by Multiplane Page Program operation. Customers only need to change their command set by using the Multiplane Page Program instead of the Cache Program operation. The Multiplane Page Program operation improves the cache program throughput by 30% for x 8 devices and by 60% for x 16 devices (see Figure 1 and Figure 2). Customers who use the standard program operations do not need any changes in their command set. Figure 1. Cache program throughput for SLC NAND Flash memories - x 8 devices 13.2 14 12 10.1 Mbit/s 10 8 6.8 8 Cache program devices Multiplane devices 6 4 2 0 Program Mbit/s Figure 2. Multiplane program Cache program throughput for SLC NAND Flash memories - x 16 devices 18 16 14 12 10 8 6 4 2 0 15.9 8.7 8.9 10.1 Cache program devices Multiplane devices Program 4/8 Cache program Cache program Multiplane program AN2664 AN2664 3.2 Impact on software/hardware Exit Cache Read The Exit Cache Read command for multiplane page program NAND Flash memories is `3Fh' instead of `34h' (as in cache program NAND Flash memories) to be in line with ONFI specification 1.0. If customers use the standard read operations, nothing must be changed. 3.3 Power-up Read Enable, Lock/Unlock Enable pin Multiplane page program SLC NAND Flash memories do not feature lock/unlock operations. Among cache program SLC NAND Flash memory devices, only the 4-Gbit memory uses the Power-up Read Enable, Lock/Unlock (PRL) pin to enable and disable the lock mechanism. If customers in their systems use the PRL pin, nothing happens when replacing a cache program with a multiplane page program device because this pin is left internally not connected. 3.4 Pin-to-pin compatibility Cache program and multiplane page program SLC NAND Flash memories are pin-to-pin compatible. This means that customers do not need any hardware upgrade if the cache program and multiplane page program devices are both available in the same package. 5/8 Conclusions 4 AN2664 AN2664 Conclusions Cache program and multiplane page program NAND devices are pin-to-pin compatible, when delivered in the same packages. All the features of the cache program SLC NAND Flash memories are kept with the new multiplane page program devices, except the Cache Program and Exit Cache Read operations. Instead of the Cache Program, customers can adopt the Multiplane Page Program operation, which also guarantees an improved program throughput. Using standard operations, no change is required in the system software and the hardware remains the same thanks to pin-to-pin compatibility. 5 References 1. Cache program devices: 2. NAND01G-B2B NAND01G-B2B_NAND02G-B2C NAND02G-B2C: 1 Gbit, 2 Gbit, 2112 byte/1056 word page, 1.8 V/3 V, NAND Flash memory. NAND04G-B2B NAND04G-B2B_NAND08G-B2A NAND08G-B2A: 4 Gbit, 8 Gbit, 2112 byte/1056 word page, 1.8 V/3 V supply voltage, NAND Flash memory. Multiplane page program devices: 6/8 NAND02G-B2D NAND02G-B2D: 2 Gbit, 2112 byte/1056 word page, multiplane architecture, 1.8 V or 3 V, NAND Flash memory. NAND04G-B2D NAND04G-B2D_NAND08G-B2C NAND08G-B2C: 4 Gbit, 8 Gbit, 2112 byte/1056 word page, multiplane architecture, 1.8 V or 3 V, NAND Flash memories. AN2664 AN2664 6 Revision history Revision history Table 3. Document revision history Date Revision 29-Nov-2007 1 Changes Initial release. 7/8 AN2664 AN2664 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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