AN2511/D 32LQD MPC500 - Datasheet Archive

 

Application Note AN2511/D Rev. 0, 5/2003 32-bit Linear Quadrature Decoder TPU Function Set (32LQD) Freescale Semiconductor, Inc.

 

Freescale Semiconductor, Inc. Application Note AN2511/D AN2511/D Rev. 0, 5/2003 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) Freescale Semiconductor, Inc. By Milan Brejl, Ph.D. Functional Overview 32-bit Linear Quadrature Decoder (32LQD 32LQD) TPU Function Set is useful for decoding position, direction and velocity information from encoder signals in motion control systems. The 32-bit Position Counter (PC) is particularly useful for linear motor systems. The function set consists of 3 TPU functions: · 32-bit Linear Quadrature Decoder (32LQD 32LQD) · Home Channel for 32-bit Linear Quadrature Decoder (32LQD 32LQD_Home) · Velocity Support for 32-bit Linear Quadrature Decoder (32LQD 32LQD_VS) The 32-bit Linear Quadrature Decoder uses two input channels to decode a pair of out-of-phase encoder signals and produce a resulting 32-bit bidirectional position counter for the CPU. An additional input channel can also be used to indicate a "home" position. When the position is reached, appropriate actions are taken. For accurate velocity measurement, Velocity Support can be added. Figure 1 illustrates the functionality. Phase A Phase B Position Counter +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 +1 +1 +1 +1 Home Change of direction HOME position reached Change of direction Figure 1. Signals processed by 32LQD 32LQD TPU function set and corresponding PC value © Motorola, Inc., 2003 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. AN2511/D AN2511/D Function Set Configuration The 32LQD 32LQD is the main function of the set. It can be used either alone, with one of the supporting functions, or with both of them. There are no restrictions on channel numbers ­ any function can run on any channel. Table 1 shows the configuration options and restrictions. Freescale Semiconductor, Inc. Table 1. 32LQD 32LQD TPU function set configuration options and restrictions TPU function 32LQD 32LQD 32LQD 32LQD_home 32LQD 32LQD_VS Optional/ Mandatory mandatory optional optional How many Assignable channels channels 2 any 2 channels: Phase A and Phase B 1 or more any 1 or more any The two out of phase encoder signals are called Phase A (primary channel) and Phase B (secondary channel). The Host Sequence (HSQ) bit 0 is used to determine to which channel Phase A is connected and to which Phase B is connected. The HSQ is also used for other configuration options ­ refer to the detailed function descriptions. Table 2 shows an example of configuration. The Phase A encoder signal is connected to channel 0 and Phase B to channel 1. TCR2 clock is selected for all timing operations and the Home channel reacts to low-high transitions. Table 2. Example of configuration Channel 0 1 2 15 TPU function 32LQD 32LQD 32LQD 32LQD 32LQD 32LQD_home 32LQD 32LQD_VS HSQ 10 11 00 10 Priority high high middle middle In this configuration, when no other functions run on the same TPU, the 32LQD 32LQD can receive and process input transitions at a rate of up to 540 kcounts per second at 40MHz IMB clock. When 32LQD 32LQD_home and 32LQD 32LQD_VS are not used, the 32LQD 32LQD running standalone can count edges at a rate of up to 800 kcounts per second at 40MHz IMB clock. This is equivalent to a 1024-pulse encoder speed of more then 11,700 rpm. Table 3 shows another example of configuration where the functions of Standard Space Vector Modulation TPU function set (svmStd) run together with 32LQD 32LQD functions on one TPU. This configuration enables the 32LQD 32LQD to receive and process input transitions at a rate of up to 363 kcounts per second 2 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. AN2511/D AN2511/D Function Set Configuration at 40MHz IMB clock. This is equivalent to a 1024-pulse encoder speed of more then 5,300 rpm. The Space Vector Modulation PWM frequency can be set up to 12.8 kHz to enable the maximum rpm. If the PWM frequency is set to 16 kHz the encoder pulses can be processed at a rate of 272 kcounts per second, that is equivalent to 3,900 rpm with a 1024-pulse encoder. If the PWM frequency is set to 20 kHz the encoder pulses can be processed at a rate of 181 kcounts per second, that is equivalent to 2,600 rpm with a 1024-pulse encoder. Table 3. Example of configuration Freescale Semiconductor, Inc. Channel 0 1 2 3 4 5 6 7 8 10 12 15 TPU function svmStd_top svmStd_top svmStd_top svmStd_bottom svmStd_bottom svmStd_bottom 32LQD 32LQD 32LQD 32LQD 32LQD 32LQD_home svmStd_sync 32LQD 32LQD_VS svmStd_fault Priority middle middle middle middle middle middle high high low low low middle Table 4 shows the TPU function code sizes. Table 4. TPU function code sizes TPU function 32LQD 32LQD 32LQD 32LQD_home 32LQD 32LQD_VS MOTOROLA Code size 40 µ instructions + 8 entries = 48 long words 10 µ instructions + 8 entries = 18 long words 19 µ instructions + 8 entries = 27 long words 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. AN2511/D AN2511/D Configuration Order The CPU configures the TPU as follows. 1. Disables the channels by clearing the two channel priority bits on each channel used (not necessary after reset). 2. Selects the channel functions on all used channels by writing the function numbers to the channel function select bits. Freescale Semiconductor, Inc. 3. Initializes function parameters. The parameters PC_init_LOWER, and PC_init_UPPER, CORR_PIN_PTR_A and CORR_PIN_PTR_B must be set before initialization. The parameter VS_period must be set if Velocity Support channel is used. 4. Set the HSQ (Host Sequence) bits to determine which channel is Phase A and which is Phase B and to select other function options. 5. Issues an HSR (Host Service Request) type %10 to both of the 32LQD 32LQD channels to initialize position counting. Issues an HSR type %10 to the 32LQD 32LQD_home and 32LQD 32LQD_VS channels, if used. 6. Enables servicing by assigning high, middle or low priority to the channel priority bits. Both Phase A and Phase B channels should be assigned the same priority. NOTE: A CPU routine that configures the TPU can be generated automatically using the MPC500 MPC500_Quick_Start Graphical Configuration Tool. Detailed Function Description 32-bit Linear Quadrature Decoder (32LQD 32LQD) 4 The 32LQD 32LQD operates on two channels and processes the incoming out-ofphase encoder signal. As a result of this processing, the bidirectional 32-bit Position Counter (PC) gets a value that reflects the position of a motion system. The PC value is incremented or decremented by 1 on each transition of Phase A or Phase B input channels ­ see Figure 2. On initialization, the PC is set to a 32-bit PC_init value entered by the CPU. 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. AN2511/D AN2511/D Detailed Function Description Phase A Phase B Position Counter +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 Phase A Freescale Semiconductor, Inc. Phase B Position Counter -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 Phase A Phase B Position Counter +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 Figure 2. 32-bit Linear Quadrature Decoder Two function modes are offered: · TCR1 clock selected · TCR2 clock selected The mode selection is done by HSQ bit 1. The HSQ bit 0 is used to determine which channel is Phase A and which is Phase B ­ see Table 5. The user has to select Phase A on one channel and Phase B on the other, and the same mode on both channels. The function offers interpolation support for very slow quadrature signals. The parameters LastEdgeT and ActualT are updated on a Host Service Request HSR = 11. The LastEdgeT then has the value of last incoming edge time in TCR clocks and the ActualT has the current value of the TCR clock. The CPU program should use 32-bit reads/writes of 32-bit parameters (PC, PC_init) to ensure their coherency. It can also use a 32-bit read of LastEdgeT and ActualT for coherency. MOTOROLA 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. AN2511/D AN2511/D Host Interface Written By CPU Written by both CPU and TPU Written By TPU Not Used Table 5. 32LQD 32LQD Control Bits Name 3 2 1 Options 0 x0 ­ Phase A (primary channel) x1 ­ Phase B (secondary channel) 0x ­ TCR1 clock selected 1x ­ TCR2 clock selected Channel Interrupt Enable x ­ Not used Channel Interrupt Status 1 00 ­ No Host Service Request 01 ­ Not used 10 ­ Initialization 11 ­ Get LastEdgeT and ActualT Host Sequence Bits (HSQ) 1 00 ­ Channel Disabled 01 ­ Low Priority 10 ­ Middle Priority 11 ­ High Priority Host Service Bits (HSR) 1 32LQD 32LQD function number (Assigned during assembly the DPTRAM code from library TPU functions) Channel Priority Freescale Semiconductor, Inc. Channel Function Select x ­ Not used 0 0 0 0 0 6 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. AN2511/D AN2511/D Detailed Function Description Table 6. 32LQD 32LQD Parameter RAM Phase B Freescale Semiconductor, Inc. Phase A Channel Parameter 15 14 13 12 11 10 9 8 7 6 5 4 0 LastEdgeT ActualT 1 PC_UPPER 2 3 PC_LOWER TCR_VALUE 4 CORR_PIN_PTR_A 5 6 CHAN_PINSTATE_A 7 0 1 2 PC_init_UPPER 3 PC_init_LOWER 4 5 CORR_PIN_PTR_B 6 CHAN_PINSTATE_B 7 3 2 1 0 Table 7. 32LQD 32LQD parameter description Parameter Format Description Parameters written by CPU Position Counter initialization PC_init_UPPER, 32-bit signed integer value PC_init_LOWER $00XC, where X is a number CORR_PIN_PTR_A 16-bit unsigned integer of PhaseB channel $00XC, where X is a number CORR_PIN_PTR_B 16-bit unsigned integer of PhaseA channel Parameters written by both TPU and CPU PC_UPPER, Position Counter value 32-bit signed integer PC_LOWER Parameters written by TPU LastEdgeT 16-bit unsigned integer TCR time of last transition * ActualT 16-bit unsigned integer Actual TCR time * TCR_VALUE 16-bit unsigned integer TCR time of last transition The actual state of the pin is CHAN_PINSTATE_A $8000 or $0000 $8000 ­ high, CHAN_PINSTATE_B $0000 ­ low * The parameter values are entered by TPU on Host Service Request 11 (Get LastEdgeT and ActualT). MOTOROLA 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc. AN2511/D AN2511/D Performance Table 8. 32LQD 32LQD State Statistics State INIT GET_TIME EDGE Freescale Semiconductor, Inc. NOTE: Phase A Phase B Max IMB Clock Cycles 28 8 36 RAM Accesses by TPU 7 3 9 Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks) EDGE EDGE EDGE EDGE GET TIME EDGE EDGE EDGE EDGE EDGE EDGE EDGE EDGE EDGE EDGE EDGE EDGE EDGE HSR 11 Figure 3. 32LQD 32LQD timing GET_TIME INIT EDGE HSR = 11 HSR = 10 Figure 4. 32LQD 32LQD state diagram 8 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. AN2511/D AN2511/D Detailed Function Description Noise Immunity The input signals can be disturbed by an impulse noise. The TPU hardware rejects short input pulses of less than a configurable number of IMB clocks. Longer pulses are processed by TPU. Furthermore the function itself uses a pin history to reject any short error pulse that is long enough to get through the hardware filter, but not long enough to last from the actual transition time to the time that the TPU services the channel. Even longer error pulses are counted on both edges resulting a net error of zero on the PC. See examples of error pulses processing on Figure 5. Freescale Semiconductor, Inc. Phase A Phase B Position Counter +1 X +1 +1 X +1 +1 +1 +1 +1 -1 -1 -1 +1 +1 X +1 Phase A Phase B Position Counter +1 +1 -1 -1 +1 +1 Figure 5. Noise immunity Home Channel for 32-bit Linear Quadrature Decoder (32LQD 32LQD_home) The 32LQD 32LQD_home function monitors an input signal, which indicates a "HOMEposition" of the motion system with a pulse. The function can be configured to react on either a low-high transition, a high-low transition or either transition. This way the user can select whether the HOME-signal is of positive or negative polarity and the action to be taken when the HOME-position is either reached, left or both. Three function modes are offered based on these options: · Detection of low-high transition · Detection of high-low transition · Detection of any transition The mode selection is done by HSQ bits ­ see Table 9. When the specified action happens the 32LQD 32LQD_home function resets the 32bit Position Counter to its initialization value (PC_init_UPPER, PC_init_LOWER) and generates a channel interrupt. MOTOROLA 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com 9 Freescale Semiconductor, Inc. AN2511/D AN2511/D Host Interface Written By CPU Written by both CPU and TPU Written By TPU Not Used Table 9. 32LQD 32LQD_home Control Bits Name 3 2 1 Options 0 00 ­ Detection of low-high transition 01 ­ Detection of high-low transition 1x ­ Detection of any transition Channel Interrupt Enable 0 ­ Channel Interrupt Disabled 1 ­ Channel Interrupt Enabled Channel Interrupt Status 1 00 ­ No Host Service Request 01 ­ Not used 10 ­ Initialization 11 ­ Not used Host Sequence Bits (HSQ) 1 00 ­ Channel Disabled 01 ­ Low Priority 10 ­ Middle Priority 11 ­ High Priority Host Service Bits (HSR) 1 32LQD 32LQD_home function number (Assigned during assembly the DPTRAM code from library TPU functions) Channel Priority Freescale Semiconductor, Inc. Channel Function Select 0 ­ Interrupt Not Asserted 1 ­ Interrupt Asserted 0 0 0 0 0 Table 10. 32LQD 32LQD_home Parameter RAM Home channel Channel 10 Parameter 15 14 13 12 11 10 9 8 7 6 5 0 1 2 3 4 5 6 PC_VS_ADDR 7 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com 4 3 2 1 0 MOTOROLA Freescale Semiconductor, Inc. AN2511/D AN2511/D Detailed Function Description Table 11. 32LQD 32LQD_home parameter description Parameter Format Description Parameters written by CPU $00XC, where X is a number of VS channel 16-bit unsigned integer $00000 if no VS channel is used. PC_VS_ADDR Freescale Semiconductor, Inc. Performance Table 12. 32LQD 32LQD_home State Statistics State INIT HOME NOTE: Max IMB Clock Cycles 8 10 RAM Accesses by TPU 0 4 Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks) H SQ = 00 Position Counter -1 -1 -1 -1 H om e +1 P C_init +1 HOME H SQ = 01 Position Counter -1 -1 -1 -1 H om e +1 P C_init +1 HOME H SQ = 1x Position Counter H om e -1 -1 -1 -1 P C_init PC _init HOME +1 +1 HO ME Figure 6. 32LQD 32LQD_home timing MOTOROLA 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com 11 Freescale Semiconductor, Inc. AN2511/D AN2511/D INIT HOME HSR = 10 Freescale Semiconductor, Inc. Figure 7. 32LQD 32LQD_home state diagram Velocity Support for 32-bit Linear Quadrature Decoder (32LQD 32LQD_VS) The 32LQD 32LQD_VS runs on an unconnected TPU channel. The function periodically measures the difference of the 32LQD 32LQD 32-bit Position Counter (PD ­ Position Difference) and the exact time corresponding to it (TD ­ Time Difference). The Time Difference slightly varies from the period of measurement (VS_period). The Time Difference is calculated as the difference between the time of the last transition counted and the time of the transition preceeding the first one counted. It is illustrated on Figure 8. VS_period Time Difference Phase A Phase B Position Counter +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 Position Difference = 9 Figure 8. Velocity Support The Time Difference and Position Difference values can be used by the CPU program to calculate the exact velocity of the motion system. 12 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. AN2511/D AN2511/D Detailed Function Description The function can use either the TCR1 or the TCR2 clock for VS_period measurement. Two function modes are offered based on this options: · TCR1 clock selected · TCR2 clock selected The mode selection is done by the HSQ bits ­ see Table 13. The selected clock must be the same as is used by the main function 16QD. Host Interface Written by both CPU and TPU Written By TPU Freescale Semiconductor, Inc. Written By CPU Not Used Table 13. 32LQD 32LQD_VS Control Bits Name 3 2 1 Options 0 Channel Function Select Channel Priority 0x ­ TCR1 clock selected 1x ­ TCR2 clock selected Channel Interrupt Enable 0 ­ Channel Interrupt Disabled 1 ­ Channel Interrupt Enabled Channel Interrupt Status 1 00 ­ No Host Service Request 01 ­ Not used 10 ­ Initialization 11 ­ Not used Host Sequence Bits (HSQ) 1 00 ­ Channel Disabled 01 ­ Low Priority 10 ­ Middle Priority 11 ­ High Priority Host Service Bits (HSR) 1 32LQD 32LQD_VS function number (Assigned during assembly the DPTRAM code from library TPU functions) 0 ­ Interrupt Not Asserted 1 ­ Interrupt Asserted 0 0 0 0 0 MOTOROLA 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com 13 Freescale Semiconductor, Inc. AN2511/D AN2511/D TPU function 32LQD 32LQD_VS generates an interrupt after each VS_period. Table 14. 32LQD 32LQD_VS Parameter RAM Freescale Semiconductor, Inc. Velocity Support Channel Parameter 15 14 13 12 11 10 9 8 7 6 5 0 VS_period 1 2 PC_VS_UPPER 3 PC_VS_LOWER VS_PD_UPPER 4 VS_PD_LOWER 5 6 VS_TD EDGE_TIME 7 4 3 2 1 0 Table 15. 32LQD 32LQD_VS parameter description Parameter VS_period Format Description Parameters written by CPU Period of VS calculations in TCR 16-bit positive integer clocks Parameters written by TPU VS_PD_UPPER, 32-bit signed integer Position difference VS_PD_LOWER VS_TD 16-bit unsigned integer Time difference Other parameters are just for TPU function inner use. 14 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. AN2511/D AN2511/D Detailed Function Description Performance Table 16. 32LQD 32LQD_VS State Statistics State INIT VS Freescale Semiconductor, Inc. NOTE: VS VS Max IMB Clock Cycles 8 30 RAM Accesses by TPU 1 13 Execution times do not include the time slot transition time (TST = 10 or 14 IMB clocks) VS VS VS Figure 9. 32LQD 32LQD_VS timing INIT VS HSR = 10 Figure 10. 32LQD 32LQD_VS state diagram MOTOROLA 32-bit Linear Quadrature Decoder TPU Function Set (32LQD 32LQD) For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc. HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 Freescale Semiconductor, Inc. JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. 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