AN2034 1-888-INTERSIL AN2032 AN2026 AN2033 ZL2004 ZL2006 - Datasheet Archive

 

May 01, 2009 Application Note AN2034.0 Introduction This application note describes the features and setup procedure for

 

Current Sharing with Digital-DCTM Devices May 01, 2009 Application Note AN2034 AN2034.0 Introduction This application note describes the features and setup procedure for Digital-DC devices configured in current sharing groups. These latest products employ an interdevice communication Bus called the Digital- DC bus (DDC bus). The DDC bus enables Zilker Labs IC's to exchange critical real-time system information to any device connected to the Bus. The DDC bus enables advanced power management, fault management, sequencing, and many other features not available in the previous generation of products. to respond will do so. DDC devices can also transmit events if their programmed algorithm requires inter device communication. Some examples include fault spreading, sequencing, phase add/drop, broadcast margin and broadcast enable. 3.3V DDC SDA SCL SALRT Overview A current sharing group is simply 2 or more parallel converters operating at the same frequency but interleaved in such a way to multiply the input and output ripple frequency by the number of paralleled converters or phases. Paralleling converters in this manner has the added benefits of reducing the input filter stress, distributing the converter thermal load, reducing volume and weight and many other advantages. Figure 1 is a typical example of a 3-phase current sharing group. Multiple current sharing groups and power rails can communicate and connect to the same DDC bus. ZL DDC Device VCC Rout Cout PH_1 VCC ZL DDC Device PH_2 VCC ZL DDC Device PH_3 DDC bus Zilker Labs (Digital-DC) products utilize a unique dedicated serial bus (DDC bus) to synchronize and communicate real-time events to other Zilker Labs devices connected to the Bus. A 5 bit address is assigned to each DDC rail, yielding a theoretical total of 32 separate power rails, including current sharing rails. Each device within a current sharing rail is assigned the same DDC address so the total number of DDC devices can exceed 32. A maximum of 8 devices or phases is allowed in a sharing group. Please ensure that the DDC signal integrity is maintained when using a large device count. Figure 1. Typical current share application Active Droop Current Sharing Zilker Labs current sharing devices use a patented form of digitally controlled active droop, resulting in the highest degree of phase current balancing. During DDC events, all devices will receive transmissions; however, only those devices configured 1 1-888-INTERSIL 1-888-INTERSIL or 1-888-468-3774|Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners Application Note 2034 The specific droop is configured based on the application and is set to the same value for each group member. The ZL device with the lowest sharing group position (specified in the ISHARE_CONFIG command) is designated as the Reference Device. The Reference Device continuously broadcasts its inductor current over the DDC bus, while each Member device receives the transmission and trims its output voltage up or down until all group members supply the same current to the load. The process of broadcasting the Reference's load current and trimming each Member's output voltage to achieve current balance continues unless a fault occurs or a phase is dropped. The recommended droop or loadline resistance for current sharing groups is between 0.5 m's and 1.5 m's. Each group member is assigned the same droop value. The equivalent droop is adjusted to the value entered as the individual member droop. This value of droop is maintained even when device(s) are added or dropped. Balanced Phase Currents Vout Reference Device 1.20 1.15 Total Load Current = 114.5A / 3 = 38.16A 1.10 1.05 1.00 0.95 0.85 0.80 0.75 0.70 Current Sharing Algorithm Figure 2 is an example of a current sharing application whose loadlines were all configured to 1 m. Due to differences in layout and IC production variances the actual member loadlines contain slope differences; they are exaggerated in this example. Each phase carries 38.16A Group Loadline is equal to configured loadline = 1 mOhm 0.65 0.55 0.60 Vout Unbalanced Phase Currents 1.20 1.15 1.10 Total Load Current = 27.5A + 35A + 52A = 114.5A 1.05 Ref Mem_1 Mem_2 38.16A / Ph 0.90 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 Iout Figure 3. Member(s) reference voltage is trimmed until all device currents equalize. Current sharing equilibrium is shown in Figure 4 with a singular loadline being plotted that represents the actual static response for the sharing group. Since each group member in this example is configured to 1 m the slope of the sharing group is equal to 1 m. 1.00 27.5A 0.90 Ref 35A 52A 0.85 0.80 Mem_1 Mem_2 Programmed Loadline = 1 mOhm/Ph. Actual Loadlines = ; Master = 1.0 mOhm Slave_1 = 1.5 mOhm Slave_2 = 2.0 mOhm 0.75 0.70 0.65 0.60 0.55 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 Iout Figure 2. Unbalanced phase currents due to slope error. The minor imbalance results in each phase contributing an unequal portion of the load current. The imbalance is detected as the Reference's load current is broadcast and each Members reference voltage is trimmed up or down until all devices in the group carry an equal portion of the load current. This effect is shown in Figure 3. Notice in this case the Reference initially sourced the majority of the load current. Each member device's reference voltage was trimmed in the positive direction until all phase's source equal current to the load. 2 Actual Current Share Loadline = 1 mOhm Vout 0.95 1.20 1.15 Total Load Current = 114.5A / 3 = 38.16A 1.10 1.05 1.00 Rail Loadline 0.95 38.16A / Ph 0.90 0.85 0.80 0.75 0.70 Each phase carries 38.16A Group Loadline is equal to configured loadline = 1 mOhm 0.65 0.60 0.55 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 Iout Figure 4. Current sharing phase balance is achieved. Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Phase Add/Drop When Zilker Labs Digital-DC power conversion devices are configured in a current sharing group, individual group members are capable of (dynamically) dropping out and adding back to the group. Group members are typically dropped or added to improve efficiency or to process a fault. Group members can be added or dropped on the fly using the power management host controller, invoking the Phase Control command. 3.3V VCC DEV_1 REF. MEM_1 POS_1 Rout Cout PH_1 DDC SDA SCL VCC DEV_2 MEM_2 POS_2 PH_2 Dropped Phase / SYNC CLOCK If the dropped group member was supplying the SYNC clock it will continue to do so even though it has become inactive. If the device supplying the SYNC clock dropped from the group and is no longer capable of supplying the clock, the remaining members will detect the absence of SYNC and respond according to their fault spreading configuration. If a host or power system manager is monitoring the group then SALRT will assert, and the PMBus can be read and will respond with the appropriate fault management alarm as described in the PMBus Power System Mgt Protocol Specification ­ Part II. If the dropped phase was the group reference a new reference will be reassigned based on the lowest Phase Position number of the existing operational members. The phase position is defined by the angular offset relative to the SYNC clock. 3 VCC DEV_3 MEM_3 POS_3 PH_3 Figure 5. 3-Phase converter showing reference, member, and position number. Figure 5 shows an example 3-phase current sharing group prior to asserting a Phase Control command to drop the reference phase (Device_1). Figure 6 illustrates the new 2-phase configuration after the reference phase is dropped. Device_2 becomes the new reference for current sharing. Device_1 supplying the SYNC clock continues to do so. Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 3.3V seamlessly added back into the group. In this example, position 1 was made active and resumed the role of reference device, see Figure 5. The phase offset of each member was automatically redistributed from 180° to 120° as shown in the top section of Figure 7. VCC DEV_1 Dropped MEM_1 POS_1 Rout Cout PH_1 DDC SDA SCL NLR Threshold Scaling VCC DEV_2 REF MEM_2 POS_2 When multiple devices are configured in a current sharing group, the effective output ripple is divided by the number of active members. When all members of the group are operating, the NLR (Non Linear Response) thresholds can be set to a small value just above the minimum ripple amplitude. When a group member is dropped the ripple amplitude will increase. PH_2 VCC DEV_3 MEM_3 POS_3 In order to avoid spurious NLR activity the Digital-DC features automatically adjust the NLR thresholds according to the ratio of active group members to total members of the group: PH_3 Figure 6. 3-Phase converter after reference phase is dropped. The timing diagram is shown in Figure 7. After the reference phase is dropped the remaining two members are redistributed and the phase displacement changes from 120° to 180°. Vt _ part = Vt _ all * Nall Nactive Where Vt_part is the NLR inner threshold setting used with some group members deactivated Vt_all is the NLR inner threshold setting configured for the group with all members operating o PH_3 o 0 o 600 o 180 POS_3 POS_2 POS_1 o 480 POS_3 PH_2 o 360 POS_2 POS_2 240 o 720 o o 360 o o 840 960 540 POS_3 o 120 POS_3 o 0 POS_2 PH_3 Nall is the total number of members in the group POS_3 POS_3 PH_2 POS_2 POS_2 PH_1 POS_1 POS_1 SYNC CLK o 720 o 900 Figure 7. 3-Phase converter timing diagram before and after Phase_1 (Reference Phase) is dropped. Phase Add The phase that was previously dropped may be added back into the group as determined by the power management host or the Phase Control command in the GUI. When the command is given to add the phase, the event is coordinated with the active member devices over the DDC bus and the previously inactive device is 4 Nactive is the number of members active in the group (that is, the number of members not faulted or intentionally deactivated). Nall and Nactive are determined automatically from the group configuration parameters. No additional programming or configuration is required. Since the available thresholds are quantized to multiples of 0.5% of the configured output voltage, the next higher available threshold is used if the result of the above formula is fractional. For additional information about NLR Please reference AN2032 AN2032 NLR Configuration DDC Products. Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Automatic Phase Distribution Digital-DC devices configured in current sharing groups feature the ability to autonomously perform phase offset. The offset resolution is 22.5° relative to the leading edge of the SYNC clock. 3.3V VCC DEV_1 REF. MEM_1 POS_1 Rout Cout Rout Cout PH_1 DDC SDA SCL SYNC SYNC_Out VCC SYNC Clock DEV_2 To configure a current sharing group a common SYNC clock must be provided to each group member. This SYNC clock can be provided by any Zilker Labs Digital DC device or the SYNC can be provided by an external source that satisfies the electrical specifications of the SYNC pin. Note: the switching frequency of each member must be configured to the same value. Once the SYNC source has been designated the SYNC pins of all group members and any other Zilker Labs device requiring synchronization and interleaving must be connected together as shown in Figure 8. Note that any of the devices whose SYNC pins are physically connected together can be configured to output the SYNC clock. The SYNC output can be configured as push-pull or open-drain. All other devices connected to the SYNC source must be configured as SYNC inputs. MEM_2 POS_2 PH_2 SYNC_In VCC DEV_3 MEM_3 POS_3 PH_3 Rail_1 SYNC_In VCC DEV_4 Rail_2 Rail_2 SYNC_In Figure 8. Example of sharing group and auxiliary output rail with a common SYNC clock. Phase Offset The current sharing group in Figure 8 will autonomously distribute each member's phase with respect to the SYNC clock. Since the sharing group contains 3 members, each member will be ideally offset in phase by 120°. The actual phase offset is represented by a 4 bit binary number resulting in 16 possible offset values in 22.5° steps. The real phase displacement will be rounded to the closest 22.5° increment. All possible phase displacements are shown in Figure 9. For the 3-phase example shown in Figure 8. the actual sharing group phase offset will be rounded as shown in Table 1. Although Rail_2 is connected to the same SYNC clock it will not be autonomously offset in phase with respect to the current sharing group. Rail_2 can be offset in phase to one of the 16 possible offset values by using the INTERLEAVE command. If the INTERLEAVE command is not used, Rail_2 will simply turn on at 0° with the rising edge of the SYNC clock. 5 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Table 1. Ideal vs actual phase offset Ideal Offset 3.3V VCC DEV_1 Actual Offset Position_1 0° 0° Position_2 120° 112.5° Position_3 360° 247.5° Sharing Group_1 REF. MEM_1 POS_1 Rout Cout PH_1 DDC SDA SCL SYNC_Out SYNC VCC DEV_2 Rail_1 MEM_2 POS_2 PH_2 SYNC_In VCC DEV_3 Sharing Group_2 REF. MEM_1 POS_1 Rout Cout PH_1 SYNC_In VCC DEV_4 Rail_2 MEM_2 POS_2 Figure 9. Phase offset resolution wheel PH_2 SYNC_In Figure 10. Example of 2 X 2-Phase current sharing groups using the same SYNC clock. INTERLEAVE Command Current sharing groups are autonomously offset in phase with respect to each group member, however when there are multiple sharing groups connected to the same SYNC clock the 2 groups will not autonomously offset from each other. Consider the 2 current sharing groups shown in Figure 10. This configuration consists of 2 output rails with each rail containing a 2-phase sharing group and a common SYNC clock. Each sharing group will autonomously phase spread within the group, but not between the 2 groups. The resulting timing waveform is shown in Figure 11. SYNC CLK DEV_1 Rail_1 DEV_2 Rail_1 DEV_3 Rail_2 DEV_4 Rail_2 o 0 o 90 o 180 o 270 o 360 o 450 o 540 o 630 o 720 o 810 o 900 o 990 Figure 11. Timing diagram for a 2 rail X 2 Phase current sharing example. Notice that the positional phase equivalents in each sharing group are not offset from each other. 6 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 If desired, Sharing Group_2 can be offset in phase from Group_1 by using the INTERLEAVE command field in the GUI or creating an equivalent command line in a configuration file. The simplest way to achieve equal phase offset for the 4 devices in Figure 10 is to offset Sharing Group_2 by 90°. This is easily done in the GUI by declaring 2 Devices in Sharing Group_2 and assigning the Position in Interleave Group as 4. SYNC CLK DEV_1 Rail_1 DEV_2 Rail_1 DEV_3 Rail_2 DEV_4 Rail_2 o 0 o o 90 180 o 270 o o 360 o 450 540 o 630 o o 720 810 o 900 o 990 Figure 14. 2 X 2-Phase current sharing groups now equally offset using INTERLEAVE command. Ramp Synchronization During turn-on and turn-off the voltage ramps of each phase are synchronized to start at the same time. This ensures that inter-phase circulating currents are minimized. Figure 12. INTERLEAVE configuration to offset Sharing Group_2 by 90° Referencing Figure 9, the value 4 represents an offset of 90°. The same entries are made for both devices in Sharing Group_2. Each current sharing phase contains a separate digital controller that executes firmware. The individual controller firmware requires synchronization prior to ramp events to minimize circulating currents. This is accomplished by forcing the reference phase to wait at least one additional firmware cycle during ramping events by configuring it to have additional Time On and Time Off Delay relative to the other group members. When the sharing group receives a hardware or PMBus enable, the member devices initialize their registers and freeze the state of their firmware, once the reference phase completes its extra timing delay it transmits a DDC Ramp Flag and all members of the group produce a sequenced PWM and begin their soft-start routine. Figure 13. INTERLEAVE configuration for 0 offset (autonomous phase control) The interleave value for Sharing Group_1 is simply INTERLEAVE = 0000. Each respective hex INTERLEAVE value can be entered into a configuration file. The new timing diagram shown in Figure 14 illustrates that each 2-phase sharing group is now equally offset in phase. 7 SYNC CLK PH_1 PH_2 PH_3 o 0 o 120 o 240 o 360 o 480 o 600 o 720 o 840 o 960 Figure 15. Start-up synchronization Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Figure 16. Setting the Reference Time On/Off Delays 10 mS greater than Member Delays Please ensure that the Time On Delay and Time Off Delay parameters for the reference phase are at least 10 ms greater than the delay parameters of each member device as shown in Figure 16. To ensure that each controller produces an identical pulse width at start-up the Min Duty Cycle command must be set to enable. This starts each sharing group member with the same initial pulse width. Alternate Ramp Control The Min Duty Cycle command is located in the USER_CONFIG field on the PMBus Advanced section of the GUI. The default value of the minimum duty Alternate Ramp Control is used to avoid regulation at ground as the current share members are enabled and waiting for the Reference Phase to cycle through an extra firmware loop. Once the Reference phase is ready it transmits a DDC ramp flag and all of the current share phases produce a turn-on rise time profile as shown in Figure 17. The Set Alternate Ramp control is located in the MFR_CONFIG field on the PMBus Advanced page of the GUI. Actual Ramp Start DV DT Programmed Rise Time Figure 17. Effect of setting Alternate Ramp Setting Alternate Ramp control to enable produces a clean dual slope monotonic output voltage ramp at turn-on. The actual programmed rise time is conserved as shown in Figure 17. Alternate ramp must be set to enable for current sharing groups. Minimum Duty Cycle Current sharing groups can be comprised of 2 to 8 phases. Each phase contains its own digital PID controller. 8 cycle is Fsw . 128 Broadcast Enable / Margin PMBus enable and margining commands can be configured with current sharing groups just like single phase converters. All devices must be connected to the same SMBus and DDCBus. The broadcast group can be comprised of current sharing devices and Single Phase devices. An example is shown in Figure 18. This configuration contains 3 Single Phase converters (Rails_1-3) and a 3-phase current sharing group (Rail_4). To configure a current sharing broadcast group assign each group member the same Rail DDC ID. Assign the same Broadcast Group Number to all devices that will respond to the broadcast command. These assignments are shown in Table 2. Table 2. Assigning Broadcast Parameters Device Rail # 1 2 3 4 5 6 1 2 3 4 4 4 Rail DDC ID 1 2 3 5 5 5 Broadcast Group 2 2 2 2 2 2 Broadcast Enable Enable Enable Enable Enable Enable Enable Broadcast Margin Enable Enable Enable Enable Enable Enable Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 3.3V DDC SDA SCL VCC VCC DEV_1 DEV_4 Rail DDC ID=1 Broadcast Group=2 Rout Cout Rail_1 Rail_1 REF. MEM_1 POS_1 PH_1 Cout Rail_4 DEV_5 Rail DDC ID=2 Broadcast Group=2 Rout Cout Rail_2 MEM_2 POS_2 Rail_2 VCC DEV_3 Rout VCC VCC DEV_2 Rail DDC ID=5 Broadcast Group=2 PH_2 VCC DEV_6 Rail DDC ID=3 Broadcast Group=2 Rout Cout Rail_3 Rail_3 MEM_3 POS_3 PH_3 Figure 18. 4 Rail power supply with PMBus broadcast margin and enable The DDC_CONFIG GUI entries for this example are shown below in Figure 20. After the Rail DDC ID and Broadcast Group are assigned the Broadcast Enable and/or Broadcast margin command(s) must be enabled in the MISC_CONFIG section of the GUI shown in Figure 19. To use Broadcast Margin, enable the output rail(s) under test using PMBus Enable of any broadcast member or configure the rail(s) to use hardware enable. Once the rail(s) are enabled use the GUI to select the appropriate margining command located on the front page of the GUI see Figure 21. Use the Configuration Device page of the GUI to change the margining range. The default range is automatically calculated to be ±5% of the nominal output voltage. Verify that all current share members have the same margin settings. Figure 19. Setting Broadcast Enable and Margin in the MISC_CONFIG field. 9 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Figure 20. DDC_CONFIG GUI to enable Broadcast Enable and Margin Figure 21. PMBus Enable and Margin Control located on Group Page of the GUI Configuring Current Sharing Consider the 3-phase current sharing group shown below in Figure 22. Ensure that each Zilker Labs device in the group is connected to the same DDC and SMBus. The device with the lowest Device Position becomes the initial Reference Phase. The Reference phase is used to provide the load current information to each member device. If the Reference Device is dropped or faults the device with the next lowest Device Position becomes the new Reference Device. 3.3V VCC DEV_1 0x20 REF. POS_1 Rail_1 Rail DDC ID = 5 Rout Cout PH_1 DDC SDA SCL SYNC SYNC_Out VCC DEV_2 0x21 MEM_1 POS_2 1. (DDC_CONFIG) SYNC_In Assign the same Rail DDC ID to each device in the current sharing group. If there are other non-current sharing devices connected to the same DDC bus make sure that those output rails have a unique Rail DDC ID. In this example, the Rail DDC ID = 5 for each current sharing devices. PH_2 DEV_3 0x22 VCC MEM_2 POS_3 PH_3 SYNC_In Figure 22. 3-phase Current Sharing Example 10 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 2. (ISHARE_CONFIG) 3. (USER_CONFIG) The ISHARE_CONFIG field contains the following entries, a. Number of Devices = number of devices or phases in current sharing group b. Device Position = Autonomous interleave position relative to SYNC Clock c. Current Share Control = Enables current sharing For this example the specific entries for each address is shown in Table 3. Table 3. ISHARE_CONFIG current share values Ph ase SM Bus Ad dress Reference M ember_1 M ember_2 0x20 0x21 0x22 Nu mb er of Devices 3 3 3 Curren t Device Share P ositio n Co ntro l 1 E nabled 2 E nabled 3 E nabled The GUI entries are shown Figure 23. The following parameters located in the USER_CONFIG field (See Figure 24 and Figure 25) on the PMBus: Advanced page pertain to current sharing groups and must be set to properly configure current sharing. a. Min Duty Cycle The minimum allowable duty cycle must be set to Enable to ensure that each phase starts the turn-on ramp with the same pulse width. Enabling Min Duty Cycle sets the default minimum value to Fsw . 128 b. SYNC Timout Enable SYNC always on if the device is providing the SYNC source. Typically the Reference Device is used to provide the SYNC Clock. However any device internal or external to the sharing group can provide the SYNC Clock. For Member devices the SYNC Timout Enable parameter can be set to SYNC off in 500 ms. This will save a little power by shutting down the SYNC clock 500 ms after Enable is deasserted. c. SYNC Input Mode / SYNC Pin Config The SYNC Input Mode is used along with the SYNC Pin Configure parameter to specify whether the device will output the SYNC clock or use the SYNC clock as an input. SYNC Clock Source mode: set SYNC Input Mode to Pinstrap Input and set SYNC Pin Configure to Output Int. Signal. The DDC device will now operate as a clock source. Configure the SYNC Output Mode command in the MFR_CONFIG field to be Push-Pull or Open Drain to satisfy your system design requirements. Reference the device data sheet for additional information. SYNC Clock Input mode: Figure 23. ISHARE_CONFIG GUI values 11 Sync Pin Configure is used to assign the internal clock as an output or as an input. Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Set the SYNC Pin Configure parameter to Input Only if the device is using the SYNC clock as an input. d. Standby Mode Standby mode must be set to Monitor Enabled for both Reference and Member Devices. Setting this parameter to monitor mode ensures that the firmware is initialized prior to enabling the output rail. The other entries in the USER_CONFIG field do not affect current sharing groups, and should be configured to meet the designer's system requirements. For additional information about these parameters please reference AN2026 AN2026 Power Navigator Users Manual and AN2033 AN2033 Zilker Labs PMBus Command Set ­ DDC Products The USER_CONFIG GUI entries for this example are shown below. Figure 24 illustrates the configuration for the Reference device. Figure 25 illustrates the configuration for Member device(s). Figure 25. USER_CONFIG field (Member) 4. (MFR_CONFIG) The following parameters located in the MFR_CONFIG field (See Figure 26) in the GUI PMBus: Advanced page must be set to properly configure current sharing. a. I Sense Delay The I Sense Delay parameter controls the blanking time between switching the top or bottom FET, allowing the filtering of noise associated with turning the switching devices on and off from the current measurement circuit. The actual value selected depends on Fsw, sensing method and duration of the resonant ring-out due to circuit parasitics. Ensure that the same blanking value is used for the Reference and Member device(s). b. I Sense Control Figure 24. USER_CONFIG field (Reference) Reference AN2026 AN2026 Power Navigator Users Manual for additional information. e. SMBus TX Inhibit SMBus TX controls the Bus mastering capabilities of Zilker Labs products that don't use the DDCBus. SMBus TX Inhibit should be set to Transmit Inhibit for the DDCBus products referenced in this document. 12 I Sense Control is used to configure the current sensing method. Various modes of current sensing are available depending on duty cycle and switching frequency. Current sensing options are shown below in Table 4. A lumped or distributed resistor can be substituted for RDSon and DCR sensing. Ensure that the same I Sense Control is used for the Reference and Member device(s). Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Table 4. Current sensing method selection Current Sense Control Ground Referenced, Down Slope (RDSon) Vout Referenced , Down Slope (Inductor DCR sensing) Vout Referenced , Up Slope (Inductor DCR Sensing) Usage Low duty cycle and low Fsw Low duty cycle and high Fsw High duty cycle c. NLR During Ramp Determines if NLR is active during ramps or waits until Power Good is asserted. This should always be set to Wait for PG for both Reference and Member device(s) when configuring current sharing groups. 5. (TEMPCO_CONFIG) The TEMPCO_CONFIG command is used to configure the temperature correction factor and temperature measurement source (internal or external) when performing temperature coefficient correction for the current sensing element. TEMPCO_CONFIG values are applied as a negative correction to a positive temperature coefficient. In general, the TEMPCO_CONFIG command is defined below: Table 5. TEMPCO_CONFIG F ield 7 f. Alternate Ramp Control Set to enable for Reference and Member device(s). Reference Alternate Ramp control in this document. e. SYNC Output Mode Configures the SYNC pin as Open Drain or Push-Pull. SYNC Output Mode is typically set to Push-Pull for the SYNC clock source and Open Drain for devices that receive the SYNC clock as an input. The MFR_CONFIG GUI entries are shown below for this example. The comments refer to current sharing groups. Reference AN2026 AN2026 Power Navigator Users Guide for additional information. 6:0 Pu rp ose Value Description Selects the tem perature sensor source for tem pco correction Sets Tem pco correction in units o of 100ppm/ C for 0 Selects the internal tem perature sensor 1 Selects the XT E MP pin for temperature measurem ents TC R SEN (EX T) R SEN (I N T) The following equations can be used to fine tune the temperature correction for internal and external sense elements. R SEN ( EXT ) = IOUT _ CAL _ GAIN × (1 + TC × (T - 25) RSEN ( INT ) = IOUT _ CAL _ OFFSET × (1 + TC × 10 -4 × (T - 25) R DSON = IOUT _ CAL _ OFFSET × (1 + TC × (T - 25) Where, IOUT_CAL_GAIN = is the impedance of the current sense element at 25°C IOUT_CAL_OFFSET = offset added to IOUT readings, this offset is used to compensate for current measurement error. TC = respective temperature coefficient RSEN(EXT) = DCR inductor resistance RSEN(INT) = internal silicon temp diode RDSON = low-side FET channel resistance Figure 26. MFR_CONFIG Field T = temperature measured by sensing device TC = temperature correction factor The following hex values can be used to accurately compensate for most designs: 13 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Table 6. Typical TEMPCO_CONFIG values by ZL part number (MAX_DUTY) PMBus Basic Commands The maximum duty cycle must be constrained as the switching frequency increases. Configure the MAX_DUTY cycle to a maximum value for each group member per Equation 2, round the result down to the closest integer value. Table 7 lists MAX_DUTY values for a few common switching frequencies. (VOUT_COMMAND) Equation 2 Set each current sharing phase to the same output voltage value. max(%)= [1 - (150ns × Fsw)]×100 (VOUT_TRIM) Table 7. MAX_DUTY values for common switching frequencies ZL Device ZL2004 ZL2004 ZL2006 ZL2006 Extenal Temp Internal Silicon Diode Diode A8 2C A8 2C Typically set to 0 (default value) for each current sharing phase. The reference phase will always retain a zero value. Member phases will adjust the trim value until all phases carry equal load current. If an offset voltage is desirable to overcome the effects of droop use the VOUT_CAL_OFFSET command to add an offset. See VOUT_CAL_OFFSET section below. Fsw (kHz) 200 400 600 800 1000 1400 (VOUT_CAL_OFFSET) The VOUT_CAL_OFFSET command is used to apply an offset voltage that can compensate for the load-line droop. While positive and negative offset values are valid a positive offset value is typically used with a magnitude of: Equation 1 Max Duty (%) 97 94 91 88 85 80 (TON_DELAY), (TOFF_DELAY) Time On Delay and Time Off Delay parameters for the reference phase must be set at least 10 mS greater than the delay parameters of each member device, reference Figure 16. VOUT _ CAL _ OFFSET = 0.5 × I MAX × RDROOP (DEADTIME) If the VOUT_CAL_OFFSET command is used ensure that each group member is assigned the same VOUT_CAL_OFFSET value. Zilker Labs requires that the H-L and L-H deadtimes are both set to a maximum value of 56 ns to obtain performance and reliability. The maximum deadtime values can be reduced in increments of 4 ns if the worst case transition times are known. Hex 0x3838 configures both deadtime edges to a maximum of 56 ns. (VOUT_DROOP) Droop resistance is used as part of the current sharing algorithm. The recommended droop or loadline resistance for current sharing groups is between 0.5 m's and 1.5 m's. Each group member is assigned the same droop value. The deadtimes of both pwm edges will dynamically find the most efficient operating point between 56 ns and the minimum value configured with the DEADTIME_CONFIG command. Please reference Figure 27. The DEADTIME command must precede the DEADTIME_CONFIG command in the text based configuration file. 14 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Table 8. 3-phase sharing group requirements (DEADTIME_CONFIG) Zilker Labs recommends that the Min Deadtime H-L and L-H are both set to a value of 16 ns to obtain performance and reliability, if the minimum transition times are known to be less than 16 ns this number can be reduced in increments of 4 ns. Hex 0x0808 configures both pwm edges as dynamic with a 16 ns minimum deadtime. Please reference Figure 27. The DEADTIME command must precede the DEADTIME_CONFIG command in the text based configuration file. Device (Phase) PH_1 Ref PH_2 Mem_1 PH_3 Mem_2 Address (Hex) SYNC 0x20 Source 12 1.0V 40 400 0x21 Input 12 1.0V 40 400 0x22 Input 12 1.0V 40 400 2.5V VIN (Volts) VOUT IOUT (Volts) (Amps) 12V DEV_1 0x20 REF. POS_1 FSW (kHz) Rail_1 Rail DDC ID = 1 Vout=1.0V Iout=120A PH_1 DDC SDA SCL SYNC SYNC_Out VCC DEV_2 0x21 MEM_1 POS_2 PH_2 SYNC_In VCC DEV_3 0x22 MEM_2 POS_3 PH_3 SYNC_In Figure 27. configuration Recommended deadtime Configuration File Figure 28. 3-phase sharing group example The three configuration files for this example are shown in Figure 29 at the end of this document. After the hardware design is completed and the design has been verified using the GUI, a configuration file is created for each group member. The configuration file can also be composed or edited using a text editor such as Microsoft Notepad. Other editors can be used as long as the filename has a .txt extension. The configuration file data can utilize both decimal and hexadecimal data. Hexadecimal data is always preceded by 0x. Comments can be added to the config file if preceded with a # sign. Consider the 3-phase sharing group shown in Figure 28. The operating requirements are shown in Table 8. 15 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Configuration File Checklist Use the following checklist as a guideline when creating configuration files for current sharing rails. 1. Follow memory restore guidelines RESTORE_FACTORY STORE_USER_ALL STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL . . STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL 2. Assign the same VOUT_DROOP value to all ZL devices in the current sharing group with a value between 0.5's and 1.5's. 3. Ensure that the Time On Delay and Time Off Delay parameters for the reference phase are at least 10 ms greater than the delay parameters of each member device. 4. Assign the same fault responses for each device. 5. Designate and configure the SYNC source for the group, if the source is one of the group devices all other device(s) in the group are configured as SYNC inputs. 6. Assign the same DDC_RAIL_ID to each device in the group using DDC_CONFIG. 7. Assign a unique phase position to each group device using ISHARE_CONFIG. 8. Enable Alternate Ramp Control for each group member. 9. Configure Standby Mode to Monitor Enabled for each group member. 10. Set the TEMPCO_CONFIG value for each group member. 11. Configure DEADTIME and DEADTIME_CONFIG commands with the DEADTIME command line always preceding DEADTIME_CONFIG. The recommended starting point is both edges set to DYNAMIC with a minimum deadtime of 16ns. The maximum deadtimes should be set to 56ns maximum. DEADTIME DEADTIME_CONFIG 0x3838 0x0808 12. Assign the maximum duty cycle to each group device per Equation 2. 13. Assign the same IOUT_CAL_GAIN to each group device in units of m's. 14. Configure the Min Duty Cycle command to Enabled. 15. Configure SYNC Timeout EN to SYNC always On. 16. Diode Emulation, Adaptive Frequency Compensation is not supported with current sharing and must be disabled. 16 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Reference (Phase_1) Line Num. Command Value Notes 1 2 3 4 RESTORE_FACTORY STORE_USER_ALL STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL 5 6 FREQUENCY_SWITCH ON_OFF_CONFIG 7 8 9 10 11 12 MFR_ID MFR_MODEL MFR_REVISION MFR_LOCATION MFR_DATE MFR_SERIAL 13 14 15 16 17 18 19 VOUT_COMMAND VOUT_MAX VOUT_DROOP VOUT_MARGIN_HIGH VOUT_MARGIN_LOW POWER_GOOD_ON POWER_GOOD_DELAY 1.00 1.15 1.00 1.05 0.95 0.90 5 # # # # # # # volts volts volts volts volts volts ms 20 21 22 23 24 VOUT_OV_FAULT_LIMIT VOUT_OV_FAULT_RESPONSE VOUT_UV_FAULT_LIMIT VOUT_UV_FAULT_RESPONSE OVUV_CONFIG 1.15 0x80 0.85 0x80 0x80 # # # # # volts shutdown 0 delay volts shutdown 0 delay shutdown 0 delay 25 26 27 VIN_UV_WARN_LIMIT VIN_UV_FAULT_LIMIT VIN_UV_FAULT_RESPONSE 10.8 9.600 0x80 # volts # volts # shutdown 0 delay 28 29 30 VIN_OV_FAULT_LIMIT VIN_OV_WARN_LIMIT VIN_OV_FAULT_RESPONSE 14.40 13.20 0x80 # volts # volts # shutdown 0 delay 31 32 33 34 35 36 37 38 IOUT_SCALE IOUT_CAL_OFFSET IOUT_OC_FAULT_LIMIT IOUT_AVG_OC_FAULT_LIMIT IOUT_UC_FAULT_LIMIT IOUT_AVG_UC_FAULT_LIMIT MFR_IOUT_OC_FAULT_RESPONSE MFR_IOUT_UC_FAULT_RESPONSE 1.2 -2 67.50 56.25 -22.50 -18.00 0x80 0x80 # # # # # # # # 39 40 41 OT_WARN_LIMIT OT_FAULT_LIMIT OT_FAULT_RESPONSE 110.0 120.0 0x80 # C O # C # shutdown 0 delay 42 43 44 UT_WARN_LIMIT UT_FAULT_LIMIT UT_FAULT_RESPONSE -20.0 -30.0 0x80 # C O # C # shutdown 0 delay 45 46 47 48 TON_DELAY TON_RISE TOFF_DELAY TOFF_FALL 49 50 51 52 PID_TAPS DEADTIME DEADTIME_CONFIG MAX_DUTY 53 54 55 56 57 58 59 USER_CONFIG MFR_CONFIG NLR_CONFIG MISC_CONFIG DDC_CONFIG ISHARE_CONFIG TEMPCO_CONFIG 60 61 STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL Advanced Gui Entries # # restores # # 400 0x1A # kHz # hardware enable Zilker Labs ZL2006 ZL2006 EV2 Austin 10/29/08 15 5 15 5 's amps amps amps amps amps shutdown 0 delay shutdown 0 delay O O # # # # ms ms ms ms # pid coefficients 0x3838 0x0808 94 0x6031 0x82D5 0x00000000 0x4480 0x0101 0x0141 0xA8 #% # sync source # # # # # disabled broadcast enabled ddc rail=1 current share en,pos_1 ext.correction # restores # Figure 29a. Configuration file for 3-phase current sharing group (Ref_Phase) 17 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Member_1 (Phase_2) Line Num. Command Value Notes 1 2 3 4 RESTORE_FACTORY STORE_USER_ALL STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL 5 6 FREQUENCY_SWITCH ON_OFF_CONFIG 7 8 9 10 11 12 MFR_ID MFR_MODEL MFR_REVISION MFR_LOCATION MFR_DATE MFR_SERIAL 13 14 15 16 17 18 19 VOUT_COMMAND VOUT_MAX VOUT_DROOP VOUT_MARGIN_HIGH VOUT_MARGIN_LOW POWER_GOOD_ON POWER_GOOD_DELAY 1.00 1.15 1.00 1.05 0.95 0.90 5 # # # # # # # volts volts volts volts volts volts ms 20 21 22 23 24 VOUT_OV_FAULT_LIMIT VOUT_OV_FAULT_RESPONSE VOUT_UV_FAULT_LIMIT VOUT_UV_FAULT_RESPONSE OVUV_CONFIG 1.15 0x80 0.85 0x80 0x80 # # # # # volts shutdown 0 delay volts shutdown 0 delay shutdown 0 delay 25 26 27 VIN_UV_WARN_LIMIT VIN_UV_FAULT_LIMIT VIN_UV_FAULT_RESPONSE 10.8 9.600 0x80 # volts # volts # shutdown 0 delay 28 29 30 VIN_OV_FAULT_LIMIT VIN_OV_WARN_LIMIT VIN_OV_FAULT_RESPONSE 14.40 13.20 0x80 # volts # volts # shutdown 0 delay 31 32 33 34 35 36 37 38 IOUT_SCALE IOUT_CAL_OFFSET IOUT_OC_FAULT_LIMIT IOUT_AVG_OC_FAULT_LIMIT IOUT_UC_FAULT_LIMIT IOUT_AVG_UC_FAULT_LIMIT MFR_IOUT_OC_FAULT_RESPONSE MFR_IOUT_UC_FAULT_RESPONSE 1.2 -2 67.50 56.25 -22.50 -18.00 0x80 0x80 # # # # # # # # 39 40 41 OT_WARN_LIMIT OT_FAULT_LIMIT OT_FAULT_RESPONSE 110.0 120.0 0x80 # C O # C # shutdown 0 delay 42 43 44 UT_WARN_LIMIT UT_FAULT_LIMIT UT_FAULT_RESPONSE -20.0 -30.0 0x80 # C O # C # shutdown 0 delay 45 46 47 48 TON_DELAY TON_RISE TOFF_DELAY TOFF_FALL 49 50 51 52 PID_TAPS DEADTIME DEADTIME_CONFIG MAX_DUTY 53 54 55 56 57 58 59 USER_CONFIG MFR_CONFIG NLR_CONFIG MISC_CONFIG DDC_CONFIG ISHARE_CONFIG TEMPCO_CONFIG 60 61 STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL Advanced Gui Entries # # restores # # 400 0x1A # kHz # hardware enable Zilker Labs ZL2006 ZL2006 EV2 Austin 10/29/08 5.0 5 5.0 5 's amps amps amps amps amps shutdown 0 delay shutdown 0 delay O O # # # # ms ms ms ms # pid coefficients 0x3838 0x0808 94 0x6051 0x82D4 0x00000000 0x4480 0x0101 0x0145 0xA8 #% # sync input # # # # # disabled broadcast enabled ddc rail=1 current share en,pos_2 ext.correction # restores # Figure 29b. Configuration file for 3-phase current sharing group (Mem_1) 18 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Member_2 (Phase_3) Line Num. Command Value Notes Advanced Gui Entries # # # restores # # 1 2 3 4 RESTORE_FACTORY STORE_USER_ALL STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL 5 6 FREQUENCY_SWITCH ON_OFF_CONFIG 7 8 9 10 11 12 MFR_ID MFR_MODEL MFR_REVISION MFR_LOCATION MFR_DATE MFR_SERIAL 13 14 15 16 17 18 19 VOUT_COMMAND VOUT_MAX VOUT_DROOP VOUT_MARGIN_HIGH VOUT_MARGIN_LOW POWER_GOOD_ON POWER_GOOD_DELAY 1.00 1.15 1.00 1.05 0.95 0.90 5 # # # # # # # volts volts volts volts volts volts ms 20 21 22 23 24 VOUT_OV_FAULT_LIMIT VOUT_OV_FAULT_RESPONSE VOUT_UV_FAULT_LIMIT VOUT_UV_FAULT_RESPONSE OVUV_CONFIG 1.15 0x80 0.85 0x80 0x80 # # # # # volts shutdown 0 delay volts shutdown 0 delay shutdown 0 delay 25 26 27 VIN_UV_WARN_LIMIT VIN_UV_FAULT_LIMIT VIN_UV_FAULT_RESPONSE 10.8 9.600 0x80 # volts # volts # shutdown 0 delay 28 29 30 VIN_OV_FAULT_LIMIT VIN_OV_WARN_LIMIT VIN_OV_FAULT_RESPONSE 14.40 13.20 0x80 # volts # volts # shutdown 0 delay 31 32 33 34 35 36 37 38 IOUT_SCALE IOUT_CAL_OFFSET IOUT_OC_FAULT_LIMIT IOUT_AVG_OC_FAULT_LIMIT IOUT_UC_FAULT_LIMIT IOUT_AVG_UC_FAULT_LIMIT MFR_IOUT_OC_FAULT_RESPONSE MFR_IOUT_UC_FAULT_RESPONSE 1.2 -2 67.50 56.25 -22.50 -18.00 0x80 0x80 # # # # # # # # 39 40 41 OT_WARN_LIMIT OT_FAULT_LIMIT OT_FAULT_RESPONSE 110.0 120.0 0x80 # C O # C # shutdown 0 delay 42 43 44 UT_WARN_LIMIT UT_FAULT_LIMIT UT_FAULT_RESPONSE -20.0 -30.0 0x80 # C O # C # shutdown 0 delay 45 46 47 48 TON_DELAY TON_RISE TOFF_DELAY TOFF_FALL 49 50 51 52 PID_TAPS DEADTIME DEADTIME_CONFIG MAX_DUTY 53 54 55 56 57 58 59 USER_CONFIG MFR_CONFIG NLR_CONFIG MISC_CONFIG DDC_CONFIG ISHARE_CONFIG TEMPCO_CONFIG 60 61 STORE_DEFAULT_ALL RESTORE_DEFAULT_ALL 400 0x1A # kHz # hardware enable Zilker Labs ZL2006 ZL2006 EV2 Austin 10/29/08 5.0 5 5.0 5 's amps amps amps amps amps shutdown 0 delay shutdown 0 delay O O # # # # ms ms ms ms # pid coefficients 0x3838 0x0808 94 0x6051 0x82D4 0x00000000 0x4480 0x0101 0x0149 0xA8 # % # sync input # # # # # disabled broadcast enabled ddc rail=1 current share en,pos_3 ext.correction # restores # Figure 29c. Configuration file for 3-phase current sharing group (Mem_2) 19 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Revision History Revision 1.0 0 Description Date Initial Release October 2008 Assigned file number AN2034 AN2034 to app note as this will be the first release with an Intersil file number. Replaced header and footer with Intersil header and footer. Updated disclaimer information to read "Intersil and it's subsidiaries including Zilker Labs, Inc." No changes to datasheet content. 20 April 2009 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Notes 21 Application Note Revision 5/01/2009 www.intersil.com Application Note 2034 Zilker Labs, Inc. 4301 Westbank Drive Building A-100 Austin, TX 78746 Tel: 512-382-8300 Fax: 512-382-8329 Copyright © 2008, Zilker Labs, Inc. All rights reserved. Zilker Labs, Digital-DC, CompZL and the Zilker Labs Logo are trademarks of Zilker Labs, Inc. All other products or brand names mentioned herein are trademarks of their respective holders. Specifications are subject to change without notice. Please see www.zilkerlabs.com for updated information. This product is not intended for use in connection with any high-risk activity, including without limitation, air travel, life critical medical operations, nuclear facilities or equipment, or the like. The reference designs contained in this document are for reference and example purposes only. THE REFERENCE DESIGNS ARE PROVIDED "AS IS" AND "WITH ALL FAULTS" AND INTERSIL AND IT'S SUBSIDIARIES INCLUDING ZILKER LABS, INC. DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS OR IMPLIED. ZILKER LABS SHALL NOT BE LIABLE FOR ANY DAMAGES, WHETHER DIRECT, INDIRECT, CONSEQUENTIAL (INCLUDING LOSS OF PROFITS), OR OTHERWISE, RESULTING FROM THE REFERENCE DESIGNS OR ANY USE THEREOF. Any use of such reference designs is at your own risk and you agree to indemnify Intersil and it's subsidiaries including Zilker Labs, Inc. for any damages resulting from such use. 22 Application Note Revision 5/01/2009 www.intersil.com