AN1943 DK3300 uPSD33XX AI08875 uPSD3334D uPSD3334D-40U6 A8-A11 64K/128K/ - Datasheet Archive

 

APPLICATION NOTE Design Guide for µPSD33xx Family INTRODUCTION As shown in Figure 1., the µPSD33xx family is a series

 

AN1943 AN1943 APPLICATION NOTE Design Guide for µPSD33xx Family INTRODUCTION As shown in Figure 1., the µPSD33xx family is a series of 8051-class microcontrollers (MCUs) containing a new fast Turbo 8032 core with a large dual-bank flash memory, a large SRAM, many peripherals, programmable logic, and JTAG In-System Programming (ISP). This document shows the steps to create a design using the DK3300 DK3300 development board, the software development tool PSDsoft Express, and Ulink USB-JTAG debugger from Keil Software. The project and debug environment (IDE), using the Raisonance development suite for Turbo µPSD, is currently not featured in this Application Note. This will be addressed in the near future. Please see the µPSD on-line resources page for new documentation at : http://www.st.com/stonline/products/families/ memories/psm/soft_c2.htm. PSDsoft has, though, been upgraded to connect to ST's JTAG programming cable (FlashLINK) or Raisonance's JTAG programming cable (R-LINK). It is important to make the correct selection in PSDsoft, using the HW Setup configuration menu. Figure 1. General Block Diagram of the µPSD33xx uPSD33XX uPSD33XX (3) 16-bit Timer/ Counters (2) External Interrupts P3.0:7 Turbo 8032 Core PFQ & BC Programmable Memory Decode and Page Logic I2 C 1st Flash: 64K, 128K, or 256K Bytes 2nd Flash: 16K or 32K Bytes SRAM: 2K, 8K, or 32K Bytes UART0 (8) GPIO, Port A (80-pin only) P1.0:7 (8) GPIO, Port 1 (8) 10-bit ADC Optional IrDA Encoder/Decoder UART1 SYSTEM BUS (8) GPIO, Port 3 General Purpose Programmable Logic, 16 Macrocells PA0:7 (8) GPIO, Port B PB0:7 (2) GPIO, Port D PD1:2 (4) GPIO, Port C PC0:7 JTAG ICE and ISP SPI 16-bit PCA (6) PWM, CAPCOM, TIMER P4.0:7 8032 Address/Data/Control Bus (80-pin device only) Supervisor: Watchdog and Low-Voltage Reset (8) GPIO, Port 4 VCC, VDD, GND, Reset, Crystal In MCU Bus Dedicated Pins AI08875 AI08875 May 2004 1/48 AN1943 AN1943 - APPLICATION NOTE TABLE OF CONTENTS INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. General Block Diagram of the µPSD33xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 µPSD33xx FAMILY OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. uPSD3334D uPSD3334D Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dk3300 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. DK3300 DK3300 Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DESIGN EXAMPLE BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Design Example Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Design Example Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ENTERING DESIGN IN PSDsoft EXPRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Select MCU and Initial Placement of Flash in Code Space or Data Space. . . . . . . . . . . . . . . . 10 Figure 6. MCU Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8. Page Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chip-Select Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9. Chip-Select Definition for 8K byte SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Chip-Select Definition for Flash Memory Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11.External Chip-Select Definition for LCD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I/O Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 12.Logic Equation for Signal LCD_rw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 User-Defined Node Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13.4-bit Down-Counter with Automatic Reload of Initial Count . . . . . . . . . . . . . . . . . . . . . . 18 Figure 14.D-Register Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Edit ABEL HDL Statements for PLD Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 15.Design Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Additional µPSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 C Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 16.Coded Example Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Fitting Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Merging 8032 Firmware with µPSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 17.Merging the Example Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 JTAG Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 18.Programming with FlashLINK/R-LINK JTAG Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 WATCH IT RUN ON DK3300 DK3300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 USING uVISION2 AND ULink JTAG DEBUGGER FROM KEIL SOFTWARE, INC. . . . . . . . . . . . . . 27 2/48 AN1943 AN1943 - APPLICATION NOTE Loading a Keil uVision2 Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Building the Project and Programming the Turbo µPSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Running Keil's ULink - USB to JTAG Debugger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 19.Setting up ULink JTAG Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 20.Setting up ULink Target Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 21.Setting up the ULink Target Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 22.Tool Menu `Load' Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 23.Keil's ULink JTAG Debugger After Successfully Invoked . . . . . . . . . . . . . . . . . . . . . . . . 30 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 1. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 APPENDIX A.PSDsoft EXPRESS PROJECT SUMMARY FILE, DK3300 DK3300_1.SUM . . . . . . . . . . . . . . . 32 APPENDIX B.PSDsoft EXPRESS ABEL HDL DESIGN FILE DK3300 DK3300_1.ABL. . . . . . . . . . . . . . . . . . 36 APPENDIX C.PSDsoft EXPRESS FITTER REPORT FILE DK3300 DK3300_1.FRP . . . . . . . . . . . . . . . . . . . . 40 APPENDIX D.DK3300 DK3300 SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 24.MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 25.Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 26.Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3/48 AN1943 AN1943 - APPLICATION NOTE µPSD33xx FAMILY OVERVIEW The µPSD33xx family is a turbo 4-clock per instruction 8032 MCU capable of being clocked up to 40MHz at 3.3V or 5.0V at industrial operating temperature range. Currently there are twelve family members that contain different combinations of flash memory size, operating voltage, and packaging (please see the full datasheet). In this Application Note, we will use uPSD3334D-40U6 uPSD3334D-40U6 as our example. The term "Turbo µPSD" is used throughout the remainder of the document for brevity (see the Turbo µPSD block diagram in Figure 2). The Turbo µPSD has a unique memory structure that includes two independent flash memory arrays (Main and Secondary) capable of read-while-write operation. This is ideal for In-Application Programming (IAP) because the 8032 can fetch instructions from one flash array while erasing/writing the other array. Individual sectors of each flash memory array can be mapped to virtually any 8032 address by the Decode PLD (DPLD) for total flexibility. The Turbo µPSD also contains a Page Register whose outputs feed the inputs of the DPLD. This allows paging (or banking) of flash memory to break the 8032's inherent limit of 64K byte addresses. The 8032 may write to the Page Register at runtime. For more complex designs, the Turbo µPSD is capable of placing each of the flash memory arrays (Main or Secondary) into 8032 code address space, into 8032 data space, or into both code and data space on the fly. Mapping flexibility like this supports IAP because either flash array may be temporarily placed into data space while the firmware is updated, then moved back into code space when finished, all under control of the 8032. Many peripherals are available in this Turbo µPSD, including: two UART channels, one IrDA channel, one SPI channel, one I2C channel, six PWM channels, eight 10-bit ADC channels, nine Timer/Counters, a watchdog timer, low-VCC detection with reset-out, a general purpose PLD, many GPIO and a USB-JTAG Debugger. All of the peripherals on Ports 1, 3, and 4 are controlled using 8032 Special Function Registers (SFRs). I/ O Signals on ports A, B, C, and D are controlled one of two ways: 1. by a block of xdata memory mapped control registers, whose base address (csiop) can be mapped anywhere using the DPLD; and 2. by the programmable logic. In addition, Turbo µPSD offers a Cross-Bar I/O, which means that Peripheral functions on Port 1 are also available on Port 4 (cross-bar switch), providing more flexibility. There is no need to sacrifice one peripheral function when two functions are available on a single pin, just use the other port. The JTAG channel on Port C is used for ISP and debug of the 8032 MCU core. ISP is ideal for rapid code iterations during firmware development and for Just-In-Time inventory management during manufacturing. JTAG ISP eliminates the need for sockets and pre-programmed devices, and requires no participation of the 8032. JTAG debug eliminates the need for expensive and intrusive hardware In-Circuit Emulator (ICE). 4/48 AN1943 AN1943 - APPLICATION NOTE Figure 2. uPSD3334D uPSD3334D Block Diagram Turbo uPSD33XX uPSD33XX (7) VCC and GND Turbo 8032 MCU Divide or Pass 256 byte SRAM/SFRs (2) Crystal Connection (1) Reference Voltage Input (80-pin only) Port 1: Available Functions (8) 10-bit ADC SPI (8) GPIO UART1 w/IrDA (3) 16-bit Timer/Cntrs (2) 8032 Timer 1 (2) UART0 (2) Interrupts (2) I2C 8032 Interrupts (8) GPIO I2C PCA: (6) 16-bit Timer/ Counter Units, CAPCOM, PWM (8) 8032 Data/Low Addr Port 4: Available Functions (8) GPIO 10mA (2) PCA CLK Inputs (6) PCA: PWM/ CAPCOM (4) 8032 High Address Supervisor, WDT/LVD System Reset (4) MCU A8-A11 A8-A11 (80-pin Pkg Only) (1) Reset Input Memory Interface with Prefetch & Branch Cache Port C: Available Functions (4) GPIO (4) Dedicated JTAG General PLD, 16 Macrocell Memory Bus (2) 8032 Timer 2 (2) UART1IrDA (4) SPI (8) MCU AD0-AD7 (80-pin Pkg Only) JTAG Debut and ISP Main Flash: 64K/128K/ 64K/128K/ 256 Bytes (8) ADC Port 3: Available Functions UART0 Local MCU Bus (2) 8032 Timer 2 (2) UART1 - IrDA (4) SPI (These signals are alternately available on Port 4) (2) Extended JTAG (2) SRAM Battery B/U Port A: Available Functions (80-pin only) Sector Selects (8) GPIO (8) PLD I/O 2nd Flash: 16K/32K 16K/32K Bytes Port B: Available Functions SRAM: 2K/8K/32K 2K/8K/32K Bytes (8) GPIO (8) PLD I/O 256 Control Registers Port D: Available Functions Decode PLD & Page Logic (2) GPIO - 80-pin (1) GPIO - 52-pin (2) Chip Selects - 80-pin (1) Chip Select - 52-pin AI09606 AI09606 5/48 AN1943 AN1943 - APPLICATION NOTE DK3300 DK3300 OVERVIEW A picture of the DK3300 DK3300 board is shown in Figure 3. Board layout and schematics are in the Appendix. Connectors CON1, CON2, and CON3 provide easy access to all Turbo µPSD signals for expansion or testing. A list of jumpers JP0 - JP16 and their functions can be found on the DK3300 DK3300 board's silk screen. For more detailed information on these jumpers, please refer to APPENDIX D., DK3300 DK3300 SCHEMATICS and the DK3300 DK3300 User's Guide. UARTs are available on connectors marked UART0 and UART1. The FlashLINK/R-LINK/ULink JTAG ISP cable connects at the connector, FLASH_LINK. The DK3300 DK3300 also has a 16-character or graphical LCD interface and a full featured real-time clock with a back-up battery, a serial EEPROM, IrDA transceiver, PWM control over LCD brightness, and a rotary encoder knob for selection of various demo applications. Figure 3. DK3300 DK3300 Development Board 6/48 AN1943 AN1943 - APPLICATION NOTE DESIGN EXAMPLE BLOCK DIAGRAM This simple design example is represented by the block diagram of Figure 4, and the memory map of Figure 5., page 8. The Flash memory is paged, and few of the 8032 interfaces (e.g., ADC, PWM, UART) are configured and used. The idea is to touch several aspects of the µPSD that may be unfamiliar to a typical 8051 user and to give you an idea of how to use the design tools and become familiar with Turbo µPSD architecture. Figure 4. Design Example Block Diagram uPSD3334D-40U6 uPSD3334D-40U6 A8-A15 A8-A15 PWM ADDR PWM 8 csboot0csboot3 32KB Secondary Flash (code) 13 8032 pin_XTAL1 13 _RESET_IN rs0 XTAL1 psel0psel1 Data Bus Repeater 8 csiop 256 Control Regs. RxD TxD RS-232 RS-232 Transceiver UART0 pin PC0 (TMS) 4 pin PC1 (TCK) pin PC2 (TSTAT) 1 JTAG ISP 2 Initial count pin PC3 (TERR) pin PC2 (TDI) pin PC2 (TDO) 1 XTAL2 16 pin P3.0 (RxD) pin P3.1 (TxD) Page Reg. (from Control Registers) 8KB SRAM 40MHz pin_XTAL2 DPLD fs0-fs7 256KB 256KB Main Flash (data) 8 DATA RESET 8 15 Latch ADC pins A0-A11 A0-A11 12 pins P0.0-P0.7 DATA 16 ADDR AD0-AD7 pin_RESET ADDR 16 8 16 Jumper ADC 8 16 PLD Macrocells ALE Down counter Pin PB0 (term_count) 8 pin PB5 (LCD_rs) pin PB6 (LCD_rw) pin PB6 (LCD_e) pins PA0-PA7 (LCD_d0 - LCD_d7) REG SELECT READ/WRITE CHIP SELECT D0-D7 LCD MODULE AI09607 AI09607 7/48 AN1943 AN1943 - APPLICATION NOTE The 8032 outputs a repetitive PWM pulse train with a slowly varying pulse width to an RC network which converts the pulse train into a slowly sweeping DC voltage (0V to 3.3V). This DC signal is looped back into an ADC input. The 8032 will write the resulting HEX ADC conversion value to the LCD so you can watch the results. The RC network and loopback is implemented with two jumper blocks (JP13 and JP14) on the DK3300 DK3300 board. Additionally and independently, a 4-bit, auto-reloading down-counter is created using PLD MicroCells. The 8032 directly loads the initial count value into four MicroCells, and that count is automatically loaded into another four MicroCells that create the 4-bit down-counter. Reloading occurs each time the counter reaches terminal count of zero. Terminal count is indicated externally by a pulse on a Turbo µPSD output pin. The down-counter is clocked by ALE signal (ALE was random choice, could be any signal). The 8032 may load a different initial count at anytime, creating a variable divider of the ALE signal. The LCD module is connected to the Turbo µPSD via a Port A for data and Port B for some glue logic and a chip-select signal. Port A is operating is an special data bus repeater mode this example, called Peripheral I/O mode. 8032 data will pass through Port A only for a given address range specified in PSDsoft Express (see Figure 5). Figure 5. Design Example Memory Map Code Space (_PSEN) Page X Data Space (_RD and _WR) Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 FFFF FFFF fs0 32K bytes uPSD (data) Main Flash fs1 fs2 32K bytes 32K bytes uPSD uPSD (data) (data) Main Flash Main Flash fs3 fs4 32K bytes 32K bytes uPSD uPSD (data) (data) Main Flash Main Flash fs5 fs6 32K bytes 32K bytes uPSD uPSD (data) (data) Main Flash Main Flash fs7 32K bytes uPSD (data) Main Flash nothing mapped 8000 6200-7FFF 6200-7FFF 6100-61FF 6100-61FF nothing mapped LCD _e and psel CSIOP 4000 3FFF 2000 1FFF 0000 csboot1 8K bytes uPSD Secondary Flash csboot0 8K bytes uPSD Secondary Flash rs0 chip select and data bus repeater for LCD control regs for Ports A, B, C, and D (xdata) 8K PSD SRAM (xdata) Common Memory Across All Data Pages 6000-60FF 6000-60FF 4000-5FFF 4000-5FFF nothing mapped 8032 SFRs and idata SRAM 0100-3FFF 0100-3FFF 0000-00FF 0000-00FF AI09608 AI09608 8/48 AN1943 AN1943 - APPLICATION NOTE The memory map in Figure 5., page 8 shows that in this design example, 16K byte secondary flash memory is used for code space, and the 256K byte main flash memory is used for data space, banked over eight pages. The nomenclature fsx, csbootx, rs0, csiop, and psel in Figure 5 refer to the individual internal Turbo µPSD memory segments. The Turbo µPSD main flash memory has a total of eight 32-Kbyte segments (fs0.fs7). The Turbo µPSD secondary flash memory has a total of four 8-Kbyte segments (csboot0csboot3), although only csboot0 and csboot1 are used in this design example. The Turbo µPSD 8-Kbyte SRAM has a single segment (rs0). A group of µPSD control registers which control I/O ports A, B, C, and D lie in a 256-byte xdata address space whose base address is named csiop. The Turbo µPSD has a data bus repeater feature that is enabled over a given address range as specified by psel. Figure 5 also shows one external memory select signal, LCD_e, for the LCD module. This memory map is specified using the software tool PSDsoft Express. Each memory segment can be placed at virtually any address, which provides an infinite number of mapping schemes. This is just one example. We will keep things simple for this particular application note, meaning the 8032 will "boot" and run code contained completely within the 16-Kbyte secondary flash in code space and we will treat the 256-Kbyte main flash as data only. However, this memory map may grow with the needs of your project. For example, if a large flash memory is needed for code space and IAP is required, a slight variation of the map in Figure 5 can accomplish this. The 8032 can boot from secondary flash (secondary flash resides in code space from 0-3FFF as in Figure 5), then the 8032 can calculate a checksum on the main flash and then program the main flash if necessary (main flash memory resides in data space from 8000-FFFF 8000-FFFF on eight pages as in Figure 5). After the contents of main flash are verified, the 8032 can write to special register, called the VM Register within the csiop register block, to "reclassify" the main flash memory from data space to code space. After which, the 8032 will have access to 256 Kbytes of flash for code in code space, paged across eight code pages in upper memory (8000-FFFF 8000-FFFF), and the 8032 will have access to 32 Kbytes of flash for code in code space common to all pages in lower memory (0-3FFF). At that point no flash memory will reside in data space. Upon reset, the memory map is reset to look like Figure 5 again. The VM Register can be accessed by the 8032 at runtime to perform a variety of manipulations. PSDsoft is used to set the initial value of the VM Register upon power-up. Future Application notes will illustrate various memory schemes. 9/48 AN1943 AN1943 - APPLICATION NOTE ENTERING DESIGN IN PSDsoft EXPRESS Highlights of the design process will be given here. The steps are simple and navigation though PSDsoft Express is easy. Invoke PSDsoft Express and follow along if you wish and also consult the DK3300 DK3300 User's Guide for more information. PSDsoft Express is free, and you will need to download and install the latest version (8.0 or later) from our website at www.st.com/psd, then look for "Software Downloads." Invoke PSDsoft Express and Create Project: 1. Start PSDsoft Express. 2. Create a new project. 3. Select your project folder and name the project (in this example, name the project "DK3300 DK3300_1" in the folder PSDexpress\my_project). Select MCU and Initial Placement of Flash in Code Space or Data Space 1. Select an MCU. In this case it is STMicroelectronics, then uPSD33xx uPSD33xx, then uPSD3334D uPSD3334D. 2. Select the main flash memory to reside in 8032 data space at power-up (means that the 8032 _RD and _WR signals are routed to the main flash array). 3. Select the secondary flash to reside in 8032 code space at power-up (means that the 8032 _PSEN signal is routed to the secondary flash array). Figure 6., page 11 shows what the screen should look like after you've made the selections. 4. Click OK. Now you will be asked if you want to use the Design Assistant, Extended Design Assistant, or Example Template. Choose Example Template. This is a predefined design that matches this application note and it runs on the DK3300 DK3300 board. 5. Choose the template for the DK3300 DK3300 Kit when prompted. Note: At runtime, the 8032 can alter the initial settings of code and data space by writing to the VM Register. 10/48 AN1943 AN1943 - APPLICATION NOTE Figure 6. MCU Selection 11/48 AN1943 AN1943 - APPLICATION NOTE Pin Definitions You will see the Pin Definitions screen appear. 1. Click through the pins and see how they are configured and how they relate to Figure 4. You will notice that you cannot change the definition of some pins because they have a fixed function. A comment about JTAG pins: This example uses 6-pin JTAG which is up to 30% faster than the default standard 4-pin JTAG. The two extra pins in the 6-pin JTAG configuration are _TSTAT and _TERR. 2. Click "Next" to move on to the Design Assistant for memory mapping and logic equations. You will see the Page Register definition screen. Figure 7. Pin Definitions 12/48 AN1943 AN1943 - APPLICATION NOTE Memory Map Defining the memory map requires defining the address range of chip-selects for individual memory elements of the Turbo µPSD (memory external to the 8032 core). Definition of the use of the Turbo µPSD Page Register is also required. Four memory blocks (Main flash, Secondary flash, SRAM, and Control Registers) external to the 8032 core are available and are individually selected segment-by-segment when 8032 addresses are presented to the Decode PLD (DPLD). Each of these memory segments has its own chip-select name (fs3, csboot1, rs0, csiop, and so forth). Equations for these chip-selects, and for any external chip-selects, must be specified using PSDsoft Express. For this example, chip-selects are defined to match the memory map of Figure 5. Page Register Since eight memory pages (or banks) are needed as shown in Figure 5, three paging bits (23 = 8) are specified as shown in Figure 8. Paging bits may be used for other types of memory manipulation (such as memory swapping), but that will be discussed in other application notes. Click "Next" to move on to the Chip Select Definition Screen. Figure 8. Page Register Definition 13/48 AN1943 AN1943 - APPLICATION NOTE Chip-Select Equations Now you will see the Chip-Select definition screen. 1. Click the chip-select signal rs0 for the 8-Kbyte xdata SRAM 2. Make sure that its definition matches the memory map in Figure 5. Note: No page number is specified for rs0 since the SRAM is common to all pages (page independent). Additional signal qualifiers (8032 control signals _rd, _wr, _psen, and ale) are NOT needed for internal µPSD chip-selects as this is taken care of in silicon. The SRAM always defaults to 8032 data space. At any time, you may click the "View" button to see how you are doing, and a summary will appear. 3. Click on the chip-select csiop (Chip Select I/O Port). This is a band of 256 xdata registers used to control Turbo µPSD Ports A, B, C, D, the Page Register, power management, and other functions. 40 of the 256 registers are used (see the complete Turbo µPSD datasheet for register definitions and their address offset from the csiop base address). There is no need to specify additional signal qualifiers for csiop, and it is not allowed to place csiop on a particular memory page. 4. Click on fs0. fs0 . fs7, which are chip-selects for the eight 32-Kbyte segments of Turbo µPSD Main flash (see Figure 9). Note: The page number is 0 for fs0, and the address range is 8000 - FFFF as shown in memory map of Figure 5. Figure 9. Chip-Select Definition for 8K byte SRAM 14/48 AN1943 AN1943 - APPLICATION NOTE 5. Click on remaining chip-selects for main flash Note: No additional qualifiers are needed for the page number assignments. 6. Click on csboot0. csboot0 . csboot3, which are chip-selects for the four 8-Kbyte segments of Turbo µPSD secondary flash memory (see Figure 10). 7. Check the address assignments for each of these chip-selects. Note: There are no page numbers assigned; the secondary flash is common to all pages. 8. Click on psel0. This address range specifies when Port A pins will behave like a data bus repeater in Peripheral I/O Mode to drive the LCD module. Port A pins were earlier specified a "Peripheral I/O Mode" which acts like a `245 bus transceiver chip connecting the 8032 data bus to external peripherals over a given address range specified by the label psel0 or psel1. The direction of this transceiver function is controlled automatically in silicon by the 8032 _rd and _wr signals (see the full µPSD datasheet for details). All we have to do is click on psel0 and enter the address range 6100 to 61FF to enable this feature for that address range as shown in Figure 5, with no Page Number assignment. psel1 is not needed because the Peripheral I/O feature is active for the logical OR of psel0 or psel1. 9. Click on LCD_e. This is an external chip-select for the LCD module. Since this is an external chipselect, we must include signal qualifiers _rd and _wr. In this design, LCD_e is true (active-high) only when the 8032 presents an address in the range of 6100 to 61FF AND when either 8032 control signal _rd is true, OR when 8032 control signal _wr is true. To create this logic, information is entered as shown in Figure 11., page 16. Since both signals _rd and _wr are active-low, the logical NOT operator (!) is used when they are specified as qualifiers. Note: Signal qualifiers may be added by setting the cursor where you want the signal name to go, then just double-clicking on the signal name in the list of eligible qualifiers. 10. Click "Next" to move on to Logic Definitions. Figure 10. Chip-Select Definition for Flash Memory Segments 15/48 AN1943 AN1943 - APPLICATION NOTE Figure 11. External Chip-Select Definition for LCD Module 16/48 AN1943 AN1943 - APPLICATION NOTE I/O Logic Equations Defined here are equations for PLD outputs for the LCD interface signals. The Design Assistant (DA) will create HDL logic statements using the ABEL language in the background after you enter logic in this pointand-click design entry environment. The DA will also create all the declaration statements in ABEL. This saves much typing and reduces the chance of error. For more complicated logic PSDsoft allows you to edit the ABEL statements directly. 1. Click on "LCD_rw" as shown in Figure 12. Note: The internal signal a0 is assigned to drive the output signal "LCD_rw". Although this was a very simple logic equation, AND, OR, XOR, NOT, and other logic operators are also available for general purpose logic. 2. Click through the remaining signal names and observe the logic assigned. Note: There is no logic equation assigned to term_count because that assignment will be made by editing the ABEL file directly. 3. Click "Next" to move on to User-Defined Node Equations. Figure 12. Logic Equation for Signal LCD_rw 17/48 AN1943 AN1943 - APPLICATION NOTE User-Defined Node Equations Here you will see how internal logic nodes are created. In this example, there are four registers (or nodes) to hold the initial count of the 4-bit down-counter, and four additional registers to create the actual 4-bit down-counter (see Figure 13). These nodes were created by: 1. Clicking the "Def Node." button; 2. naming the node; and 3. selecting the type node (e.g., combinatorial, D-register, J-K register). In this example, all eight nodes are D-register type. When a register is created, you can specify its source of Input, Clock, Reset (see Figure 13). Once the nodes are created: 1. Click though the signal names and look at the assignments. Notes: There are no definitions for inputs on any of the eight nodes. For the down_count nodes, the inputs are defined elsewhere (the ABEL file). For the init_count nodes, no logic input (or clock input) is specified because the 8032 will load the nodes directly by writing to the appropriate Output MacroCell register that resides the band of 256 registers of csiop. It may seem odd to divide the design entry this way (some point-and-click entry and some direct ABEL file editing), but many declaration statements are automatically created in the background by the point-and-click entry. You will see that when it is time to enter ABEL equations for the down-counter, there is very little typing involved. 2. Click "Done." Now you will see the main PSDsoft flow diagram that will guide you through the remaining steps. Note: You may view a summary report at this time by pulling down the "Report" selection in the main menu bar at the top of the screen, then selecting "Design Assistant Summary." Your report will match the one in APPENDIX A. Figure 13. 4-bit Down-Counter with Automatic Reload of Initial Count 8032 data bus (initial count) 4-bit auto-reloading down-counter 8032 WRITEs to OMCs in control register space (csiop) to load initial count D3 AB3 D2 AB2 D1 AB1 4 nodes to hold initial count D0 AB0 term_count ALE AB7 OD 4 nodes to form counter 18/48 AB6 OC AB5 OB AB4 OA 1 PLD output defined for terminal count AI09609 AI09609 AN1943 AN1943 - APPLICATION NOTE Figure 14. D-Register Node Set PRE Input D Q Clock CLR Reset AI09610 AI09610 19/48 AN1943 AN1943 - APPLICATION NOTE Edit ABEL HDL Statements for PLD Design If your PSDsoft flow diagram does not include the block "Edit/Add Logic Statements" as shown in Figure 15: 1. Pull down the "Project" selection in the main menu bar at the top of the screen. 2. Select "Preference." 3. Click the box that says "Enable ABEL Editing Capability." 4. Click "OK." To see the "HDL Assistant" window: 1. Click the "Edit/Add Logic Statements" box. 2. Browse this box to see ABEL logic and syntax examples that you can cut and paste into future designs. 3. Close the HDL Assistant and you will see the ABEL HDL source file. All the declarations and logic equations generated from the Design Assistant are there, and should match APPENDIX B. Figure 15. Design Flow Diagram 20/48 AN1943 AN1943 - APPLICATION NOTE There are only two regions in the ABEL file in which you can type statements, otherwise the Design Assistant (DA) will overwrite what you have typed next time you get into the DA. The first safe region. For ABEL declarations and lies between the two statements: "// Begin user preserved declarations" and "// End user preserved declarations." The second safe region. For logic equations and lies between the two statements: "// Begin user preserved equations" and "// End user preserved equations." Scroll down to the declaration region in the ABEL file, which should look like the following: // Begin user preserved declarations (not affected by iterations of DA usage) = WSIPSD PROPERTY `DataBus_OMC D[7:4]:down_count[3:0] MCELLAB'; // This statement forces the alignment // of down_count bits [3.0] to the MCU data bus bit positions [7.4]. // If this WSIPSD PROPERTY statement was not present, then PSDsoft // would pick random MCU bit positions. The WSIPSD PROPERTY is needed // only if the MCU will read or write to MicroCells and only if a // particular MCU data bus position is required by the designer. WSIPSD PROPERTY `DataBus_OMC D[3:0]:init_count[3:0] MCELLAB'; // This statement forces the alignment // of init_count bits [3.0] to the MCU data bus bit positions [3.0]. DCOUNT = [down_count3.down_count0]; // 4-bit down counter INIT = [init_count3.init_count0];// 4-bit initial count from MCU //INIT = [0,1,0,0]; // End user preserved = declarations (not affected by iterations of DA usage) Note: The WSIPSD PROPERTY statements are needed whenever you want to dictate the placement of certain MicroCells of the PLD. If you do not enter any WSIPSD PROPERTY declarations statement, then the PSDsoft "fitter" process will place the MicroCells in random order. This is not a problem for most designs. However, in this example we want to load an initial count for the down-counter from the 8032 data bus so we must make sure the output MicroCells holding the initial count are in the correct bit order and the correct position in the bank of eight output MicroCells. The property statement: WSIPSD PROPERTY `DataBus_OMC D[7:4]:down_count[3:0] MCELLAB' forces the order of the bits of the down-counter and places them on the upper half of the 8032 data bus. The property statement: WSIPSD PROPERTY `DataBus_OMC D[3:0]:init_count[3:0] MCELLAB' forces the order of the bits of the initial count and places them on the lower half of the 8032 data bus. When the 8032 writes to the OMCAB register at address csiop+0x20, the lower four bits of the byte will get loaded into the initial count. There is also a OMCAB mask register at csiop+0x22 that is used to prevent the 8032 from disturbing the other bits in the OMCAB register while writing. If the PROPERTY statements above ended with MCELLBC instead of MCELLAB, then the other bank of eight output MicroCells would be used for the counter. See the complete µPSD datasheet and PSDsoft Express User's Guide for more details. 21/48 AN1943 AN1943 - APPLICATION NOTE The next declaration statements DCOUNT and INIT create a shorthand notation for use in the logic equations. Scroll down in the ABEL file to the logic equations until you see: // Begin user preserved = equations term_count = (DCOUNT = 0); // term_count true when count reaches zero when term_count then DCOUNT := INIT; else DCOUNT := DCOUNT - 1; // End user preserved = = (not affected by iterations of DA usage) // automatically reload counter with initial // value after a count of zero is reached // specify down count action equations (not affected by iterations of DA usage) These three statements define the down-counter and the PLD output that appears on pin PB0 (term_count). Note: Very little typing is needed to implement logic designs. The same approach is used to create state machines, shifters, and so forth. Close the ABEL file and you will see the PSDsoft flow diagram again. 22/48 AN1943 AN1943 - APPLICATION NOTE Additional µPSD Configuration Click the box "Additional PSD Configuration." This is where you can choose to set the security bit to prevent a device programmer from examining or copying the contents of the Turbo µPSD. The only way to defeat the security bit is to erase the entire Turbo µPSD, then it can be used again as a blank part. Note: You may also click through the other sheets on this screen to set the JTAG USERCODE value and set sector protection on individual µPSD Non-Volatile memory segments. (Just click "OK" for now.) C Code Generation All the projects are now available as zipped files on-line (see Figure 16). Please visit ST at www.st.com/ psd, then look for "Software Downloads." Figure 16. Coded Example Generation 23/48 AN1943 AN1943 - APPLICATION NOTE Fitting Design Click the next highlighted box in the design flow, "Fit Design to Silicon." PSDsoft will compile all the configuration selections and present a report (also available in APPENDIX C). The fitter report documents how pins are configured and how the programmable logic is allocated. It also shows how many programmable logic product terms are used, which is needed to estimate power consumption. Merging 8032 Firmware with µPSD Configuration Now that all Turbo µPSD pins and configuration settings have been defined, PSDsoft Express will create a single object file (*.obj) that is a composite of the 8032 firmware (*.hex) and the Turbo µPSD configuration. FlashLINK/R-LINK or third party programmer tools can use this object file to program a Turbo µPSD device. PSDsoft Express will create DK3300 DK3300_1.obj for this design example. During this merging process, PSDsoft Express will input firmware files from the 8032 compiler/linker in Srecord or Intel HEX format. It will map the content of these files into the physical memory segments of the Turbo µPSD according to the choices that were made in the `Chip Select Equations' screen. This mapping process translates the absolute system addresses inside 8032 firmware files into physical internal Turbo µPSD addresses that are used by a programmer device to program the Turbo µPSD. This address translation process is transparent. All you need to do is type (or browse) the file name that was generated from the 8032 linker into the appropriate boxes and PSDsoft Express does the rest. You can specify a single file name for more than one Turbo µPSD chip-select, or a different file name for each Turbo µPSD chipselect. It depends on how the 8032 linker has created the firmware file(s). For each Turbo µPSD chip-select in which you have specified a firmware file name, PSDsoft Express will extract firmware from that file only between the specified start and stop addresses, and ignore firmware outside of the start and stop addresses. Click on "Merge MCU Firmware" in the main flow diagram. You will see an information window pop up to remind you to be sure you have configured the firmware compiler and linker to support a paged memory mapping scheme. Select "OK" and you will see the screen shown in Figure 17., page 25. Step 1. In the left column are Turbo µPSD memory segment chip-selects (e.g., FS0, FS1). The next column shows the logic equations for selection of each Turbo µPSD memory segment. These equations reflect the choices that were made while defining Turbo µPSD internal chip-select equations in an earlier step. In the middle of the screen are hexadecimal start and stop addresses that PSDsoft Express has filled in, based on the chip-select equations. On the right are fields to enter (browse) the 8032 firmware files. To select a firmware file: 1. Select "Intel Hex Record" for 'Record Type' as shown in Figure 17. 2. Slide the bar on the right side all the way down to the bottom until you see CSBOOT0. 3. Use the 'Browse' button and select the firmware file for CSBOOT0, PSDexpress\Examples\DK3300 DK3300_1.hex. This is a small example program that exercises the PWM and ADC channels of the Turbo µPSD on the DK3300 DK3300 board, and this code fits completely within the 8Kbyte flash segment CSBOOT0. This specification places firmware in secondary Turbo µPSD flash memory segment csboot0. PSDsoft Express will extract any firmware that lies inside the file DK3300 DK3300_1.hex between MCU addresses 0000 and 1FFF and place it in Turbo µPSD memory segment csboot0. Step 2. Click OK to generate the composite object file, DK3300 DK3300_1.obj. 24/48 AN1943 AN1943 - APPLICATION NOTE Figure 17. Merging the Example Firmware 25/48 AN1943 AN1943 - APPLICATION NOTE JTAG Programming Selection of The Programming Tool (either FlashLINK OR R-LINK) is done in the HW setup window. 1. Click the "STMicroelectronics JTAG/ISP" box to program the Turbo µPSD. You will be asked how many JTAG devices are on the target circuit board. 2. Choose "Only One" to see the screen shown in Figure 18. This window enables you to perform JTAG-ISP operations and also offers a loop back test for your FlashLINK/R-LINK cable. If this is your first use, test your FlashLINK or R-LINK cable and PC parallel or USB port by clicking the 'HW Setup' button, then click 'LoopTest' button and follow the directions. To define your JTAG-ISP environment: 1. Connect the JTAG ribbon cable to the target system 2. Power-up the target system 3. Click 'Execute' on the JTAG screen. The Log window at the bottom of the JTAG screen shows the progress. Programming should just take a few seconds. Note: For this example project, PSDsoft Express should have filled in the folder and filename of the object file to program, the µPSD device, and the JTAG-ISP operation, as shown in Figure 18. For this design example, we have chosen to use the six JTAG-ISP pins so the screen should indicates a 6-pin JTAG is being used. There are optional choices available when the "Properties." button is clicked. One choice includes setting the state of all pins on port A, B, C, or D during JTAG-ISP operations (make them inputs or outputs). The default state of these pins is "input", which is fine for this design example. The other choice allows you to specify a USERCODE value to compare before any JTAG-ISP operation starts. This is typically used in a manufacturing environment (see on-screen description for details). 4. After JTAG-ISP operations are complete, click on the 'Save' button so that you can save the JTAG setup for this programming session to a file for later use. Note: You may restore the setup of a different previous session by clicking the 'Browse.' button. Figure 18. Programming with FlashLINK/R-LINK JTAG Cable 26/48 AN1943 AN1943 - APPLICATION NOTE WATCH IT RUN ON DK3300 DK3300 After JTAG programming completes in just a few seconds, you should see a message appear on the LCD: "PWM to ADC DEMO" You will see the HEX value of the ADC conversion sweep up and down between 0x000 and 0x3FF as the PWM pulse width changes. If you do not see the ADC value change, make sure there are two jumpers installed on the DK3300 DK3300 board. On JP13, install one jumper across the opposite row of pins next to the word "PWM0," and the other jumper, JP14, install one jumper across the opposite row of pins next to the word "ADC7." Remove the jumper next the word "ADC7" and watch the ADC value on the LCD drop to 000 hex. USING uVISION2 AND ULink JTAG DEBUGGER FROM KEIL SOFTWARE, INC. This next section will briefly highlight the features of the Keil uVision2 and ULink JTAG debugger. Keil's PK51 Professional Developers Kit Version 7.08a was used for this example. Please refer to Keil documentation for more detail. Loading a Keil uVision2 Project The file, "DK3300 DK3300_dsn_1.ZIP" is available, and contains all of the source and project files needed to build this design in Keil's uVision2. To get this file: 1. Click on the "Generate C Code" box on the PSDsoft flow diagram. 2. Chose the "Coded Examples" tab 3. Choose the selection for the DK3300 DK3300 board. 4. Specify the folder in which you want the ZIP file written. 5. Click "Generate." The ZIP file contains two folders, "DK3300 DK3300_c" and "DK3300 DK3300_p." DK3300 DK3300_c has all the Keil 8032 files, DK3300 DK3300_p has the PSDsoft Express project files for this application note. To invoke Keil uVision2: 1. Pull down the "Project" menu 2. Select "Open Project." 3. Open the uVision2 project that you just got from the ZIP file at .\Dk3300_c\DK3300 DK3300_1.Uv2. Everything should be ready to go. Building the Project and Programming the Turbo µPSD You can build the project for this application note and create a new Intel HEX-80 HEX-80 file, "DK3300 DK3300_1.hex:" 1. Invoke PSDsoft Express and open the project DK3300 DK3300_1. 2. Go to the "Merge MCU Firmware" section and use the scroll bar at the right hand side and scroll down until you see CSBOOT0. 3. Put your cursor under the File Name and use the "Browse." button to select the new HEX file from the folder where your DK3300 DK3300_1.hex was created. 4. Click the "OK" button. "DK3300 DK3300_1.OBJ," which contains your firmware as well as the Turbo µPSD's configurations, is created in your PSDsoft Express Project folder(.\DK3300 DK3300_p). You can now program the DK3300 DK3300 board with FlashLINK/R-LINK cable just as before. The LCD should display the PWM to ADC demo information. 27/48 AN1943 AN1943 - APPLICATION NOTE Running Keil's ULink - USB to JTAG Debugger The Turbo µPSD features a built-in JTAG debugger which can provide ICE (In-Circuit Emulator) like functions. Currently this debugger is only supported by Keil, it makes use of a USB to JTAG adapter called ULink. Our current PSD system architecture already makes use of this JTAG port to perform programming of the Flash and PLD using the FlashLINK/R-LINK cable. This same JTAG port can also be used for debugging the hardware in the Turbo Core. Note: Please unplug the FlashLINK/R-LINK cable, then plug-in the ULink cable to the JTAG connector. In order to use the JTAG debugger, the Keil environment must be configured first: 1. Start the Keil uVision tool as normal. 2. Click the "Options for Target" icon in the tools bar, as shown in Figure 19. 3. In the Options for Target system dialog menu, select the "Debug" option. Please select Use "ST uPSD ULink Driver" as shown in Figure 20., page 29. 4. Click the "Settings" button next to the ST-uPSD ULink Driver, you should have the target setup as shown in Figure 20. If you are using Keil's software version 7.07A or earlier, please clear all the boxes under "Cache Options" and "Misc. Options." However, if version 7.07B or later is used, you should have these options enabled to improve the speed. Note: The Turbo µPSD programming functions can also be setup in this menu (see Figure 21., page 29). Under the PSDsoft Project Files, make sure to specify the correct path which points to your PSDsoft Project's *.ini file so that Keil software can automatically merge the *.hex file with your Turbo µPSD's configurations setup to generate the final *.obj file. The *.obj file will be used to program your Turbo µPSD devce when you click the "Load" button in the tool's menu (see Figure 22). Figure 19. Setting up ULink JTAG Debugger 28/48 AN1943 AN1943 - APPLICATION NOTE Figure 20. Setting up ULink Target Options Figure 21. Setting up the ULink Target Options Figure 22. Tool Menu `Load' Button 29/48 AN1943 AN1943 - APPLICATION NOTE In this project, DK3300 DK3300_1.Uv2 has USB-JTAG Debugger already selected for the debugger tool; you just need to connected the ULink cable to your PC's USB port, then click the Debug icon in the toolbar to start the debugger. The screen should look like Figure 23 when the debugger is running successfully. Now you should be able to run your code and set break points, single-step, view 8032 internal registers and SFRs, view blocks of memory, etc. as you normally would using the Keil uVision ULink. Note: A maximum of 4 break points can be set at any point in time. Figure 23. Keil's ULink JTAG Debugger After Successfully Invoked 30/48 AN1943 AN1943 - APPLICATION NOTE CONCLUSION Congratulations! You have seen the majority of steps to implement a Turbo µPSD design on the DK3300 DK3300 board. This design guide showed the basic steps to pre-configure the memories with PSDsoft, compile, program in Flash and debug with the Keil debugger suite. You still need to review the relevant documentation in this CD-ROM about the µPSD Turbo architecture and the additional documentation from Keil Software Inc. You may also use the new debugger environment from Raisonance, S.A, which comes with its own C Compiler and high-level language debugger (RIDE). This tool chain is provided on a separate CD-ROM. REVISION HISTORY Table 1. Document Revision History Date Rev. # 04-May-2004 1.0 Revision Details First Issue 31/48 AN1943 AN1943 - APPLICATION NOTE APPENDIX A. PSDsoft EXPRESS PROJECT SUMMARY FILE, DK3300 DK3300_1.SUM * PSDsoft Express Version 8.00 Summary of Design Assistant * PROJECT : dk3300_1 DATE : 09/17/2003 DEVICE : uPSD3334D uPSD3334D TIME : 09:22:47 MCU/DSP : uPSD33XX uPSD33XX * Initial setting for Program and Data Space: = Main PSD flash memory will reside in this space at power-up: Only Data Space Secondary PSD flash memory will reside in this space at power-up: Program Space Only Pin Definitions: = Pin Signal Pin Name Name Type - - -pa7 pa7 Peripheral I/O mode pa6 pa6 Peripheral I/O mode pa5 pa5 Peripheral I/O mode pa4 pa4 Peripheral I/O mode pa3 pa3 Peripheral I/O mode pa2 pa2 Peripheral I/O mode pa1 pa1 Peripheral I/O mode pa0 pa0 Peripheral I/O mode pb7 LCD_e External chip select - Active Hi pb6 LCD_a1 Combinatorial pb5 LCD_a0 Combinatorial pb4 term_count Combinatorial tdo tdo Dedicated JTAG - TDO tdi tdi Dedicated JTAG - TDI pc4 _terr Dedicated JTAG - /TERR pc3 tstat Dedicated JTAG - TSTAT tck tck Dedicated JTAG - TCK tms tms Dedicated JTAG - TMS 32/48 AN1943 AN1943 - APPLICATION NOTE ale ale ALE output _psen _psen Bus control output _rd _rd Bus control output _wr _wr Bus control output p4.0 PWM0 GP I/O mode p3.1 UART0_TxD UART0 TxD p3.0 UART0_RxD UART0 RxD p1.7 ADC_Ch7 ADC channel7 input a11 a11 Address line a10 a10 Address line a9 a9 Address line a8 a8 Address line ad7 a7 Data/Address line ad6 a6 Data/Address line ad5 a5 Data/Address line ad4 a4 Data/Address line ad3 a3 Data/Address line ad2 a2 Data/Address line ad1 a1 Data/Address line ad0 a0 Data/Address line debug JTAG_debug_pin JTAG debug pin Xtal1 Xtal1 Xtal1 Xtal2 Xtal2 Xtal2 _Reset_In _Reset_In Reset In Vref VREF VREF input User defined nodes: = Node Node Name Type - -init_count0 D-type register init_count1 D-type register init_count2 D-type register init_count3 D-type register down_count0 D-type register down_count1 D-type register down_count2 D-type register down_count3 D-type register 33/48 AN1943 AN1943 - APPLICATION NOTE Page Register settings: = pgr0 is used for paging pgr1 is used for paging pgr2 is used for paging pgr3 is not used pgr4 is not used pgr5 is not used pgr6 is not used pgr7 is not used Equations: = rs0 = (address >= ^h4000) & (address = ^h6000) & (address = ^h8000) & (address = ^h8000) & (address = ^h8000) & (address = ^h8000) & (address = ^h8000) & (address = ^h8000) & (address = ^h8000) & (address = ^h8000) & (address = ^h0000) & (address = ^h2000) & (address = ^h6100) & (address = ^h6100) & (address = ^h6100) & (address