AN1317 1N4007 BYT01-400V BZX55C15V 1N4148 BZX55C10V - Datasheet Archive
AN1317 - APPLICATION NOTE NON ISOLATED POWER SUPPLIES IN BUCK AND INVERTER CONFIGURATION USING VIPer20 DEVICE A. Bailly - S.
® AN1317 AN1317 - APPLICATION NOTE NON ISOLATED POWER SUPPLIES IN BUCK AND INVERTER CONFIGURATION USING VIPer20 DEVICE A. Bailly - S. Luciano INTRODUCTION The VIPer20 is a full integrated switching device. It replaces the conventional PWM driver circuit, its associated high voltage Power MOSFET switch and a full set of other passive components, and provide a high level of performance thanks to its current mode structure and standby operation capability. 1. SCOPE The VIPer20 is initially designed to be used at the primary side of any off line power supplies in isolated flyback configuration but it is also the right solution for different types of not isolated power supplies applications where low power (1W to 5W), wide input voltage range and low prices are required. In this case, a simple two pins inductor can replace an expensive safety transformer. The basic principle of this type of supplies is to convert a high voltage source to a low voltage one by the only way of the switching frequency and duty cycle management. The applications like home appliances (microwave oven, washing machine, triac drivers.), industrial applications (motors control,.) do not require galvanic isolation between the mains lines and the low voltage load, especially when one of the low voltage outputs must be connected to one of the mains lines. All these applications will take benefits from VIPer20 features: · Full integrated PWM start up current source and high voltage Power MOSFET, allow to build simple, robust, cost effective and compact power supplies. · Built in overtemperature and overcurrent protection provide a safe control in overload conditions. This application note gives all the elements to enable the designer to start the development of his own non isolated power supply using the VIPer20. It defines the key components, and highlights the differences between the Buck and the Inverter (also called Buck-Boost) topologies. 2. NOT ISOLATED TOPOLOGIES 2.1 VIPer20 In Buck Topology The basic schematic of a VIPer20 in Buck topology delivering 2W typical, with a fixed output voltage, is given fig. 1. The Buck structure is composed here by the on chip Power MOSFET, the inductor L1, the free wheeling diode D3, the output filtering capacitor C5 and the output load itself. In this topology, the VIPer20 switching duty cycle is very low (a few percent) because of the very high difference between the input and the output voltages. Its value would be at the maximum equal to the voltages ratio, when in continuous mode and even less in discontinuous mode. If the switching frequency is too high, the Power MOSFET conduction time will decrease accordingly, which may result in early burst mode operation if lower than the minimum turn on time of the device. In practice, the chosen January 2001 1/23 AN1317 AN1317 - APPLICATION NOTE switching frequency will be comprised between 20 kHz and 30 kHz, just above audible values. During the start up phase, the VIPer20 is in standby mode and its on chip high voltage current source sources a current on the VDD pin until the voltage across the capacitor C2 reaches the VDDon threshold. Then, this current source is turned off and the device starts switching. After a transition phase during which the output voltage grows up, the VDD supply of the VIPer20 is provided by the capacitor C2 and finally, from the positive output through the diode D2 when the output voltage becomes higher than the current VDD value. Figure 1: 2W typical single output not isolated power supply with Buck topology D1 AC IN 1N4007 1N4007 D2 BYT01-400V BYT01-400V R1 10k VDD OSC 13V C2 10uF 16V DRAIN + COMP SOURCE VIPer20 C1 22uF 400V R2 3.9k C3 10nF C4 100nF L1 +13V 470uH D3 BYT01-400V BYT01-400V AC IN C5 33uF 16V DZ1 BZX55C15V BZX55C15V GND OUT In normal operation, the output voltage regulation is achieved by the VIPer20 error amplifier which accurately compares the VDD value to the internal 13V voltage reference. The forward voltage across the diode D2 is here partially compensated by the forward voltage across the diode D3. So, the output voltage and the on chip voltage reference values are equal, except for diode forward voltage differences due to different diodes current: It is generally higher in the free wheeling diode D3, resulting in a slightly lower output voltage. A typical characteristic of the Buck is that the inductor charge and discharge paths are exclusively done through the output load. It is a slight advantage in normal operation because the energy is transferred to the load during both turn on and turn off cycles, but in very low or no load conditions, it has two drawbacks: · The charge of the start up tank capacitor C2 is impossible, especially when the input voltage is slowly 2/23 AN1317 AN1317 - APPLICATION NOTE increased. If no protection is foreseen, it is possible to apply the input voltage directly on the output, with large overvoltages. · Once started, overvoltages may also occur at the output, mainly for low input voltage values. The root cause of the last phenomenon resides in the duty cycle increase at low input voltage, together with a low output load. Fig. 2 shows the drain current shape for two input voltages. The lower is the input voltage, and the higher is the turn on. As a consequence, the turn off phase during which the energy is sent to C2 through D2 is reduced, and the device is increasing its drain current to maintain a correct regulated voltage on the VDD pin at 13 V. If the load is not able to absorb the corresponding current during the on phase, overvoltage is resulting on the output. Figure 2: Drain current for two input voltages in low load conditions 50mA/Div - 10µs/Div Vin = 200V Iout = 5mA Vin = 50V Iout = 5mA Fig. 3 shows an extreme case where the phenomenon reaches its critical phase, with a continuous mode of operation. The following computation demonstrates the risk of overvoltage and/or overcurrent on the output. 3/23 AN1317 AN1317 - APPLICATION NOTE Figure 3: Switching cycle in continuous mode in low input voltage condition IDRAIN Ts tON Ts - ton IP I0 Charge Discharge t The average currents consumed by the VIPer20 IDD and the output current Iout can be expressed as: 1 IDD = - ( I P + I 0 ) ( T S t on ) 2 Ts and 1 I out = - ( I p + I 0 ) t on 2 Ts By using these two equations: I DD Iout = t on -Ts to n Finally, by introducing the duty cycle expression in continuous mode: V in to n d = - = -Ts V ou t The minimum output current mandatory to keep the output voltage under control is given by: V out I out = I DD -V in V out To prevent these disturbances resulting in possible output overvoltage or incorrect start up, a 15V zener diode DZ1 is added. It allows a current to flow at the output, insuring a correct start up and clamps any possible overvoltage. Nevertheless, as shown in the above last formula, the current flowing in this zener can be very high when the input voltage approaches the output one. Section 5 describes a schematic modification to overcome this issue. Fig. 4 presents the operation of the free wheeling diode in this condition: Actually it is always blocked, as the voltage on the cathode never becomes negative. Also on this figure, it can be observed that the voltage drop Vd across D3 is about 5V while the output voltage is at 15V. It means that VDD is about 10V 4/23 AN1317 AN1317 - APPLICATION NOTE because the input voltage is too low to insure a proper operation of the converter, which is about to shut down. Figure 4: Buck non isolated - VIPer20 source voltage with VIN = 47 V, IOUT=5 mA. DZ1 conducting Vd 2.2 VIPer20 In Inverter Topology The inverter schematic is derived from the Buck one of fig. 1 by just swapping the inductor L1 and the free wheeling diode D3. The resulting schematic is given fig. 5. There is a major difference with the Buck from a functional point of view : when the on chip Power MOSFET is turned on, the inductor L1 does not charge anymore through the load but between the mains lines. The output load now gets all its energy during the MOSFET off state, through the inductor L1 and the free wheeling diode D3. As a consequence, the zener diode DZ1 is no more necessary because of two reasons: · The charge of the tank capacitor C2, now independent from the load, is always possible. · Both VIPer20 supply (VDD pin) and output load are receiving energy form the inductor L1 at the same period of time. So, there is no possible difference between the VDD voltage and the output one, which is always under control. Compared to the Buck, the current flowing through the load is in the opposite direction so that the output voltage becomes now negative. As a consequence, the output capacitor C5 polarity must be swapped and the anode of the diode D2, supplying the VIPer20, must now be connected to the ground lead GND OUT to insure a correct positive supply to the VDD pin. 5/23 AN1317 AN1317 - APPLICATION NOTE Figure 5: 2W typical single output not isolated power supply with Inverter topology D1 AC IN D2 1N4007 1N4007 BYT01-400V BYT01-400V R1 10k VDD DRAIN OSC 13V + C2 10uF COMP SOURCE VIPer20 16V R2 3.9k C1 22uF 400V C3 10nF C4 100nF L1 470uH AC IN GND OUT D3 BYT01-400V BYT01-400V C5 33uF 16V -13V 3. DESIGN METHODOLOGY The schematic of either fig. 1 or fig. 5 can be separated into six blocks: · The oscillator network composed by R1 and C3. · The Buck or inverter structure, which is composed by the on chip MOSFET, the inductor L1, the free wheeling diode D3 and the output filtering capacitor C5. · The VIPer20 supply circuit, composed by D2 and C2. · The front rectifier and filter. · The error amplifier compensation network composed by R2 and C4. All these functions will be detailed in the next paragraphs. 3.1 Switching Frequency And Duty Cycle Sections 1 and 2 showed that the input voltage transformation is entirely managed by the VIPer20 which controls the switching duty cycle. Whatever the topology is, the goal is to look for the widest load regulation range, trying to reach the VIPer20 minimum turn on time (TONmin = 500 ns typ.) for the lowest output load. For maximum load, although the VIPer20 is perfectly compatible from the continuous mode, it must be avoided because the power dissipation in the free wheeling diode D3 would be too high and the inductor size and price would increase. For all the above reasons, these topologies are operated at 6/23 AN1317 AN1317 - APPLICATION NOTE low switching frequency and always in discontinuous mode. As an example, to get a 13V output voltage with a 265 Vrms input voltage, the maximum duty cycle V ou t d = - would be less than 5%. With a switching frequency of 100 kHz, the maximum conduction V in time would always be equal or lower than TONmin, leading to a permanent burst mode operation. In practice the switching frequency is chosen just above the audio ones, in the 20 kHz to 30 kHz range and the VIPer20 will work in discontinuous mode with a duty cycle of about 2% to 3% at high line and about 6% to 10% at low line. From the VIPer20 datasheet, the switching frequency is given here below: 2.3 550 F s = - 1 - R1 C3 R 1 150 On the schematic of fig. 1 and fig. 5, R1=10k and C3=10nF have been chosen to get a switching frequency near by 20 kHz (21.7 kHz typical). 3.2 Inductor In normal operation, for both topologies, the switching cycle consists of two phases. First, the Power MOSFET is switched on during ton, D3 is blocked, the inductor connected to the high voltage source stores the energy. Second, the Power MOSFET is switched off during tdis, the inductor restores its energy to the load through D3, and to the VDD pin through D2. As described in section 2, the load is supplied during ton and tdis with the Buck topology, and only during tdis with the inverter one. A typical switching cycle is shown on fig. 6. Knowing the output power, the switching frequency and the maximum VIPer20 peak current, L1 can be computed as follow: for the Buck: with d = t on F s 1 1 P out = - L 1 I 2 p Fs + - Ip V out d I DD V out 2 2 and t o n ( V in V out ) = L 1 I p V out 1 P ou t = - L 1 I 2 p F s 1 + - I DD V ou t 2 V in V out P o ut + I DD V out L 1 = 2 -V out 2 F 1 + - I p s V in V o ut 7/23 AN1317 AN1317 - APPLICATION NOTE Figure 6: Switching diagram in normal operation (discontinuous mode) IDRAIN Ts tDis tON t OFF IP Charge Discharge t for the Inverter: 1 P out = - L 1 I 2 p F s I DD V out 2 P out + IDD V out L 1 = 2 -I 2p F s In practice, with a less than 10% error, the VIPer20 consumption and also the power transferred to the load during the conduction time of the MOSFET for the Buck (Vin»Vout) can be neglected. In this case, the calculation becomes the same for both topologies: P out L 1 2 -I 2p F s For a 2W maximum output power, with Ip=IDpeak=0.5A min, Fs=20kHz, it gives L1l 800µH. The power delivered by these topologies is limited by the minimum VIPer20 current capability and by the I Dlim fact that continuous mode has to be avoided. The maximum output current is therefore about - . 2 It gives also a maximum inductance value, for a given frequency: V ou t L 1max -I Dlim Fs On fig. 9 and 11 of section 4, a 2 W typical output power can be obtained with an inductor value of 470 µH (IDlim=0.67A typical). 8/23 AN1317 AN1317 - APPLICATION NOTE 3.3 Output Capacitor The output capacitor C5 is an element linked with the desired output ripple amplitude Vout, which depends on the output voltage and on the application to supply. The worst case occurs for the maximum load, when the VIPer20 delivers its maximum peak current during the longer conduction time. The charge of the capacitor C5 is: Q5 = i dt = ( C 5 V out ) With the hypothesis that the VIPer20 is at the limit of the continuous mode, which is a worst case making easier the calculation of the current in the capacitor: i dt 1 T- I p 1 - s = - - - = - T s I p 2 2 2 8 1 - T 8 s Ip C 5 = -V o ut Example with Vout=100 mVpp, Fs=20 kHz, Ip=IDpeak=0.5 A min, C5l 31 µF Ip Ip The maximum peak current flowing through this capacitor is - during the charge and - during the 2 2 discharge. To avoid an excessive power dissipation in the capacitor and a high output ripple, the ESR of the output capacitor must be low. Table 1 gives a picture of the ESR impact, with Ip =0.7A typical. Table 1: Output ripple versus capacitor technology Capacitor Type Capacitor Value ESR at 100KHz IR at 100KHz Standard Electrolytic Electrolytic Solid Al Electrolytic OS-CON Electrolytic Low Z 33 µF / 16V 33 µF / 16V 33 µF / 16V 270 µF / 16V 7 700 m 50 m 120 m 90 mA 1460 mA 1580 mA 630 mA Output Ripple VR = Ip · ESR 4.9 V 490 mV 35 mV 84 mV The above example illustrates that the computed capacitor value has to be tuned according to the application needs, the capacitor technology and its associated cost. 3.4 VIPer20 Supply Circuit For both topologies, fig. 7 shows the three different mode: · The start up phase: The on chip high voltage current source is turned on. It sources a current out of the VDD pin in order to charge the tank capacitor C2 until the VDDon threshold is reached. This capacitor then supplies the VIPer20 during the following phase. 9/23 AN1317 AN1317 - APPLICATION NOTE · A transition phase: It takes place immediately after the previous one. The current source is turned off and the device starts switching. At the very beginning, the output voltage is lower than VDD one, the diode D2 is blocked, the VIPer20 is still supplied by C2. When the output voltage, increasing cycles after cycles, reaches VDDon, D2 conducts, supplying the VIPer20 from the output. Obviously, the value of C2 must be large enough to maintain the VDD voltage above the VDDoff threshold, before being supplied from the output. If it is not the case, the VIPer20 will loop into endless start up cycles. · The normal operation: The VDD pin is fully supplied by the low voltage output and regulated at 13 V. Figure 7: VIPer20 supply phases in Buck or Inverter topologies Vout VDD Start up phase Transition phase Normal operation VDDreg tss VDDon VDDoff tch t The calculation of the VDD tank capacitor C2 can be done as follow: The minimum start up time tss must be higher than the output capacitor C5 charging time t ch, which is function of the nominal output voltage and the average output current: C 5 V DDo ff t ss > t ch = -I outavg During the very first start up cycles, C5 is empty, the output voltage is more or less null and the VIPer20 delivers its maximum peak current IDlim during the Power MOSFET on state. Due to the low output voltage, the inductor L1 discharges very slowly (tdis»Ts) so that the switching is done in continuous mode. At that time, the average output current is almost equal to IDlim. 10/23 AN1317 AN1317 - APPLICATION NOTE While the output voltage grows up, the discontinuous mode is reached and the average output current becomes the half of the maximum peak current: t = 0 Iou tavg I Dlim The average output current for and 1 t = t ss Ioutavg - I 2 Dlim 0 t t ss can be approximate as: 3 I outavg - IDlim 4 At the beginning of the start up phase, the capacitor C2 is charged at VDDon, and it can supply the VDD pin down to VDDoff. So, tss can be expressed as: IDDo C 2 t ss = - , with V DDhyst = V DDon V DDoff V DDhyst So: -( C5 V out ) / ( 3 I Dlim ) I DD0 t ss 4 C2 = - > I DD0 -V DDhyst V DDhyst Finally: 4 C 5 V out C2 > I DD0 -3 IDlim V DDh yst With: Vout=13V, IDD0=16mA, Ip=IDlim=0.5A min, VDDhyst=2.4V, C5=33µF, C2>7.6 µF. 3.5 Front Rectifier And Filter As single wave rectification is chosen because it allows to have the output ground connected to one of the mains lines, as it is required in most of the non isolated applications. As the involved power is low, the input filtering can be achieved without huge bulk capacitor. Any usual rectification diode having a reverse voltage of 800 V will fit the needs. On the schematic of fig. 1 and 5, we used the part number 1N4007 1N4007. The energy stored in the bulk capacitor during the conduction time of the diode must be equal to the total power dissipated when the diode is blocked. P out P in Referring to fig. 8 and with the efficiency of the converter = - , it comes: 1 1 - C1 ( V 2 inpeak V 2 in low ) = ( t 2 t 1 ) P out - 2 The designer can easily choose Vinlow according to the input voltage range and the output ripple he can accept, knowing that a Vinlow reasonable value is 70% of Vinpeak. 11/23 AN1317 AN1317 - APPLICATION NOTE Figure 8: Single wave filtering Vin Ts Vinpeak VDC Vinlow t1 t t2 t2 and C1 can now be extracted as follow: Ts t2 V inlow V in low = V inp eak sin 2 - t 2 = - arc sin - + Ts T s 2 V inpeak 1 ( t 2 t 1 ) Pout - C 1 = 2 -2 2 ( V in peak V low ) , with Ts t 1 = -4 A wide range input voltage design, fitting both American and European standards, is considered: The minimum AC voltage is 85 Vrms, so Vinpeak=120V, 60 Hz. The designer needs a 2 W maximum output power and he chooses Vinlow=80% of Vinpeak. Knowing that the typical efficiency for this type of converter is about 70%, he gets C1=19.4µF. He will retain 22 µF which is the closest higher normalized value, with a voltage of 400 V to cover the whole range. 3.6 Compensation Network The R2 and C4 network connected on the COMP pin of the VIPer20 insures a correct stability of the converter. Note that both Buck and inverter topologies are working in discontinuous, and have a very similar dynamic behavior. So, the values indicated on the schematics are convenient for both topologies and in all load conditions. 12/23 AN1317 AN1317 - APPLICATION NOTE 4. MEASUREMENT RESULTS The following graphs show typical results using the schematics of fig. 1 and fig. 5. Unless specified, the measurements are done at ambient temperature. 4.1 Buck And Inverter Output Characteristics Figure 9: Typical output characteristic of the Buck topology Vout (V) 16 15 14 13 12 11 10 9 8 7 Vin = 300V Vin = 200V Vin = 100V 0 50 100 150 200 250 300 Iout (mA) Figure 10: Buck non isolated - Output voltage at low load and low input voltage Vout (V) 16 14 12 10 -100mA -30mA -5mA 0mA 8 6 20 30 40 50 Vin (V) 13/23 60 70 80 90 AN1317 AN1317 - APPLICATION NOTE Fig. 10 illustrates the Buck behavior in low load and low input voltage conditions, as described in section 2.1. The output voltage is clamped to 15V by the zener diode. At the opposite, as shown in fig. 11 and fig. 12, the output voltage regulation of the Inverter is much better whatever are the load and the input voltage. Figure 11: Typical output characteristic of the fig. 5 Inverter schematic -Vout (V) 14 Vin = 300V 13 Vin = 200V 12 Vin = 100V 11 10 9 8 7 0 50 100 150 200 250 300 -Iout (mA) Figure 12: Inverter non isolated - Output voltage versus load and input voltage -Vout (V) 15 10 -100mA -30mA -5mA 0mA 5 0 0 50 100 150 200 250 300 350 Vin (V) 14/23 AN1317 AN1317 - APPLICATION NOTE 4.2 Buck And Inverter Power Measurements Figure 13: Buck non isolated - Input power versus output power Pin (W) 4 3.5 3 2.5 2 1.5 1 Vin = 300V 0.5 Vin = 200V Vin = 100V 0 0 0.5 1 1.5 2 2.5 3 Pout (W) Figure 14: Inverter non isolated - Input power versus output power Pin(W) 3.5 3 2.5 2 1.5 Vin = 300V 1 Vin = 200V 0.5 Vin = 100V 0 0 15/23 0.5 1 1.5 Pout(W) 2 2.5 AN1317 AN1317 - APPLICATION NOTE Figure 15: Typical efficiency of a Buck non isolated Efficiency 80% 70% 60% 50% 40% 30% Vin = 300V Vin = 200V 20% 10% Vin = 100V 0% 0 50 100 150 200 250 300 Iout (mA) Figure 16: Typical efficiency of an non isolated inverter Efficiency 80% 70% 60% 50% 40% 30% Vin = 300V 20% Vin = 200V 10% Vin = 100V 0% 0 50 100 150 -Iout (mA) 200 250 300 4.3 Short Circuit Fig. 17 shows the inductor current when submitted to a short circuit on the output. It can be seen that this current exceeds the current limitation of the VIPer20 (It is about 3 A for a limitation of 0.67 A for the 16/23 AN1317 AN1317 - APPLICATION NOTE device). This situation is due to the fact that the minimum turn on of the device is not sufficiently short to keep the drain current under control, especially because the inductor is saturated. Figure 17: Buck non isolated - Inductor current in short circuit condition at Vin = 400 V Nevertheless, the device is protected against such events and can be connected directly across the front bulk capacitor charged at 400 V without any problem. This corresponds to the worst case of a saturated transformer, which is never reached practically. Would it happen, the resulting power dissipation would be limited by the thermal shutdown of the device. Figure 18: Buck non isolated - Short circuit output current at Vin = 400 V 17/23 AN1317 AN1317 - APPLICATION NOTE Fig. 18 represents the output short circuit current. Its duty cycle is about 27% for a peak value of 1.4 A. This results in an average current of 0.4 A which is perfectly compatible with the type of diodes generally used for rectifying the output. Actually, these types of converter can withstand the short circuit condition indefinitely. The temperature elevation of the components is quite moderate. 5. SCHEMATICS IMPROVEMENTS AND VARIANTS 5.1 Non Isolated Buck With Output Overvoltage Protection The inherent inconvenient of the Buck, already described in paragraph 2.1 and 4.1, is the output voltage increase, in low load and low input voltage conditions. On the initial schematic of fig. 1, the zener diode properly clamps the output voltage surges when a minimum load is guaranteed and if the input voltage rise and fall times between 20V to 50V typical, is short enough. Otherwise, the output voltage may rise such values that the power dissipation in DZ1 becomes very high, as shown on fig. 19. Figure 19: Buck non isolated - DZ1 power dissipation in short circuit Pz (mW) 600 500 400 300 200 100 0 20 40 60 80 100 120 Vin (v) The solution implemented on the schematic of fig. 20, allows to drastically improve the output voltage control, by reducing the nominal switching frequency if the input voltage decreases below a threshold. This frequency shifter consists of a diode D4 connected on the OSC pin of the VIPer20, and receiving a fraction of the input voltage through R3 and R4. When the input voltage becomes low, a current is sunk through D4 from the middle point of the oscillator network R1-C3, thus increasing the charging time of C3 and decreasing the switching frequency. The resistances R3 and R4 are chosen in such a way that the frequency begins to decrease at 100 Vdc of input bulk voltage, and stops completely the oscillator at 30 Vdc. Fig. 21 and 22 illustrates this behavior for two input voltages, and the final results is shown on fig. 23: Overvoltages still occur at low input voltage or at low output load conditions, but with a reasonable amount of power dissipated in the clamping zener diode. 18/23 AN1317 AN1317 - APPLICATION NOTE Figure 20: Buck non isolated with switching frequency shifter D1 AC IN 1N4007 1N4007 D2 BYT01-400V BYT01-400V R3 470k D4 R1 56k VDD DRAIN OSC C2 10uF 16V C1 22uF 400V 13V 1N4148 1N4148 + COMP SOURCE VIPer20 R2 3.9k R4 33k C3 2.2nF C4 100nF L1 +13V 470uH D3 BYT01-400V BYT01-400V AC IN Figure 21: Nominal oscillator frequency at Vin = 140V 19/23 C5 33uF 16V DZ1 BZX55C15V BZX55C15V GND OUT AN1317 AN1317 - APPLICATION NOTE Figure 22: Shifted oscillator frequency at Vin=70V Figure 23: Buck non isolated - Output voltage response with frequency shifter Vout (V) 16 14 12 10 -100mA -30mA -5mA 0mA 8 6 20 30 40 50 60 70 80 90 Vin (V) 20/23 AN1317 AN1317 - APPLICATION NOTE 5.2 Adjustable Output Voltage Structures On the schematics of fig. 1 and 5, the output voltage is fixed and equal to the reference voltage of the VIPer20, that is to say 13 V. When different voltages are needed, it is possible to modify these basic structures to get other values. Fig. 24 presents a +23V output non isolated Buck converter with a zener diode DZ2 in series with the VDD pin which imposes the output voltage to be 10 V higher than the reference of the VIPer20. As a results, the output voltage will be regulated at +23 V. The resistor R1, optionally added here on the line input, is an example of an inrush limiter and filter. When lower output voltages are specified, an another configuration can be used, as shown on fig. 25. An inductor with an intermediate tap is used in order to deliver a -5 V. This inductor can be of the same type than an inexpensive drum vertically mounted on a PCB, except that three pins are provided instead of two for a standard inductor. Figure 24: Buck non isolated - Output voltage increased R1 D1 AC IN 100 DZ2 1N4007 1N4007 D2 BZX55C10V BZX55C10V R2 10k VDD BYT01-400V BYT01-400V DRAIN OSC 13V C2 10uF 16V + COMP U1 VIPer20 C1 22uF 400V R3 3.9k SOURCE C6 2.2uF 35V C3 10nF C4 100nF L1 +23V 470uH D3 BYT01-400V BYT01-400V AC IN 21/23 C5 33uF 16V DZ1 BZX55CxxV GND OUT AN1317 AN1317 - APPLICATION NOTE Figure 25: Non isolated inverter - Reduced output voltage. D1 AC IN D2 1N4007 1N4007 BYT01-400V BYT01-400V R2 10k VDD DRAIN OSC 13V C2 10uF 16V + COMP SOURCE U1 VIPer20 C1 1uF 400V R3 3.9k C3 10nF C4 100nF L1 470uH AC IN GND OUT D3 BYT01-400V BYT01-400V C5 22uF 16V -xxV 6. CONCLUSION It has been demonstrated that the simple topologies as the Buck or the inverter can be used directly on off line applications to build efficient non isolated power supplies in the range of a few watts. A VIPer20 device can minimize the total number of components by offering the error amplifier, the PWM and the Power MOSFET together inside a single piece of silicon. A special care must be taken when designing the Buck topology, as it can provide serious output overvoltages in case of low input voltage, and/or low output load. A simple zener diode on the output, or a more efficient switching frequency shifter network can overcome this issue. The benefits of such low power structures over more conventional 50 Hz transformers followed by rectifiers, filters and serial regulators can be listed as follow: · Wide range of input voltages with good output regulation · Higher efficiency and lower standby consumption · Lighter weight, with direct implementation on a standard PCB 22/23 AN1317 AN1317 - APPLICATION NOTE Information furnished is believed to be accurate and reliable. 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