AN-655 /RS-232 RS-232C ADN2830 ADN8830 12-BIT AD8628 ADR291 AD8565 FLD5F15CA

APPLICATION NOTE One Technology Way · P.O. Box 9106 · Norwood, MA 02062-9106 · Tel: 781/329-4700 ·

AN-655 AN-655 APPLICATION NOTE One Technology Way · P.O. Box 9106 · Norwood, MA 02062-9106 · Tel: 781/329-4700 · Fax: 781/326-8703 · www.analog.com Tunable Laser Reference Design for Designers with the ADuC832/ADN8830/ADN2830 by Nobuhiro Matsuzoe FEATURES Single Board Solution for Tunable Lasers 8-Channel Selectable Wavelength Control Wavelength Locking at 25 GHz/50 GHz Spacing AutoPower Control (APC) AutoTemperature Control (ATC) AutoFrequency Control (AFC) Laser Bias, Temperature Monitoring EEPROM-Based Autorestoring Serial Interfaces (SPI®/I2C®/RS-232 /RS-232) to Host System Wavelength Stability < 2 pm (typ) LD Temperature Stability < 0.01°C APPLICATIONS DWDM Transmission System Optical Instrumentation GENERAL DESCRIPTION This tunable laser reference design offers a single board solution with complete control requirements for DFB tunable laser subsystems. Designed to work from +3 V/5 V power supplies, it provides a low cost, low power tunable laser solution designed for ease of use with standard serial control interfaces. A mixed-signal monolithic microprocessor, the ADuC832based wave locker feedback loop is designed to meet the requirements of ITU-T grid spacing in a 50 GHz/25 GHz system. An integrated 12-bit ADC with an 8-channel multiplexer allows users to monitor laser bias current and laser temperature via SPI, I2C, or RS-232C RS-232C serial interfaces. The ADN2830 ADN2830 laser bias controller can sink up to 200 mA (single)/400 mA (dual) and its integrated feedback control loop can maintain output optical power constant over temperature changes during wave locking. The ADN8830 ADN8830 TEC controller enables excellent laser temperature stability and precise wavelength control with 1 pm resolution. A patented PWM/linear based TEC drive architecture enables high efficiency and minimizes external filtering components. FUNCTIONAL BLOCK DIAGRAM MUX MICROCONVERTER GPIO 12-BIT 12-BIT DAC i8051 12-BIT 12-BIT DAC AUTO-ZERO OP AMP AD8628 AD8628 ADuC832 AUTO-ZERO OP AMP TEC CONTROLLER 2.5V REFERENCE ADN8830 ADN8830 AD8628 AD8628 ADR291 ADR291 TEC ETALON FILTER WAVELENGTH MONITOR PD POWER MONITOR PD AD8565 AD8565 REV. B 12-BIT 12-BIT SER ADC T/H THERMISTOR CW LASER 8 TUNABLE LASER CW LASER AVERAGE POWER CONTROLLER ADN2830 ADN2830 AN-655 AN-655 TURNABLE LASER MODULE THERMISTOR TEC WAVE LOCKER POWER MONITOR LASER DIODE MODULATOR CONTINUOUS OPTICAL OUT TEC CONTROLLER ADN8830 ADN8830 I/V AD8628 AD8628 DIGITAL I/O MICROPROCESSOR SERIAL PORT MODULATED OPTICAL OUT TRANSMIT DATA LASER CONTROLLER ADN2830 ADN2830 ANALOG I/O 2 2 I2C LINK TO HOST MICROCONVERTER ADuC832 Figure 1. Typical Block Diagram of Optical Transmitter with DFB Laser Module Free Spectral Range (FSR) cycle FS, is precalibrated by the manufacturer to align with the ITU grid spacing as shown in Figure 2b. Because the monitor signal has periodic cycles, the algorithm of wavelength locking requires two different tuning methods, coarse tuning, and fine tuning. During the first phase, the laser temperature must settle to the particular temperature corresponding to the target wavelength, where the wavelength is assumed within the capture range. In the case of Figure 2b, there are two locking points on both slopes, positive slope and negative slope, within a single FSR. Thus, the capture range must be half of the SFR. Feedforward control with a look-up table is used in this coarse tuning phase. After the wavelength settles within the capture range, the fine tuning phase acquires the wave length errors between the target wavelength and actual wavelength by monitoring the wave locker signal. Then the wavelength errors will be fed back to the temperature control circuit. The fine tuning phase maintains the wavelength within an allowable wavelength deviation range over ambient temperature changes. The ITU-T recommendation specifies wavelength stability as a frequency deviation in G.692. This deviation is defined as the difference between the nominal central frequency and the actual central frequency (Figure 2c). A maximum frequency deviation is given by WAVELENGTH TUNING Because an optical transmitter requires a small formfactor design, use of the refractive index of a semiconductor laser is commonly used to alter the wavelength. As the refractive index can be changed by both the temperature and the density of carriers, transmitter designers can choose from two different types of the wavelength-tunable laser modules-distributed feedback (DFB) lasers and distributed Bragg reflector (DBR) lasers. In general, the DBR laser is capable of a fast tuning speed and a wide tuning range. However, it requires multiple programmable current sources for wavelength control, which results in a complex system design. In contrast, the DFB lasers can be controlled by temperature of the laser chip, which results in a lower system cost and higher reliability since the DFB lasers are widely used today. The wavelength of the DFB laser is related to temperature with a typical temperature coefficient of 0.1 nm/K. By using a thermoelectric cooler (TEC) and a thermistor with a built-in module, the laser chip temperature can be adjusted, thus wavelength is controlled. Figure 1 shows a simplified block diagram of an optical transmitter designed with the DFB laser. The wavelength tuning range of the DFB laser is limited by an allowable operating temperature range. In fact, DFB lasers provide a tuning range of a couple of nanometers which is equivalent to 8 to 16 ITU-T grid channels depending on the channel-to-channel spacing of the wavelength. f < (FS 2.0B ) /4 where: FS is the frequency slot WAVELENGTH LOCKING The internal or external wavelength locker generates two monitor signals corresponding to the wavelength and optical output power respectively. The wavelength locker consists of the wavelength selective element and the photodetector diode as shown in Figure 2a. The builtin Fabry Perot etalon works as a wavelength filter which has a periodic characteristic similar to a comb filter. The peak-to-peak range of the etalon filter, referred to as the B is the bit rate. In 10 Gbps transmit applications with 50 GHz Grid spacing, the frequency deviation f must be less than 7.5 GHz which means wavelength deviation must be less than 67 pm. The test result of the wavelength deviation taken by the reference design is shown in Figure 2d. 2 REV. B AN-655 AN-655 OPTICAL INPUT POWER MPD TO µC I/V ETALON FILTER I/V TO µC DEMONSTRATION BOARD The tunable laser reference design board (demo board) demonstrates autopower control (APC), autotemperature control (ATC) and autofrequency control (AFC). Figure 3 shows simplified setup of the demo board. The demo board has a mount space for a tunable DFB laser module in a 14-lead butterfly package. The demo board also provides a power supply terminal, analog I/O ports, and a serial port. To mount laser modules, a power photodetector must be floating within the laser module package as seen in Figure 4. OPTICAL OUTPUT WAVELENGTH MPD WAVELENGTH LOCKER COMPUTER Figure 2a. Wavelength Locker Block Diagram POWER SUPPLY (+5V/5V) RS-232C RS-232C CABLE WAVELENGTH MONITOR PD MONITOR CURRENT (A) LOCK POINT POWER MONITOR PD FSR WAVELENGTH (nm) LASER MODULE Figure 2b. Wavelength Locker Characteristics FC-APC (PANDA FIBER) WAVELENGTH METER OPTICAL POWER (dB) TUNABLE RANGE = 3nm FS F Figure 3. Demo Board Setup 6 7 5 4 3 2 1 WAVELENGTH (THz) TEC Figure 2c. Frequency Slots and Allowable Frequency Deviation RTH PD1 PD2 8 9 10 11 12 13 14 Figure 4. Laser Module Pin Assignment (reference: Fujitsu Quantum Devices, FLD5F6CA Data Sheet) NOTES 1. 1-HOUR WAVELENGTH STABILITY AT 25C, WAVE LOCKER ENABLED, 2 SEC INTERVAL. 2. F: LOCK POINT 1.5pm MAX TO MIN: 3pm. 3. LASER: FLD5F15CA FLD5F15CA, FUJITSU QUANTUM DEVICES LTD. 4. THE WAVELENGTH STABILITY IS MEASURED IN 3pm ACCURACY. 5. AFC STABILITY IS AFFECTED BY ACCUMULATIVE ERRORS OF APC AND ATC CONTROL LOOP. Figure 2d. AFC Typical Performance REV. B 3 AN-655 AN-655 GETTING STARTED To ensure proper operation, follow the steps below. 1) Calculate the target voltages of the wavelength lock point according to the following equation: [ ] VLOCKPOINT = VREF (R 46 × Im2 ) V where: [ ] [ ] VREF = 2.50 V R 46 = 2490 The photo current Im2 needs to be solved at each lock point, because the Im2 may differ from lock point to lock point, laser to laser. Table 1 is an example of the calculation result from the 8-channel wavelength tunable laser module. Table 1. Wavelength Im2 Lock Point ADC Code [THz] [nm] VLOCKPOINT [mA] [V] [Dec] [Hex] 0 189.4496 521.4 1.202 1969 07B1 1 1582.851 189.4003 573.4 1.072 1757 06DD 2 1583.265 189.3508 511.4 1.227 2010 07DA 3 1583.692 189.2997 563.4 1.097 1798 0706 4 1584.110 189.2498 527.4 1.187 1944 0798 5 1584.529 189.1997 556.8 1.114 1824 0720 6 1584.942 189.1504 524.3 1.194 1957 07A5 7 2) 1582.439 1585.365 189.1000 553.3 1.122 1839 072F Calculate the voltage setpoint for ADN8830 ADN8830 according to the following equation: [ ] VDAC = (G × TLASER ) VOFFSET V where: TLASER is target temperature of the thermistor in Celsius. G = 0.0658 [ ] VOFFSET = 0.659 V Table 2 is an example of the calculation result from the 8-channel wavelength tunable laser module. Table 2. Wavelength TLASER VDAC DAC Code [THz] [nm] RTH [] [C] [V] [Dec] Curve Slope [Hex] 0 1582.439 189.4496 16810 12.191 0.144 236 00EC Positive 1 1582.851 189.4003 14370 15.941 0.390 639 027F Negative 2 1583.265 189.3508 12350 19.658 0.634 1040 0410 Positive 3 1583.692 189.2997 10630 23.433 0.883 1447 05A7 Negative 4 1584.110 189.2498 9220 27.106 1.125 1843 0733 Positive 5 1584.529 189.1997 8040 30.728 1.363 2233 08B9 Negative 6 1584.942 189.1504 7060 34.247 1.594 2612 0A34 Positive 7 1585.365 189.1000 6210 37.802 1.828 2996 0BB4 Negative 4 REV. B AN-655 AN-655 3) Compile and download the software to the ADuC832. To select the download/debug mode, position the switch (S5) to DEBUG, and then press the reset button (S3).This sets the ADuC832 to download mode. To select the normal mode, position the switch (S5) to NORMAL and press the reset button (S3). ADuC832 executes downloaded program after reset. 4) Mount the laser module to the mount pads labeled U13. The ADN2830 ADN2830 is capable of sinking a current up to 200 mA. The maximum TEC voltage limit is set at 3.5 V ±5% by default. To change the TEC voltage limiter, change the value of R24 and R25 which is configured as a voltage divider to set the voltage to the VLIM pin of ADN8830 ADN8830. Maximum TEC voltage can be given by: [ ] Maximum TEC voltage = (1.5 V - VLIM ) × 4 V 5) Set JP1 and JP2. To protect the laser module from accidental damage, it is recommended to close JP1 and JP2 if the program has been changed. Shorting JP1 enables the ADN8830 ADN8830 to shut down mode regardless of control signals from the ADuC832. Shorting JP2 enables the ADN2830 ADN2830 to ALS (Automatic Laser Shutdown) mode regard less of control signals from ADuC832. 6) Apply +3 V and 5 V to the power supply terminal block (J1) located at the top of the demo board. 7) Leave JP2 open. ADN2830 ADN2830 starts to drive the laser diode. 8) Calibrate the optical output power by adjusting the multiturn potentiometer (R48). 9) Leave JP1 open. ADN8830 ADN8830 starts to control the laser temperature to the initial temperature setpoint selected by switch (S4). 10) Press S1 or S2 buttons to change the wavelength lock point. S1 increments and S2 decrements the wavelength point by 1. 11) To change the target wavelength lock point directly, configure the 3-bit DIP switch (S4) according to Table 3. This change is effective only when the ADuC832 is powered up or after reset. Table 3. Ch# S4(1) S4(2) S4(3) 0 OFF OFF OFF 1 ON OFF OFF 2 OFF ON OFF 3 ON ON OFF 4 OFF OFF ON 5 ON OFF ON 6 OFF ON ON 7 ON ON ON 12) 7-segment LED (DS1) displays the selected wavelength and DS1 blinks until the laser temperature is set. TEMPLOCK LED (D1) is lit when the laser temperature is settled within the capture range. WL_LOCK LED (D2) is lit when the wavelength is locked within ITU grid ±12pm. REV. B 5 AN-655 AN-655 To maintain optimal linearity over the required temperature range, the value of the thermistor resistance should be calculated at the lowest and the highest operating temperature according to the following equation: INTERFACING WAVELENGTH MONITOR PD Figure 5 shows the current-to-voltage conversion circuit on the demo board. The conversion gain is set by R46. The input range of the wavelength monitor current Im2 is up to 1.0 mA by default. The wavelength monitor voltage, Vim2, is calculated by: 1 1 RTH = R25 × exp B Tx T25 where: [ ] Vim2 = 2.5 (2490 × Im2 ) V AVDO Im2 R25 is thermistor resistance at 25 °C. B is thermistor constant R46 249 T25 is temperature in K. DAC1 2.5V REF Typically, B = 3450 and R25 = 10K Vm2 R58 NOT POPULATED R1, R2, and R3 are given by: R57 0 R1 = Figure 5. I/V Conversion Circuit INTERFACING 12-BIT 12-BIT DAC AND ADN8830 ADN8830 By using the interface circuit shown in Figure 6, the laser temperature is controlled by DAC output voltage. This scales the DAC voltage range from 0 V to 2.5 V for temperature range from 10°C to 50°C. The interface circuit linearizes the thermistor transfer function. The TEMPSET pin of ADN8830 ADN8830 is fixed at 1.25 V. The THERMIN pin is connected to the resistor network which includes the thermistor. The characteristic of voltage-to-temperature is shown in Figure 7. R2 = R3 = ADN8830 ADN8830 THERMIN R3 RTH Figure 6. Application Circuit Using DAC Control Voltage 2.5 IDEAL CONTROL VOLTAGE (V) R mid R high + R mid R low 2R high R low R high + R low 2 R mid IMPLEMENTING THE WAVELENGTH LOCK As the first phase, the program executes the coarse tuning with the ADN8830 ADN8830 TEC controller. The program reads S4 switch position, then generates the fixed control voltage to let the ADN8830 ADN8830 settle the laser temperature corresponding to the selected wavelength set by S4. Because the ADN8830 ADN8830 has a local control loop for the temperature control, the program waits for the temperature locked signal from the ADN8830 ADN8830. After the laser temperature is settled within the capture range of the wavelength lock, the program starts the fine tuning. This phase uses the monitor signal from the wavelength locker. The program reads the actual wavelength and compares with the target wavelength being stored in the memory. Then the program adjusts the temperature control voltage, which corresponds to the error amount between the target wavelength and the monitored wavelength. Figure 8 shows the overview of the program flow including the course and fine tuning. Details of the course and fine tuning are shown in Figure 9 and Figure 10 respectively. TEMPSET DAC0 2R low R high R low + R high R low = R low + R 3 R2 R1 R low R high where: R high = R high + R 3 2.5V ADuC832 2R low R high ACTUAL LINEARIZATION ERROR < 0.5% 0 10 50 THERMISTOR TEMPERATURE (C) Figure 7. V-to-Temperature Characteristic 6 REV. B AN-655 AN-655 START START COARSE TUNE LOAD AND SET AN INITIAL TEMPERATURE NEGATE LASER AND TEC SHUTDOWN LASER TEMP IN CAPTURE RANGE OF WAVE LOCKER? NO YES START FINE TUNE YES TARGET CHANNEL CHANGED? NO START A/D CONVERSION UPDATE D/A CONVERTER TO INCREMENT LASER TEMP SET LOOP GAIN MOVING AVERAGE FILTERING COMPARE ACQUIRED DATA WITH TARGET DATA UPDATE D/A CONVERTER TO DECREMENT LASER TEMP SET LOOP GAIN Figure 8. Overview of Program Flow Chart REV. B 7 AN-655 AN-655 START COARSE TUNE TURN OFF LASER/TEC LOAD TARGET DATA READ S4 SWITCH ADC GAIN/OFFSET CALIBRATION LOCK POINT CALIBRATION SET LOCKING SLOPE SET TARGET TEMPERATURE TURN ON LASER/TEC DELAY NO TEMPERATURE LOCKED? GO TO FINE TUNE Figure 9. Coarse Tuning Flow Chart 8 REV. B AN-655 AN-655 START FINE TUNE BACK TO COARSE TUNE BACK TO COARSE TUNE POSITIVE SLOPE NEGATIVE SLOPE CHECK SLOPE POLARITY YES GRID CHANNEL CHANGED? YES GRID CHANNEL CHANGED? NO NO 8 A/D CONVERSIONS 8 A/D CONVERSIONS AVR. FILTERING AVR. FILTERING DELAY DELAY LOCKPOINTADC LP < ADC FLAG = 0 LOCKPOINTADC ELSE DECREMENT LASER TEMPERATURE LP > ADC FLAG = 1 INCREMENT LASER TEMPERATURE ELSE DECREMENT LASER TEMPERATURE INCREMENT LASER TEMPERATURE Figure 10. Fine Tuning Flow Chart ADuC832 SOFTWARE The demo software is written in i8051 assembly that uses 1.2 kB out of 62 kB on-chip EE/Flash and 80 bytes out of 256 bytes of on-chip RAM in ADuC832. The transaction time of the wavelength lock routine is approximately 0.3 ms at 4 MHz of the CPU core clock setting. The essential part of the program is listed below. The first control phase is labeled FF_Tune (Feed-Forward Tuning), and second control phase is labeled L_Lock (Lambda Lock). ORG 0060H 0060H ; MAIN PROGRAM MAIN: ; =cpu configure= SETB ALS CLR SD ; Shutdown TEC, ADN8830 ADN8830 (ACTIVE LOW) MOV ADCCON1, #11001100b ; Select Ext. Vref, single conversion MOV DACCON, #00011111b ; DAC0 On, 12bit, Asynchronous MOV DAC0H, #007h ; DAC0 to 4th WL, Set TEMP =28.033degC MOV DAC0L, #096h ; MOV PLLCON, #00000000b ; Set core clock to 16MHz SETB EA ; Enable Interrupt MOV P0, #00101000b ; Turn on 7SEG display with `8' CLR LLOCK_LED ; Turn off WL Lock LED MOV CALN_L, #020h ; Lock point calib. value at neg. slope MOV CALN_H, #000h ; MOV CALP_L, #010h ; Lock point calib. value at pos. slope MOV CALP_H, #000h ; MOV CALDAC_L, #000h ; DAC initial value calib. low byte MOV CALDAC_H, #000h REV. B ; Shutdown laser driver, ADN2830 ADN2830 (ACTIVE HIGH) ; DAC initial value calib. high byte 9 AN-655 AN-655 CALL DACDATA ; Load DAC data table to ram (30h to 3Fh) CALL LP_DATA ; Load lock point data table to ram (40h to 4Fh) CALL SW_DETECT ; Read 3-bit DIP SW position CALL ADCCAL ; ADC Gain and Offset calib. CALL AUTO_DEMO ; Enable Auto demo if S1/S2 pushed MOV ECON, #06H ; Erase all pages of data Flash/EE CALL REV_WRITE ; Write board and firm revision to Flash/EE FF_TUNE: ; =Feed-forward tuning (coarse-tune)= SETB ALS ; Turn off Laser, Active High CLR SD ; Turn off TEC, Active LOW CLR PBFLAG ; Clear PBFLAG CLR P3.6 ; Turn off Temp lock LED CALL CH_LOAD ; Load selected DAC initial value CALL LP_LOAD ; Load selected Lock point value CALL SLOPE_CHECK ; Check slope polarity MOV P0, WL_SEL ; display selected wavelength ch# on 7seg SETB LEDBI ; Turn on 7seg display SETB LEDLE ; 7seg Latch enabled CALL LP_CAL ; Lock point offset calibration CALL DAC_CAL ; DAC initial value calibration MOV DAC0H, DACINT_H ; Update DAC to target temp MOV DAC0L, DACINT_L ; Update DAC to target temp SETB SD ; Turn on TEC CLR ALS ; Turn on Laser CLR TMPLKFLAG ; Clear temp lock indicate flag MOV R0, #00H ; SET Page Pointer ADDRESS MOV R1, #03H ; SET Byte Location ADDRESS MOV R2, WL_SEL ; SET 1byte Value to write CALL EE_WRITE ; Call Flash/EE Write routine CALL TEMP_LOCK ; Sit here until FF_Tune completion L_LOCK: ; =Lambda lock Loop (fine tune)= SETB LEDBI ; Turn on 7seg display MOV A, #07h ; Set delay time, A*12.5msec CALL DELAY ; Call delay program, 100msec JNB SLOPEFLAG, LL_POS ; Check slope polarity, positive or negative LL_NEG: ; =Lambda locking at Negative slope= CALL PB_DETECT ; Detect push-button sw JNB PBFLAG, LOOP_N ; Jump LOOP_N if PB is not pushed JMP FF_TUNE ; if PBFLAG=1(PB detected), back to FF_TUNE LOOP_N: MOV A, #40d ; Set delay time, A * 12.5msec 10 REV. B AN-655 AN-655 CLR P2.7 ; Test signal for cpu transaction monitoring CALL DELAY ; Call delay program SETB P2.7 ; Test signal for cpu transaction monitoring CALL ADC ; Take 8 * samples CALL AVR ; Averaging CALL SUBTRACT ; Subtract (LOCKPOINT - ADCDATA) CALL LOCK_INDICATE ; Turn LED on if result is in lock range CALL GAIN_DECISION ; Check if error amount is