AN-46 QS5991 QS5992 QS5993 QS5V991 QS5V993 AN-45 QS5920 MAPN-0046-00 QS5919

Q QUALITY SEMICONDUCTOR, INC. Frequently Asked Questions (FAQ) About QSI Phase-Locked Loops The following is a list of the most

AN-46 AN-46 Q QUALITY SEMICONDUCTOR, INC. Frequently Asked Questions (FAQ) About QSI Phase-Locked Loops The following is a list of the most commonly asked questions about QSI phase-locked loop (PLL) clock drivers. The following answers provide a brief explanation to each question. More complete explanations to some of the questions in this application note are covered in separate application notes. Please refer to the QSI web site at www.qualitysemi.com for more information. 1. What is the propagation delay of the input clock when the PLL is in Test Mode? Propagation delays can vary depending on the configuration of the PLL. Table 1 shows the typical propagation delay of selected popular PLLs with different configurations. These values will change slightly depending on the variation of supply voltage and ambient temperature. For QS5991 QS5991, QS5992 QS5992, QS5993 QS5993, QS5V991 QS5V991, and QS5V993 QS5V993 devices propagation delay, please refer to AN-45 AN-45 "TurboClock Test Mode". 2. What happens to the outputs if the input clock and/or the feedback signal are gated HIGH, LOW, or allowed to float (lost signal)? an ow N There are two possibilities depending on the particular PLL product family used. There is no difference as to whether the inputs are gated HIGH, LOW, or left to float. All three possibilities assume a DC value by the time they reach the phase/frequency detector and since the phase/frequency detector only operates on the edge of a signal (can be either positive or negative depending on the PLL and its configuration), a DC value has no effect. (a) QS5920 QS5920 The VCO will default to a low frequency if the feedback input is gated or allowed to float. If the input clock is gated or allowed to float (but not the feedback), then the VCO will drift at a maximum slew rate towards the minimum frequency. The maximum slew rate for the QS5920 QS5920 is given in Table 2. MAPN-0046-00 MAPN-0046-00 JULY 31, 1998 Application Note AN-46 AN-46 (b) QS5919 QS5919 family, QS5991 QS5991 family A number of possibilities exist depending on when the inputs are gated or left to float. If the inputs are gated or allowed to float at the same time, and away from the synchronizing edge, then the drift will be ideally be zero. But because of leakage currents in the chargepump switches and parasitic capacitive coupling onto the VCO control node, the VCO will drift very minimally (at a rate depending on the amount of leakage and the difference in leakage between N- and P-fets) to either the maximum or minimum frequency. ny pa If the inputs are gated or allowed to float at the same time, close to or on the synchronizing edge, then the VCO could drift at the maximum slew rate either towards the maximum frequency or minimum frequency depending on the final state of the phase/ frequency detector. The final state of the phase/ frequency detector could be to increase the VCO frequency, decrease the VCO frequency, or keep the VCO frequency the same. The maximum slew rate for the QS5919 QS5919 family and the QS5991 QS5991 family is given in Table 2. om C If the clock input is gated or left to float one or more synchronizing edges before the feedback input is gated or left to float, then the VCO will drift at the maximum slew rate towards the minimum frequency. If the clock input is gated or left to float one or more synchronizing edges after the feedback input is gated or left to float, then the VCO will drift at the maximum slew rate towards the maximum frequency. For an uncontrolled loss (i.e. signals left to float) of the input clock and feedback signal, the worst case drift would be at the maximum slew rate towards either the maximum frequency or minimum frequency. QUALITY SEMICONDUCTOR, INC. 1 AN-46 AN-46 Table 1. Propagation Delays for QSI PLL's Propagation Delay Part Number FS=Low FS=Mid FS=High QS5919 QS5919 8ns N/A 7ns QS5919T QS5919T 8ns N/A 7ns QS5LV919 QS5LV919 10ns N/A 8ns QS5920 QS5920 15ns N/A 12ns QS5931 QS5931 8ns N/A 7ns QS5931T QS5931T 8ns N/A 7ns QS5LV931 QS5LV931 10ns N/A 8ns QS59910 QS59910 (TEST=Mid) 44ns 44ns 26ns QS59920 QS59920 (TEST=Mid) 44ns 44ns 26ns QS59910 QS59910 (TEST=High) 12ns 12ns 9ns QS59920 QS59920 (TEST=High) 12ns 12ns 9ns ny pa Note: Under nomimal supply voltage and room temperature at 25°C. Table 2. Typical Slew Rates for QSI's PLLs om C Propagation Delay Part Number QS5919 QS5919 QS5919T QS5919T QS5LV919 QS5LV919 QS5920 QS5920 QS5931 QS5931 QS5931T QS5931T QS5LV931 QS5LV931 QS5991 QS5991 QS5992 QS5992 QS5993 QS5993 QS59910 QS59910 QS59920 QS59920 QS5V991 QS5V991 QS5V993 QS5V993 an ow N FS=Low 6.3MHz/us 6.3MHz/us 5.5-11MHz/us 4-5MHz/us 6.3MHz/us 6.3MHz/us 5.5-11MHz/us 4.5MHz/us 4.5MHz/us 4.5MHz/us 4.5MHz/us 4.5MHz/us 4.3MHz/us 4.3MHz/us FS=Mid N/A N/A N/A N/A N/A N/A N/A 7.5MHz/us 7.5MHz/us 7.5MHz/us 7.5MHz/us 7.5MHz/us 7.2MHz/us 7.2MHz/us FS=High 12.7MHz/us 12.7MHz/us 11-22MHz/us 7-9MHz/us 12.7MHz/us 12.7MHz/us 11-22MHz/us 12.2MHz/us 12.2MHz/us 12.2MHz/u 12.2MHz/us 12.2MHz/us 11.7MHz/us 11.7MHz/us Note: Under nomimal supply voltage and room temperature at 25°C. 2 QUALITY SEMICONDUCTOR, INC. MAPN-00046-00 MAPN-00046-00 JULY 31, 1998 AN-46 AN-46 3. How long will the PLL take to lock given the same frequency but different phase? Assume the PLL has locked onto an incoming clock signal. If this incoming clock signal suddenly changes phase but not frequency, then the phase/frequency detector will, for example, produce a "pump down" signal for the charge pump and pull current out of the loop filter (see Figure 1). Because of the series resistor in the loop filter, the VCO control voltage suddenly steps down by a certain amount (depending on the pump current and resistor value) and hence suddenly reduces the frequency of the VCO (depending on the gain of the VCO). This allows the input clock to accumulate phase faster than the output and at some number of clock cycles later, the phase error has reduced to zero and the VCO control voltage returns to its original value (the number of clockcycles its takes to reduce the phase error is much less than the time required for the loop filter capacitor to slew significantly and hence the final VCO control voltage is very similar to the initial control voltage). The number of clock cycles it takes to re-lock depends on the frequency of the input and the amount of phase mis-alignment. For example, a QS5919 QS5919 configured with 2xQ as the feedback and with a 100MHz input clock can re-align a 180° phase shift in around 20 clock cycles. Figure 1. Example Phase Re-alignment of PLL ny pa CLK FB If the phase change results in the input clock's synchronizing edge to lead the feedback's synchronizing edge, then the VCO frequency will increase and the phase will re-align a number of clock cycles later and then return to its original frequency. an ow N 4. How does jitter at the input affect the output? Side effects when cascading PLLs? Input jitter at certain frequencies can be a problem when cascading PLL's. The resulting jitter at the output can have little or no effect on system performance, or it can render the system as being completely unusable. MAPN-0046-00 MAPN-0046-00 JULY 31, 1998 om C The magnitude of the closed-loop system response represents the jitter transfer characteristic of the system. The magnitude of this response exceeds unity (or 0dB) over some range of frequencies due to the closed-loop zero of the loop filter at a frequency lower than that of the poles. For QSI's PLL's, the amount of "peaking" and the frequency band at which this occurs depends mainly on the loop filter characteristic and the configuration of the PLL. The effect of this peaking on cascaded PLL's is that any jitter in this spectrum will grow exponentially from one stage to the next. The 3dB closed-loop frequencies for QSI's PLL's in different configurations are shown in Table 3 (refer to Figure 2 for the jitter transfer characteristic). QUALITY SEMICONDUCTOR, INC. 3 AN-46 AN-46 Table 3. Loop Filter Characteristic Frequencies 3dB Frequency Part Number FS = Low FS = MID FS = HIGH Feed Back QS5919/QS5919T/ QS5919/QS5919T/ QS5931/QS5931T QS5931/QS5931T 2.4MHz N/A 4.6MHz 2xQ 1.1MHz N/A 2.4MHz Q0, Q1, Q2, Q3, Q4, or Q5 600kHz N/A 1.1MHz Q/2 4.0MHz N/A 7.1MHz 2xQ 2.0MHz N/A 4.0MHz Q0, Q1, Q2, Q3, Q4, or Q5 1.0MHz N/A 2.0MHz Q/2 QS5920/QS5920A QS5920/QS5920A 1.2MHz N/A 2.3MHz QFB QS5991/QS5992/ QS5991/QS5992/ QS5993/QS59910 QS5993/QS59910 880kHz 1.5MHz 1.5MHz 3F0:1 = LL 1.8MHz 3.2MHz 3.2MHz 3F0:1 = LM, LH, ML, MM, MH, HL, or HM 500kHz 730kHz 770kHz 3F0:1 = HH 870kHz 1.4MHz 1.4MHz 3F0:1 = LL 1.7MHz 3.0MHz 3.1MHz 3F0:1 = LM, LH, ML, MM, MH, HL, or HM 430kHz 680kHz 720kHz QS5LV919/QS5LV931 QS5LV919/QS5LV931 QS5V991/QS5V993 QS5V991/QS5V993 ny pa om C 3F0:1 = HH Figure 2. Jitter Transfer Characteristic Gain an ow N 0dB 3dB 40dB/decade 3dB Frequency The frequency band at which the peaking occurs depends on the configuration of the PLL (i.e. feedback dividers, FS settings, etc.) since this changes the damping ratio and hence moves the spacing between the zero (f2) and the lowest frequency pole 4 Frequency (at a frequency lower than f3). The effect of this peaking on cascaded PLL's is that any input jitter in this spectrum will grow exponentially from one stage to the next. QUALITY SEMICONDUCTOR, INC. MAPN-00046-00 MAPN-00046-00 JULY 31, 1998