AN-45 IDT7052 IDTY052 IDT7134 IDT7050 A10-A0 IDT74FCT521 A23-A12 11-A1 D15-D8 - Datasheet Archive

 

TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 Integrated Device Technology, Inc. By John R. Mick INTRODUCTION Integrated Device

 

INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 Integrated Device Technology, Inc. By John R. Mick INTRODUCTION Integrated Device Technology is continuing to pioneer higher speed and higher density static RAMs. As IDT has improved its CEMOSTM technology, new RAM architectures and additional features have become feasible. The end result is that design engineers now have powerful new integrated circuits available for demanding applications. One such circuit is the IDT7052 IDT7052 FourPort RAM. This device is a Four-port 2K by 8bit Static RAM built using a 12-transistor four-ported static RAM cell. Each of the four-ports is independent in terms of the byte that it can read or write. This now IDT7052 IDT7052 FourPort RAM provides the system architect with better ways to look at computer system design. For example, the IDT7052 IDT7052 can be used in a multiprocessor environment to provide a common memory among several processors. An example of such an architecture is shown in CPU 1 PORT PORT 1 2 Figure 1. Here we see each of the four RAM ports connected to a high performance microprocessor. These processors could also be intelligent controllers, DSP engines, or a combination of the two. The FourPort RAM can be used in such computer architectures as hypercubes and parallel processing machines for storage and movement of data. It offers unheard of opportunities in digital signal processing (DSP) where new architectures for Fast-Fourier-Transforms (FFTs), recursive and non-recursive digital filters, windowing functions, and special purpose algorithms can take advantage of multiple ports into a shared memory. The IDT7052 IDT7052 FourPort RAM can increase system performance and reduce parts count by providing simultaneous access to the data by more than one processor at a time. VCC CPU 2 IDTY052 IDTY052 2K x 8 FourPortTM RAM CPU 3 PORT PORT 3 4 R1 Row Select R1 Q2 Q2 Q1 CPU 4 Q1 Bit Line 1 Bit Line 2 Figure 1. Four-Port RAM Providing Common Memory to Four CPU's Figure 2. Typical Four-Transistor SRAM Cell UNDERSTANDING THE FourPort RAM In order to effectively design with the IDT7052 IDT7052 FourPort RAM, it is important for the design engineer to understand its construction and architectural features. This is most easily accomplished by starting with a simple single port RAM cell and evolving its architecture into the FourPort structure. Figure 2 shows a typical single port static RAM built using a four-transistor cell. This architecture is commonly used by most static RAM manufacturers to build static RAMs because it offers high density, good speed and low power. In its simplest description, the device consists of two Nchannel transistors (Q1) and two resistors (R1) that are connected so as to form two simple cross-coupled inverters. This gives a regenerative action such that one N-channel transistor is ON and the other N-channel transistor is OFF. Thereby, a single bit of memory is formed. ln order to interface to this cross-coupled pair of inverters, two additional Nchannel transistors (Q2) are connected between the inverter outputs and the bit-lines. The gates of these two N-channel transistors are connected to a line called the row select. These Q2 transistors connected between the cell and the bit lines are usually called transmission gates. The result is that when a particular row of cells in the RAM is addressed, these two transistors are turned on and one bit-line will reflect a HIGH and the other bit-line will reflect a LOW as determined by the current state of the static RAM cell. An expanded example of this RAM architecture is shown in Figure 3. Here we see a 16-bit RAM, organized four-rows by four columns internally, in a more complete form. The bit-lines of the cells are connected to the inputs of a sense amplifier by means of N-channel switches. These switches are controlled by the column address deocoder. The sense ampilifier will detect whether the state of the bit is a logic one or a logic zero depending on the relative polarity of the two bit-lines going into the differential sense amplifier. We usually call the transistors connected between the sense amplifier and bit-lines a data multiplexer or data selector. The IDT logo is a registered trademark of Integrated Device Technology, Inc. ©1996 Integrated Device Technology, Inc. 1 3560/1 INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 VCC A2 A3 VCC VCC VCC VCC VCC VCC VCC VCC VCC A1 Row Address Decoder VCC VCC A0 VCC VCC VCC VCC Column Address Decoder CS WE OE DataOut DataIn Control Logic Figure 3. An Example Four-Transistor Cell for a 16-bit SRAM. When we wish to write the simple RAM as shown in Figure 3, a row address line is selected by the row address decoder and the N-channel pass transistors (Q2 of Figure 2) connected to the bit lines are turned on by pulling their gates high. Now however, the write amplifier driven by the Data-In line (Figure 3) is turned on by the write enable signal via the control logic. The write amplifier will drive one bit-line HIGH and the other bit-line LOW as determined by the logic state of the data input. The output of the write amplifier is more powerful than the inverter transistors (Q1 in Figure 2) in the RAM cell and it easily overpowers these inverter transistors if it is necessary to flip the static RAM bit. In its simplest form, this is all there is to the circuitry of a static RAM. Functions such as chip enable are used to simply enable or disable the entire operation of the RAM. Output enable on a static RAM is used to turn "on" the outputs during a read cycle and turn "off" the outputs during write cycles. It can be used to solve timing problems in high speed applications. 2 INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc A1 Vcc Vcc Row Address Decoder Vcc Vcc A0 Vcc Vcc Vcc Vcc Column Address Decoder A2 A3 CS WE OE Data In Data Out Control Logic Figure 4. An Example of a Six-Transistor 16-bit SRAM. Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc A1 Vcc Vcc Row Address Decoder Vcc Vcc A0 Vcc Vcc Vcc Vcc Row Address Decoder Column Address Decoder A2 A3 Column Address Decoder DataOut DataOut DataIn CS WE OE DataIn Control Logic Control Logic LEFT PORT RIGHT PORT Figure 5. An example 16-bit Dual-Port RAM. 3 CS WE OE A0 A1 A2 A3 INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 A variation on the standard four-transistor static RAM call is the six-transistor static RAM cell as shown in Figure 4. In this Figure we see that the two pull-up resistors (R1 of Figure 2) have been replaced by two P-channel transistors. The operation of such a six-transistor cell is identical to the fourtransistor cell previously described. The difference between the two approaches is that the physical size of the cell with the P-channel transistors is larger than the cell with the resistors. The standby power can be lower for the six-transistor cell because there is no power being dissipated. In a fourtransistor cell, one of the the pull-up resistors is always dissipating power since one transistor of the cell is always ON. The six-transistor cell can have higher radiation hardened characteristics than the four-transistor cell because the voltage swings in the cell are larger. This is because the internal node in the cell that is high is pulled to the +5V rail by the Pchannel transistor. In addition, the six-transistor cell provides higher internal noise margins in the circuit for this same reason. Most manufacturers of static RAMs use the fourtransistor cell because it allows static RAMs of higher density to be fabricated with smaller die sizes. Next, let's look at a typical dual-port RAM such as the IDT7134 IDT7134, a 4K by 8-bit device. An example schematic diagram showing a sixteen-bit two-port RAM is shown in Figure 5. Here we see our standard cross-coupled inverter pairs using two N-channel transistors with resistor pull-ups (Q1 and R1 of Figure 2) to form the sixteen memory bits. 4 Notice however, now there are two pairs of N-channel transmission gates connected to each RAM cell's true and compliment outputs and two pairs of bit-lines associated with each cell. Each pair of bit-lines is a read/write port into the dual-port RAM. Each pair of transmission gates has its own row address control so that Port A can select any memory cell in the RAM and Port B can select any memory cell in the RAM. This is the technique used in IDT dual-port RAMs to provide total independent access to individual bytes. Each pair of bitlines is connected to a sense amplifier and a write buffer via a data multiplexer so that each port on the 2-port RAM can read or write data at its selected address. Now for the FourPort RAM operation. Figure 6 shows a minimal schematic diagram for the IDT7052 IDT7052 12-transistor FourPort RAM cell. The two inverters making up the basic memory cell are fabricated using two N-channel pulldown transistors and two P-channel pullup transistors. They are connected in the normal cross-coupled inverter fashion to make a single memory cell. Four individual memory ports are achieved by using four pairs of N-channel pass transistors to connect to four pairs of bit-lines. Four individual row addresses are used to select each pair of transmission gates connected between the RAM cell outputs and the bit-line pairs. Four sense-amplifier/write-buffers are used to provide individual read/write paths from each port to all the cells in the RAM. INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 Vcc RESISTO R PULL-UPS RESISTO R PULL-UPS P1-Row Sel 1 P2-Row Sel 1 P3-Row Sel 1 P4-Row Sel 1 Vcc P1-Row Sel 2 P2-Row Sel 2 P3-Row Sel 2 P4-Row Sel 2 Figure 6. A Simple Example of a Twelve Transistor FourPort RAM Configuration. From this discussion, the design engineer should understand the mechanism used to implement a FourPort RAM. As described, we can see how we can make each port of the FourPort RAM totally independent from the other ports. Do not confuse this statement to mean that independent reads and writes can always be performed without data corruption. If two ports write to the same byte at the same time, one or both values may be lost. Likewise, if one port writes to a byte at the same time another part is reading the byte, the read may be corrupted even though the byte write is completed correctly. This application note does not discuss issues of data integrity in the case of multiple accesses to the same location, when one of the asynchronous accesses is a write cycle. These problems are discussed in detail in Application Note 02 and will not be further discussed here. Suffice it to say that the IDT7050 IDT7050 and IDT7052 IDT7052 FourPort RAMs have a BUSY input to allow external hardware or software arbitration schemes to be implemented to meet the specific needs of the designer's system. The BUSY input serves only to block write cycles from the port to which this signal is applied. It has no effect on a read 5 cycle. Note that in the following applications were are not using the BUSY input of the FourPort RAM so it should be tied HIGH. We probably will not always mention this, so do not forget it or you will not be able to write into the FourPort RAM. Once the rules are understood however, only engineering creativity is needed to visualize new architectural opportunities for FourPort RAMs. This powerful new memory technology will provide increased performance in future electronic processing systems. CASCADING THE FourPort RAM Perhaps the most easily understood techniques in designing with static RAMs are width and depth expansion. Width expansion of any port of the FourPort RAM is straightforward. No additional parts are needed to build 16, 24 or 32 bit wide or wider memories. Any port of the FourPort RAM can be viewed the same as a simple single port static RAM. All the same rules apply and they can be applied individually to each port of the FourPort RAM. INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 ADDR ESS 23-12 ADDR ESS 11-1 Upper Address Decode ADDR STB BLOCK SELECT HIGH-RW LOW-RW R/W CE A10-A0 A10-A0 IDT7052 IDT7052 2Kx8 4-PORT RAM I/O7-I/O0 CE A10-A0 A10-A0 IDT7052 IDT7052 2Kx8 4-PORT RAM I/O7-I/O0 OE DATA 15-8 R/W LOW-OE OE OE DATA 7-0 Figure 7. A 4K x 16-bit FourPort CE Controlled RAM Depth expansion of the FourPort RAM is also quite simple. If one port is viewed as a static RAM, it is expanded similar to a single port device. Lower addresses are connected between devices and upper addresses are decoded by means of a standard decoder such as an lDT74FCT138 or lDT74FCT139. The outputs of the decoders can be used either to control the chip selects or control the write-enable and output-enable individually. Simple examples of expansion of one port of a FourPort RAM to a 4K-word by 16-bit configuration are shown in Figure 7 and Figure 8. Figure 7 shows the Chip Enable HIGH-OE R/W CE A10-A0 A10-A0 IDT7052 IDT7052 2Kx8 4-PORT RAM I/O7-I/O0 IDT7052 IDT7052 2Kx8 4-PORT RAM I/O7-I/O0 OE R/W CE A10-A0 A10-A0 HIGH-OE A 23 -A 13 HIGH-R/ W Upper Address Decode R/W Decode OE Decode CE A10-A0 A10-A0 R/W I/O7-I/O0 OE A11 A 1 LOW-R/ W LOW-OE ADDR STB BLOCK SELECT R/W Decode OE Decode CE R/W OE I/O7-I/O0 CE A10-A0 A10-A0 R/W A12 A10-A0 A10-A0 IDT7052 IDT7052 2Kx8 4-PORT RAM IDT7052 IDT7052 2Kx8 4-PORT RAM OE expansion method while Figure 8 shows write-enable, outputenable expansion. The two schemes are similar, but, sometimes one can have a timing advantage over the other. This is usually a function of the actual timing signals that are available or have already been generated. Once the depth expansion is understood, we can view the CPU interconnect schemes by simply looking at a one deep FourPort RAM. We recognize that deeper versions can be realized as just described. A10-A0 A10-A0 IDT7052 IDT7052 2Kx8 4-PORT RAM IDT7052 IDT7052 2Kx8 4-PORT RAM I/O7-I/O0 CE R/W OE I/O7-I/O0 DATA 15-8 Figure 8. A 4K x 16-bit FourPort OE and R/W Controlled RAM 6 DATA7-0 INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 CONNECTING THE FourPort RAM TO CPUs A Z80A Example Probably the easiest interface of the IDT7052 IDT7052 FourPort RAM is to a Z80A. This processor still provides a great priceperformance tradeoff! By using four Z80As with the IDT7052 IDT7052 FourPort RAM, significant performance advantages can result. For example, no time need be lost due to DMA channels. The data placed in memory by one Z80A on one port is instantly available to another Z80A on another port. In a similar fashion, parallel processing can be performed by multiple processors working on the data in shared memory. The typical connection scheme for the IDT7052 IDT7052 (or IDT7050 IDT7050 1 Kx8 FourPort RAM) to a Z80A is shown in Figure 9. Here we see the eleven address lines, A10-A0 A10-A0, of the FourPort RAM are connected to the A10-A0 A10-A0 lines of the Z80A. This places the FourPort RAM in a contiguous 2K address space of the Z80A. The 2K byte segment actually used is determined by upper address decode circuit. A PAL or an IDT74FCT521 IDT74FCT521 could be used to perform this function. The data lines are connected between the processor and the RAM. The Z80A has a RD line that can be connected to the FourPort OE and a WR line that can be connected to the FourPort R/W input. This works along the lines of the a Chip Enable expansion method just described. When the Z80A addresses the FourPort RAM, either a read or write will be performed depending on the instruction being executed. If RD goes LOW, the FourPort RAM will output data from the addressed byte. If WR goes LOW, the FourPort RAM will write data into the addressed byte. IDT7 0 5 2 4 -PORT RAM Z8 0 A CPU MREQ Port -x A15 _ 5 A11 A10 _ A0 D7 _ D0 DE CODE CE A 10 _ 11 A0 I/ O7 _ 8 I/ O0 RD WR +5V OE R/ W BUSY Figure 9. Interfacing the Z80A to One Port of the FourPort RAM. DTACK AS A23-A12 A23-A12 DECODE 12 A 11-A1 11-A1 11 A10-A0 A10-A0 68000 CPU D7-D0 I/O7-I/O0 R/W IDT7052 IDT7052 2Kx8 4-PORT RAM I/O7-I/O0 R/W 8 IDT7052 IDT7052 2Kx8 4-PORT RAM OE D15-D8 D15-D8 8 OE UDS LDS R/W CE PAL DECODE Figure 10. A 16-bit FourPort RAM with the 68000 CPU. A 68000 CONNECTION EXAMPLE If we wish to build a 16-bit microprocessor interface to one port of the IDT7052 IDT7052 FourPort RAM, a typically interface might be as shown in Figure 10. Here we see two IDT7052s used in a 16-bit configuration. One FourPort RAM is connected to the lower eight data bits (D7-D0) and the other FourPort RAM is connected to the upper eight data bits (D15-D8 D15-D8). This completes a 16-bit data bus. Address lines A10-A0 A10-A0 of the FourPort 7 RAM are connected between RAMs and also connected to address lines A11-A1 A11-A1 respectively of the 68000. Remember, the 68000 does not have an A0 address line but uses UpperData-Strobe (UDS) and Lower-Data-Strobe (LDS) to control the upper and lower byte selection. These two signals in conjunction with the R/W signal are decoded in a PAL to generate the individual FourPort RAM R/W and OE control signals. Figure 11 shows the truth table needed for the PAL. INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 It has been my experience when working with the 68000, that once these signals are generated, they are useful throughout the design to control other peripherals, etc. Basically, how- R/W X 1 0 1 0 1 0 INPUTS OUTPUTS UDS LDS URW LRW UOE LOE 1 0 0 1 1 0 0 1 0 0 0 0 1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 Figure 11. 68000 16-bit Control PAL Truth Table. ever, in this example we simply have a lower byte FourPort RAM and an upper byte FourPort RAM. The upper address lines of the 68000, A23-A12 A23-A12 in this case, are used to position the 2K bytes of FourPort RAM in continuous address space of the 68000. The actual location can be anywhere from 0x000000 to 0xFFFFFF as long as the overall range is on 2K byte boundaries. Usually we include address strobe (AS) in the decoding as it can solve some timing problems. A timing review will show if it is needed. An output of the decode circuit can be used to generate the data acknowledge (DTACK) if it is needed. Usually design engineers have an overall plan for generating the memory CEs and DTACK, so what is shown here is only to remind you of solving the overall problem. Address of Bytes in a Big-Endian 32-bit Word Word Address 0x0024 0x0020 0x001c 0x0018 0x0014 0x0010 0x000c 0x0008 0x0004 0x0000 Word Address 0x0014 0x0012 0x0010 0x000e 0x000c 0x000a 0x0008 0x0006 0x0004 0x0002 0x0000 Word Address - etc 0x0010 0x000f 0x000e 0x000d 0x000c 0x000b 0x000a 0x0009 0x0008 0x0007 0x0006 0x0005 0x0004 0x0003 0x0002 0x0001 0x0000 Bits 31-24 0x0024 0x0020 0x001c 0x0018 0x0014 0x0010 0x000c 0x0008 0x0004 0x0000 Bits 23-16 - etc 0x0021 0x001d 0x0019 0x0015 0x0011 0x000d 0x0009 0x0005 0x0001 Bits 15-8 - etc 0x0022 0x001e 0x001a 0x0016 0x0012 0x000e 0x000a 0x0006 0x0002 Bits 7-0 - etc 0x0023 0x001f 0x001b 0x0017 0x0013 0x000f 0x000b 0x0007 0x0003 Address of Bytes in a Big-Endian 16-bit Word Bits 15-8 Bits 7-0 0x0014 - etc 0x0012 0x0013 0x0010 0x0011 0x000e 0x000f 0x000c 0x000d 0x000a 0x000b 0x0008 0x0009 0x0006 0x0007 0x0004 0x0005 0x0002 0x0003 0x0000 0x0001 Address of Bytes in an 8-bit Word Bits 7-0 - etc 0x0010 0x000f 0x000e 0x000d 0x000c 0x000b 0x000a 0x0009 0x0008 0x0007 0x0006 0x0005 0x0004 0x0003 0x0002 0x0001 0x0000 Figure 12. Memory Map for 8, 16, and 32-bit Ordering. 8 INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 HOW ABOUT 8-BITS, 16-BITS 16-BITS AND 32-BITS 32-BITS IN THE SAME SYSTEM!!! This is perhaps the most interesting example to talk about. We will use an 8-bit Z80A, a 16-bit 68000 and a 32-bit R3000 R3000 RISC microprocessor to discuss the design techniques. We have chosen the three processors because they are typical, they are fun to work with and they have had broad acceptance in the microprocessor world. First, let's look at Figure 12 to understand memory addressing and "memory space". All three of our selected microprocessors are "byte" addressable machines. That means they can address bytes as well as words in the case of the 68000 and R3000 R3000. The 68000 is a BigEndian machine and the R3000 R3000 will be operated in Big-Endian mode to keep things simple. (DEC and Intel f ans can make the appropriate transformation. In fact, the FourPort RAM might make a really exciting byte-ordering problem solver between machines by connecting one port as Big-Endian and another port as Little-Endian to the same microprocessor and similarity for the second processor.) IDT79R3010 IDT79R3010 FPA I - CACHE IDT79R3000 IDT79R3000 CPU D - CACHE ADDRESS BUS DATA BUS ADDRESS REGISTER D7-D0 D15-D8 D15-D8 OE I/O7 - I/O0 W0 R0 R/W OE W1 R1 R/W OE I/O7 - I/O0 CE I/O7 - I/O0 DECODE W2 R2 D31-D24 D31-D24 OE A A31 - A13 I/O7 - I/O0 A12 - A2 R/W CONTROL PAL R/W BYTE PAL W3 R3 A1-A0 ACCT1-0 R/W D23-D16 D23-D16 IDT74FCT52 IDT74FCT52 IDT74FCT52 IDT74FCT52 IDT74FCT52 IDT74FCT52 IDT74FCT52 IDT74FCT52 One Port of Four-Port RAM NOTE: Tie BUSY to +5V. Other Address Space Figure 13. Using a 32-bit Wide FourPort Memory with the R3000 R3000. Since we are talking about byte addressable machines, Figure 12 shows the byte addresses of an 8-bit machine, the byte addresses of a 16-bit machine and the byte addresses of a 32-bit machine. Likewise, word addresses of 16-bit and 32bit machines are shown. What is intended here is to point out that we want the consecutive byte ordering of all of the machines to remain constant. By doing this, we keep the ability to do indexing into an array of bytes from any of the processors as a simple task. For example, a 40 byte index from any byte address is the same in all processors talking to each other through the FourPort RAM. We can look at Figure 12 as representing the Z80A, 68000 and R3000 R3000 respectively. Next, let's look at the interface needed for each of our three processors. We will build on our previous examples in this application note but there are differences needed to allow proper addressing. Let's begin by looking at the R3000 R3000. The reader should refer to IDT's wealth of information on the IDT79R3000 IDT79R3000 RISC microprocessor if you are not familiar with the standard CPU, FPA, Cache and I/O interface. We will use four of the IDT7052 IDT7052 FourPort RAMs to give a 32-bit wide memory for this example. We assume the first port is connected to the R3000 R3000, the second port is connected to the 68000 and the third port is connected to the Z80A. The fourth port could be connected to a second one of any of these processors or a wide selection of other things. 9 A typical R3000 R3000 interface is shown in Figure 13. The key element here is to understand that we are interfacing to a 32bit data bus, 32-bit address bus with byte encoded control signals and to an R3000 R3000 interface. We are able to implement the required byte control per Figure 12 by using the "BYTE PAL" shown in Figure 13. The truth table for this PAL is shown in Figure 14. Using this decoding, we are able to do all of the required operations. This includes 32-bit word operations, 24bit three-byte operations, 16-bit half-word operations and 8-bit byte operations. The signals available are A0, A1, AccessType0, and AccessType1, all from the R3000 R3000 address register, and we assume a R/W input from the "Control PAL" shown in Figure 13. There may be other options here, but this R/W signal must be realized in some fashion. The upper address bits from the R3000 R3000 are decoded in the fashion previously discussed to locate the total 8K bytes of FourPort RAM in the R3000 R3000 address space. Working out the timing of the R3000 R3000 interface is most of the work. Remember that at this interface point there are several flexibilities in the final timing. With an R3000 R3000 running at 16 MHz, a data transfer cycle is in multiples of 67 nanoseconds, 20 MHz gives 50 nanoseconds, and 25 MHz allows 40 nanoseconds. Thus depending on the processor speed and the FourPort RAM speed selected block refill may or may not be desired. In any case, we should be able to run with zero, INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 one or two stall cycles. As mentioned before, the design engineer usually has a plan for address decoding and control handshake which is more closely tied to the overall system ACCT0 1 1 INPUTS A1 0 0 A0 0 0 W3 1 0 W2 1 0 W1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 design. From this standpoint, interfacing to one port of the FourPort RAM is no different than interfacing to an EPROM, DRAM, SRAM, or peripheral. OUTPUTS W0 R3 1 0 0 1 COMMENTS R2 0 1 R1 0 1 R0 0 1 0 1 1 1 0 0 1 1 0 0 1 1 1 0 1 1 Tri-Byte Read Tri-Byte Read Tri-Byte Write Tri-Byte Write 1 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 Half-Word Read Half-Word Read Half-Word Write Half-Word Write 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 Read Byte 0 Read Byte 1 Read Byte 2 Read Byte 3 Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Word Read Word Write Figure 14. 32-bit R3000 R3000 Control PAL Truth Table (Big-Endian). DTACK AS A23-A13 A23-A13 A 12-A2 12-A2 DECODE 11 11 CE A10-A0 A10-A0 8 W0 R0 D15-D8 D15-D8 8 W1 R1 W2 R2 68000 CPU W3 R3 A1 UDS LDS R/W CONTROL PAL DECODE I/O7-I/O0 R/W OE I/O7-I/O0 R/W OE I/O7-I/O0 R/W OE I/O7-I/O0 R/W OE 8 Figure 15. A 32-bit FourPort RAM with the 68000 CPU. 10 One Port of FourPort RAM D7-D0 7052 4-PORT RAM 7052 4-PORT RAM 7052 4-PORT RAM 7052 4-PORT RAM INTRODUCTION TO IDT's FourPortTM RAM R/W 1 1 0 0 1 1 1 1 0 0 0 0 INPUTS LDS A1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 1 1 UDS APPLICATION NOTE AN-45 AN-45 0 0 0 0 W2 1 1 0 1 W1 1 1 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 W3 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 OUTPUTS W0 R3 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 COMMENTS R2 0 1 1 1 R0 1 0 1 1 Word Read Word Read Word Write Word Write 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 R1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 Read Byte 0 Read Byte 1 Read Byte 2 Read Byte 3 Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Figure 16. 32-bit 68000 Configuration Control PAL Truth Table. memory system. Every thing else about the design is the same as the previous 68000 example. Lastly, let's look at the 8-bit interface to the Z80A microprocessor. It also should be viewed as being hooked into a 32bit memory system. A detailed block diagram is shown in Figure 17. Notice that all four of the IDT7052 IDT7052 FourPort RAMs are connected to the D7-D0 data bus. Address lines A1 and A0 will be used to select the device to which the Z80A processor will talk. In fact, A1, A0, RD and WR are inputs to the control PAL decode. The truth table to be implemented is detailed in Figure 18. This processor is only capable of performing byte reads or writes so the decoding is siraightforward. A1 and A0 are used to do byte selection. Thus, the FourPort RAM A10 A0 address inputs are connect to the A12-A2 A12-A2 address lines of the Z80A. This keeps the byte addressing as desired in the memory map of Figure 12. Again the remaining part of the design is as shown in the previous Z80A example. Next, let's look at the 16-bit 68000 interface in a 32-bit memory system. A detailed block diagram is shown in Figure 15. The key thing to notice here is that four of the IDT7052 IDT7052 FourPort RAMs are used. Notice that two of the devices are connected to the D7-D0 data bus and two of the devices are connected to the D15-D8 D15-D8 databus on the 68000. Address line A1 will be used to select which pair of FourPort RAMs that the processor will read or write. For example, when A1 is LOW, control signals W3, W2, R3 and R2 will be enabled. When A1 is HIGH, control signals W1, W0, R1 and R0 will be enabled. This is shown in complete detail in the truth table of Figure 16. If we study this truth table, we see how we accomplish both 16-bit word (half-word) reads and writes as well as 8-bit byte reads and writes. All of this is consistent with the memory map shown in Figure 12. The technique here is actually to use A1 to select either the lower half-word or the upper half-word in a 32-bit FourPort RAM WAIT MREQ A15-A13 A15-A13 A12-A2 A12-A2 DECODE 3 11 CE A10-A0 A10-A0 8 W0 R0 W1 Z80A CPU R1 W2 R2 W3 R3 A1 A0 RD WR CONTROL PAL DECODE I/O7-I/O0 R/W OE I/O7-I/O0 R/W OE I/O7-I/O0 R/W OE I/O7-I/O0 R/W OE Not e: Tie 8 One Port of Four-Port RAM D7-D0 IDT7052 IDT7052 4-PORT RAM IDT7052 IDT7052 4-PORT RAM IDT7052 IDT7052 4-PORT RAM BUSY to + 5V. Figure 17. A 32-bit FourPort RAM with a Z80A CPU. 11 IDT7052 IDT7052 4-PORT RAM INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 INPUTS WR RD 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 OUTPUTS A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 W3 1 1 1 1 0 1 1 1 W2 1 1 1 1 1 0 1 1 W1 1 1 1 1 1 1 0 1 W0 1 1 1 1 1 1 1 0 COMMENTS R3 0 1 1 1 1 1 1 1 R2 1 0 1 1 1 1 1 1 R1 1 1 0 1 1 1 1 1 R0 1 1 1 0 1 1 1 1 Read Byte 0 Read Byte 1 Read Byte 2 Read Byte 3 Write Byte 0 Write Byte 1 Write Byte 2 Write Byte 3 Figure 18. 32-bit Z80A Control PAL Truth Table. SYSTEM DESIGN IDEAS Now that we have discussed how the the FourPort RAM is built and we have a good idea of how to connect it to many processors, let's look at some system level uses for this type of FourPort PAM. The key in all of this discussion is to keep track of the data bus width being used in the design. Similarly, the decoding and processor address connections must take this into account. This is one point that the design engineer usually does not have to deal with when working with single port memories. The purpose of this three processor example is to show a few interconnect schemes to typical microprocessors. From this discussion, the design engineer should be able to extend the concepts presented here to other 8-bit, 16-bit and 32-bit microprocessors. Just keep the techniques in mind and work out the desired memory mapping and timing. DIGITAL SIGNAL PROCESSING (DSP) Digital signal processing applications have been expanding as new developments in semiconductor technology provide increased packing density and new architectures in integrated circuits. The IDT7052 IDT7052 FourPort RAM is another in the continuing growth of integrated circuits that allow design engineers to realize new system designs. Addr Addr-P1 P4 Control Data P4 IDT7052 IDT7052 Four-Port RAM Address Sequencer Addr-P3 Control Data P1 Data P2 X Y Addr-P2 Data P3 IDT 7217 Multiplier/Accumulator Timing Generator Z Figure 19. A Simple DSP Engine Using a FourPort RAM One of the simplest DSP algorithms that can be implemented is the finite-impulse-response (FIR) filter. In this type of algorithm, the impulse response of the filter has nonzero values only for a finite duration. These types of filters are easily implemented using only multiplication and summation. Figure 19 shows a block diagram of a DSP machine that takes advantage of the FourPort RAM to interface to a multiplieraccumulator (MAC) such as the IDT7210 IDT7210. In this example, two of the four ports of the FourPort RAM are used to feed data to the MAC inputs and a third port of FourPort RAM is used to receive completed results f rom the MAC output. The fourth port of the FourPort RAM is connected to a local data-address bus to interface to the remainder of the system. 12 In the actual operation of such a processor as shown in Figure 19, data is loaded into the FourPort RAM via Port 4. The algorithm usually needs coeff icients and these are also loaded into the FourPort RAM using Port 4. An address sequencer has the responsibility of providing the correct sequence of addresses to Ports 1, 2 and 3. This unit operates in conjunction with the timing generator to execute the algorithm. Let's look at an example. Suppose our algorithm is: y(n) - A0 * x(n) + A1 * x(n-1) + A2 * x(n-2) + A3 * x(n-3) INTRODUCTION TO IDT's FourPortTM RAM APPLICATION NOTE AN-45 AN-45 We could read this as the current processed value is equal to the current sample times A0, plus the first past sample times A1, plus the second past sample times A2, plus the third past sample times A3. This already shows its potential as a FourPort RAM application. Now, we initialize our system at power-up by putting the values A0, A1, A2, and A3 into the FourPort RAM. We would most likely clear the four locations for the data, Then we start taking data. Each time we receive a data value, we can overwrite the fourth past sample. For each new sample, we will compute a new y(n) and put it into the FourPort RAM. At some point we will extract the sequence of values for y(n) that we have computed. As can be seen, we can have several operations happening on the same clock cycle. RAM ports 1 and 2 could be outputting data, RAM port 3 could be inputting data, and RAM port 4 could be inputting or outputting data, all simultaneously. The speed implications are obvious. Needless to say, this is a simple example for the purpose of demonstration. But if we wanted to work on 1024 samples with 128 coeff icients and a more complex algorithm, all we have to do is follow the same methodology. See IDT application note 42 for a more detailed example of how to use this method to implement a matrix multiplication. writes a two at address zero. Every so often CPU 2 checks address zero and when it sees a two, it knows it is master. It performs any needed data reads or writes. When it is finished, it writes a three at address zero. CPU 3 writes a four and CPU 4 writes a one. Thus, a simple token passing scheme. "Fail safe" mechanisms can be implemonted to keep the token moving if there is any failure. Another obvious scheme is to set up a simple software semaphore path between each pair of processors. This technique can be used to pass data between processor pairs. The semaphore for each processor can use a different byte (or word) address for each semaphore in each direction. By using this method, many different software handshake techniques can be implemented. Rather than use a test and set instruction for semaphores in this application, another interlocking mechanism, like separate locations dedicated to the status of each processor, should be used to guarantee clean communications between tasks. In addition, several hardware approaches are usually available in most multiprocessor environments. These include individual interrupts between processors as well as broadcast interrupt approaches. In either case, after the data has been set up in a private buffer, processor A can interrupt processor B to notify it of the pending message. The data structures used in such an environment can include pointer passing and linkage conventions consistent with modern day software techniques. CPU to CPU to CPU to CPU Referring to Figure 1 where we started this application note, we see that we have a FourPort RAM connected between four CPUs. How do we efficiently communicate each processor's status to the other processors? You will need to work an acceptable software semaphore scheme or do hardware handshaking using external circuitry. The most obvious software scheme is token passing. After each processor has determined its order in the token passing scheme, the token passing protocol boils down to each processor taking its turn. This can be achieved by reading one memory location to see who is master. Usually multiple reads and compares are performed to avoid any data corruption problems. A good example of this mechanism is detailed in IDT application note 43. Let's take an example. The byte at address zero contains the token. The current value is one. CPU 1 is master of the FourPort RAM and can read or write data. When finished, it SUMMARY The FourPort RAM is a truly new innovative integrated circuit memory that offers now communications methods for computing machines. It provides exceptional speeds because of its opportunity for parallelism. The IDT7052 IDT7052 2Kx 8bit FourPort RAM and the IDT7050 IDT7050 1K x 8-bit FourPort RAM are the first in a series of memories that will pioneer these now architectural frontiers. At speeds as fast as some of the fastest standard static RAMs, they bring now performance dimensions to parallel communication between tasks of a computing machine. These devices utilize the latest in IDTs CEMOS technology to provide the design engineer with an economical high performance, low power, small size and highly reliable "Speciality Memory" for todays performance-driven designs. 13