AMMC-6420 AMMC-5618 60E-03 30E-03 80E-03 40E-03 10E-03 20E-03 70E-03 00E-03 - Datasheet Archive

 

6 - 18 GHz Power Amplifier Data Sheet Chip Size: 2000 x 2000 µm (78.5 x 78.5 mils) Chip Size Tolerance: ± 10

 

AMMC - 6420 6 - 18 GHz Power Amplifier Data Sheet Chip Size: 2000 x 2000 µm (78.5 x 78.5 mils) Chip Size Tolerance: ± 10 µm (±0.4 mils) Chip Thickness: 100 ± 10 µm (4 ± 0.4 mils) Pad Dimensions: 100 x 100 µm (4 ± 0.4 mils) Description Features AMMC-6420 AMMC-6420 MMIC is a broadband 1W power amplifier designed for use in frequency bands between 6 to 18GHz. It is a cost-effective alternative in commercial communications systems to a discrete FET hybrid. The MMIC has a partial input and output match to 50 but can be easily externally matched by single element for narrow band frequency coverage The MMIC is unconditionally stable over all frequencies and bias conditions. Gate voltage is set using the Vg pin to optimize for linear or saturated power amplification. A temperature compensated RF output power detector circuit allows differential output power detection of 0.3V/W at 18 GHz. For improved reliability and moisture protection, the die is passivated at the active areas. · Wide frequency range: 6 - 18 GHz · High gain: 20 dB · Power: @17 GHz, P-2dB=30.5 dBm · Highly linear: OIP3=38dBm · Integrated RF power detector · 5.5 Volt, -0.6 Volt, 800mA operation Applications · Microwave Radio systems · Satellite VSAT and DBS systems · LMDS & Pt-Pt mmW Long Haul · 802.16 & 802.20 WiMax BWA · WLL and MMDS loops · Can be driven by AMMC-5618 AMMC-5618 (6-20 GHz) MMIC increasing luding overall gain. AMMC-6420 AMMC-6420 Absolute Maximum Ratings[1] Symbol Parameters/Conditions Units Min. Max. Vd Positive Drain Voltage V Vg Gate Supply Voltage V Id Drain Current mA 1500 Pin CW Input Power dBm 23 Tch Operating Channel Temp. °C Tstg Storage Case Temp. °C Tmax Maximum Assembly Temp (60 sec max) °C 7 -3 0.5 +150 -65 +150 +300 Note: 1. Operation in excess of any one of these conditions may result in permanent damage to this device. Note: These devices are ESD sensitive. The following precautions are strongly recommended. Ensure that an ESD approved carrier is used when dice are transported from one destination to another. Personal grounding is to be worn at all times when handling these devices. AMMC-6420 AMMC-6420 DC Specifications/Physical Properties [1] Symbol Parameters and Test Conditions Units Id Drain Supply Current (under any RF power drive and temperature) (Vd=5.5 V, Vg set for Id Typical) mA Vg Gate Supply Operating Voltage (Id(Q) = 800 (mA) V qch-b Thermal Resistance[2] (Backside temperature, Tb = 25°C) Min. °C/W Max. 800 -0.8 Typ. 1000 -0.6 -0.4 8.9 Notes: 1. Ambient operational temperature TA=25°C unless otherwise noted. 2. Channel-to-backside Thermal Resistance (ch-b) = 10.7°C/W at Tchannel (Tc) = 120°C as measured using infrared microscopy. Thermal Resistance at backside temperature (Tb) = 25°C calculated from measured data. AMMC-6420 AMMC-6420 RF Specifications [3, 4, 5] (TA= 25°C, Vd=5.5, Id(Q)=800 mA, Zo=50 ) Symbol Parameters and Test Conditions Units Min. Typ. Gain Small-signal Gain[4] dB 16.5 20 Max. Sigma 0.45 P-1dB Output Power at 1dB Gain Compression dBm 27 29 0.27 P-3dB Output Power at 3dB Gain Compression dBm 30 0.23 OIP3 Third Order Intercept Point; Df=10MHz; Pin=-20dBm dBm 38 0.75 RLin Input Return Loss[4] dB -3 0.23 RLout Output Return Loss[4] dB -6 0.25 Isolation Min. Reverse Isolation dB -45 1.10 Notes: 3. Small/Large -signal data measured in wafer form TA = 25°C. 4. 100% on-wafer RF test is done at frequency = 8, 12, and 18 GHz. 5. Specifications are derived from measurements in a 50 test environment. Aspects of the amplifier performance may be improved over a more narrow bandwidth by application of additional conjugate, linearity, or power matching. LSL 1 LSL 18 Gain at 12 GHz 19 0 LSL 8 P-1dB at 8 GHz 9 0 1 8 9 P-1dB at 18 GHz Typical distribution of Small Signal Gain and Output Power @P-1dB. Based on 1500 part sampled over several production lots AMMC-6420 AMMC-6420 Typical Performances (TA = 25°C, Vd =5.5 V, ID = 800 mA, Zin = Zout = 50 ) NOTE: These measurements are in a 50 test environment. Aspects of the amplifier performance may be improved over a more narrow bandwidth by application of additional conjugate, linearity, or power matching. 0 0 0 P- PAE S1[dB] -0 0 -0 S1 [dB] 1 10 P- [dBm], PAE [%] - Return Loss [dB] 0 -10 -0 0 -1 1 0 8 10 1 1 1 Frequency [GHz] 18 -80 0 -0 Figure 1. Typical Gain and Reverse Isolation S11[dB] S[dB] 8 10 1 1 1 Frequency [GHz] 18 0 10 Figure 2. Typical Return Loss (Input and Output) Po[dBm], and, PAE[%] IP [dBm] 10 1 1 Frequency [GHz] 1 18 0 0 90 Pout(dBm) PAE[%] Id(total) 8 0 9 8 Figure 3. Typical Output Power (@P-2) and PAE 0 10 Noise Figure [dB] 0 0 80 Ids [mA] S1[dB] 0 S1[dB] 0 0 1 10 0 1 0 0 8 10 1 1 Frequency [GHz] 1 18 0 8 10 1 1 Frequency [GHz] 1 18 Figure 5. Typical Output 3rd Order Intercept Pt. Figure 4. Typical Noise Figure 0 -10 0 0 10 Pin [dBm] 0 0 1 Figure 6. Typical Output Power, PAE, and Total Drain Current versus Input Power at 18GHz 0 - - -10 -10 0 S11[dB] -1 -1 S11_0 S11_-0 S11_8 0 10 1 Frequency [GHz] 0 Figure 7. Typical S11 over temperature - S1_0 S1_-0 S1_8 1 -0 -0 - S1[dB] 0 S[dB] 0 - S_0 S_-0 S_8 0 10 1 Frequency[GHz] Figure 8. Typical S22 over temperature 0 10 0 10 1 Frequency[GHz] 0 Figure 9. Typical Gain over temperature P- [dBm] 0 8 P-_8deg 0 P-_0deg P-_-0deg 10 1 Frequency [GHz] 0 Figure 10. Typical P-2 over temperature Typical Scattering Parameters [1], (TA = 25°C, Vd =5.5 V, ID = 800 mA, Zin = Zout = 50 ) Freq GHz S11 S21 S12 S22 dB Mag Phase dB Mag Phase dB Mag Phase dB Mag Phase 1 -0.85 0.91 -69.53 -16.32 0.15 175.58 -51.70 2.60E-03 60E-03 -95.53 -0.74 0.92 -61.37 2 -1.28 0.86 -114.70 1.47 1.18 49.05 -46.75 4.60E-03 60E-03 -125.88 -2.93 0.71 -110.65 3 -2.06 0.79 -141.33 -25.02 0.06 -63.29 -57.72 1.30E-03 30E-03 -130.77 -0.59 0.93 -134.98 4 -2.91 0.72 -156.19 -0.83 0.91 159.65 -57.72 1.30E-03 30E-03 64.56 -1.18 0.87 -171.79 5 -3.20 0.69 -162.66 16.56 6.73 57.13 -57.72 1.30E-03 30E-03 110.37 -4.56 0.59 151.19 6 -2.91 0.72 -170.79 23.65 15.22 -63.61 -54.90 1.80E-03 80E-03 56.43 -12.67 0.23 -160.02 7 -2.73 0.73 -178.53 23.09 14.27 -160.60 -57.72 1.30E-03 30E-03 -35.93 -6.90 0.45 -173.75 8 -2.46 0.75 172.56 20.74 10.89 128.10 -57.08 1.40E-03 40E-03 -78.75 -7.10 0.44 -179.00 9 -2.22 0.77 162.29 18.44 8.36 74.59 -57.08 1.40E-03 40E-03 -109.63 -5.99 0.50 175.99 10 -2.28 0.77 148.18 17.16 7.21 31.07 -54.90 1.80E-03 80E-03 -136.34 -5.33 0.54 163.53 11 -2.76 0.73 131.48 17.00 7.08 -9.66 -53.56 2.10E-03 10E-03 153.71 -5.56 0.53 149.41 12 -3.89 0.64 107.67 18.09 8.02 -52.96 -53.15 2.20E-03 20E-03 151.00 -6.70 0.46 135.78 13 -6.19 0.49 66.21 19.92 9.91 -104.92 -50.17 3.10E-03 10E-03 104.36 -9.09 0.35 126.82 14 -8.87 0.36 -17.97 21.27 11.57 -169.21 -47.54 4.20E-03 20E-03 48.68 -11.27 0.27 138.43 15 -5.93 0.51 -100.42 20.85 11.03 119.60 -48.40 3.80E-03 80E-03 -7.09 -9.02 0.35 143.80 16 -3.97 0.63 -145.89 19.42 9.35 52.62 -46.56 4.70E-03 70E-03 -83.32 -7.32 0.43 126.32 17 -3.82 0.64 -177.46 18.11 8.05 -15.59 -47.96 4.00E-03 00E-03 -127.39 -7.66 0.41 102.27 18 -5.51 0.53 151.43 17.25 7.29 -95.95 -50.46 3.00E-03 00E-03 150.09 -9.92 0.32 88.21 19 -12.43 0.24 103.81 13.56 4.77 158.78 -52.04 2.50E-03 50E-03 140.32 -6.05 0.50 80.79 20 -8.88 0.36 -63.36 3.19 1.44 47.46 -46.20 4.90E-03 90E-03 102.64 -3.22 0.69 31.22 21 -2.37 0.76 -118.45 -14.91 0.18 -35.35 -48.87 3.60E-03 60E-03 59.47 -2.57 0.74 -14.04 22 -0.99 0.89 -145.51 -37.99 0.01 20.47 -54.90 1.80E-03 80E-03 2.36 -2.14 0.78 -48.95 23 -0.65 0.93 -161.21 -35.39 0.02 1.97 -54.43 1.90E-03 90E-03 -23.94 -1.79 0.81 -76.03 24 -0.54 0.94 -171.73 -44.58 0.01 -16.33 -56.48 1.50E-03 50E-03 38.32 -1.49 0.84 -97.03 25 -0.46 0.95 -179.38 -46.20 0.00 -33.78 -66.02 5.00E-04 00E-04 46.67 -1.22 0.87 -113.22 26 -0.40 0.95 174.06 -56.48 0.00 -41.36 -60.00 1.00E-03 00E-03 158.26 -1.08 0.88 -126.30 Note: 1. Data obtained from on-wafer measurements. Biasing and Operation Assembly Techniques The recommended quiescent DC bias condition for optimum efficiency, performance, and reliability is Vd=5.5 volts with Vg set for Id=800 mA. Minor improvements in performance are possible depending on the application. The drain bias voltage range is 3 to 5.5V. A single DC gate supply connected to Vg will bias all gain stages. Muting can be accomplished by setting Vg to the pinch-off voltage Vp (-1.0V). The backside of the MMIC chip is RF ground. For microstrip applications the chip should be attached directly to the ground plane (e.g. circuit carrier or heatsink) using electrically conductive epoxy [1,2]. An optional output power detector network is also provided. The differential voltage between the Det-Ref and Det-Out pads can be correlated with the RF power emerging from the RF output port. The detected voltage is given by : V = (Vref - Vdet) - Vofs where Vref is the voltage at the DET_R port, Vdet is a voltage at the DET_O port, and Vofs is the zero-input-power offset voltage. There are three methods to calculate : 1. Vofs can be measured before each detector measurement (by removing or switching off the power source and measuring ). This method gives an error due to temperature drift of less than 0.01dB/50°C. 2. Vofs can be measured at a single reference temperature. The drift error will be less than 0.25dB. 3. Vofs can either be characterized over temperature and stored in a lookup table, or it can be measured at two temperatures and a linear fit used to calculate at any temperature. This method gives an error close to the method #1. The RF ports are AC coupled at the RF input to the first stage and the RF output of the final stage. No ground wired are needed since ground connections are made with plated through-holes to the backside of the device. For best performance, the topside of the MMIC should be brought up to the same height as the circuit surrounding it. This can be accomplished by mounting a gold plate metal shim (same length and width as the MMIC) under the chip which is of correct thickness to make the chip and adjacent circuit the same height. The amount of epoxy used for the chip and/or shim attachment should be just enough to provide a thin fillet around the bottom perimeter of the chip or shim. The ground plain should be free of any residue that may jeopardize electrical or mechanical attachment. The location of the RF bond pads is shown in Figure 12. Note that all the RF input and output ports are in a Ground-Signal-Ground configuration. RF connections should be kept as short as reasonable to minimize performance degradation due to undesirable series inductance. A single bond wire is normally sufficient for signal connections, however double bonding with 0.7 mil gold wire or use of gold mesh is recommended for best performance, especially near the high end of the frequency band. Thermosonic wedge bonding is preferred method for wire attachment to the bond pads. Gold mesh can be attached using a 2 mil round tracking tool and a tool force of approximately 22 grams and a ultrasonic power of roughly 55 dB for a duration of 76 +/- 8 mS. The guided wedge at an untrasonic power level of 64 dB can be used for 0.7 mil wire. The recommended wire bond stage temperature is 150 +/- 2°C. Caution should be taken to not exceed the Absolute Maximum Rating for assembly temperature and time. The chip is 100um thick and should be handled with care. This MMIC has exposed air bridges on the top surface and should be handled by the edges or with a custom collet (do not pick up the die with a vacuum on die center). This MMIC is also static sensitive and ESD precautions should be taken. Notes: 1. Ablebond 84-1 LM1 silver epoxy is recommended. 2. Eutectic attach is not recommended and may jeopardize reliability of the device. Vg Vd 1 Vd 2 DQ DET _O RF in RF out Vg Vd 1 DQ Vd 2 DET _R Figure 11. AMMC-6420 AMMC-6420 Schematic RFin RFout Figure 12. AMMC-6420 AMMC-6420 Bonding pad locations Vd 68 pF Vg 0 .5 nH Vg V d1 Vd2 DET _ O AMMC-6420 AMMC-6420 RFI RFInput RFOutput RFO DET _ R Vg Vd2 V d1 0 .5 nH Notes: 1. =>1mF capacitors on DC biasing lines not shown required. 2. Vg connections recommended on both sides for devices operating at or above 1 condition. Vg 68 pF Vd 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 1 0.1 0 5 10 15 20 25 Pout[dBm] 30 35 0.01 Figure 14. AMMC-6420 AMMC-6420 Typical Detector Voltage and Output Power, Freq=12GHz Det_R - Det_O [V] Det_R - Det_O [V] Figure 13. AMMC-6420 AMMC-6420 Assembly diagram Ordering Information: AMMC-6420-W10 AMMC-6420-W10 = 10 devices per tray AMMC-6420-W50 AMMC-6420-W50 = 50 devices per tray For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved. Obsoletes AV01-0219EN AV01-0219EN AV02-1370EN AV02-1370EN - September 4, 2008