RISC86 C0000 - Datasheet Archive

 

® Mobile AMD-K6 -2+ ® Processor Data Sheet Publication # 23446 Issue Date: June 2000 Rev: B Amendment/0 Preliminary

 

Preliminary Information ® Mobile AMD-K6 -2+ ® Processor Data Sheet Publication # 23446 Issue Date: June 2000 Rev: B Amendment/0 Preliminary Information © 2000 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, K6, 3DNow!, and combinations thereof, TriLevel Cache, and Super7 are trademarks, and AMD-K6 and RISC86 RISC86 are registered trademarks of Advanced Micro Devices, Inc. MMX is a trademark of Intel Corporation. Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii 1 Mobile AMD-K6®-2+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 1.2 2 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Mobile AMD-K6®-2+ Processor Microarchitecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Enhanced RISC86 RISC86® Microarchitecture . . . . . . . . . . . . . . . . . . . 6 Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . . 9 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 11 Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Register X and Y Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Branch History Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Branch Target Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Branch Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Contents PowerNow! Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Super7TM Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Instruction Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Floating-Point Register Data Types . . . . . . . . . . . . . . . . . . . . . 28 MMXTM/3DNow!TM Technology Registers . . . . . . . . . . . . . . . . 29 MMXTM Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . . 29 3DNow!TM Technology Data Types . . . . . . . . . . . . . . . . . . . . . . 30 EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 iii Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 3.2 4 Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . . 37 Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . 46 Task State Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Descriptors and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Instructions Supported by the Mobile AMD-K6-2+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . 55 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 iv 23446B/0-June 2000 Signal Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 A20M# (Address Bit 20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 87 A[31:3] (Address Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 ADS# (Address Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ADSC# (Address Strobe Copy) . . . . . . . . . . . . . . . . . . . . . . . . 89 AHOLD (Address Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 AP (Address Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 APCHK# (Address Parity Check) . . . . . . . . . . . . . . . . . . . . . . 92 BE[7:0]# (Byte Enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 BF[2:0] (Bus Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 BOFF# (Backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 BRDY# (Burst Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 BRDYC# (Burst Ready Copy) . . . . . . . . . . . . . . . . . . . . . . . . . 97 BREQ (Bus Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 CACHE# (Cacheable Access) . . . . . . . . . . . . . . . . . . . . . . . . . 98 CLK (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 D/C# (Data/Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 D[63:0] (Data Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 DP[7:0] (Data Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 EADS# (External Address Strobe) . . . . . . . . . . . . . . . . . . . . 102 EWBE# (External Write Buffer Empty) . . . . . . . . . . . . . . . . 103 FERR# (Floating-Point Error) . . . . . . . . . . . . . . . . . . . . . . . 104 FLUSH# (Cache Flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 HIT# (Inquire Cycle Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 HITM# (Inquire Cycle Hit To Modified Line) . . . . . . . . . . . 106 HLDA (Hold Acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . 107 HOLD (Bus Hold Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 107 IGNNE# (Ignore Numeric Exception) . . . . . . . . . . . . . . . . . 108 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 INTR (Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 110 INV (Invalidation Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 110 KEN# (Cache Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LOCK# (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 M/IO# (Memory or I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 NA# (Next Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . 114 PCD (Page Cache Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Contents Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49 4.50 4.51 4.52 4.53 4.54 4.55 5 PowerNow! Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.1 5.2 5.3 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Enhanced Power Management Features . . . . . . . . . . . . . . . 131 Enhanced Power Management Register (EPMR) . . . . . . . . 131 EPM 16-Byte I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Dynamic Core Frequency and Core Voltage Control . . . . . 134 Effective Bus Divisors EBF[2:0] . . . . . . . . . . . . . . . . . . . . . . . 134 Dynamic Core Frequency Control . . . . . . . . . . . . . . . . . . . . . 135 Voltage Identification (VID) Outputs . . . . . . . . . . . . . . . . . . 137 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.1 6.2 6.3 Contents PCHK# (Parity Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 PWT (Page Writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 RSVD (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . 119 SMIACT# (System Management Interrupt Active) . . . . . . 120 STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 TRST# (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 VCC2DET (VCC2 Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 VCC2H/L# (VCC2 High/Low) . . . . . . . . . . . . . . . . . . . . . . . . 124 VID[4:0] (Voltage Identification) . . . . . . . . . . . . . . . . . . . . . 124 W/R# (Write/Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 WB/WT# (Writeback or Writethrough) . . . . . . . . . . . . . . . . 125 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 141 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Data-NA# Requested. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Pipeline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Pipeline Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Memory Reads and Writes . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Single-Transfer Memory Read and Write . . . . . . . . . . . . . . . 144 Misaligned Single-Transfer Memory Read and Write . . . . . 146 Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . 148 Burst Writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 v Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 6.4 6.5 6.6 7 7.2 7.3 7.4 Signals Sampled During the Falling Transition of RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 RESET Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 State of Processor After RESET . . . . . . . . . . . . . . . . . . . . . . 186 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 State of Processor After INIT . . . . . . . . . . . . . . . . . . . . . . . . 189 Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 8.1 8.2 8.3 8.4 8.5 8.6 vi I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Misaligned I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . 153 Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 154 Hold and Hold Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . 154 HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 158 AHOLD-Initiated Inquire Miss. . . . . . . . . . . . . . . . . . . . . . . . 160 AHOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . 164 AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Bus Backoff (BOFF#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Locked Operation with BOFF# Intervention . . . . . . . . . . . . 172 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Basic Special Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Stop Grant and Stop Clock States . . . . . . . . . . . . . . . . . . . . . 179 INIT-Initiated Transition from Protected Mode to Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Power-on Configuration and Initialization . . . . . . . . . . . . . . 185 7.1 8 23446B/0-June 2000 MESI States in the L1 Data Cache and L2 Cache . . . . . . . . 193 Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Cache-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Cache Disabling and Flushing . . . . . . . . . . . . . . . . . . . . . . . 197 L1 and L2 Cache Disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 L2 Cache Disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 L2 Cache and Tag Array Testing . . . . . . . . . . . . . . . . . . . . . 198 Cache-Line Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Contents Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 8.7 8.8 8.9 8.10 8.11 8.12 8.13 9 Write Merge Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 9.1 9.2 10 10.2 10.3 Floating-Point Execution Unit . . . . . . . . . . . . . . . . . . . . . . . 223 Handling Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . 223 External Logic Support of Floating-Point Exceptions . . . . . 223 Multimedia and 3DNow! Execution Units . . . . . . . . . . . . . . 225 Floating-Point and MMX/3DNow! Instruction Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 FERR# and IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . 227 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 Contents EWBE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Memory Type Range Registers . . . . . . . . . . . . . . . . . . . . . . . 219 UC/WC Cacheability Control Register (UWCCR) . . . . . . . . 219 Floating-Point and Multimedia Execution Units . . . . . . . . . 223 10.1 11 Cache-Line Replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Write to a Cacheable Page . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Write to a Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Write Allocate Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Write Allocate Logic Mechanisms and Conditions . . . . . . . 204 Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Hardware Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Software Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Cache States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Internal Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 WBINVD and INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Cache-Line Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Writethrough versus Writeback Coherency States . . . . . . . 214 A20M# Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . 214 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 SMM Operating Mode and Default Register Values . . . . . 227 SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 I/O Trap Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . 237 vii Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 12 Test and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 12.1 12.2 12.3 12.4 12.5 12.6 13 13.2 13.3 13.4 13.5 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . 272 Pin Connection Requirements . . . . . . . . . . . . . . . . . . . . . . . 273 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15.1 15.2 15.3 15.4 viii Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Enter Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Exit Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Enter Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Exit Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Enter Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . 266 Exit Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . 266 EPM Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Enter EPM Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . 266 Exit EPM Stop Grant State. . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Enter Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Exit Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 14.1 14.2 14.3 15 Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Tri-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Boundary-Scan Test Access Port (TAP) . . . . . . . . . . . . . . . . 241 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 TAP Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . 248 Cache Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 L2 Cache and Tag Array Testing . . . . . . . . . . . . . . . . . . . . . 253 Level-2 Cache Array Access Register (L2AAR) . . . . . . . . . . 253 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 13.1 14 23446B/0-June 2000 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Contents Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 16 Signal Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 279 16.1 16.2 16.3 16.4 16.5 16.6 17 CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 279 Clock Switching Characteristics for 100-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . 281 Output Delay Timings for 100-MHz Bus Operation . . . . . . 282 Input Setup and Hold Timings for 100-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . 286 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 17.1 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . 293 Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 296 18 Pin Description Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 19 Pin Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 20 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 20.1 21 321-Pin Staggered CPGA Package Specification . . . . . . . . 301 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Contents ix Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet x 23446B/0-June 2000 Contents Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 List of Figures Figure 1. Mobile AMD-K6®-2+ Processor Block Diagram. . . . . . . . . . . . . . 7 Figure 2. Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. The Instruction Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. Mobile AMD-K6-2+ Processor Decode Logic . . . . . . . . . . . . . . . 13 Figure 5. Mobile AMD-K6-2+ Processor Scheduler . . . . . . . . . . . . . . . . . . 16 Figure 6. Register X and Y Functional Units . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. EAX Register with 16-Bit and 8-Bit Name Components. . . . . . 22 Figure 8. Integer Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 9. Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 11. Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 12. FPU Status Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 13. FPU Control Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 14. FPU Tag Word Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 15. Packed Decimal Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 16. Precision Real Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 17. MMXTM/3DNow!TM Technology Registers. . . . . . . . . . . . . . . . . . 29 Figure 18. MMXTM Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 19. 3DNow!TM Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 20. EFLAGS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 21. Control Register 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 22. Control Register 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 23. Control Register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 24. Control Register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 25. Control Register 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 26. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 27. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 28. Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 29. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . . 36 Figure 30. Machine-Check Address Register (MCAR) . . . . . . . . . . . . . . . . 38 Figure 31. Machine-Check Type Register (MCTR) . . . . . . . . . . . . . . . . . . . 38 Figure 32. Test Register 12 (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 List of Figures xi Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Figure 33. Time Stamp Counter (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 34. Extended Feature Enable Register (EFER)- MSR C000_0080h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 35. SYSCALL/SYSRET Target Address Register (STAR) . . . . . . . 40 Figure 36. Write Handling Control Register (WHCR)- MSR C0000 C0000_0082h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 37. UC/WC Cacheability Control Register (UWCCR)- MSR C0000 C0000_0085h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 38. Processor State Observability Register (PSOR)- MSR C000_0087h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 39. Page Flush/Invalidate Register (PFIR)- MSR C000_0088h . . 42 Figure 40. L2 Tag or Data Location - EDX . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 41. L2 Data - EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 42. L2 Tag Information - EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 43. Enhanced Power Management Register (EPMR)- MSR C000_0086h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 44. Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 45. Task State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 46. 4-Kbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 47. 4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 48. Page Directory Entry 4-Kbyte Page Table (PDE) . . . . . . . . . . . 50 Figure 49. Page Directory Entry 4-Mbyte Page Table (PDE) . . . . . . . . . . 50 Figure 50. Page Table Entry (PTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 51. Application Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 52. System Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 53. Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 54. Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 55. Enhanced Power Management Register (EPMR)- MSR C000_0086h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 56. EPM 16-Byte I/O Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Figure 57. Bus Divisor and Voltage ID Control (BVC) Field . . . . . . . . . . 136 Figure 58. Waveform Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 59. Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 60. Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 61. Misaligned Single-Transfer Memory Read and Write . . . . . . 147 xii List of Figures Preliminary Information 23446B/0-June 2000 Mobile AMD-K6®-2+ Processor Data Sheet Figure 62. Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . . 149 Figure 63. Burst Writeback due to Cache-Line Replacement . . . . . . . . . 151 Figure 64. Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Figure 65. Misaligned I/O Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 66. Basic HOLD/HLDA Operation . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 67. HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . 157 Figure 68. HOLD-Initiated Inquire Hit to Modified Line. . . . . . . . . . . . . 159 Figure 69. AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 70. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Figure 71. AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 165 Figure 72. AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Figure 73. BOFF# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Figure 74. Basic Locked Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 75. Locked Operation with BOFF# Intervention. . . . . . . . . . . . . . 173 Figure 76. Interrupt Acknowledge Operation . . . . . . . . . . . . . . . . . . . . . . 175 Figure 77. Basic Special Bus Cycle (Halt Cycle) . . . . . . . . . . . . . . . . . . . . 177 Figure 78. Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Figure 79. Stop Grant and Stop Clock Modes, Part 1 . . . . . . . . . . . . . . . . 180 Figure 80. Stop Grant and Stop Clock Modes, Part 2 . . . . . . . . . . . . . . . . 181 Figure 81. INIT-Initiated Transition from Protected Mode to Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Figure 82. L1 and L2 Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . 192 Figure 83. L1 Cache Sector Organization. . . . . . . . . . . . . . . . . . . . . . . . . . 193 Figure 84. Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 202 Figure 85. Write Allocate Logic Mechanisms and Conditions . . . . . . . . . 204 Figure 86. Page Flush/Invalidate Register (PFIR)- MSR C000_0088h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Figure 87. UC/WC Cacheability Control Register (UWCCR)- MSR C000_0085h (Model D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 88. External Logic for Supporting Floating-Point Exceptions. . . 224 Figure 89. SMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Figure 90. TAP State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Figure 91. L2 Cache Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 Figure 92. L2 Cache Sector and Line Organization . . . . . . . . . . . . . . . . . 254 List of Figures xiii Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Figure 93. L2 Tag or Data Location - EDX . . . . . . . . . . . . . . . . . . . . . . . . . 254 Figure 94. L2 Data - EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Figure 95. L2 Tag Information - EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Figure 96. LRU Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Figure 97. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Figure 98. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Figure 99. Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . 258 Figure 100. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . 259 Figure 101. Clock Control State Transitions . . . . . . . . . . . . . . . . . . . . . . . . 269 Figure 102. Suggested Component Placement . . . . . . . . . . . . . . . . . . . . . . 272 Figure 103. CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Figure 104. Diagrams Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Figure 105. Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Figure 106. Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . 289 Figure 107. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Figure 108. Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . 290 Figure 109. TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Figure 110. TRST# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Figure 111. Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Figure 112. Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Figure 113. Power Consumption versus Thermal Resistance . . . . . . . . . . 294 Figure 114. Processor's Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . 295 Figure 115. Measuring Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 296 Figure 116. Mobile AMD-K6-2+ Processor Top-Side View . . . . . . . . . . . . . 297 Figure 117. Mobile AMD-K6-2+ Processor Bottom-Side View . . . . . . . . . . 298 Figure 118. 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 301 xiv List of Figures Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 List of Tables Table 1. Table 2. General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 3. General-Purpose Register Doubleword, Word, and Byte Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 4. Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 5. Mobile AMD-K6®-2+ Processor MSRs . . . . . . . . . . . . . . . . . . . . 37 Table 6. Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . . 39 Table 7. SYSCALL/SYSRET Target Address Register (STAR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 8. Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 9. Application Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 10. System Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 11. Summary of Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . 54 Table 12. Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 13. Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 14. MMXTM Technology Instructions . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 15. 3DNow!TM Technology Instructions . . . . . . . . . . . . . . . . . . . . . . 83 Table 16. 3DNow!TM Technology DSP Extensions . . . . . . . . . . . . . . . . . . . 84 Table 17. Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 18. Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 19. Input Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 20. Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 21. Input/Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . 127 Table 22. Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 23. Bus Cycle Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 24. Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 25. Enhanced Power Management Register (EPMR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 26. EPM 16-Byte I/O Block Definition . . . . . . . . . . . . . . . . . . . . . . 134 Table 27. Processor-to-Bus Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 28. Bus Divisor and Voltage ID Control (BVC) Definition . . . . . . 136 Table 29. Bus-Cycle Order During Misaligned Transfers . . . . . . . . . . . . 146 Table 30. A[4:3] Address-Generation Sequence During Bursts . . . . . . . 148 Table 31. Bus-Cycle Order During Misaligned I/O Transfers . . . . . . . . . 153 Table 32. List of Tables Execution Latency and Throughput of Execution Units . . . . . 17 Interrupt Acknowledge Operation Definition. . . . . . . . . . . . . 174 xv Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Table 33. Table 34. Output Signal State After RESET . . . . . . . . . . . . . . . . . . . . . . 186 Table 35. Register State After RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 36. PWT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 37. PCD Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Table 38. CACHE# Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Table 39. L1 and L2 Cache States for Read and Write Accesses . . . . . . 207 Table 40. Valid L1 and L2 Cache States and Effect of Inquire Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 41. L1 and L2 Cache States for Snoops, Flushes, and Invalidation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 42. EWBEC Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Table 43. WC/UC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Table 44. Valid Masks and Range Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Table 45. Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . 229 Table 46. SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Table 47. SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Table 48. I/O Trap Dword Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 234 Table 49. I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Table 50. Boundary Scan Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 245 Table 51. Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . 246 Table 52. Supported Tap Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table 53. Tag versus Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Table 54. DR7 LEN and RW Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 261 Table 55. Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Table 56. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Table 57. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Table 58. Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Table 59. CLK Switching Characteristics for 100-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Table 60. Output Delay Timings for 100-MHz Bus Operation . . . . . . . . 282 Table 61. Input Setup and Hold Timings for 100-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Table 62. RESET and Configuration Signals for 100-MHz Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Table 63. TCK Waveform and TRST# Timing at 25 MHz . . . . . . . . . . . . 287 Table 64. Test Signal Timing at 25 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Table 65. xvi Encodings For Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . 176 Package Thermal Specifications. . . . . . . . . . . . . . . . . . . . . . . . 293 List of Tables Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Table 66. Table 67. List of Tables 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 301 Valid Ordering Part Number Combinations . . . . . . . . . . . . . . 303 xvii Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet xviii 23446B/0-June 2000 List of Tables Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Revision History Date Rev May 2000 A Initial release. June 2000 B Added 533- and 550-MHz specifications and OPNs. Revision History Description xix Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet xx 23446B/0-June 2000 Revision History Preliminary Information 23446B/0-June 2000 Mobile AMD-K6®-2+ Processor 1 s s s s s s s s s s s s Mobile AMD-K6®-2+ Processor Data Sheet Advanced 6-Issue RISC86 RISC86® Superscalar Microarchitecture x Ten parallel specialized execution units x Multiple sophisticated x86-to-RISC86 instruction decoders x Advanced two-level branch prediction x Speculative execution x Out-of-order execution x Register renaming and data forwarding x Issues up to six RISC86 RISC86 instructions per clock Innovative TriLevel CacheTM Design x 192-Kbyte total internal cache · Internal split, two-way set associative, 64-Kbyte L1 Cache - 32-Kbyte instruction cache with additional 20-Kbytes of predecode cache - 32-Kbyte writeback dual-ported data cache - MESI protocol support · Internal full-speed, four-way set associative, 128-Kbyte, L2 Cache x Multiport internal cache design enabling simultaneous 64-bit reads/writes of L1 and L2 caches x 100-MHz frontside bus to optional Level-3 cache on Super7TM platforms 3DNow!TM Technology x Additional instructions to improve 3D graphics and multimedia performance x Separate multiplier and ALU for superscalar instruction execution PowerNow! Technology for high-performance and advanced low-power modes Compatible with Super7 platform notebook designs x Leverages high-speed 100-MHz processor bus x Accelerated Graphic Port (AGP) support High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit High-Performance Industry-Standard MMXTM Instructions x Dual integer ALU for superscalar execution 321-pin Ceramic Pin Grid Array (CPGA) Package Industry-Standard System Management Mode (SMM) IEEE 1149.1 Boundary Scan x86 Binary Software Compatibility Low Voltage 0.18-Micron Process Technology Chapter 1 Mobile AMD-K6®-2+ Processor 1 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 The Mobile AMD-K6 ® -2+ processor is an advanced 6th generation x86 mobile processor delivering high performance for notebook PC systems. The Mobile AMD-K6-2+ processor is built on AMD's 0.18um process technology and adds PowerNow! technology for high performance and low power modes of operation, allowing for significant improvements in the battery life of notebook PCs. The Mobile AMD-K6-2+ processor supports AMD's innovative TriLevel CacheTM design for enhanced system performance. The TriLevel Cache design provides a large 64-Kbyte L1 cache, a 128-Kbyte L2 cache operating at full processor speed on a backside bus, and up to 1 Mbyte of available L3 cache memory on the external 100-MHz frontside bus. This combination of the largest and fastest cache memory subsystem gives the Mobile AMD-K6-2+ processor a performance edge over competing x86 mobile CPU solutions. The Mobile AMD-K6-2+ processor also incorporates a superscalar MMX unit, support for a 100-MHz frontside bus, and AMD's innovative 3DNow!TM technology for highperformance multimedia and 3D graphics operation. The Mobile AMD-K6-2+ processor includes several other key features for the mobile market. The processor is implemented using an AMD-developed, state-of-the-art low power 0.18-micron process technology. This process technology features a split-plane design that allows the processor core to operate at a lower voltage while the I/O portion operates at the industry-standard 3.3V level. The 0.18-micron process technology with the split-plane voltage design enables the Mobile AMD-K6-2+ processor to deliver excellent portable PC performance solutions while utilizing a lower processor core voltage, which results in lower power consumption and longer battery life. In addition, the Mobile AMD-K6-2+ processor includes the complete industry-standard System Management Mode (SMM), which is critical to system resource and power management. The Mobile AMD-K6-2+ processor also features the industry-standard Stop-Clock (STPCLK#) control circuitry and the Halt instruction, both required for implementing the ACPI power management specification. The Mobile AMD-K6-2+ processor is offered in an industry-standard Super7TM compatible, 321-pin Ceramic Pin Grid Array (CPGA) package. The Mobile AMD-K6-2+ processor's RISC86 RISC86 microarchitecture is a decoupled decode/execution superscalar design that implements state-of-the-art design techniques to achieve leading-edge performance. Advanced design techniques implemented in the Mobile AMD-K6-2+ processor include multiple x86 instruction decode, single-clock internal RISC operations, ten execution units that support superscalar operation, out-of-order execution, data forwarding, speculative execution, and register renaming. In addition, the processor supports the industry's most advanced branch prediction logic by implementing an 8192-entry branch history table, the industry's only branch target cache, and a return address stack, which combine to deliver better than a 95% prediction rate. These design techniques enable the Mobile AMD-K6-2+ processor to issue, execute, and retire multiple x86 instructions per clock, resulting in excellent scaleable performance. 2 Mobile AMD-K6®-2+ Processor Chapter 1 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 AMD's 3DNow! technology is an instruction set extension to x86 that includes 21 new instructions to improve 3D graphics operations and other single precision floatingpoint compute intensive operations. AMD has already shipped millions of AMD-K6 family processors with 3DNow! technology for desktop PCs, revolutionizing the 3D experience with up to four times the peak floating-point performance of previous generation solutions. AMD is now bringing this advanced capability to notebook computing, working in conjunction with advanced mobile 3D graphic controllers to reach new levels of realism in mobile computing. With support from Microsoft® and the x86 software developer community, a new generation of visually compelling applications is coming to market that support 3DNow! technology. The Mobile AMD-K6-2+ processor remains pin compatible with existing Super7TM notebook solutions, however to take advantage of the PowerNow! technology features a number of new pins and registers have been defined that need to be supported in the notebook platform. The Mobile AMD-K6-2+ processor has undergone extensive testing and is compatible with Windows® 98, Windows NT® and other leading operating systems. The Mobile AMD-K6-2+ processor is also compatible with more than 60,000 software applications, including the latest 3DNow! technology and MMX technology software. As the world's second-largest supplier of processors for the Windows environment, AMD has shipped more than 50 million Microsoft Windows compatible processors in the last five years. The Mobile AMD-K6-2+ processor is the next generation in a long line of Microsoft Windows compatible processors from AMD. With its combination of state-of-the-art features, leading-edge performance, high-performance multimedia engine, x86 compatibility, and low-cost infrastructure, the Mobile AMD-K6-2+ processor is the superior choice for performance notebook computers. 1.1 PowerNow! Technology AMD has added a number of new features to the Mobile AMD-K6-2+ processor. These features are called PowerNow! technology. The goal of PowerNow! technology is to allow both high-performance and extended battery life in the same notebook system. When the notebook is running under AC power, the processor operates at maximum performance, within the thermal boundaries of the notebook system design. When the notebook is running on DC power, the processor can run in an advanced low power mode, providing significant benefits in battery life to the user. PowerNow! technology also provides the user with an option to make a trade-off between performance and run-time while battery powered, through the ability to dynamically change the processor bus frequency and core voltage in a manner that is transparent to system operation. Chapter 1 Mobile AMD-K6®-2+ Processor 3 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 1.2 23446B/0-June 2000 Super7TM Platform Initiative AMD and its industry partners are delivering many firsts to the notebook PC market with the Super7 platform. Super7 notebook platforms were the first in the industry to support a 100MHz front-side bus and AMD's TriLevel Cache architecture. Super7TM Platform Features: s s s 4 100-MHz processor bus-The Mobile AMD-K6-2+ processor supports a 100-MHz, 800 Mbyte/second frontside bus to provide a high-speed interface to Super7 platformbased chipsets. The 100-MHz interface to the frontside L3 cache and main system memory speeds up access to the frontside cache and main memory by 50 percent over the 66-MHz Socket 7 interface-resulting in a significant 10% increase in overall system performance. Accelerated graphics port support-AGP improves the performance of mid-range PCs that have small amounts of video memory in the graphics sub-system. The industry-standard AGP specification enables a 133-MHz graphics interface and will scale to even higher levels of performance in the future. Support for backside L2 and frontside L3 cache-The Super7 platform has the 'headroom' to support higher-performance Mobile AMD-K6 processors, with clock speeds scaling to 550 MHz and beyond. Mobile AMD-K6®-2+ Processor Chapter 1 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 2 2.1 Internal Architecture Introduction The Mobile AMD-K6-2+ processor implements advanced design techniques known as the RISC86 RISC86 microarchitecture. The RISC86 RISC86 microarchitecture is a decoupled decode/execution design approach that yields superior sixth-generation performance for x86-based software. This chapter describes the techniques used and the functional elements of the RISC86 RISC86 microarchitecture. 2.2 Mobile AMD-K6®-2+ Processor Microarchitecture Overview When discussing processor design, it is important to understand t he t e r m s a r ch i t e c t u re , m i c r o a r ch i t e c t u re , a n d d e s i g n implementation. The term architecture refers to the instruction set and features of a processor that are visible to software p rog ra m s r u n n in g o n t h e p ro c e s s or. The a rchit ec t u re de term ines what software the proce ssor can run. The architecture of the Mobile AMD-K6-2+ processor is the industry-standard x86 instruction set. The term microarchitecture refers to the design techniques used in the processor to reach the target cost, performance, and functionality goals. The Mobile AMD-K6 family of processors are based on a sophisticated RISC core known as the Enhanced R I S C 8 6 m i c ro a rch i t e c t u re . Th e E n h a n c e d R I S C 8 6 microarchitecture is an advanced, second-order decoupled d e c o d e / e x e c u t i o n d e s i g n a p p ro a ch t h a t e n a b l e s industry-leading performance for x86-based software. The term design implementation refers to the actual logic and circuit designs from which the processor is created according to the microarchitecture specifications. Chapter 2 Internal Architecture 5 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet Enhanced RISC86 RISC86® Microarchitecture 23446B/0-June 2000 The En h a n c e d R I S C 86 m ic ro a rch it e c t u re d e f in es t h e characteristics of the AMD-K6 family of processors. The innovative RISC86 RISC86 microarchitecture approach implements the x86 instruction set by internally translating x86 instructions into RISC86 RISC86 operations. These RISC86 RISC86 operations were specially designed to include direct support for the x86 instruction set while observing the RISC performance principles of fixed length encoding, regularized instruction fields, and a large register set. The Enhanced RISC86 RISC86 microarchitecture used in the Mobile AMD-K6-2+ processor enables higher processor core performance and promotes straightforward extensions, such as those added in the current Mobile AMD-K6-2+ processor and those planned for the future. Instead of directly executing complex x86 instructions, which have lengths of 1 to 15 bytes, the Mobile AMD-K6-2+ processor ex e c u t e s t h e s im p le r an d ea s ie r f i xe d -le n g t h R I S C 86 opera tio ns , while maintaining the instruction co ding efficiencies found in x86 programs. The Mobile AMD-K6-2+ processor contains parallel decoders, a centralized RISC86 RISC86 operation scheduler, and ten execution units that support superscalar operation - multiple decode, execution, and retirement-of x86 instructions. These elements are packed into an aggressive and highly efficient six-stage pipeline. Mobile AMD-K6®-2+ Processor Block Diagram. As shown in Figure 1 on page 7, the high-performance, out-of-order execution engine of the Mobile AMD-K6-2+ processor is mated to a split, level-one, 64-Kbyte, writeback cache with 32 Kbytes of instruction cache and 32 Kbytes of data cache. Backing up the level-one cache is a large, unified, level-two, 128-Kbyte, writeback cache. The level-one instruction cache feeds the decoders and, in turn, the decoders feed the scheduler. The ICU issues and retires RISC86 RISC86 operations contained in the scheduler. The system bus interface is an industry-standard 64-bit Super7 and Socket 7 demultiplexed bus. The Mobile AMD-K6-2+ processor combines the latest in processor microarchitecture to provide the highest x86 performance for today's personal computers. The Mobile AMD-K6-2+ processor offers true sixth-generation performance and x86 binary software compatibility. 6 Internal Architecture Chapter 2 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 32 KByte Level-One Instruction Cache 64 Entry ITLB Predecode Logic 20 KByte Predecode Cache 16 Byte Fetch Level-One Cache Controller Branch Logic (8192-Entry BHT) (16-Entry BTC) (16-Entry RAS) Dual Instruction Decoders x86 to RISC86 RISC86 100 MHz Super7TM Bus Interface Out-of-Order Execution Engine Six RISC86 RISC86® Operation Issue Level-Two Cache Load Unit (128 KByte) Store Unit Four RISC86 RISC86 Decode Scheduler Buffer (24 RISC86 RISC86) Register Unit X (Integer/ Multimedia/3DNow!TM) Instruction Control Unit Register Unit Y (Integer/ Multimedia/3DNow!) Branch Resolution Unit Floating- Point Unit Store Queue Level-One Dual-Port Data Cache (32 KByte) 128 Entry DTLB Figure 1. Mobile AMD-K6®-2+ Processor Block Diagram Decoders. Decoding of the x86 instructions begins when the on-chip level-one instruction cache is filled. Predecode logic determines the length of an x86 instruction on a byte-by-byte basis. This predecode information is stored, along with the x86 instructions, in the level-one instruction cache, to be used later by the decoders. The decoders translate on-the-fly, with no additional latency, up to two x86 instructions per clock into RISC86 RISC86 operations. Note: In this chapter, "clock" refers to a processor clock. The Mobile AMD-K6-2+ processor categorizes x86 instructions into three types of decodes-short, long, and vector. The decoders process either two short, one long, or one vector decode at a time. The three types of decodes have the following characteristics: s Short decodes-x86 instructions less than or equal to seven bytes in length s Long decodes-x86 instructions less than or equal to 11 bytes in length s Vector decodes-complex x86 instructions Chapter 2 Internal Architecture 7 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Short and long decodes are processed completely within the decoders. Vector decodes are started by the decoders and then completed by fetched sequences from an on-chip ROM. After decoding, the RISC86 RISC86 operations are delivered to the scheduler for dispatching to the executions units. Scheduler/Instruction Control Unit. The centraliz ed scheduler or buffer is managed by the Instruction Control Unit (ICU). The ICU buffers and manages up to 24 RISC86 RISC86 operations at a time. This equals from 6 to 12 x86 instructions. This buffer size (24) is perfectly matched to the processor's six-stage RISC86 RISC86 pipeline and four RISC86-operations decode rate. The scheduler accepts as many as four RISC86 RISC86 operations at a time from the decoders and retires up to four RISC86 RISC86 operations per clock cycle. The ICU is capable of simultaneously issuing up to six RISC86 RISC86 operations at a time to the execution units. This consists of the following types of operations: s Memory load operation s Memory store operation s Complex integer, MMX or 3DNow! register operation s Simple integer, MMX or 3DNow! register operation s Floating-point register operation s Branch condition evaluation Registers. When managing the 24 RISC86 RISC86 operations, the ICU uses 69 physical registers contained within the RISC86 RISC86 microarchitecture. 48 of the physical registers are located in a general register file and are grouped as 24 committed or architectural registers plus 24 rename registers. The 24 architectural registers consist of 16 scratch registers and 8 registers that correspond to the x86 general-purpose registers- EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. There is an analogous set of registers specifically for MMX and 3DNow! o p e ra t i o n s . Th e re a re 9 M M X / 3 D N ow ! c o m m i t t e d o r architectural registers plus 12 MMX/3DNow! rename registers. The 9 architectural registers consist of one scratch register and 8 registers that correspond to the MMX registers (mm0­mm7). For more detailed information, see the 3DNow!TM Technology Manual, order# 21928. 8 Internal Architecture Chapter 2 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Branch Logic. The Mobile AMD-K6-2+ processor is designed with highly sophisticated dynamic branch logic consisting of the following: s s s Branch history/Prediction table Branch target cache Return address stack The Mobile AMD-K6-2+ processor implements a two-level branch prediction scheme based on an 8192-entry branch history table. The branch history table stores prediction information that is used for predicting conditional branches. Because the branch history table does not store predicted target addresses, special address ALUs calculate target addresses on-the-fly during instruction decode. The branch target cache augments predicted branch performance by avoiding a one clock cache-fetch penalty. This specialized target cache does this by supplying the first 16 bytes of target instructions to the decoders when branches are predicted. The return address stack is a unique device specifically designed for optimizing CALL and RETURN pairs. In summary, the Mobile AMD-K6-2+ processor uses dynamic branch logic to minimize delays due to the branch instructions that are common in x86 software. 3DNow!TM Technology. AMD has taken a lead role in improving the multimedia and 3D capabilities of the x86 processor family with the introduction of 3DNow! technology, which uses a packed, single-precision, floating-point data format and Single Instruction Multiple Data (SIMD) operations based on the MMX technology model. 2.3 Cache, Instruction Prefetch, and Predecode Bits The writeback level-one cache on the Mobile AMD-K6-2+ processor is organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way set associativity. The level-two cache is 128 Kbytes, and is organized as a unified, fourway set-associative cache. The cache line size is 32 bytes, and lines are fetched from external memory using an efficient pipelined burst transaction. As the level-one instruction cache is filled from the level-two cache or from external memory, each instruction byte is analyzed for instruction boundaries using predecoding logic. Predecoding annotates information (5 bits Chapter 2 Internal Architecture 9 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 per byte) to each instruction byte that later enables the d e co de rs t o e f f i ci e n t ly d e c o d e mul t i pl e i ns t r u c t i o n s simultaneously. Cache The processor cache design takes advantage of a sectored organization (see Figure 2). Each sector consists of 64 bytes configured as two 32-byte cache lines. The two cache lines of a sector share a common tag but have separate pairs of MESI (Modified, Exclusive, Shared, Invalid) bits that track the state of each cache line. Two forms of cache misses and associated cache fills can take place-a tag-miss cache fill and a tag-hit cache fill. In the case of a tag-miss cache fill, the level-one cache miss is due to a tag mismatch, in which case the required cache line is filled either from the level-two cache or from external memory, and the level-one cache line within the sector that was not required is marked as invalid. In the case of a tag-hit cache fill, the address matches the tag, but the requested cache line is marked as invalid. The required level-one cache line is filled from the level-two cache or from external memory, and the level-one cache line within the sector that is not required remains in the same cache state. Prefetching The Mobile AMD-K6-2+ processor conditionally performs cache prefetching which results in the filling of the required cache line first, and a prefetch of the second cache line making up the other half of the sector. From the perspective of the external bus, the two cache-line fills typically appear as two 32-byte burst read cycles occurring back-to-back or, if allowed, as pipelined cycles. The 3DNow! technology includes an instruction called PREFETCH that allows a cache line to be prefetched into the level-one data cache and the level-two cache. The PREFETCH instr ucti on fo rmat is defined in Table 1 5, "3DNow !TM Technology Instructions," on page 83. For more detailed information, see the 3DNow!TM Technology Manual, order# 21928. Predecode Bits 10 Decoding x86 instructions is particularly difficult because the instructions are variable-length and can be from 1 to 15 bytes long. Predecode logic supplies the five predecode bits that are associated with each instruction byte. The predecode bits indicate the number of bytes to the start of the next x86 instruction. The predecode bits are stored in an extended Internal Architecture Chapter 2 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 instruction cache alongside each x86 instruction byte as shown in Figure 2. The predecode bits are passed with the instruction bytes to the decoders where they assist with parallel x86 instruction decoding. Tag Address Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits . . Byte 0 Predecode Bits MESI Bits Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits . . Byte 0 Predecode Bits MESI Bits Figure 2. Cache Sector Organization 2.4 Instruction Fetch and Decode Instruction Fetch The processor can fetch up to 16 bytes per clock out of the levelone instruction cache or branch target cache. The fetched information is placed into a 16-byte instruction buffer that feeds directly into the decoders (see Figure 3 on page 12). Fetching can occur along a single execution stream with up to seven outstanding branches taken. The instruction fetch logic is capable of retrieving any 16 contiguous bytes of information within a 32-byte boundary. There is no additional penalty when the 16 bytes of instructions lie across a cache line boundary. The instruction bytes are loaded into the instruction buffer as they are consumed by the decoders. Although instructions can be consumed with byte g ra nu l a r i t y, t h e i n s t r u c t i o n b u f f e r i s m a n a g e d o n a memory-aligned word (two bytes) organization. Therefore, instructions are loaded and replaced with word granularity. When a control transfer occurs -such as a JMP instruction- the entire instruction buffer is flushed and reloaded with a new set of 16 instruction bytes. Chapter 2 Internal Architecture 11 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 16 Bytes 32-Kbyte Level-One Instruction Cache Branch-Target Cache 16 x 16 Bytes 16 Bytes 2:1 Branch Target Address Adders Return Address Stack 16 x 16 Bytes Fetch Unit 16 Instruction Bytes plus 16 Sets of Predecode Bits Instruction Buffer Figure 3. The Instruction Buffer Instruction Decode The Mobile AMD-K6-2+ processor decode logic is designed to decode multiple x86 instructions per clock (see Figure 4 on page 13). The decode logic accepts x86 instruction bytes and their predecode bits from the instruction buffer, locates the actual inst ruct io n boundaries, and g ene rat es RI SC86 operations from these x86 instructions. RISC86 RISC86 operations are fixed-length internal instructions. Most RISC86 RISC86 operations execute in a single clock. RISC86 RISC86 operations are combined to perform every function of the x86 instruction set. Some x86 instructions are decoded into as few as zero RISC86 RISC86 operations - for instance a NOP - or one RISC86 RISC86 operation - a register-to-register add. More complex x86 instructions are decoded into several RISC86 RISC86 operations. 12 Internal Architecture Chapter 2 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Instruction Buffer Short Decoder #1 Short Decoder #2 Long Decoder On-Chip ROM Vector Decoder RISC86 RISC86® Sequencer Vector Address 4 RISC86 RISC86 Operations Figure 4. Mobile AMD-K6®-2+ Processor Decode Logic The Mobile AMD-K6-2+ processor uses a combination of decoders to convert x86 instructions into RISC86 RISC86 operations. The hardware consists of three sets of decoders-two parallel short decoders, one long decoder, and one vector decoder. The two parallel short decoders translate the most commonly-used x86 instructions ( moves, shifts, branches, ALU, FPU) and the extensions to the x86 instruction set (including MMX and 3DNow! instructions) into zero, one, or two RISC86 RISC86 operations each. The short decoders only operate on x86 instructions that are up to seven bytes long. In addition, they are designed to d e c o d e u p t o t w o x 8 6 i n s t r u c t i o n s p e r c l o ck . T h e commonly-used x86 instructions that are greater than seven bytes but not more than 11 bytes long, and semi-commonly-used x86 instructions that are up to seven bytes long are handled by the long decoder. Chapter 2 Internal Architecture 13 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 The long decoder only performs one decode per clock and generates up to four RISC86 RISC86 operations. All other translations (complex instructions, serializing conditions, interrupts and exceptions, etc.) are handled by a combination of the vector decoder and RISC86 RISC86 operation sequences fetched from an on-chip ROM. For complex operations, the vector decoder logic provides the first set of RISC86 RISC86 operations and a vector (initial ROM address) to a sequence of further RISC86 RISC86 operations. The same types of RISC86 RISC86 operations are fetched from the ROM as those that are generated by the hardware decoders. Note: Although all three sets of decoders are simultaneously fed a copy of the instruction buffer contents, only one of the three types of decoders is used during any one decode clock. The decoders or the on-chip RISC86 RISC86 ROM always generate a group of four RISC86 RISC86 operations. For decodes that cannot fill the entire group with four RISC86 RISC86 operations, RISC86 RISC86 NOP operations are placed in the empty locations of the grouping. For example, a long-decoded x86 instruction that converts to only three RISC86 RISC86 operations is padded with a single RISC86 RISC86 NOP operation and then passed to the scheduler. Up to six groups or 24 RISC86 RISC86 operations can be placed in the scheduler at a time. All of the common, and a few of the uncommon, floating-point instructions (also known as ESC instructions) are hardware decoded as short decodes. This decode generates a RISC86 RISC86 floating-point operation and, optionally, an associated floating-point load or store operation. Floating-point or ESC instruction decode is only allowed in the first short decoder, but non-ESC instructions can be decoded simultaneously by the second short decoder along with an ESC instruction decode in the first short decoder. All of the MMX and 3DNow! instructions, with the exception of the EMMS, FEMMS, and PREFETCH instructions, are hardware decoded as short decodes. The MMX instruction decode generates a RISC86 RISC86 MMX operation and, optionally, an associated MMX load or store operation. A 3DNow! instruction decode generates a RISC86 RISC86 3DNow! operation and, optionally, an associated load or store operation. MMX and 3DNow! instructions can be decoded in either or both of the short decoders. 14 Internal Architecture Chapter 2 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 2.5 Centralized Scheduler The scheduler is the heart of the Mobile AMD-K6-2+ processor (see Figure 5 on page 16). It contains the logic necessary to manage out-of-order execution, data forwarding, register renaming, simultaneous issue and retirement of multiple RISC86 RISC86 operations, and speculative execution. The scheduler's buffer can hold up to 24 RISC86 RISC86 operations. This equates to a maximum of 12 x86 instructions. The scheduler can issue RISC86 RISC86 operations from any of the 24 locations in the buffer. When possible, the scheduler can simultaneously issue a RISC86 RISC86 operation to any available execution unit (store, load, branch, register X integer/multimedia, register Y integer/multimedia, or floating-point). In total, the scheduler can issue up to six and retire up to four RISC86 RISC86 operations per clock. The main advantage of the scheduler and its operation buffer is the ability to examine an x86 instruction window equal to 12 x86 instructions at one time. This advantage is due to the fact that the scheduler operates on the RISC86 RISC86 operations in parallel and allows the Mobile AMD-K6-2+ processor to perform dynamic on-the-fly instruction code scheduling for optimized execution. Although the scheduler can issue RISC86 RISC86 operations for out-of-order execution, it always retires x86 instructions in order. Chapter 2 Internal Architecture 15 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 From Decode Logic RISC86 RISC86 #0 RISC86 RISC86 #1 RISC86 RISC86 #2 Centralized RISC86 RISC86® Operation Scheduler RISC86 RISC86 #3 RISC86 RISC86 Issue Buses RISC86 RISC86 Operation Buffer Figure 5. Mobile AMD-K6®-2+ Processor Scheduler 2.6 Execution Units The Mobile AMD-K6-2+ processor contains ten parallel execution units- store, load, integer X ALU, integer Y ALU, MMX ALU (X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU, floating-point, and branch condition. Each unit is independent and capable of handling the RISC86 RISC86 operations. Table 1 on page 17 details the execution units, functions performed within these units, operation latency, and operation throughput. The store and load execution units are two-stage pipelined designs. The store unit performs data writes and register calculation for LEA/PUSH. Data memory and register writes from stores are available after one clock. Store operations are held in a store queue prior to execution. From there, they execute in order. The load unit performs data memory reads. Data is available from the load unit after two clocks. 16 Internal Architecture Chapter 2 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 The I nt eg er X execution unit can operat e on all AL U operations, multiplies, divides (signed and unsigned), shifts, and rotates. The Integer Y execution unit can operate on the basic word and doubleword ALU operations - ADD, AND, CMP, OR, SUB, XOR, zero-extend and sign-extend operands. Table 1. Execution Latency and Throughput of Execution Units Functional Unit Function Latency Throughput LEA/PUSH, Address (Pipelined) 1 1 Memory Store (Pipelined) 1 1 Memory Loads (Pipelined) 2 1 Integer ALU 1 1 2­3 2­3 1 1 MMX ALU Multimedia (processes MMX Shifts, Packs, Unpack MMX instructions) MMX Multiply 1 1 1 1 2 1 Integer Y Basic ALU (16-bit and 32-bit operands) 1 1 Branch Resolves Branch Conditions 1 1 FPU FADD, FSUB, FMUL 2 2 3DNow! ALU 2 1 3DNow! Multiply 2 1 3DNow! Convert 2 1 Store Load Integer X Integer Multiply Integer Shift 3DNow! Register X and Y Pipelines The fu nct io nal unit s t ha t ex ec ut e M MX and 3 D N ow! instructions share pipeline control with the Integer X and Integer Y units. The register X and Y functional units are attached to the issue bus for the register X execution pipeline or the issue bus for the register Y execution pipeline or both. Each register pipeline has dedicated resources that consist of an integer execution unit and an MMX ALU execution unit, therefore allowing superscalar operation on integer and MMX instructions. In addition, both the X and Y issue buses are connected to the 3DNow! ALU, the MMX/3DNow! multiplier and MMX shifter, which allows the appropriate RISC86 RISC86 operation to be issued through either bus. Figure 6 on page 18 shows the details of the X and Y register pipelines. Chapter 2 Internal Architecture 17 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Scheduler Buffer (24 RISC86 RISC86® Operations) Issue Bus for the Register X Execution Pipeline Integer X ALU MMXTM TM ALU Issue Bus for the Register Y Execution Pipeline MMX Shifter MMX/ 3DNow!TM TM Multiplier 3DNow! ALU MMX ALU Integer Y ALU Figure 6. Register X and Y Functional Units The branch condition unit is separate from the branch prediction logic in that it resolves conditional branches such as JCC and LOOP after the branch condition has been evaluated. 2.7 Branch-Prediction Logic Sophisticated branch logic that can minimize or hide the impact of changes in program flow is designed into the Mobile AMD-K6-2+ processor. Branches in x86 code fit into two categories -unconditional branches, which always change program flow (that is, the branches are always taken) and conditional branches, which may or may not divert program flow (that is, the branches are taken or not-taken). When a conditional branch is not taken, the processor simply continues decoding and executing the next instructions in memory. Typical applications have up to 10% of unconditional branches and another 10% to 20% conditional branches. The Mobile AMD-K6-2+ processor branch logic has been designed to handle 18 Internal Architecture Chapter 2 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 this type of program behavior and its negative effects on instruction execution, such as stalls due to delayed instruction fetching and the draining of the processor pipeline. The branch logic contains an 8192-entry branch history table, a 16-entry by 16-byte branch target cache, a 16-entry return address stack, and a branch execution unit. Branch History Table The Mobile AMD-K6-2+ processor handles unconditional branches without any penalty by redirecting instruction fetching to the target address of the unconditional branch. However, conditional branches require the use of the dynamic branch-prediction mechanism built into the Mobile AMD-K6-2+ p ro c e s s o r. A t wo -l eve l a d a p t ive h i s t o ry a l g o r i t h m i s implemented in an 8192-entry branch history table. This table stores executed branch information, predicts individual branches, and predicts the behavior of groups of branches. To accommodate the large branch history table, the Mobile AMD -K6-2+ processor does not st ore predict ed target addresses. Instead, the branch target addresses are calculated on-the-fly using ALUs during the decode stage. The adders calculate all possible target addresses before the instructions are fully decoded and the processor chooses which addresses are valid. Branch Target Cache To avoid a one clock cache-fetch penalty when a branch is predicted taken, a built-in branch target cache supplies the first 16 bytes of instructions directly to the instruction buffer (assuming the target address hits this cache). (See Figure 3 on page 12.) The branch target cache is organized as 16 entries of 16 bytes. In total, the branch prediction logic achieves branch prediction rates greater than 95%. Return Address Stack The return address stack is a special device designed to optimize CALL and RET pairs. Software is typically compiled with subroutines that are frequently called from various places in a program. This is usually done to save space. Entry into the subroutine occurs with the execution of a CALL instruction. At that time, the processor pushes the address of the next instruction in memory following the CALL instruction onto the stack (allocated space in memory). When the processor encounters a RET instruction (within or at the end of the subroutine), the branch logic pops the address from the stack and begins fetching from that location. To avoid the latency of Chapter 2 Internal Architecture 19 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 main memory accesses during CALL and RET operations, the return address stack caches the pushed addresses. Branch Execution Unit 20 The branch execution unit enables efficient speculative execution. This unit gives the processor the ability to execute instructions beyond conditional branches before knowing whether the branch prediction was correct. The Mobile AMD-K6-2+ processor does not permanently update the x86 registers or memory locations until all speculatively executed conditional branch instructions are resolved. When a prediction is incorrect, the processor backs out to the point of the mispredicted branch instruction and restores all registers. The Mobile AMD-K6-2+ processor can support up to seven outstanding branches. Internal Architecture Chapter 2 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 3 Software Environment This chapter provides a general overview of the Mobile AMD-K6-2+ processor's x86 software environment and briefly describes the data types, registers, operating modes, interrupts, and instructions supported by the Mobile AMD-K6-2+ processor architecture and design implementation. The Mobile AMD-K6-2+ processor implements the same ten MSRs as the Mobile AMD-K6-2-P processor Model 8, and the bits and fields within these ten MSRs are defined identically. The Mobile AMD-K6-2+ processor supports two additional MSRs for a total of twelve MSRs. See "Model-Specific Registers (MSR)" on page 37 for the MSR definitions. 3.1 Registers The Mobile AMD-K6-2+ processor contains all the registers defined by the x86 architecture, including general-purpose, segment, floating-point, MMX/3DNow! technology, EFLAGS, control, task, debug, test, and descriptor/memory-management registers. In addition, this chapter provides information on the Mobile AMD-K6-2+ processor MSRs. Note: Areas of the register designated as Reserved should not be modified by software. Chapter 3 Software Environment 21 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet General-Purpose Registers 23446B/0-June 2000 The eight 32-bit x86 general-purpose registers are used to hold integer data or memory pointers used by instructions. Table 2 contains a list of the general-purpose registers and the functions for which they are used. Table 2. General-Purpose Registers Register Function EAX Commonly used as an accumulator EBX Commonly used as a pointer ECX Commonly used for counting in loop operations EDX Commonly used to hold I/O information and to pass parameters EDI Commonly used as a destination pointer by the ES segment ESI Commonly used as a source pointer by the DS segment ESP Used to point to the stack segment EBP Used to point to data within the stack segment In order to support byte and word operations, EAX, EBX, ECX, and EDX can also be used as 8-bit and 16-bit registers. The shorter registers are overlaid on the longer ones. For example, the name of the 16-bit version of EAX is AX (low 16 bits of EAX) and the 8-bit names for AX are AH (high order bits) and AL (low order bits). The same naming convention applies to EBX, ECX, and EDX. EDI, ESI, ESP, and EBP can be used as smaller 16-bit registers called DI, SI, SP, and BP respectively, but these registers do not have 8-bit versions. Figure 7 shows the EAX register with its name components, and Table 3 lists the doubleword (32-bit) general-purpose registers and their corresponding word (16-bit) and byte (8-bit) versions. 31 16 15 8 7 0 EAX AX AH AL Figure 7. EAX Register with 16-Bit and 8-Bit Name Components 22 Software Environment Chapter 3 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Table 3. General-Purpose Register Doubleword, Word, and Byte Names 32-Bit Name (Doubleword) EAX AX AH AL EBX BX BH BL ECX CX CH CL EDX DX DH DL EDI DI ­ ­ ESI SI ­ ­ ESP SP ­ ­ EBP Integer Data Types 16-Bit Name (Word) 8-Bit Name 8-Bit Name (High-order Bits) (Low-order Bits) BP ­ ­ Four types of data are used in general-purpose registers-byte, word, doubleword, and quadword integers. Figure 8 shows the format of the integer data registers. Byte Integer 7 0 Precision - 8 Bits Word Integer 15 0 Precision - 16 Bits Doubleword Integer 31 0 Precision - 32 Bits Quadword Integer 63 0 Precision - 64 Bits Figure 8. Integer Data Registers Chapter 3 Software Environment 23 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet Segment Registers 23446B/0-June 2000 The six 16-bit segment registers are used as pointers to areas (segments) of memory. Table 4 lists the segment registers and their functions. Figure 9 shows the format for all six segment registers. Table 4. Segment Register Segment Registers Segment Register Function CS Code segment, where instructions are located DS Data segment, where data is located ES Data segment, where data is located FS Data segment, where data is located GS Data segment, where data is located SS Stack segment 15 0 Figure 9. Segment Register Segment Usage 24 The operating system determines the type of memory model that is implemented. The segment register usage is determined by the operating system's memory model. In a Real mode memory model the segment register points to the base address in memory. In a Protected mode memory model the segment register is called a selector and it selects a segment descriptor in a descriptor table. This descriptor contains a pointer to the base of the segment, the limit of the segment, and various protection attributes. For more information on descriptor formats, see "Descriptors and Gates" on page 51. Figure 10 on page 25 shows segment usage for Real mode and Protected mode memory models. Software Environment Chapter 3 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Physical Memory Segment Base Segment Register Real Mode Memory Model Descriptor Table Physical Memory Base Limit Base Base Limit Segment Base Segment Selector Protected Mode Memory Model Figure 10. Segment Usage Instruction Pointer The instruction pointer (EIP or IP) is used in conjunction with the code segment register (CS). The instruction pointer is either a 32-bit register (EIP) or a 16-bit register (IP) that keeps track of where the next instruction resides within memory. This register cannot be directly manipulated, but can be altered by modifying return pointers when a JMP or CALL instruction is used. Floating-Point Registers The floating-point execution unit in the Mobile AMD-K6-2+ processor is designed to perform mathematical operations on non-integer numbers. This floating-point unit conforms to the IEEE 754 and 854 standards and uses several registers to meet these standards - eight numeric floating-point registers, a status word register, a control word register, and a tag word register. Chapter 3 Software Environment 25 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 The eight floating-point registers are physically 80 bits wide and labeled FPR0­FPR7. Figure 11 shows the format of these floating-point registers. See "Floating-Point Register Data Types" on page 28 for information on allowable floating-point data types. 79 78 64 63 Sign 0 Exponent Significand Figure 11. Floating-Point Register The 16-bit FPU status word register contains information about the state of the floating-point unit. Figure 12 shows the format of this register. 15 14 13 12 11 10 9 8 B Symbol B C3 TOSP C2 C1 C0 ES SF PE UE OE ZE DE IE C 3 TOSP C 2 C C 1 0 7 6 5 4 3 2 1 0 E S S F P U O Z E E E E D E I E Description Bits FPU Busy 15 Condition Code 14 Top of Stack Pointer 13­11 Condition Code 10 Condition Code 9 Condition Code 8 Error Summary Status 7 Stack Fault 6 Exception Flags Precision Error 5 Underflow Error 4 Overflow Error 3 Zero Divide Error 2 Denormalized Operation Error 1 Invalid Operation Error 0 TOSP Information 000 = FPR0 111 = FPR7 Figure 12. FPU Status Word Register 26 Software Environment Chapter 3 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 The FPU control word register allows a programmer to manage the FPU processing options. Figure 13 shows the format of this register. 15 14 13 12 11 10 9 8 Y R C 7 P C 6 5 4 3 2 1 0 P U O Z D I M M M M M M Reserved Symbol Y RC PC PM UM OM ZM DM IM Description Infinity Bit (80287 compatibility) Rounding Control Precision Control Exception Masks Precision Underflow Overflow Zero Divide Denormalized Operation Invalid Operation Bits 12 11­10 9­8 5 4 3 2 1 0 Rounding Control Information 00b = Round to the nearest or even number 01b = Round down toward negative infinity 10b = Round up toward positive infinity 11b = Truncate toward zero Precision Control Information 00b = 24 bits Single Precision Real 01b = Reserved 10b = 53 bits Double Precision Real 11b = 64 bits Extended Precision Real Figure 13. FPU Control Word Register The FPU tag word register contains information about the registers in the register stack. Figure 14 shows the format of this register. 15 14 13 TAG (FPR7) 12 11 TAG (FPR6) 10 9 TAG (FPR5) 87 TAG (FPR4) 65 TAG (FPR3) 43 TAG (FPR2) 21 TAG (FPR1) 0 TAG (FPR0) Tag Values 00 = Valid 01 = Zero 10 = Special 11 = Empty Figure 14. FPU Tag Word Register Chapter 3 Software Environment 27 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet Floating-Point Register Data Types 79 78 S 23446B/0-June 2000 Floating-point registers use four different types of data - packed decimal, single-precision real, double-precision real, and extended-precision real. Figures 15 and 16 show the formats for these registers. 72 71 0 Ignore or Zero Precision - 18 Digits, 72 Bits Used, 4-Bits/Digit Description Bits Ignored on Load, Zeros on Store 78-72 Sign Bit 79 Figure 15. Packed Decimal Data Register 31 30 Single-Precision Real S 23 22 0 Biased Exponent Significand S = Sign Bit Double-Precision Real 52 51 63 62 S 0 Biased Exponent Significand S = Sign Bit Extended-Precision Real 79 78 S 64 63 62 Biased Exponent S = Sign Bit 0 I Significand I = Integer Bit Figure 16. Precision Real Data Registers 28 Software Environment Chapter 3 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 MMXTM/3DNow!TM Technology Registers The Mobile AMD-K6-2+ processor implements eight 64-bit MMX/3DNow! registers for use by multimedia software. These registers are mapped on the floating-point register stack. The MMX and 3DNow! instructions refer to these registers as mm0 to mm7. Figure 17 shows the format of these registers. For more information, see the AMD-K6® Processor Multimedia Technology Manual, order# 20726 and the 3DNow!TM Technology Manual, order# 21928. 63 0 mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7 Figure 17. MMXTM/3DNow!TM Technology Registers MMXTM Technology Data Types Chapter 3 For the MMX instructions, the MMX registers use three types of data-packed eight-byte integer, packed quadword integer, and packed dual doubleword integer. Figure 18 on page 30 shows the format of these data types. Software Environment 29 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 Packed Bytes Integer 63 56 55 Byte 7 48 47 Byte 6 40 39 Byte 5 32 31 Byte 4 24 23 Byte 3 16 15 Byte 2 8 0 7 Byte 1 Byte 0 Packed Words Integer 63 48 47 Word 3 32 31 16 Word 2 0 15 Word 1 Word 0 Packed Doubleword Integer 63 32 0 31 Doubleword 1 Doubleword 0 Figure 18. MMXTM Technology Data Types 3DNow!TM Technology Data Types For 3DNow! instructions, the MMX/3DNow! registers use packed single-precision real data. Figure 19 shows the format of the 3DNow! data type. Packed Single Precision Floating Point 63 62 S 55 54 32 31 30 Biased Exponent S Significand 0 23 22 Biased Exponent S = Sign Bit Significand S = Sign Bit Figure 19. 3DNow!TM Technology Data Types 30 Software Environment Chapter 3 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet 23446B/0-June 2000 EFLAGS Register The EFLAGS register provides for three different types of flags - system, control, and status. The system flags provide operating system controls, the control flag provides directional information for string operations, and the status flags provide information resulting from logical and arithmetic operations. Figure 20 shows the format of this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 V I I D P V I F A V R C M F N T I O P L O D F F I F 8 7 6 T F S F Z F 5 4 A F 3 2 P F 1 0 C F Reserved Symbol ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF Description Bits ID Flag 21 Virtual Interrupt Pending 20 Virtual Interrupt Flag 19 Alignment Check 18 Virtual-8086 Mode 17 Resume Flag 16 Nested Task 14 I/O Privilege Level 13­12 Overflow Flag 11 Direction Flag 10 Interrupt Flag 9 Trap Flag 8 Sign Flag 7 Zero Flag 6 Auxiliary Flag 4 Parity Flag 2 Carry Flag 0 Figure 20. EFLAGS Registers Chapter 3 Software Environment 31 Preliminary Information Mobile AMD-K6®-2+ Processor Data Sheet Control Registers 23446B/0-June 2000 The five co