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Mamba (AM8629x) July 9, 2009 AMCC Confidential ­ For AMCC Sales Staff Internal Review Only AM8218x ("Maui")

 

Preview of Maui (AM8218x) and Mamba (AM8629x) July 9, 2009 AMCC Confidential ­ For AMCC Sales Staff Internal Review Only AM8218x ("Maui") Processor 16/32bit w/ECC HSS x1 DDR2 SDRAM Controller HSS x1 4 External Channels EBC DMA Controller SATA SATA/ PCIe 32KB OCM RAID5 XOR PLB4 128b 2-way crossbar 256KB 256KB L2 Cache 32K I-Cache TRNG PKA 32K D-Cache MMU Turbo Security Engine MAL USB2.0 OTG TCP/IP Assist 464 CPU with FPU JTAG Trace PHY UIC On-Chip Peripheral Bus (OPB) 100MHz Max. CPU Complex 464 processor core Core speeds of 800MHz and 1GHz Up to 2000 DMIPS 32KB I-cache/32KB D-cache 256KB 256KB L2 cache with parity Integrated FPU Memory and Bus Architecture 32-bit DDR2 SDRAM controller with ECC, supports both x16 or x32, up to 512MB 512MB memory bank 8-bit NAND/eNAND Flash controller 32KB On-Chip Memory (OCM) 8-bit External Peripheral Bus Controller (EBC) with two chip-select System Resources Universal Interrupt Controller: TBD external interrupts Up to TBD general purpose I/Os DMA Controller with four independent channels Real Time Clock (RTC) with battery backup High Speed & Inter-Chip Connectivity Single PCI Express x1, SERDES shared with second SATA controller Two x1 SATA controllers (SATA 1.0 and 2.0 compliant) Network Connectivity One 10/100/1G 10/100/1G Ethernet MACs supporting RGMII/MII Integrated TCP/IP (TOE) engine One USB2.0 On-the-Go port with integrated PHY, both host and device modes supported Two UARTs Special Functionality Turbo Security Engine: Optional on-chip IPSec/SSL/bulk data security acceleration engine (Crypto Engine) RAID5 XOR engine Power TBDW est. typical power @ 800 MHz CPU NAND FlashCtrl RTC UARTs IICs GPIOs GPT 10/100/1G 10/100/1G Ethernet MAC SPI Package Options: 18x18mm Wirebond FPBGA , 0.8mm pitch Target Applications Network Attached Storage (NAS) AMCC CONFIDENTIAL ­ PRELIMINARY AND SUBJECT TO CHANGE APPLIED MICRO PROPRIETARY AND CONFIDENTIAL Page 2 AM8629x ("Mamba") Processor NAND NOR SDIO 2GE Ethernet PKA/ TRNG OPB Bridge TOE Pre-Classifier CCF High Bandwidth Fabric 256KB 256KB L2 256KB 256KB L2 32K 32K I-Cache D-Cache 32K 32K I-Cache D-Cache 464 Core with FPU 32KB OCM Queue Manager Traffic Manager DMA XOR 464 Core with FPU Interrupt Package Options: 27mm² Debug/ FCBGA Controller Trace Security On-Chip Peripheral Bus (AHB) IEEE 1588 LCD x1 PCIe/SATA DDR2/3 SDRAM Controller x1/x4 PCIe/Trace Serial Interfaces 32bit/ 16bit x1 PCIe/SATA CPU Complex 464 processor core Core speeds of 600MHz, 800MHz, and 1GHz Integrated FPU 32KB I-Cache and 32KB D-Cache with parity 256KB 256KB L2 cache per core Symmetric Multiprocessing (SMP) support Memory and Bus Architecture 32-bit DDR2/3 SDRAM controller, supports both x16 or x32 NAND/eNAND and NOR Flash controllers 32KB On-Chip Memory (OCM) High Speed & Inter-Chip Connectivity 2x GE ports (RGMII) IEEE 1588 support Hardware NAT 3x PCI-e ports: Two x1 Gen1/2 and one x1/x4 Gen 1/2 2xSATA (SERDES shared with PCIe) 2x USB interfaces (one OTG) with integrated PHY System Resources Universal Interrupt Controller: TBD external interrupts Up to TBD general purpose I/Os DMA Controller Real Time Clock (RTC) with battery backup Integrated SDIO interface Integrated LCD controller Support for hardware Java Virtual Machine One two-channel TDM interface Special Functionality Integrated security engine Hardware acceleration for RAID5/6 Advanced Power Management Queue Manager/Traffic Manager Hardware-based packet classifier. Power TBDW typical power UART (2) IIC SPI 2xTDM USB OTG + PHY USB H/D + PHY Power Mgmt RTC Core Complex Target Applications Wireless LAN Access Points Network Attached Storage (NAS) Residential Gateways Multi-Function Printers AMCC CONFIDENTIAL ­ PRELIMINARY AND SUBJECT TO CHANGE APPLIED MICRO PROPRIETARY AND CONFIDENTIAL Page 3