AM1707 SPRS637B ARM926EJ-STM 128MB 256MB ARM926EJ-S SPRS637A 168KB 128KB ARM926 - Datasheet Archive

 

www.ti.com SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 AM1707 ARM Microprocessor Check for Samples: AM1707 1 AM1707

 

AM1707 AM1707 www.ti.com SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 AM1707 AM1707 ARM Microprocessor Check for Samples: AM1707 AM1707 1 AM1707 AM1707 ARM Microprocessor 1.1 Features · Highlights ­ 375/456-MHz ARM926EJ-STM ARM926EJ-STM RISC Core ­ ARM9 Memory Architecture ­ Programmable Real-Time Unit Subsystem ­ Enhanced Direct-Memory-Access Controller 3 (EDMA3) ­ Two External Memory Interfaces ­ Three Configurable 16550 type UART Modules ­ Two Serial Peripheral Interfaces (SPI) ­ Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) ­ Two Master/Slave Inter-Integrated Circuit ­ USB 2.0 OTG Port With Integrated PHY ­ Three Multichannel Audio Serial Ports ­ 10/100 Mb/s Ethernet MAC (EMAC) ­ One 64-Bit General-Purpose Timer ­ One 64-bit General-Purpose/Watchdog Timer ­ Three Enhanced Pulse Width Modulators ­ Three 32-Bit Enhanced Capture Modules · Applications ­ Industrial Automation ­ Home Automation ­ Test and Measurement ­ Portable Data Terminals ­ Educational Consoles ­ Power Protection Systems · 375/456-MHz ARM926EJ-STM ARM926EJ-STM RISC Core ­ 32-Bit and 16-Bit (Thumb®) Instructions ­ Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 16K-Byte Data Cache ­ 8K-Byte RAM (Vector Table) ­ 64K-Byte ROM · Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Transfer Controllers · · · · · · · · · ­ 32 Independent DMA Channels ­ 8 Quick DMA Channels ­ Programmable Transfer Burst Size 128K-Byte RAM Memory 3.3V LVCMOS IOs (except for USB interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128MB 128MB Address Space ­ EMIFB · 32-Bit or 16-Bit SDRAM With 256MB 256MB Address Space Three Configurable 16550 type UART Modules: ­ UART0 With Modem Control Signals ­ 16-byte FIFO ­ 16x or 13x Oversampling Option ­ Autoflow control signals (CTS, RTS) on UART0 only LCD Controller Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select Programmable Real-Time Unit Subsystem (PRUSS) ­ Two Independent Programmable Realtime Unit (PRU) Cores · 32-Bit Load/Store RISC architecture · 4K Byte instruction RAM per core · 512 Bytes data RAM per core · PRU Subsystem (PRUSS) can be disabled via software to save power ­ Standard power management mechanism · Clock gating · Entire subsystem under a single PSC clock gating domain ­ Dedicated interrupt controller ­ Dedicated switched central resource Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Two Master/Slave Inter-Integrated Circuit (I2C 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM926EJ-S ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited. ARM, Jazelle are registered trademarks of ARM Limited. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 2010, Texas Instruments Incorporated ADVANCE INFORMATION 123 AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com ADVANCE INFORMATION BusTM) · One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth · USB 1.1 OHCI (Host) With Integrated PHY (USB1) · USB 2.0 OTG Port With Integrated PHY (USB0) ­ USB 2.0 High-/Full-Speed Client ­ USB 2.0 High-/Full-/Low-Speed Host ­ End Point 0 (Control) ­ End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx · Three Multichannel Audio Serial Ports: ­ Six Clock Zones and 28 Serial Data Pins ­ Supports TDM, I2S, and Similar Formats ­ DIT-Capable (McASP2) ­ FIFO buffers for Transmit and Receive · 10/100 Mb/s Ethernet MAC (EMAC): ­ IEEE 802.3 Compliant (3.3-V I/O Only) ­ RMII Media Independent Interface ­ Management Data I/O (MDIO) Module · Real-Time Clock With 32 KHz Oscillator and Separate Power Rail · One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers) · One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose 2 Timers) · Three Enhanced Pulse Width Modulators (eHRPWM): ­ Dedicated 16-Bit Time-Base Counter With Period And Frequency Control ­ 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs ­ Dead-Band Generation ­ PWM Chopping by High-Frequency Carrier ­ Trip Zone Input · Three 32-Bit Enhanced Capture Modules (eCAP): ­ Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs ­ Single Shot Capture of up to Four Event Time-Stamps · Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP) · 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch · Commercial, Industrial, Automotive or Extended Temperature · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki AM1707 AM1707 ARM Microprocessor Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 1.2 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Trademarks ADVANCE INFORMATION All trademarks are the property of their respective owners. AM1707 AM1707 ARM Microprocessor Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 3 AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 1.3 www.ti.com Description The device is a low-power ARM microprocessor based on an ARM926EJ-STM ARM926EJ-STM. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The ARM926EJ-S ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM. ADVANCE INFORMATION The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The device has a complete set of development tools for the ARM. These include C compilers and a WindowsTM debugger interface for visibility into source code execution. 4 AM1707 AM1707 ARM Microprocessor Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 1.4 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Functional Block Diagram JTAG Interface ARM Subsystem System Control ARM926EJ-S ARM926EJ-S CPU With MMU PLL/Clock Generator w/OSC Input Clock(s) GeneralPurpose Timer GeneralPurpose Timer (Watchdog) 4 KB ETB 16 KB 16 KB I-Cache D-Cache Power/Sleep Controller RTC/ Pin 32-KHz Multiplexing OSC 8 KB RAM (Vector Table) 64 KB ROM Switched Central Resource (SCR) Peripherals GPIO McASP w/FIFO (3) EDMA3 I2C (2) eCAP (3) SPI (2) UART (3) PRU Subsystem Connectivity Control Timers eHRPWM (3) Customizable Interface Serial Interfaces Audio Ports eQEP (2) USB2.0 OTG Ctlr PHY USB1.1 OHCI Ctlr PHY (10/100) EMAC (RMII) MDIO Display Internal Memory LCD Ctlr 128 KB RAM ADVANCE INFORMATION DMA External Memory Interfaces HPI MMC/SD (8b) EMIFA(8b/16B) NAND/Flash 16b SDRAM EMIFB SDRAM Only (16b/32b) AM1707 AM1707 ARM Microprocessor Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 5 AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 1 2 3 4 ADVANCE INFORMATION 5 www.ti.com . 1 1.1 Features . 1 1.2 Trademarks . 3 1.3 Description . 4 1.4 Functional Block Diagram . 5 Revision History . 7 Device Overview . 8 3.1 Device Characteristics . 8 3.2 Device Compatibility . 9 3.3 ARM Subsystem . 9 3.4 Memory Map Summary . 12 3.5 Pin Assignments . 15 3.6 Terminal Functions . 16 Device Configuration . 34 4.1 Boot Modes . 34 4.2 SYSCFG Module . 35 4.3 Pullup/Pulldown Resistors . 37 Device Operating Conditions . 38 AM1707 AM1707 ARM Microprocessor 6 6.14 6.15 6.16 6.17 6.3 6.4 Power Supplies . 43 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations . 43 6.5 Reset 6.6 6.7 6.8 6.9 6 . Crystal Oscillator or External Clock Input . Clock PLLs . Interrupts . General-Purpose Input/Output (GPIO) . 75 82 85 88 93 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) . 95 . . 108 . 135 6.18 Serial Peripheral Interface Ports (SPI0, SPI1) 6.19 6.20 Enhanced Capture (eCAP) Peripheral 126 Enhanced Quadrature Encoder (eQEP) Peripheral . 129 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) . 131 6.21 6.22 LCD Controller 6.23 6.24 Timers . 150 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) . 152 Universal Asynchronous Receiver/Transmitter (UART) . 157 USB1 Host Controller Registers (USB1.1 OHCI) . 159 6.25 6.26 . . Power and Sleep Controller (PSC) . 6.27 USB0 OTG (USB2.0 OTG) 161 6.28 Host-Port Interface (UHPI) 169 6.29 6.30 176 Programmable Real-Time Unit Subsystem (PRUSS) . 179 . . 6.33 Real Time Clock (RTC) . Device and Documentation Support . 7.1 Device Support . 7.2 Documentation Support . 6.31 7 8 Emulation Logic 182 6.32 Peripheral Information and Electrical Specifications . 42 Parameter Information . 42 Recommended Clock and Control Signal Transition Behavior . 43 66 6.13 Recommended Operating Conditions . 39 Notes on Recommended Power-On Hours (POH) . 40 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted) . 41 6.1 6.2 61 External Memory Interface A (EMIFA) 6.12 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted) . 38 5.4 EDMA 6.11 5.1 5.2 5.3 . . External Memory Interface B (EMIFB) . Memory Protection Units . MMC / SD / SDIO (MMCSD) . Ethernet Media Access Controller (EMAC) . Management Data Input/Output (MDIO) . 6.10 IEEE 1149.1 JTAG 188 190 193 193 193 Mechanical Packaging and Orderable Information . 194 8.1 Device and Development-Support Tool Nomenclature . 194 48 8.2 Packaging Materials Information 50 8.3 54 8.4 45 . Thermal Data for ZKB . Mechanical Drawings . 194 195 195 58 Contents Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 2 Revision History This data manual revision history highlights the changes made to the SPRS637A SPRS637A device-specific data manual to make it an SPRS637B SPRS637B revision. Table 2-1. Revision History ADDITIONS/MODIFICATIONS/DELETIONS Global - Changed SPI td(SCSL_SPC)S min from P to 2P Global - Replaced all "CLKIN" references with "OSCIN" Global - Updated SPI Electrical parameters Added Section 5.3, Notes on Recommended Power-On Hours (POH). Section 6.5- Updated "All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence" to " All pins are tri-stated with the exception of RESETOUT, which remains active through the reset sequence, and RTCK/GP7[14]. If an emulator is driving TCK into the device during reset, then RTCK/GP7[14] will drive out RTCK. If TCK is not being driven into the device during reset, then RTCK/GP7[14] will drive low." Updated Warm Reset Timing Diagram - Figure 6-5 ADVANCE INFORMATION Updated the PLL diagram - Figure 6-9 Revision History Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 7 AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com 3 Device Overview 3.1 Device Characteristics Table 3-1 provides an overview of the device . The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count. Table 3-1. Characteristics of the device HARDWARE FEATURES AM1707 AM1707 EMIFB 16/32bit, upto 512Mb SDRAM EMIFA Asynchronous (8/16-bit bus width) RAM, Flash, 16bit upto 128Mb SDRAM, NOR, NAND Flash Card Interface MMC and SD cards supported. EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers Timers 2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as Watch Dog) 3 (one with RTS and CTS flow control) SPI ADVANCE INFORMATION UART 2 (Each with one hardware chip select) I2C 2 (both Master/Slave) Multichannel Audio Serial Port [McASP] Peripherals Not all peripherals pins are available at the same time (for more detail, see the Device Configurations section). 3 (each with transmit/receive, FIFO buffer, 16/12/4 serializers) 10/100 Ethernet MAC with Management Data I/O eHRPWM 1 (RMII Interface) 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs eQEP 2 32-bit QEP channels with 4 inputs/channel UHPI 1 (16-bit multiplexed address/data) USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY USB 1.1 (USB1) Full-Speed OHCI (as host) with on-chip PHY General-Purpose Input/Output Port 8 banks of 16-bit PRU Subsystem (PRUSS) 2 Programmable PRU Cores LCD Controller Size (Bytes) On-Chip Memory Organization 1 168KB 168KB RAM, 64KB ROM ARM 16KB I-Cache 16KB D-Cache 8KB RAM (Vector Table) 64KB ROM ADDITIONAL MEMORY 128KB 128KB RAM JTAG BSDL_ID DEVIDR0 register CPU Frequency MHz Core (V) Voltage 0x8B7D F02F (Silicon Revision 1.1) 0x9B7D F02F (Silicon Revision 2.0) ARM926 ARM926 375 MHz (1.2V) or 456 MHz (1.3V) 1.2 V nominal for 375 MHz version 1.3 V nominal for 456 MHz version I/O (V) Package Product Status (1) 8 3.3 V 17 mm x 17 mm, 256-Ball 1 mm pitch, PBGA (ZKB) (1) Product Preview (PP), Advance Information (AI), or Production Data (PD) 375 MHz Versions -PD 456 MHz Version - AI ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 3.2 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Device Compatibility The ARM926EJ-S ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. 3.3 ARM Subsystem 3.3.1 ARM926EJ-S ARM926EJ-S RISC CPU The ARM Subsystem integrates the ARM926EJ-S ARM926EJ-S processor. The ARM926EJ-S ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead. The ARM926EJ-S ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including: · ARM926EJ ARM926EJ -S integer core · CP15 system control coprocessor · Memory Management Unit (MMU) · Separate instruction and data caches · Write buffer · Separate instruction and data (internal RAM) interfaces · Separate instruction and data AHB bus interfaces · Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S ARM926EJ-S Technical Reference Manual, available at http://www.arm.com 3.3.2 CP15 The ARM926EJ-S ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode. Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 9 ADVANCE INFORMATION The ARM Subsystem includes the following features: · ARM926EJ-S ARM926EJ-S RISC processor · ARMv5TEJ (32/16-bit) instruction set · Little endian · System Control Co-Processor 15 (CP15) · MMU · 16KB Instruction cache · 16KB Data cache · Write Buffer · Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) · ARM Interrupt controller AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 3.3.3 www.ti.com MMU ADVANCE INFORMATION A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are: · Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme. · Mapping sizes are: ­ 1MB (sections) ­ 64KB (large pages) ­ 4KB (small pages) ­ 1KB (tiny pages) · Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions) · Hardware page table walks · Invalidate entire TLB, using CP15 register 8 · Invalidate TLB entry, selected by MVA, using CP15 register 8 · Lockdown of TLB entries, using CP15 register 10 3.3.4 Caches and Write Buffer The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following features: · Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA) · Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache · Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables · Critical-word first cache refilling · Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption · Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address. · Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory. The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry. 3.3.5 Advanced High-Performance Bus (AHB) The ARM Subsystem uses the AHB port of the ARM926EJ-S ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB) To support real-time trace, the ARM926EJ-S ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926EJ-S ARM926EJ-S Subsystem in the device also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts: 10 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com · · SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Trace Port provides real-time trace capability for the ARM9. Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers. The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data. This device uses ETM9TM version r2p2 and ETB version r0p1. Documentation on the ETM and ETB is available from ARM Ltd. Reference the ' CoreSightTM ETM9TM Technical Reference Manual, revision r0p1' and the 'ETM9 Technical Reference Manual, revision r2p2'. 3.3.7 ARM Memory Mapping By default the ARM has access to most on and off chip memory areas, EMIFA, EMIFB, and the additional 128K byte on chip SRAM. Likewise almost all of the on chip peripherals are accessible to the ARM by default. ADVANCE INFORMATION See Table 3-2 for a detailed top level device memory map that includes the ARM memory space. Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 11 AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 3.4 www.ti.com Memory Map Summary Table 3-2. AM1707 AM1707 Top Level Memory Map End Address Size 0x0000 0000 0x0000 0FFF 4K 0x0000 1000 0x01BB FFFF 0x01BC 0000 0x01BC 0FFF 0x01BC 1000 0x01BC 1800 0x01BC 1900 0x01BF FFFF 0x01C0 0000 0x01C0 7FFF 32K EDMA3 Channel Controller - 0x01C0 8000 ADVANCE INFORMATION Start Address ARM Mem Map EDMA Mem Map 0x01C0 83FF 1024 EDMA3 Transfer Controller 0 - 0x01C0 8400 0x01C0 87FF 1024 EDMA3 Transfer Controller 1 - 0x01C0 8800 0x01C0 FFFF 0x01C1 0000 0x01C1 0FFF 4K PSC 0 0x01C1 1000 0x01C1 1FFF 4K PLL Controller 0x01C1 2000 0x01C1 3FFF 0x01C1 4000 0x01C1 4FFF 0x01C1 5000 0x01C1 FFFF 0x01C2 0000 - PRUSS Mem Map Master Peripheral Mem Map LCDC Mem Map PRUSS Local Address Space 4K ARM ETB memory - 0x01BC 17FF 2K ARM ETB reg - 0x01BC 18FF 256 ARM Ice Crusher - - 4K SYSCFG 0x01C2 0FFF 4K Timer64P 0 - 0x01C2 1000 0x01C2 1FFF 4K Timer64P 1 - 0x01C2 2000 0x01C2 2FFF 4K I2C 0 - 0x01C2 3000 0x01C2 3FFF 4K RTC - 0x01C2 4000 0x01C3 FFFF - - 0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 - 0x01C4 1000 0x01C4 1FFF 4K SPI 0 - 0x01C4 2000 0x01C4 2FFF 4K UART 0 0x01C4 3000 0x01CF FFFF 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control - 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Control - 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data - 0x01D0 3000 0x01D0 3FFF 0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control - 0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Control - 0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data - 0x01D0 7000 0x01D0 7FFF 0x01D0 8000 0x01D0 8FFF 4K McASP 2 Control - 0x01D0 9000 0x01D0 9FFF 4K McASP 2 AFIFO Control - 0x01D0 A000 0x01D0 AFFF 4K McASP 2 Data - 0x01D0 B000 0x01D0 BFFF 0x01D0 C000 0x01D0 CFFF 4K UART 1 - 0x01D0 D000 0x01D0 DFFF 4K UART 2 - 0x01D0 E000 0x01DF FFFF - - 0x01E0 0000 0x01E0 FFFF 64K USB0 - 0x01E1 0000 0x01E1 0FFF 4K UHPI - 12 - - - - - - Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Table 3-2. AM1707 AM1707 Top Level Memory Map (continued) Start Address End Address Size ARM Mem Map EDMA Mem Map PRUSS Mem Map Master Peripheral Mem Map LCDC Mem Map 0x01E1 1000 0x01E1 1FFF 0x01E1 2000 0x01E1 2FFF 4K 0x01E1 3000 0x01E1 3FFF 0x01E1 4000 0x01E1 4FFF 0x01E1 5000 0x01E1 5FFF 0x01E1 6000 0x01E1 FFFF 0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM - 0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers - 0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers - 0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port - 0x01E2 5000 0x01E2 5FFF 4K USB1 - 0x01E2 6000 0x01E2 6FFF 4K GPIO - 0x01E2 7000 0x01E2 7FFF 4K PSC 1 - 0x01E2 8000 0x01E2 8FFF 4K I2C 1 0x01E2 9000 0x01EF FFFF 0x01F0 0000 0x01F0 0FFF 4K 0x01F0 1000 0x01F0 1FFF 0x01F0 2000 0x01F0 2FFF 0x01F0 3000 SPI 1 - 4K LCD Controller - 4K Memory Protection Unit 1 (MPU 1) - 4K Memory Protection Unit 2 (MPU 2) - ADVANCE INFORMATION - - eHRPWM 0 - 4K HRPWM 0 - 4K eHRPWM 1 - 0x01F0 3FFF 4K HRPWM 1 - 0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2 - 0x01F0 5000 0x01F0 5FFF 4K HRPWM 2 - 0x01F0 6000 0x01F0 6FFF 4K ECAP 0 - 0x01F0 7000 0x01F0 7FFF 4K ECAP 1 - 0x01F0 8000 0x01F0 8FFF 4K ECAP 2 - 0x01F0 9000 0x01F0 9FFF 4K EQEP 0 - 0x01F0 A000 0x01F0 AFFF 4K EQEP 1 - 0x01F0 B000 0x3FFF FFFF 0x4000 0000 0x47FF FFFF 128M EMIFA SDRAM data (CS0) - 0x4800 0000 0x5FFF FFFF 0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) - 0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) - 0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) - 0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) - 0x6800 0000 0x6800 7FFF 32K EMIFA Control Registers - 0x6800 8000 0x7FFF FFFF 0x8000 0000 0x8001 FFFF 0x8002 0000 0xB000 7FFF 0xB000 8000 0xCFFF FFFF 0xD000 0000 0xFFFD FFFF 0xFFFE 0000 0xFFFE DFFF 0xFFFE E000 0xFFFE FFFF On-chip RAM - 0xFFFC FFFF 0xFFFD 0000 128K 0xBFFF FFFF 0xC000 0000 - 0xAFFF FFFF 0xB000 0000 - 32K EMIFB Control Registers - 256M EMIFB SDRAM Data 64K ARM local ROM 8K ARM Interrupt Controller - Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 13 AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com Table 3-2. AM1707 AM1707 Top Level Memory Map (continued) Start Address End Address Size 0xFFFF 0000 0xFFFF 1FFF 8K 0xFFFF 2000 0xFFFF FFFF ARM Mem Map ARM local RAM EDMA Mem Map - PRUSS Mem Map Master Peripheral Mem Map LCDC Mem Map ARM local RAM (PRU 0 Only) - ADVANCE INFORMATION 14 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 3.5 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. 3.5.1 Pin Map (Bottom View) Figure 3-1 shows the pin assignments for the ZKB package. 2 3 4 5 6 7 8 9 10 AXR1[11]/ GP5[11] SPI0_CLK/ EQEP1I/ GP5[2]/ BOOT[2] SPI1_CLK/ EQEP1S/ GP5[7]/ BOOT[7] EMA_CS[3]/ AMUTE2/ GP2[6] EMA_CS[0]/ UHPI_HAS/ GP2[4] EMA_A[0]/ LCD_D[7]/ GP1[0] EMA_A[4]/ LCD_D[3]/ GP1[4] T VSS VSS AXR1[0]/ GP4[0] R DVDD AXR1[1]/ GP4[1] UART0_RXD/ I2C0_SDA/ TM64P0 TM64P0_IN12/ IN12/ GP5[8]/ BOOT[8] P AXR1[3]/ EQEP1A/ GP4[3] AXR1[2]/ GP4[2] N AXR1[5]/ EPWM2B/ GP4[5] AXR1[4]/ EQEP1B/ GP4[4] AXR1[10]/ GP5[10] M AXR1[9]/ GP4[9] AXR1[8]/ EPWM1A/ GP4[8] AXR1[7]/ EPWM1B/ GP4[7] AXR1[6]/ EPWM2A/ GP4[6] DVDD VSS VSS L AHCLKR1/ GP4[11] ACLKR1/ ECAP2/ APWM2/ GP4[12] AFSR1/ GP4[13] AMUTE0/ RESETOUT DVDD CVDD AHCLKX1/ EPWM0B/ GP3[14] ACLKX1/ EPWM0A/ GP3[15] AFSX1/ EPWMSYNCI/ EPWMSYNCO/ GP4[10] DVDD K RTCK/GP7[14] SPI0_ENA/ SPI0_SOMI[0]/ EMA_OE/ SPI1_ENA/ UART0_CTS/ UHPI_HDS1/ EQEP0I/ UART2_RXD/ EQEP0A/ AXR0[13]/ GP5[0]/ GP5[3]/ GP5[12] GP2[7] BOOT[0] BOOT[3] 11 12 13 14 15 EMA_D[0]/ EMA_D[9]/ EMA_A[8]/ EMA_SDCKE/ MMCSD_DAT[0]/ UHPI_HD[9]/ UHPI_HD[0]/ LCD_PCLK/ GP2[0] LCD_D[9]/ GP0[0]/ GP1[8] GP0[9] BOOT[12] EMA_CLK/ OBSCLK/ AHCLKR2/ GP1[15] 16 VSS VSS T DVDD R EMA_A[1]/ EMA_BA[0]/ MMCSD_CLK/ LCD_D[4]/ UHPI_HCNTL0/ GP1[14] GP1[1] EMA_A[5]/ LCD_D[2]/ GP1[5] EMA_A[9]/ LCD_HSYNC/ GP1[9] EMA_D[2]/ EMA_D[10]/ EMA_D[1]/ MMCSD_DAT[2]/ UHPI_HD[10]/ MMCSD_DAT[1]/ UHPI_HD[2]/ LCD_D[10]/ UHPI_HD[1]/ GP0[2] GP0[10] GP0[1] UART0_TXD/ EMA_A[2]/ SPI1_SOMI[0]/ SPI0_SIMO[0]/ EMA_CS[2]/ EMA_BA[1]/ SPI1_SCS[0]/ I2C0_SCL/ I2C1_SCL/ EQEP0S/ UHPI_HCS/ LCD_D[5]/ MMCSD_CMD/ TM64P0 TM64P0_OUT12/ OUT12/ UART2_TXD/ UHPI_HHWIL/ UHPI_HCNTL1/ GP5[5]/ GP5[1]/ GP2[5]/ GP5[9]/ GP5[13] GP1[13] GP1[2] BOOT[5] BOOT[1] BOOT[15] BOOT[9] EMA_A[6]/ LCD_D[1]/ GP1[6] EMA_A[11]/ LCD_AC_ ENB_CS/ GP1[11] EMA_WE_ EMA_D[4]/ EMA_D[12]/ EMA_D[3]/ EMA_D[11]/ DQM[1]/ MMCSD_DAT[4]/ UHPI_HD[12]/ MMCSD_DAT[3]/ UHPI_HD[11]/ UHPI_HDS2/ UHPI_HD[4]/ LCD_D[12]/ UHPI_HD[3]/ LCD_D[11] AXR0[14]/ GP0[4] GP0[12] GP0[3] GP0[11] GP2[8] P SPI0_SCS[0]/ SPI1_SIMO[0]/ UART0_RTS/ I2C1_SDA/ EMA_WAIT[0]/ EMA_RAS/ EMA_A[10]/ UHPI_HRDY/ EMA_CS[5]/ LCD_VSYNC/ EQEP0B/ GP5[6]/ GP5[4]/ GP2[10] GP2[2] GP1[10] BOOT[6] BOOT[4] EMA_A[3]/ LCD_D[6]/ GP1[3] EMA_A[7]/ LCD_D[0]/ GP1[7] EMA_A[12]/ LCD_MCLK/ GP1[12] EMA_D[8]/ EMA_D[6]/ EMA_D[14]/ EMA_D[5]/ EMA_D[13]/ UHPI_HD[8]/ MMCSD_DAT[6]/ UHPI_HD[14]/ MMCSD_DAT[5]/ UHPI_HD[13]/ LCD_D[8]/ UHPI_HD[6]/ LCD_D[14]/ UHPI_HD[5]/ LCD_D[13]/ GP0[14] GP0[5] GP0[13] GP0[8] GP0[6] N DVDD DVDD VSS VSS DVDD EMA_WE/ UHPI_HRW/ AXR0[12]/ GP2[3]/ BOOT[14]] EMA_D[7]/ EMA_WE_ EMA_D[15]/ MMCSD_DAT[7]/ DQM[0]/ UHPI_HD[15]/ UHPI_HINT/ UHPI_HD[7]/ LCD_D[15]/ AXR0[15]/ GP0[7]/ GP0[15] GP2[9] BOOT[13] M VSS VSS VSS VSS DVDD DVDD EMB_CAS EMB_D[22] EMB_D[23] EMA_CAS/ EMA_CS[4]/ GP2[1] L CVDD CVDD VSS VSS CVDD CVDD DVDD EMB_D[20] EMB_WE_ DQM[0]/ GP5[15] EMB_WE EMB_D[21] K J TMS TDI TDO TRST EMU0/GP7[15] CVDD CVDD VSS VSS CVDD CVDD CVDD EMB_D[5]/ GP6[5] EMB_D[19] EMB_D[6]/ GP6[6] EMB_D[7]/ GP6[7] J H RTC_XI RTC_XO TCK NC USB0_ VDDA33 VDDA33 RVDD CVDD VSS VSS CVDD CVDD RVDD EMB_D[3]/ GP6[3] EMB_D[17] EMB_D[18] EMB_D[4]/ GP6[4] H G RTC_CVDD RTC_VSS RESET USB0_DM DVDD CVDD CVDD VSS VSS CVDD CVDD DVDD EMB_D[1]/ GP6[1] EMB_D[31] EMB_D[16] EMB_D[2]/ GP6[2] G F OSCOUT OSCIN NC USB0_DP DVDD CVDD RSV1 VSS VSS VSS DVDD DVDD EMB_D[15]/ GP6[15] EMB_D[29] EMB_D[30] EMB_D[0]/ GP6[0] F E PLL0_VSSA OSCVSS USB0_ VDDA18 VDDA18 USB0_ DRVVBUS/ GP4[15] DVDD VSS VSS DVDD DVDD VSS VSS DVDD EMB_D[13]/ GP6[13] EMB_D[27] EMB_D[28] EMB_D[14]/ GP6[14] E D PLL0_VDDA USB0_ID C USB1_ VDDA33 VDDA33 USB1_ VDDA18 VDDA18 USB0_ VDDA12 VDDA12 B RSV2 VSS A VSS 1 ADVANCE INFORMATION 1 AFSX0/ GP2[13]/ BOOT[10] AXR0[6]/ UART1_TXD/ RMII_RXER/ AXR0[10]/ ACLKR2/ GP3[10] GP3[6] AXR0[2]/ RMII_TXEN/ AXR2[3]/ GP3[2] EMB_CS[0] EMB_A[0]/ GP7[2] EMB_A[4]/ GP7[6] EMB_A[8]/ GP7[10] EMB_D[9]/ GP6[9] EMB_D[10]/ GP6[10] EMB_D[11]/ GP6[11] EMB_D[12]/ GP6[12] D AFSR0/ GP3[12] ACLKX0/ ECAP0/ APWM0/ GP2[12] AXR0[5]/ AXR0[1]/ UART1_RXD/ RMII_RXD[1]/ RMII_TXD[1]/ AXR0[9]/ AFSX2/ ACLKX2/ GP3[9] GP3[5] GP3[1] EMB_BA[0]/ GP7[1] EMB_A[1]/ GP7[3] EMB_A[5]/ GP7[7] EMB_A[9]/ GP7[11] EMB_SDCKE EMB_CLK EMB_WE_ DQM[1]/ GP5[14] EMB_D[8]/ GP6[8] C USB1_DM ACLKR0/ ECAP1/ APWM1/ GP2[15] AHCLKX0/ AHCLKX2/ USB_ REFCLKIN/ GP2[11] AXR0[8]/ MDIO_D/ GP3[8] AXR0[4]/ AXR0[0]/ RMII_RXD[0]/ RMII_TXD[0]/ AXR2[1]/ AFSR2/ GP3[4] GP3[0] EMB_BA[1]/ GP7[0] EMB_A[2]/ GP7[4] EMB_A[6]/ GP7[8] EMB_A[11]/ GP7[13] EMB_WE_ DQM[2] EMB_D[25] EMB_A[12]/ GP3[13] DVDD B VSS USB1_DP AHCLKR0/ RMII_MHZ_ 50_CLK/ GP2[14]/ BOOT[11] AXR0[11]/ AXR2[0]/ GP3[11] AXR0[7]/ MDIO_CLK/ GP3[7] AXR0[3]/ RMII_CRS_DV/ AXR2[2]/ GP3[3] EMB_RAS EMB_A[10]/ GP7[12] EMB_A[3]/ GP7[5] EMB_A[7]/ GP7[9] EMB_WE_ DQM[3] EMB_D[24] EMB_D[26] VSS VSS A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AMUTE1/ USB0_VBUS EHRPWMTZ/ GP4[14] Figure 3-1. Pin Map (ZKB) Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 15 AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 3.6 www.ti.com Terminal Functions Table 3-3 to Table 3-23 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description. 3.6.1 Device Reset and JTAG Table 3-3. Reset and JTAG Terminal Functions PIN No. SIGNAL NAME ZKB TYPE (1) PULL (2) DESCRIPTION RESET RESET G3 L4 AMUTE0/ RESETOUT I (3) O Device reset input IPD Reset output. Multiplexed with McASP0 mute output. JTAG ADVANCE INFORMATION TMS J1 I IPU JTAG test mode select TDI TDO J2 I IPU JTAG test data input J3 O IPD JTAG test data output TCK H3 I IPU JTAG test clock TRST J4 I IPD JTAG test reset EMU[0]/GP7[15] J5 I/O IPU Emulation Signal RTCK/GP7[14] K1 I/O IPD JTAG Test Clock Return Clock Output (1) (2) (3) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Open drain mode for RESETOUT function. 3.6.2 High-Frequency Oscillator and PLL Table 3-4. High-Frequency Oscillator and PLL Terminal Functions PIN No. TYPE (1) PULL (2) R12 O IPU OSCIN F2 I Oscillator input OSCOUT F1 O Oscillator output OSCVSS E2 GND SIGNAL NAME EMA_CLK/OBSCLK/AHCLKR2/ GP1[15] ZKB DESCRIPTION PLL Observation Clock 1.2-V OSCILLATOR Oscillator ground 1.2-V PLL PLL0_VDDA D1 PWR PLL analog VDD (1.2-V filtered supply) PLL0_VSSA E1 GND PLL analog VSS (for filter) (1) (2) 16 I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 3.6.3 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Real-Time Clock and 32-kHz Oscillator Table 3-5. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions SIGNAL NAME PIN No. ZKB TYPE (1) PULL (2) DESCRIPTION RTC_CVDD G1 PWR RTC_XI H1 I Low-frequency (32-kHz) oscillator receiver for real-time clock RTC_XO H2 O Low-frequency (32-kHz) oscillator driver for real-time clock RTC_Vss G2 GND (1) (2) RTC module core power (isolated from rest of chip CVDD) Oscillator ground (for filter) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.4 External Memory Interface A (ASYNC, SDRAM) PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED ADVANCE INFORMATION Table 3-6. External Memory Interface A (EMIFA) Terminal Functions DESCRIPTION ZKB EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] M16 I/O IPD EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] N14 I/O IPD EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] N16 I/O IPD EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] P14 I/O IPD EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] P16 I/O IPD EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] R14 I/O IPD EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] T14 I/O IPD EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] N12 I/O IPD EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] M15 I/O IPU EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] N13 I/O IPU EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] P13 I/O IPU EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] R15 I/O IPU EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] T13 I/O IPU (1) (2) UHPI, LCD, GPIO MMC/SD, UHPI, EMIFA data bus GPIO, BOOT MMC/SD, UHPI, GPIO MMC/SD, UHPI, GPIO, BOOT I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 17 AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com Table 3-6. External Memory Interface A (EMIFA) Terminal Functions (continued) SIGNAL NAME PIN No. TYPE (1) PULL (2) MUXED DESCRIPTION ZKB N11 O IPU EMA_A[11]/ LCD_AC_ENB_CS/GP1[11] P11 O IPU EMA_A[10]/LCD_VSYNC/GP1[10] N8 O IPU EMA_A[9]/LCD_HSYNC/GP1[9] R11 O IPU EMA_A[8]/LCD_PCLK/GP1[8] T11 O IPU EMA_A[7]/LCD_D[0]/GP1[7] N10 O IPD EMA_A[6]/LCD_D[1]/GP1[6] P10 O IPD EMA_A[5]/LCD_D[2]/GP1[5] R10 O IPD EMA_A[4]/LCD_D[3]/GP1[4] T10 O IPD EMA_A[3]/LCD_D[6]/GP1[3] N9 O IPD EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] P9 O IPU EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] ADVANCE INFORMATION EMA_A[12]/LCD_MCLK/GP1[12] R9 O EMA_A[0]/LCD_D[7]/GP1[0] T9 EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] LCD, GPIO EMIFA address bus IPU MMCSD, UHPI, GPIO EMIFA address bus. O IPD LCD, GPIO P8 O IPU LCD, UHPI, GPIO EMA_BA[0]/LCD_D[4]/GP1[14] R8 O IPU LCD, GPIO EMA_CLK/OBSCLK/AHCLKR2/GP1[15] R12 O IPU McASP2, GPIO, EMIFA clock OBSCLK EMA_SDCKE/GP2[0] T12 O IPU GPIO EMA_RAS /EMA_CS[5]/GP2[2] N7 O IPU EMA_CAS /EMA_CS[4]/GP2[1] L16 O IPU EMA_RAS/ EMA_CS[5] /GP2[2] N7 O IPU EMA_CAS/ EMA_CS[4] /GP2[1] L16 O IPU EMIF A SDRAM, GPIO EMA_CS[3] /AMUTE2/GP2[6] T7 O IPU McASP2, GPIO EMA_CS[2] /UHPI_HCS/GP2[5]/BOOT[15] P7 O IPU UHPI, GPIO, BOOT EMA_CS[0] /UHPI_HAS/GP2[4] T8 O IPU UHPI, GPIO EMA_WE /UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] M13 O IPU UHPI, MCASP0, EMIFA SDRAM write GPIO, BOOT enable EMA_WE_DQM[1] /UHPI_HDS2/AXR0[14]/GP2[8] P12 O IPU EMIFA write enable/data mask for EMA_D[15:8] EMIF A chip select, GPIO UHPI, McASP, GPIO EMA_WE_DQM[0] /UHPI_HINT/AXR0[15]/GP2[9] EMIFA bank address EMIFA SDRAM clock enable EMIFA SDRAM row address strobe EMIFA SDRAM column address strobe EMIFA Async Chip Select EMIFA SDRAM chip select EMIFA write enable/data mask for EMA_D[7:0] M14 O IPU EMA_OE /UHPI_HDS1/AXR0[13]/GP2[7] R7 O IPU UHPI, McASP0, GPIO EMIFA output enable EMA_WAIT[0]/ UHPI_HRDY/GP2[10] N6 I IPU UHPI, GPIO EMIFA wait input/interrupt 18 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 3.6.5 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 External Memory Interface B (SDRAM only) Table 3-7. External Memory Interface B (EMIFB) Terminal Functions SIGNAL NAME PIN No. ZKB TYPE (1) PULL (2) G14 O IPD EMB_D[30] F15 O IPD EMB_D[29] F14 O IPD EMB_D[28] E15 O IPD EMB_D[27] E14 O IPD EMB_D[26] A14 O IPD EMB_D[25] B14 O IPD EMB_D[24] A13 O IPD EMB_D[23] L15 O IPD EMB_D[22] L14 O IPD EMB_D[21] K16 O IPD EMB_D[20] K13 O IPD EMB_D[19] J14 O IPD EMB_D[18] H15 O IPD EMB_D[17] H14 O IPD EMB_D[16] G15 O IPD EMB_D[15]/GP6[15] F13 I/O IPD EMB_D[14]/GP6[14] E16 I/O IPD EMB_D[13]/GP6[13] E13 I/O IPD EMB_D[12]/GP6[12] D16 I/O IPD EMB_D[11]/GP6[11] D15 I/O IPD EMB_D[10]/GP6[10] D14 I/O IPD EMB_D[9]/GP6[9] D13 I/O IPD EMB_D[8]/GP6[8] C16 I/O IPD EMB_D[7]/GP6[7] J16 I/O IPD EMB_D[6]/GP6[6] J15 I/O IPD EMB_D[5]/GP6[5] J13 I/O IPD EMB_D[4]/GP6[4] H16 I/O IPD EMB_D[3]/GP6[3] H13 I/O IPD EMB_D[2]/GP6[2] G16 I/O IPD EMB_D[1]/GP6[1] G13 I/O IPD EMB_D[0]/GP6[0] F16 I/O IPD EMB_A[12]/GP3[13] B15 O IPD EMB_A[11]/GP7[13] B12 O IPD EMB_A[10]/GP7[12] A9 O IPD EMB_A[9]/GP7[11] C12 O IPD EMB_A[8]/GP7[10] D12 O IPD EMB_A[7]/GP7[9] A11 O IPD EMB_A[6]/GP7[8] B11 O IPD EMB_A[5]/GP7[7] C11 O DESCRIPTION IPD (1) (2) ADVANCE INFORMATION EMB_D[31] MUXED EMIFB SDRAM data bus GPIO GPIO EMIFB SDRAM row/column address bus I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 19 AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com Table 3-7. External Memory Interface B (EMIFB) Terminal Functions (continued) PIN No. SIGNAL NAME ZKB TYPE (1) PULL (2) MUXED DESCRIPTION D11 O IPD EMB_A[3]/GP7[5] A10 O IPD EMB_A[2]/GP7[4] B10 O IPD EMB_A[1]/GP7[3] C10 O IPD EMB_A[0]/GP7[2] D10 O IPD EMB_BA[1]/GP7[0] B9 O IPU EMB_BA[0]/GP7[1] C9 O IPU EMB_CLK C14 O IPU EMIF SDRAM clock EMB_SDCKE C13 I/O IPU EMIFB SDRAM clock enable EMB_WE K15 O IPU EMIFB write enable EMB_RAS A8 O IPU EMIFB SDRAM row address strobe EMB_CAS ADVANCE INFORMATION EMB_A[4]/GP7[6] L13 O IPU EMIFB column address strobe EMB_CS[0] D9 O IPU EMIFB SDRAM chip select 0 EMB_WE_DQM[3] A12 O IPU EMB_WE_DQM[2] B13 O IPU EMB_WE_DQM[1] /GP5[14] C15 O IPU EMB_WE_DQM[0] /GP5[15] K14 O IPU 3.6.6 EMIFB SDRAM row/column address GPIO EMIFB SDRAM bank address EMIFB write enable/data mask for EMB_D GPIO Serial Peripheral Interface Modules (SPI0, SPI1) Table 3-8. Serial Peripheral Interface (SPI) Terminal Functions PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB SPI0 SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4] N4 I/O IPU UART0, EQEP0B, GPIO, BOOT SPI0 chip select SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3] R5 I/O IPU UART0, EQEP0A, GPIO, BOOT SPI0 enable SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] T5 I/O IPD eQEP1, GPIO, BOOT SPI0 clock SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] P6 I/O IPD SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] R6 I/O IPD SPI1_SCS[0] /UART2_TXD/GP5[13] P4 I/O IPU SPI1_ENA /UART2_RXD/GP5[12] R4 I/O IPU SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] T6 I/O IPD SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] N5 I/O IPU SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] P5 I/O IPU eQEP0, GPIO, BOOT SPI0 data slave-in-master-out SPI0 data slave-out-master-in SPI1 UART2, GPIO eQEP1, GPIO, BOOT I2C1, GPIO, BOOT (1) (2) 20 SPI1 chip select SPI1 enable SPI1 clock SPI1 data slave-in-master-out SPI1 data slave-out-master-in I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 3.6.7 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2) The eCAP Module pins function as either input captures or auxilary PWM 32-bit outputs, depending upon how the eCAP module is programmed. Table 3-9. Enhanced Capture Module (eCAP) Terminal Functions PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB eCAP0 ACLKX0/ECAP0/APWM0/GP2[12] C5 I/O IPD McASP0, GPIO enhanced capture 0 input or auxiliary PWM 0 output eCAP1 I/O IPD McASP0, GPIO L2 I/O IPD McASP1, GPIO enhanced capture 2 input or auxiliary PWM 2 output eCAP2 ACLKR1/ECAP2/APWM2/GP4[12] (1) (2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 21 ADVANCE INFORMATION B4 ACLKR0/ECAP1/APWM1/GP2[15] enhanced capture 1 input or auxiliary PWM 1 output AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 3.6.8 www.ti.com Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2) Table 3-10. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions SIGNAL NAME PIN No. TYPE (1) PULL (2) MUXED DESCRIPTION ZKB eHRPWM0 eHRPWM0 A output (with high-resolution) ACLKX1/EPWM0A/GP3[15] K3 I/O IPD AHCLKX1/EPWM0B/GP3[14] K2 I/O IPD eHRPWM0 B output McASP1, GPIO AMUTE1/EPWMTZ/GP4[14] D4 I/O IPD McASP1, eHRPWM1, eHRPWM0 trip zone GPIO, eHRPWM2 input AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] K4 I/O IPD Sync input to McASP1, eHRPWM0, eHRPWM0 module or GPIO sync output to external PWM eHRPWM1 eHRPWM1 A output (with high-resolution) ADVANCE INFORMATION AXR1[8]/EPWM1A/GP4[8] M2 I/O IPD AXR1[7]/EPWM1B/GP4[7] M3 I/O IPD eHRPWM1 B output IPD McASP1, eHRPWM1, eHRPWM1 trip zone GPIO, eHRPWM2 input AMUTE1/EPWMTZ/GP4[14] D4 I/O McASP1, GPIO eHRPWM2 eHRPWM2 A output (with high-resolution) AXR1[6]/EPWM2A/GP4[6] M4 I/O IPD AXR1[5]/EPWM2B/GP4[5] N1 I/O IPD eHRPWM2 B output AMUTE1/EPWMTZ/GP4[14] D4 I/O IPD McASP1, eHRPWM1, eHRPWM2 trip zone GPIO, eHRPWM2 input (1) (2) 22 McASP1, GPIO I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 3.6.9 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Enhanced Quadrature Encoder Pulse Module (eQEP) Table 3-11. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB eQEP0 SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] R5 I IPU SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] N4 I IPU SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] R6 I IPD SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] P6 I IPD SPIO, UART0, GPIO, BOOT SPI1, GPIO, BOOT EQEP0A quadrature input EQEP0B quadrature input eQEP0 index eQEP0 strobe eQEP1 P1 I IPD AXR1[4]/EQEP1B/GP4[4] N2 I IPD SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] T5 I IPD SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] T6 I IPD McASP1, GPIO (1) (2) SPI1, GPIO, BOOT eQEP1 quadrature input eQEP1 quadrature input eQEP1 index eQEP1 strobe I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 23 ADVANCE INFORMATION AXR1[3]/EQEP1A/GP4[3] AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 3.6.10 www.ti.com Boot Table 3-12. Boot Mode Selection Terminal Functions (1) PIN No. TYPE (2) PULL (3) P7 I IPU EMIFA, UHPI, GPIO EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] M13 I IPU EMIFA, UHPI, McASP0, GPIO EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] M15 I IPU EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] T13 I IPU AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] A4 I IPD McASP0, EMAC, GPIO AFSX0/GP2[13]/BOOT[10] D5 I IPD McASP0, GPIO UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] P3 I IPU UART0, I2C0, Timer0, GPIO UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] R3 I IPU SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] T6 I IPD SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] N5 I IPU SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] P5 I IPU SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] N4 I IPU SPI0, UART0, eQEP0, GPIO SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] R5 I IPU SPI0, UART0, eQEP0, GPIO SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] T5 I IPD SPIO, eQEP1, GPIO SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] P6 I IPD SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] R6 I IPD SIGNAL NAME ZKB EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] ADVANCE INFORMATION (1) (2) (3) 24 MUXED DESCRIPTION EMIFA, MMC/SD, UHPI, GPIO UART0, I2C0, Timer0, Boot Mode GPIO Selection Pins SPI1, eQEP1, GPIO SPI1, I2C1, GPIO SPI0, eQEP0, GPIO Boot decoding will be defined in the ROM datasheet. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2) Table 3-13. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB UART0 UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] R3 I IPU I2C0, BOOT, Timer0, GPIO, UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] P3 O IPU I2C0, Timer0, GPIO, UART0 transmit BOOT data SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/BOOT[4] N4 O IPU SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3] R5 I IPU I IPD UART0 receive data UART0 ready-to-send output SPIO, eQEP0, GPIO, BOOT UART0 clear-to-send input UART1 C6 UART1_TXD/AXR0[10]/GP3[10] (3) D6 O IPD I UART1 receive data McASP0, GPIO UART1 transmit data IPU UART2 SPI1_ENA/UART2_RXD/GP5[12] R4 SPI1_SCS[0]/UART2_TXD/GP5[13] (1) (2) (3) P4 O IPU UART2 receive data SPI1, GPIO UART2 transmit data I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if UART1 boot mode is used. 3.6.12 Inter-Integrated Circuit Modules(I2C0, I2C1) Table 3-14. Inter-Integrated Circuit (I2C) Terminal Functions PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB I2C0 UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] R3 I/O IPU UART0, Timer0, GPIO, BOOT I2C0 serial data UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] P3 I/O IPU UART0, Timer0, GPIO, BOOT I2C0 serial clock SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] N5 I/O IPU SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] P5 I/O IPU I2C1 (1) (2) SPI1, GPIO, BOOT I2C1 serial data I2C1 serial clock I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 25 ADVANCE INFORMATION UART1_RXD/AXR0[9]/GP3[9] (3) AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com 3.6.13 Timers Table 3-15. Timers Terminal Functions PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB TIMER0 UART0_RXD/I2C0_SDA/TM64P0 SDA/TM64P0_IN12/GP5 IN12/GP5[8]/BOOT[8] R3 I IPU UART0_TXD/I2C0_SCL/TM64P0 SCL/TM64P0_OUT12/GP5 OUT12/GP5[9]/BOOT[9] P3 O IPU UART0, I2C0, GPIO, BOOT Timer0 lower input Timer0 lower output TIMER1 (Watchdog ) No external pins. The Timer1 peripheral signals are not pinned out as external pins. (1) (2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor ADVANCE INFORMATION 26 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 3.6.14 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Universal Host-Port Interface (UHPI) Table 3-16. Universal Host-Port Interface (UHPI) Terminal Functions SIGNAL NAME PIN No. TYPE (1) PULL (2) MUXED DESCRIPTION ZKB M16 I/O IPD EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] N14 I/O IPD EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] N16 I/O IPD EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] P14 I/O IPD EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] P16 I/O IPD EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] R14 I/O IPD EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] T14 I/O IPD EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] N12 I/O IPD EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/ BOOT[13] M15 I/O IPU EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] N13 I/O IPU EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] P13 I/O IPU EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] R15 I/O IPU EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/ BOOT[12] T13 I/O IPU EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] P9 I/O IPU EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] R9 I/O EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] P8 EMIFA, LCD, GPIO EMIFA, MMC/SD, GPIO, BOOT UHPI data bus EMIFA, MMC/SD, GPIO EMIFA, MMC/SD, GPIO, BOOT IPU EMIFA, MMCSD_CMD, GPIO UHPI access control I/O IPU EMIFA, LCD, GPIO UHPI half-word identification control M13 I/O IPU EMIFA, McASP, GPIO, BOOT UHPI read/write EMA_CS[2]/ UHPI_HCS /GP2[5]/BOOT[15] P7 I/O IPU EMIFA, GPIO, BOOT UHPI chip select EMA_WE_DQM[1]/ UHPI_HDS2 /AXR0[14]/GP2[8] P12 I/O IPU EMA_OE/ UHPI_HDS1 /AXR0[13]/GP2[7] R7 I/O IPU M14 I/O IPU EMA_WAIT[0]/ UHPI_HRDY /GP2[10] N6 I/O IPU EMA_CS[0]/ UHPI_HAS /GP2[4] T8 I/O IPU EMA_WE/UHPI_HRW /AXR0[12]/GP2[3]/BOOT[14] EMA_WE_DQM[0]/ UHPI_HINT /AXR0[15]/GP2[9] (1) (2) EMIFA, McASP0, GPIO UHPI data strobe UHPI host interrupt EMIFA, GPIO UHPI ready UHPI address strobe I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 27 ADVANCE INFORMATION EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com 3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2) Table 3-17. Multichannel Audio Serial Ports (McASPs) Terminal Functions PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB McASP0 EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9] M14 I/O IPU EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8] P12 I/O IPU EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] R7 I/O IPU M13 I/O IPU EMIFA, UHPI, GPIO, BOOT AXR0[11]/ AXR2[0]/GP3[11] A5 I/O IPD McASP2, GPIO UART1_TXD/AXR0[10]/GP3[10] D6 I/O IPD GPIO UART1_RXD/AXR0[9]/GP3[9] C6 I/O IPD GPIO AXR0[8]/MDIO_D/GP3[8] B6 I/O IPU AXR0[7]/MDIO_CLK/GP3[7] A6 I/O IPD AXR0[6]/RMII_RXER/ACLKR2/GP3[6] D7 I/O IPD AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] C7 I/O IPD AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] B7 I/O IPD AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] A7 I/O IPD AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] D8 I/O IPD AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] C8 I/O IPD AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] B8 I/O IPD AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] B5 I/O IPD McASP2, USB, GPIO McASP1 transmit master clock ACLKX0/ECAP0/APWM0/GP2[12] C5 I/O IPD eCAP0, GPIO McASP0 transmit bit clock AFSX0/GP2[13]/BOOT[10] D5 I/O IPD GPIO, BOOT McASP0 transmit frame sync AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] A4 I/O IPD EMAC, GPIO, BOOT McASP0 receive master clock ACLKR0/ECAP1/APWM1/GP2[15] B4 I/O IPD eCAP1, GPIO McASP0 receive bit clock AFSR0/GP3[12] C4 I/O IPD GPIO McASP0 receive frame sync AMUTE0/RESETOUT L4 I/O IPD RESETOUT McASP0 mute output EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] ADVANCE INFORMATION (1) (2) 28 EMIFA, UHPI, GPIO MDIO, GPIO McASP0 serial data EMAC, McASP2, GPIO I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Table 3-17. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued) PIN No. TYPE (1) PULL (2) T4 I/O IPU AXR1[10]/GP5[10] N3 I/O IPU AXR1[9]/GP4[9] M1 I/O IPD AXR1[8]/EPWM1A/GP4[8] M2 I/O IPD eHRPWM1 A, GPIO AXR1[7]/EPWM1B/GP4[7] M3 I/O IPD eHRPWM1 B, GPIO AXR1[6]/EPWM2A/GP4[6] M4 I/O IPD eHRPWM2 A, GPIO AXR1[5]/EPWM2B/GP4[5] N1 I/O IPD eHRPWM2 B, GPIO AXR1[4]/EQEP1B/GP4[4] N2 I/O IPD AXR1[3]/EQEP1A/GP4[3] P1 I/O IPD AXR1[2]/GP4[2] P2 I/O IPD AXR1[1]/GP4[1] R2 I/O IPD AXR1[0]/GP4[0] T3 I/O IPD AHCLKX1/EPWM0B/GP3[14] K2 I/O IPD eHRPWM0, GPIO McASP1 transmit master clock ACLKX1/EPWM0A/GP3[15] K3 I/O IPD eHRPWM0, GPIO McASP1 transmit bit clock AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] K4 I/O IPD eHRPWM0, GPIO McASP1 transmit frame sync AHCLKR1/GP4[11] L1 I/O IPD GPIO McASP1 receive master clock ACLKR1/ECAP2/APWM2/GP4[12] L2 I/O IPD eCAP2, GPIO McASP1 receive bit clock AFSR1/GP4[13] L3 I/O IPD GPIO McASP1 receive frame sync eHRPWM0, eHRPWM1, eHRPWM2, GPIO McASP1 mute output McASP0, EMAC, GPIO McASP2 serial data SIGNAL NAME MUXED DESCRIPTION ZKB McASP1 AMUTE1/EPWMTZ/GP4[14] GPIO McASP1 serial data eQEP1, GPIO GPIO D4 I/O IPD AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] B8 I/O IPD AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] D8 I/O IPD AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] A7 I/O IPD AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] B7 I/O IPD AXR0[11]/AXR2[0]/GP3[11] A5 I/O IPD AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] B5 I/O IPD McASP0, USB, GPIO McASP2 transmit master clock AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] C8 I/O IPD McASP0, EMAC, GPIO McASP2 transmit bit clock AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] C7 I/O IPD McASP0, EMAC, GPIO McASP2 transmit frame sync EMA_CLK/OBSCLK/AHCLKR2/GP1[15] R12 I/O IPU EMIFA, GPIO, OBSCLK McASP2 receive master clock AXR0[6]/RMII_RXER/ACLKR2/GP3[6] D7 I/O IPD McASP0, EMAC, GPIO McASP2 receive bit clock EMA_CS[3]/AMUTE2/GP2[6] T7 I/O IPU EMIFA, GPIO McASP2 mute output McASP2 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 29 ADVANCE INFORMATION AXR1[11]/GP5[11] AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com 3.6.16 Universal Serial Bus Modules (USB0, USB1) Table 3-18. Universal Serial Bus (USB) Terminal Functions SIGNAL NAME PIN No. TYPE (1) PULL (2) MUXED DESCRIPTION ZKB USB0 2.0 OTG (USB0) USB0_DM G4 A NA USB0 PHY data minus USB0_DP F4 A NA USB0 PHY data plus USB0_VDDA33 VDDA33 H5 PWR NA USB0 PHY 3.3-V supply USB0_VDDA18 VDDA18 E3 PWR NA USB0 PHY 1.8-V supply input USB0_VDDA12 VDDA12 (3) C3 PWR NA USB0 PHY 1.2-V LDO output for bypass cap USB0_ID D2 A NA USB0 PHY identification (mini-A or mini-B plug) USB0_VBUS D3 A NA USB0 bus voltage USB0_DRVVBUS/GP4[15] E4 0 IPD GPIO USB0 controller VBUS control output. AHCLKX0/AHCLKX2/USB_REFCLKIN/ GP2[11] B5 I IPD USB_REFCLKIN. Optional clock input. ADVANCE INFORMATION USB1 1.1 OHCI (USB1) USB1_DM B3 A NA USB1 PHY data minus USB1_DP A3 A NA USB1 PHY data plus USB1_VDDA33 VDDA33 C1 PWR NA USB1 PHY 3.3-V supply USB1_VDDA18 VDDA18 C2 PWR NA USB1 PHY 1.8-V supply AHCLKX0/AHCLKX2/USB_REFCLKIN/ GP2[11] B5 I NA USB_REFCLKIN. Optional clock input. (1) (2) (3) 30 IPD I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Core power supply LDO output for USB PHY. This pin must be connected via a 0.22 uF capacitor to VSS. Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 3.6.17 Ethernet Media Access Controller (EMAC) Table 3-19. Ethernet Media Access Controller (EMAC) Terminal Functions SIGNAL NAME PIN No. TYPE (1) PULL (2) MUXED DESCRIPTION ZKB RMII A4 I/O IPD AXR0[6]/RMII_RXER/ACLKR2/GP3[6] D7 I IPD AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] C7 I IPD AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] B7 I IPD AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] A7 I IPD AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] D8 O IPD AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] C8 O IPD AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] B8 O IPD AXR0[8]/MDIO_D/GP3[8] B6 I/O IPU AXR0[7]/MDIO_CLK/GP3[7] A6 O IPD EMAC 50-MHz clock input or output McASP0, GPIO, BOOT EMAC RMII receiver error EMAC RMII receive data EMAC RMII carrier sense data valid McASP0, McASP2, GPIO EMAC RMII transmit enable EMAC RMII trasmit data MDIO (1) (2) MDIO serial data McASP0, GPIO MDIO clock I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.18 Multimedia Card/Secure Digital (MMC/SD) Table 3-20. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions PIN No. SIGNAL NAME TYPE (1) PULL (2) MUXED DESCRIPTION ZKB EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] R9 O IPU EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] P9 I/O IPU EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] M15 I/O IPU EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] N13 I/O IPU EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] N15 I/O IPU EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] P13 I/O IPU EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] P15 I/O IPU EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] R13 I/O IPU EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] R15 I/O IPU EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] T13 I/O IPU (1) (2) EMIFA, UHPI, GPIO MMCSD Clock MMCSD Command EMIFA, UHPI, GPIO, BOOT EMIFA, UHPI, GPIO MMC/SD data EMIFA, UHPI, GPIO, BOOT I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 31 ADVANCE INFORMATION AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 3.6.19 www.ti.com Liquid Crystal Display Controller (LCD) Table 3-21. Liquid Crystal Display Controller (LCD) Terminal Functions PIN No. SIGNAL NAME ZKB TYPE (1) PULL (2) EMA_D[15]/UHPI_HD[15]/LCD_D [15]/GP0[15] M16 I/O N14 I/O IPD EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] N16 I/O IPD EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] P14 I/O IPD EMA_D[11]/UHPI_HD[11]/LCD_D[11 ]/GP0[11] P16 I/O IPD EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] R14 I/O IPD EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] T14 I/O IPD EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] DESCRIPTION IPD EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] MUXED EMIFA, UHPI, GPIO LCD data bus I/O IPD T9 I/O IPD EMA_A[3]/LCD_D[6]/GP1[3] N9 I/O IPD EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] ADVANCE INFORMATION N12 EMA_A[0]/LCD_D[7]/GP1[0] P8 I/O IPU EMA_BA[0]/LCD_D[4]/GP1[14] R8 I/O IPU EMA_A[4]/LCD_D[3]/GP1[4] T10 I/O IPD EMA_A[5]/LCD_D[2]/GP1[5] R10 I/O IPD EMA_A[6]/LCD_D[1]/GP1[6] P10 I/O IPD EMA_A[7]/LCD_D[0]/GP1[7] N10 I/O IPD EMA_A[8]/LCD_PCLK/GP1[8] T11 O IPU EMA_A[9]/LCD_HSYNC/GP1[9] R11 O IPU LCD horizontal sync EMA_A[10]/LCD_VSYNC/GP1[10] N8 O IPU LCD vertical sync EMA_A[11]/ LCD_AC_ENB_CS /GP1[11] P11 O IPU LCD AC bias enable chip select EMA_A[12]/LCD_MCLK/GP1[12] N11 O IPU LCD memory clock (1) (2) EMIFA, GPIO EMIFA, UHPI, GPIO LCD data bus EMIFA, GPIO LCD pixel clock I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor 3.6.20 Reserved and No Connect Table 3-22. Reserved and No Connect Terminal Functions SIGNAL NAME PIN No. ZKB TYPE (1) DESCRIPTION RSV1 F7 PWR Reserved. (Leave unconnected, do not connect to power or ground.) RSV2 B1 PWR Reserved. For proper device operation, this pin must be tied directly to CVDD. NC F3 - No Connect (leave unconnected) H4 - No Connect (leave unconnected) NC (1) PWR = Supply voltage. 32 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 3.6.21 Supply and Ground Table 3-23. Supply and Ground Terminal Functions SIGNAL NAME PIN No. TYPE (1) ZKB DESCRIPTION PWR Core supply voltage pins RVDD (Internal RAM supply) H6, H12 PWR Internal ram supply voltage pins DVDD (I/O supply) B16, E5, E8, E9, E12, F5, F11, F12, G5, G12, K5, K12, L5, L11, L12, M5, M8, M9, M12, R1, R16 PWR I/O supply voltage pins VSS (Ground) A1, A2, A15, A16, B2, E6, E7, E10, E11, F8, F9, F10, G8, G9, H8, H9, J8, J9, K8, K9, L7, L8, L9, L10, M6, M7, M10, M11, T1, T2, T15, T16 GND Ground pins (1) ADVANCE INFORMATION CVDD (Core supply) F6,G6, G7, G10, G11, H7, H10, H11, J6, J7, J10, J11, J12, K6, K7, K10, K11,L6 PWR = Supply voltage, GND - Ground. Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 33 AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com 4 Device Configuration 4.1 Boot Modes This device supports a variety of boot modes through an internal ROM bootloader. This device does not support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by the values of the BOOT pins ADVANCE INFORMATION The following boot modes are supported: · NAND Flash boot ­ 8-bit NAND · NOR Flash boot ­ NOR Direct boot (8-bit or 16-bit) ­ NOR Legacy boot (8-bit or 16-bit) ­ NOR AIS boot (8-bit or 16-bit) · HPI Boot · I2C0 / I2C1 Boot ­ EEPROM (Master Mode) ­ External Host (Slave Mode) · SPI0 / SPI1 Boot ­ Serial Flash (Master Mode) ­ SERIAL EEPROM (Master Mode) ­ External Host (Slave Mode) · UART0 / UART1 / UART2 Boot ­ External Host 34 Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 4.2 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 SYSCFG Module Many registers are accessible only by a host (ARM) when it is operating in its privileged mode. (ex. from the kernel, but not from user space code). Table 4-1. System Configuration (SYSCFG) Module Register Access BYTE ADDRESS ACRONYM 0x01C1 4000 REVID Revision Identification Register REGISTER DESCRIPTION ACCESS - 0x01C14008 DIEIDR0 Device Identification Register 0 - 0x01C1 400C DIEIDR1 Device Identification Register 1 - 0x01C1 4010 DIEIDR2 Device Identification Register 2 - 0x01C1 4014 DIEIDR3 Device Identification Register 3 - 0x01C1 4018 DEVIDR0 Device Identification Register 0 - 0x01C1 4020 BOOTCFG Boot Configuration Register Privileged mode 0x01C1 4038 KICK0R Kick 0 Register Privileged mode 0x01C1 403C KICK1R Kick 1 Register Privileged mode 0x01C1 4040 HOST0CFG Host 0 Configuration Register 0x01C1 4044 HOST1CFG Host 1 Configuration Register 0x01C1 40E0 IRAWSTAT Interrupt Raw Status/Set Register Privileged mode 0x01C1 40E4 IENSTAT Interrupt Enable Status/Clear Register Privileged mode - - 0x01C1 40E8 IENSET Interrupt Enable Register Privileged mode 0x01C1 40EC IENCLR Interrupt Enable Clear Register Privileged mode 0x01C1 40F0 EOI End of Interrupt Register Privileged mode 0x01C1 40F4 FLTADDRR Fault Address Register Privileged mode 0x01C1 40F8 FLTSTAT Fault Status Register 0x01C1 4110 MSTPRI0 Master Priority 0 Register Privileged mode 0x01C1 4114 MSTPRI1 Master Priority 1 Register Privileged mode 0x01C1 4118 MSTPRI2 Master Priority 2 Register Privileged mode 0x01C1 4120 PINMUX0 Pin Multiplexing Control 0 Register Privileged mode 0x01C1 4124 PINMUX1 Pin Multiplexing Control 1 Register Privileged mode - 0x01C1 4128 PINMUX2 Pin Multiplexing Control 2 Register Privileged mode 0x01C1 412C PINMUX3 Pin Multiplexing Control 3 Register Privileged mode 0x01C1 4130 PINMUX4 Pin Multiplexing Control 4 Register Privileged mode 0x01C1 4134 PINMUX5 Pin Multiplexing Control 5 Register Privileged mode 0x01C1 4138 PINMUX6 Pin Multiplexing Control 6 Register Privileged mode Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 35 ADVANCE INFORMATION The following system level features of the chip are controlled by the SYSCFG peripheral: · Readable Device, Die, and Chip Revision ID · Control of Pin Multiplexing · Priority of bus accesses different bus masters in the system · Capture at power on reset the chip BOOT[15:0] pin values and make them available to software · Special case settings for peripherals: ­ Locking of PLL controller settings ­ Default burst sizes for EDMA3 TC0 and TC1 ­ Selection of the source for the eCAP module input capture (including on chip sources) ­ McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals ­ Control of the reference clock source and other side-band signals for both of the integrated USB PHYs ­ Clock source selection for EMIFA and EMIFB · Selects the source of emulation suspend signal of peripherals supporting this function. AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com Table 4-1. System Configuration (SYSCFG) Module Register Access (continued) BYTE ADDRESS ACRONYM 0x01C1 413C PINMUX7 Pin Multiplexing Control 7 Register REGISTER DESCRIPTION Privileged mode ACCESS 0x01C1 4140 PINMUX8 Pin Multiplexing Control 8 Register Privileged mode 0x01C1 4144 PINMUX9 Pin Multiplexing Control 9 Register Privileged mode 0x01C1 4148 PINMUX10 PINMUX10 Pin Multiplexing Control 10 Register Privileged mode 0x01C1 414C PINMUX11 PINMUX11 Pin Multiplexing Control 11 Register Privileged mode 0x01C1 4150 PINMUX12 PINMUX12 Pin Multiplexing Control 12 Register Privileged mode 0x01C1 4154 PINMUX13 PINMUX13 Pin Multiplexing Control 13 Register Privileged mode 0x01C1 4158 PINMUX14 PINMUX14 Pin Multiplexing Control 14 Register Privileged mode 0x01C1 415C PINMUX15 PINMUX15 Pin Multiplexing Control 15 Register Privileged mode 0x01C1 4160 PINMUX16 PINMUX16 Pin Multiplexing Control 16 Register Privileged mode 0x01C1 4164 PINMUX17 PINMUX17 Pin Multiplexing Control 17 Register Privileged mode Pin Multiplexing Control 18 Register Privileged mode PINMUX19 PINMUX19 Pin Multiplexing Control 19 Register Privileged mode SUSPSRC Suspend Source Register Privileged mode 0x01C1 4174 - Reserved 0x01C1 4178 - Reserved 0x01C1 417C CFGCHIP0 Chip Configuration 0 Register Privileged mode 0x01C1 4180 CFGCHIP1 Chip Configuration 1 Register Privileged mode 0x01C1 4184 CFGCHIP2 Chip Configuration 2 Register Privileged mode 0x01C1 4188 CFGCHIP3 Chip Configuration 3 Register Privileged mode 0x01C1 418C 36 PINMUX18 PINMUX18 0x01C1 4170 ADVANCE INFORMATION 0x01C1 4168 0x01C1 416C CFGCHIP4 Chip Configuration 4 Register Privileged mode Device Configuration - - Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 4.3 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Pullup/Pulldown Resistors Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors. An external pullup/pulldown resistor needs to be used in the following situations: · Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state. · Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. Tips for choosing an external pullup/pulldown resistor: · Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors. · Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which, by definition, have margin to the VIL and VIH levels. · Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net. · For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin). · Remember to include tolerances when selecting the resistor value. · For pullup resistors, also remember to include tolerances on the IO supply rail. · For most systems, a 1-k resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application. · For most systems, a 20-k resistor can be used to compliment the IPU/IPD on the boot and configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application. · For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) for the device, see Section 5.2, Recommended Operating Conditions. · For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table. Device Configuration Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 37 ADVANCE INFORMATION For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device boot and configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switching operating modes. AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 www.ti.com 5 Device Operating Conditions 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted) (1) Core (CVDD, RVDD, RTC_CVDD, PLL0_VDDA ) Supply voltage ranges I/O, 1.8V (USB0_VDDA18 VDDA18, USB1_VDDA18 VDDA18) -0.5 V to 1.4 V (2) -0.5 V to 2 V (2) I/O, 3.3V (DVDD, USB0_VDDA33 VDDA33, USB1_VDDA33 VDDA33) -0.5 V to 3.8V (2) VI I/O, 1.2V (OSCIN, RTC_XI) VI I/O, 3.3V (Steady State) Input voltage ranges -0.3 V to CVDD + 0.3V -0.3V to DVDD + 0.3V VI I/O, 3.3V (Transient) DVDD + 20% up to 20% of Signal Period ADVANCE INFORMATION VI I/O, USB 5V Tolerant Pins: (USB0_DM, USB0_DP, USB0_ID, USB1_DM, USB1_DP) VI I/O, USB0 VBUS Output voltage ranges 5.25V (3) 5.50V (3) VO I/O, 3.3V (Steady State) -0.5 V to DVDD + 0.3V VO I/O, 3.3V (Transient Overshoot/Undershoot) 20% of DVDD for up to 20% of the signal period Clamp Current Input or Output Voltages 0.3V above or below their respective power rails. Limit clamp current that flows through the I/O's internal diode protection cells. Storage temperature range, Tstg (default) ±20mA -55°C to 150°C Commercial (default) (2) (3) 38 -40°C to 90°C -40°C to 105°C Automotive (T version) (1) 0°C to 90°C Industrial (D version) Extended (A version) Operating Junction Temperature ranges, TJ -40°C to 125°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS, PLL0_VSSA, OSCVSS, RTC_VSS Up to a max of 24 hours. Device Operating Conditions Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 AM1707 AM1707 www.ti.com 5.2 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 Recommended Operating Conditions MIN NOM MAX UNIT 375 MHz version 1.14 1.2 1.32 V 456 MHz version 1.25 1.3 1.35 V CVDD Supply voltage, Core (CVDD, RTC_CVDD, PLL0_VDDA ) RVDD Supply Voltage, Internal RAM 1.14 1.2 1.32 V Supply voltage, I/O, 1.8V (USB0_VDDA18 VDDA18, USB1_VDDA18 VDDA18) 1.71 1.8 1.89 V Supply voltage, I/O, 3.3V (DVDD, USB0_VDDA33 VDDA33, USB1_VDDA33 VDDA33) 3.15 3.3 3.45 V 0 0 0 V Supply ground (VSS, PLL0_VSSA, OSCVSS (1), RTC_VSS (1) VSS High-level input voltage, I/O, 3.3V (2) 2 V High-level input voltage, RTC_XI 0.7*RTC_CVDD V High-level input voltage, OSCIN VIH 0.7*CVDD Low-level input voltage, I/O, 3.3V VIL (2) 0.8 V Low-level input voltage, RTC_XI 0.3*RTC_CVDD V Low-level input voltage, OSCIN 0.3*CVDD VHYS Input Hysteresis 160 USB USB0_VBUS tt Transition time, 10%-90%, All Inputs (unless otherwise specified in the electrical data sections) 4.75 5 mV 5.25 0.25P or 10 V (3) ns Commercial (default) (1) (2) (3) MHz Industrial (D suffix) 0 456 (1.3V) MHz 0 375(1.2V) MHz Automotive (T suffix) ARM Operating Frequency (SYSCLK6) 375 (1.2V) 456 (1.3V) Extended (A suffix) FSYSCLK6 0 0 375 (1.2V) MHz When an external crystal is used, oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground. These I/O specifications do not apply to USB I/Os. USB0 I/Os adhere to USB2.0 specification. USB1 I/Os adhere to USB1.1 specification. Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals. Device Operating Conditions Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1707 AM1707 39 ADVANCE INFORMATION DVDD AM1707 AM1707 SPRS637B SPRS637B ­ FEBRUARY 2010 ­ REVISED AUGUST 2010 5.3 www.ti.com Notes on Recommended Power-On Hours (POH) The information in the section be