ALC5620 JATR-1076-21 REG-00H REG-02H REG-04H REG-08H REG-10H REG-12H REG-14H - Datasheet Archive

 

I2S AUDIO CODEC + VOICE PCM INTERFACE DATASHEET Rev. 1.0 15 August 2007 Track ID: JATR-1076-21 Realtek Semiconductor Corp. No. 2,

 

ALC5620 ALC5620 I2S AUDIO CODEC + VOICE PCM INTERFACE DATASHEET Rev. 1.0 15 August 2007 Track ID: JATR-1076-21 JATR-1076-21 Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw ALC5620 ALC5620 Datasheet COPYRIGHT ©2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer's general information on the Realtek ALC5620 ALC5620 Audio Codec IC. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. REVISION HISTORY Revision 1.0 Release Date 2007/08/15 Summary First release I2C + I2S Audio Codec + Voice PCM Interface ii Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet Table of Contents 1. GENERAL DESCRIPTION .1 2. FEATURES .2 3. SYSTEM APPLICATIONS.2 4. FUNCTION BLOCK DIAGRAM.3 4.1. 4.2. 5. PIN ASSIGNMENTS .5 5.1. 6. GREEN PACKAGE AND VERSION IDENTIFICATION .5 PIN DESCRIPTIONS.6 6.1. 6.2. 6.3. 6.4. 7. FUNCTION BLOCK .3 AUDIO MIXER PATH.4 DIGITAL I/O PINS .6 ANALOG I/O PINS .6 FILTER/REFERENCE.7 POWER/GROUND .7 FUNCTIONAL DESCRIPTION.8 7.1. POWER .8 7.2. RESET .8 7.2.1. Power-On Reset (POR) .8 7.3. CLOCKING .9 7.3.1. Phase-Locked Loop .9 7.3.2. I2C and Stereo I2S.10 7.3.3. Voice_I2S/PCM Interface .11 7.3.4. Voice ADC.11 7.4. DIGITAL DATA INTERFACE .12 7.4.1. Stereo and Voice I2S/PCM Interface .12 7.5. AUDIO DATA PATH .15 7.5.1. Stereo ADC and Voice ADC.15 7.5.2. Stereo DAC.15 7.5.3. Voice to Stereo Digital Path.15 7.5.4. Voice DAC.15 7.6. MIXERS .16 7.6.1. Headphone Mixer .16 7.6.2. MONO Mixer.16 7.6.3. Speaker Mixer.17 7.6.4. ADC Record Mixer .17 7.7. ANALOG AUDIO INPUT PATH .18 7.7.1. Line Input .18 7.7.2. Phone Input .18 7.7.3. Microphone Input .18 7.8. ANALOG AUDIO OUTPUT DATA PATH .19 7.8.1. Speaker Output .19 7.8.2. Headphone Output.20 7.8.3. MONO Output .20 7.9. AVC CONTROL .21 7.10. HARDWARE SOUND EFFECTS .22 7.10.1. Equalizer Block.22 I2C + I2S Audio Codec + Voice PCM Interface iii Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.10.2. Pseudo Stereo and Spatial 3D Sound .22 7.11. I2C CONTROL INTERFACE .23 7.11.1. Addressing Setting .23 7.11.2. Complete Data Transfer .23 7.12. ODD-ADDRESSED REGISTER ACCESS .24 7.13. POWER MANAGEMENT .24 7.14. GPIO AND INTERRUPT .25 8. MIXER REGISTERS LIST.26 8.1. REG-00H REG-00H: RESET .26 8.2. REG-02H REG-02H: SPEAKER OUTPUT VOLUME .26 8.3. REG-04H REG-04H: HEADPHONE OUTPUT VOLUME .27 8.4. REG-08H REG-08H: PHONE INPUT/MONO OUTPUT VOLUME .27 8.5. REG-0AH: LINE_IN VOLUME .28 8.6. REG-0CH: STEREO DAC VOLUME .28 8.7. REG-0EH: MIC VOLUME .29 8.8. REG-10H REG-10H: MIC ROUTING CONTROL .29 8.9. REG-12H REG-12H: ADC RECORD GAIN .30 8.10. REG-14H REG-14H: ADC RECORD MIXER CONTROL.31 8.11. REG-18H REG-18H: VOICE DAC OUTPUT VOLUME .31 8.12. REG-1CH: OUTPUT MIXER CONTROL .32 8.13. REG-22H REG-22H: MICROPHONE CONTROL .33 8.14. REG-26H REG-26H: POWER DOWN CONTROL/STATUS.33 8.15. REG-34H REG-34H: MAIN SERIAL DATA PORT CONTROL (STEREO I2S) .35 8.16. REG-36H REG-36H: EXTEND SERIAL DATA PORT CONTROL (VODAC_I2S/PCM).36 8.17. REG-3AH: POWER MANAGEMENT ADDITION 1.37 8.18. REG-3CH: POWER MANAGEMENT ADDITION 2 .38 8.19. REG-3EH: POWER MANAGEMENT ADDITION 3 .39 8.20. REG-40H REG-40H: GENERAL PURPOSE CONTROL REGISTER 1 .40 8.21. REG-42H REG-42H: GENERAL PURPOSE CONTROL REGISTER 2 .41 8.22. REG-44H REG-44H: PLL CONTROL .41 8.22.1. AC-LINK PLL Clock Setting Table (Unit: MHz) .42 8.23. REG-4CH: GPIO PIN CONFIGURATION.43 8.24. REG-4EH: GPIO PIN POLARITY .44 8.25. REG-50H REG-50H: GPIO PIN STICKY .45 8.26. REG-52H REG-52H: GPIO PIN WAKE-UP.46 8.27. REG-54H REG-54H: GPIO PIN STATUS .47 8.28. REG-56H REG-56H: PIN SHARING .48 8.29. REG-58H REG-58H: OVER-TEMP/CURRENT STATUS .49 8.30. REG-5CH: GPIO_OUTPUT PIN CONTROL.50 8.31. REG-5EH: MISC CONTROL .50 8.32. REG-60H REG-60H: STEREO DAC CLOCK CONTROL_1 .52 8.33. REG-62H REG-62H: STEREO DAC CLOCK CONTROL_2 .53 8.34. REG-64H REG-64H: VODAC_PCM CLOCK CONTROL_1 .54 8.35. REG-66H REG-66H: VODAC_PCM CLOCK CONTROL_2 .55 8.36. REG-68H REG-68H: PSEUDO STEREO AND SPATIAL EFFECT BLOCK CONTROL .56 8.37. REG-6AH: INDEX ADDRESS .57 8.38. REG-6CH: INDEX DATA .57 8.39. REG-6EH: EQ STATUS .57 8.40. INDEX-00H INDEX-00H: EQ BAND-0 COEFFICIENT (LP0: A1) .58 8.41. INDEX-01H INDEX-01H: EQ BAND-0 GAIN (LP0: HO).58 8.42. INDEX-02H INDEX-02H: EQ BAND-1 COEFFICIENT (BP1: A1) .58 8.43. INDEX-03H INDEX-03H: EQ BAND-1 COEFFICIENT (BP1: A2) .58 8.44. INDEX-04H INDEX-04H: EQ BAND-1 GAIN (BP1: HO) .58 8.45. INDEX-05H INDEX-05H: EQ BAND-2 COEFFICIENT (BP2: A1) .59 I2C + I2S Audio Codec + Voice PCM Interface iv Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.46. 8.47. 8.48. 8.49. 8.50. 8.51. 8.52. 8.53. 8.54. 8.55. 8.56. 8.57. 8.58. 8.59. 8.60. 8.61. 8.62. 8.63. 8.64. 8.65. 8.66. 8.67. 9. INDEX-06H INDEX-06H: EQ BAND-2 COEFFICIENT (BP2: A2) .59 INDEX-07H INDEX-07H: EQ BAND-2 GAIN (BP2: HO) .59 INDEX-08H INDEX-08H: EQ BAND-3 COEFFICIENT (BP3: A1) .59 INDEX-09H INDEX-09H: EQ BAND-3 COEFFICIENT (BP3: A2) .59 INDEX-0AH: EQ BAND-3 GAIN (BP3: HO).60 INDEX-0BH: EQ BAND-4 COEFFICIENT (HPF: A1).60 INDEX-0CH: EQ BAND-4 GAIN (HPF: HO) .60 INDEX-10H INDEX-10H: EQ CONTROL AND STATUS REGISTER .61 INDEX-11H INDEX-11H: EQ INPUT VOLUME CONTROL .61 INDEX-12H INDEX-12H: EQ OUTPUT VOLUME CONTROL.62 INDEX-20H INDEX-20H: AUTO VOLUME CONTROL REGISTER 0 .62 INDEX-21H INDEX-21H: AUTO VOLUME CONTROL REGISTER 1 .63 INDEX-22H INDEX-22H: AUTO VOLUME CONTROL REGISTER 2 .63 INDEX-23H INDEX-23H: AUTO VOLUME CONTROL REGISTER 3 .63 INDEX-24H INDEX-24H: AUTO VOLUME CONTROL REGISTER 4 .63 INDEX-25H INDEX-25H: AUTO VOLUME CONTROL REGISTER 5 .64 INDEX-39H INDEX-39H: DIGITAL INTERNAL REGISTER .64 INDEX-44H INDEX-44H: CLASS AB INTERNAL REGISTER .64 INDEX-4AH: CLASS D TEMPERATURE SENSOR .65 INDEX-54H INDEX-54H: AD_DA_MIXER_INTERNAL REGISTER .65 REG-7CH: VENDOR ID 1 .66 REG-7EH: VENDOR ID 2 .66 ELECTRICAL CHARACTERISTICS .67 9.1. DC CHARACTERISTICS .67 9.1.1. Absolute Maximum Ratings .67 9.1.2. Recommended Operating Conditions .67 9.1.3. Static Characteristics .68 9.2. ANALOG PERFORMANCE CHARACTERISTICS .68 10. APPLICATION CIRCUITS .71 11. MECHANICAL DIMENSIONS.72 12. APPENDIX A: STEREO I2S CLOCK TABLE.73 12.1. 13. 13.1. 13.2. 14. MASTER/SLAVE MODE .73 APPENDIX B: VOICE PCM INTERFACE.74 MASTER MODE: (VOICE_PORT_SEL=0) .74 SLAVE MODE: (VOICE_PORT_SEL=1).75 ORDERING INFORMATION .75 I2C + I2S Audio Codec + Voice PCM Interface v Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet List of Tables TABLE 1. TABLE 2. TABLE 3. TABLE 4. TABLE 5. TABLE 6. TABLE 7. TABLE 8. TABLE 9. TABLE 10. TABLE 11. TABLE 12. TABLE 13. TABLE 14. TABLE 15. TABLE 16. TABLE 17. TABLE 18. TABLE 19. TABLE 20. TABLE 21. TABLE 22. TABLE 23. TABLE 24. TABLE 25. TABLE 26. TABLE 27. TABLE 28. TABLE 29. TABLE 30. TABLE 31. TABLE 32. TABLE 33. TABLE 34. TABLE 35. TABLE 36. TABLE 37 TABLE 38. TABLE 39. TABLE 40. TABLE 41. TABLE 42. TABLE 43. TABLE 44. TABLE 45. TABLE 46. TABLE 47. TABLE 48. TABLE 49. TABLE 50. TABLE 51. TABLE 52. DIGITAL I/O PINS .6 ANALOG I/O PINS .6 FILTER/REFERENCE .7 POWER/GROUND.7 POWER SETTING FOR BEST PERFORMANCE .8 RESET OPERATION .8 POWER-ON RESET VOLTAGE .8 CLOCK SETTING TABLE FOR 48K (UNIT: MHZ).9 CLOCK SETTING TABLE FOR 44.1K (UNIT: MHZ).10 ADDRESSING SETTING .23 WRITE WORD PROTOCOL .24 READ WORD PROTOCOL .24 REG-00H REG-00H: RESET .26 REG-02H REG-02H: SPEAKER OUTPUT VOLUME .26 REG-04H REG-04H: HEADPHONE OUTPUT VOLUME .27 REG-08H REG-08H: PHONE INPUT / MONO OUTPUT VOLUME.27 REG-0AH: LINE_IN VOLUME.28 REG-0CH: STEREO DAC VOLUME .28 REG-0EH: MIC VOLUME .29 REG-10H REG-10H: MIC ROUTING CONTROL .29 REG-12H REG-12H: ADC RECORD GAIN .30 REG-14H REG-14H: ADC RECORD MIXER CONTROL .31 REG-18H REG-18H: VOICE DAC OUTPUT VOLUME .31 REG-1CH: OUTPUT MIXER CONTROL .32 REG-22H REG-22H: MICROPHONE CONTROL.33 REG-26H REG-26H: POWER DOWN CONTROL/STATUS .33 TRUTH TABLE FOR POWER DOWN MODE: (PD= POWER DOWN).34 REG-34H REG-34H: MAIN SERIAL DATA PORT CONTROL (STEREO I2S).35 REG-36H REG-36H: EXTEND SERIAL DATA PORT CONTROL (VODAC_I2S/PCM) .36 REG-3AH: POWER MANAGEMENT ADDITION 1 .37 REG-3CH: POWER MANAGEMENT ADDITION 2 .38 REG-3EH: POWER MANAGEMENT ADDITION 3.39 REG-40H REG-40H: GENERAL PURPOSE CONTROL REGISTER 1 .40 REG-42H REG-42H: GENERAL PURPOSE CONTROL REGISTER 2 .41 REG-44H REG-44H: PLL CONTROL .41 I2C+I2S CLOCK SETTING TABLE FOR 48K: (UNIT: MHZ) .42 I2C+I2S CLOCK SETTING TABLE FOR 44.1K: (UNIT: MHZ).42 REG-4CH: GPIO PIN CONFIGURATION .43 REG-4EH: GPIO PIN POLARITY .44 REG-50H REG-50H: GPIO PIN STICKY .45 REG-52H REG-52H: GPIO PIN WAKE-UP .46 REG-54H REG-54H: GPIO PIN STATUS .47 REG-56H REG-56H: PIN SHARING .48 REG-58H REG-58H: OVER-TEMP / CURRENT STATUS .49 REG-5CH: GPIO_OUTPUT PIN CONTROL .50 REG-5EH: MISC CONTROL .50 REG-60H REG-60H: STEREO DAC CLOCK CONTROL_1.52 REG-62H REG-62H: STEREO DAC CLOCK CONTROL_2.53 REG-64H REG-64H: VODAC_PCM CLOCK CONTROL_1 .54 REG-66H REG-66H: VODAC_PCM CLOCK CONTROL_2 .55 REG-68H REG-68H: PSEUDO STEREO AND SPATIAL EFFECT BLOCK CONTROL.56 REG-6AH: INDEX ADDRESS .57 I2C + I2S Audio Codec + Voice PCM Interface vi Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet TABLE 53. TABLE 54. TABLE 55. TABLE 56. TABLE 57. TABLE 58. TABLE 59. TABLE 60. TABLE 61. TABLE 62. TABLE 63. TABLE 64. TABLE 65. TABLE 66. TABLE 67. TABLE 68. TABLE 69. TABLE 70. TABLE 71. TABLE 72. TABLE 73. TABLE 74. TABLE 75. TABLE 76. TABLE 77. TABLE 78. TABLE 79. TABLE 80. TABLE 81. TABLE 82. TABLE 83. TABLE 84. TABLE 85. TABLE 86. TABLE 87. REG-6CH: INDEX DATA .57 REG-6EH: EQ STATUS .57 INDEX-00H INDEX-00H: EQ BAND-0 COEFFICIENT (LP0: A1).58 INDEX-01H INDEX-01H: EQ BAND-0 GAIN (LP0: HO) .58 INDEX-02H INDEX-02H: EQ BAND-1 COEFFICIENT (BP1: A1) .58 INDEX-03H INDEX-03H: EQ BAND-1 COEFFICIENT (BP1: A2) .58 INDEX-04H INDEX-04H: EQ BAND-1 GAIN (BP1: HO).58 INDEX-05H INDEX-05H: EQ BAND-2 COEFFICIENT (BP2: A1) .59 INDEX-06H INDEX-06H: EQ BAND-2 COEFFICIENT (BP2: A2) .59 INDEX-07H INDEX-07H: EQ BAND-2 GAIN (BP2: HO).59 INDEX-08H INDEX-08H: EQ BAND-3 COEFFICIENT (BP3: A1) .59 INDEX-09H INDEX-09H: EQ BAND-3 COEFFICIENT (BP3: A2) .59 INDEX-0AH: EQ BAND-3 GAIN (BP3: HO) .60 INDEX-0BH: EQ BAND-4 COEFFICIENT (HPF: A1) .60 INDEX-0CH: EQ BAND-4 GAIN (HPF: HO).60 INDEX-10H INDEX-10H: EQ CONTROL AND STATUS REGISTER .61 INDEX-11H INDEX-11H: EQ INPUT VOLUME CONTROL .61 INDEX-12H INDEX-12H: EQ OUTPUT VOLUME CONTROL .62 INDEX-20H INDEX-20H: AUTO VOLUME CONTROL REGISTER 0 .62 INDEX-21H INDEX-21H: AUTO VOLUME CONTROL REGISTER 1 .63 INDEX-22H INDEX-22H: AUTO VOLUME CONTROL REGISTER 2 .63 INDEX-23H INDEX-23H: AUTO VOLUME CONTROL REGISTER 3 .63 INDEX-24H INDEX-24H: AUTO VOLUME CONTROL REGISTER 4 .63 INDEX-25H INDEX-25H: AUTO VOLUME CONTROL REGISTER 5 .64 INDEX-39H INDEX-39H: DIGITAL INTERNAL REGISTER.64 INDEX-44H INDEX-44H: CLASS AB INTERNAL REGISTER .64 INDEX-4AH: CLASS D TEMPERATURE SENSOR .65 INDEX-54H INDEX-54H: AD_DA_MIXER_INTERNAL REGISTER .65 REG-7CH: VENDOR ID 1.66 REG-7EH: VENDOR ID 2.66 ABSOLUTE MAXIMUM RATINGS .67 RECOMMENDED OPERATING CONDITIONS.67 STATIC CHARACTERISTICS .68 ANALOG PERFORMANCE CHARACTERISTICS .68 ORDERING INFORMATION .76 I2C + I2S Audio Codec + Voice PCM Interface vii Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet List of Figures FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. FIGURE 9. FIGURE 10. FIGURE 11. FIGURE 12. FIGURE 13. FIGURE 14. FIGURE 15. FIGURE 16. FIGURE 17. BLOCK DIAGRAM .3 AUDIO MIXER PATH .4 PIN ASSIGNMENTS .5 PCM MONO DATA MODE A FORMAT (BCLK_POLARITY=0) .12 PCM MONO DATA MODE A FORMAT (BCLK_POLARITY=1) .12 PCM MONO DATA MODE B FORMAT (BCLK_POLARITY=0) .13 PCM STEREO DATA MODE A FORMAT (BCLK_POLARITY=0).13 PCM STEREO DATA MODE B FORMAT (BCLK_POLARITY=0).13 I2S DATA FORMAT (BCLK_POLARITY=0) .14 LEFT-JUSTIFIED DATA FORMAT (BCLK_POLARITY=0) .14 RIGHT-JUSTIFIED DATA FORMAT (BCLK_POLARITY=0) .14 AUTO VOLUME CONTROL BLOCK DIAGRAM.21 DATA TRANSFER OVER I2C CONTROL INTERFACE .23 GPIO IMPLEMENTATION .25 POWER CONTROL TO MIC INPUT .40 GPIO AND IRQ LOGIC .48 JACK-INSERT-DETECT PULL UP RESISTER IMPLEMENTED VIA AN EXTERNAL CIRCUIT.51 I2C + I2S Audio Codec + Voice PCM Interface viii Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 1. General Description The ALC5620 ALC5620 is a highly-integrated dual I2S/PCM interface audio codec with multiple input/output ports and is designed for mobile computing and communications. It provides a dual-channel Hi-Fi codec for playback, and dual-channel ADC for recording via an I2S interface. In addition, an Independent Voice DAC is provided with PCM interface for Bluetooth applications. Both Stereo audio and voice functions are supported via the I2S/PCM configurable interface. To reduce component count, the device can connect directly to: · MONO or stereo differential analog inputs · Stereo headphone · Single-end or BTL MONO output · MONO or Stereo Bridge-Tied Load (BTL) speaker Multiple analog input and output pins are provided for seamless integration with analog connected wireless communication devices. Differential input/output connections efficiently reduce noise interference, providing better sound quality. Class-AB or Class-D amplifiers are easily swapped via simple register configuration, and the 1 Watt speaker removes the need for an additional amplifier, further cutting both cost and required board area. Additionally, a flexible hardware 5-band equalizer with configurable gain, bandwidth, and center frequency, and enriches the sound experience. The ALC5620 ALC5620 operates at supply voltages from 1.8 to 5 Volts. To extend battery life, each section of the device can be powered down individually under software control. Leakage current in maximum power saving state is less than 10µA. The ALC5620 ALC5620 is available in a 7x7mm `Green' QFN package, making it ideal for use in handheld portable systems. I2C + I2S Audio Codec + Voice PCM Interface 1 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 2. Features High Performance I2S Codec 16-bit stereo DAC SNR 90dB, THD+N -85dB 16-bit stereo ADC SNR 85dB, THD+N -80dB Supports I2S/PCM input and output interface One analog stereo input (LINE-IN) One analog MONO single-ended or differential input (PHONE and PHONEN input) Stereo, single-ended MONO, or differential analog microphone inputs, with boost pre-amplifiers (+20/+30/+40dB) BTL (Bridge-Tied Load) Max. output with on-chip 1W speaker driver (SPKVDD=5V, 8 load) Stereo headphone output with on-chip 45mW headphone driver (HPVDD=3.3V, 16 load) 25mW SE or 75mW BTL MONO output support (AVDD=3.3V, 32 load) Microphone switch detection Integrated 16-bit I2S/PCM interface voice DAC for blue-tooth and other external devices Power management and enhanced power saving Supports digital 5 band equalizer (EQ) Supports digital spatial sound and pseudo stereo effect Supports pop noise suppression Internal PLL can receive wide range of clock input (Digital IO power > 2.3V) Digital power supplies from 1.8V to 3.6V, speaker amplifier power supplies from 2.3V to 5V Analog power and headphone power supplies from 2.3V to 3.6V 7 x 7mm 48-pin QFN package 3. System Applications Tablet PC system/Ultra-Mobile PC (UMPC) GPS/Personal Navigation Device (PND) or Multi-Media phone PDA Phone/Smartphone Personal Media Player (PMP) I2C + I2S Audio Codec + Voice PCM Interface 2 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 4. 4.1. Function Block Diagram Function Block Figure 1. I2C + I2S Audio Codec + Voice PCM Interface Block Diagram 3 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 4.2. Audio Mixer Path Figure 2. I2C + I2S Audio Codec + Voice PCM Interface Audio Mixer Path 4 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 5. Pin Assignments Figure 3. 5.1. Pin Assignments Green Package and Version Identification Green package is indicated by a `G' in the location marked `T' in Figure 3. The version number is shown in the location marked `V'. I2C + I2S Audio Codec + Voice PCM Interface 5 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 6. Pin Descriptions 6.1. Digital I/O Pins Table 1. Name MCLK EXTCLK SDAC BLCK SADC SDALRCK RESET# SADLRCK SCL SDA A1 GPIO1 / VBCLK GPIO2 / IRQOUT GPIO3 / VSLRCK GPIO4 / VSDAC GPIO5 / VSADC 6.2. Digital I/O Pins Type Pin Description Characteristic Definition I 2 Master Clock Input Schmitt trigger I/O 3 External Reference Clock Input/Output Schmitt trigger I 5 Stereo I2S/PCM DAC Data Input Schmitt trigger I/O 6 Stereo I2S/PCM Bit Clock Master: VOL=0.1*DVDD, VOH=0.9*DVDD Slave: Schmitt trigger O 8 Stereo I2S/PCM ADC Data Output VOL =0.1*DVDD, VOH =0.9*DVDD I/O 10 Stereo I2S/PCM DAC Synchronous Signal Master: VOL=0.1*DVDD, VOH=0.9*DVDD Slave: Schmitt trigger I 11 H/W Reset Input (Low Active) Schmitt trigger I/O 12 Stereo I2S/PCM ADC Synchronous Signal Master: VOL=0.1*DVDD, VOH=0.9*DVDD Slave: Schmitt trigger I 13 I2C Clock Schmitt trigger 2 I/O 14 I C Data Schmitt trigger I 15 I2C Address A1 A1: Input I/O 44 General Purpose Input and Output 1 / GPIO: Input / Output Voice I2S/PCM Bit Clock VBCLK: Slave input / Master output I/O 45 General Purpose Input and Output 2 / GPIO: Input / Output Interrupt Output IRQOUT: Output I/O 46 General Purpose Input and Output 3 / GPIO: Input / Output Voice I2S/PCM Synchronous Signal VSLRCK: Slave input / Master output I/O 47 General Purpose Input and Output 4 / GPIO: Input / Output 2 Voice I S/PCM DAC Data Input SDAC: Schmitt trigger input I/O 48 General Purpose Input and Output 5 / GPIO: Input / Output 2 Voice I S/PCM ADC Data Output SADC: Voice data output Total: 16 Pins Analog I/O Pins Table 2. Name PHONEP PHONEN MIC1P MIC1N MIC2P MIC2N LINE_IN_L Type I I I I I I I Pin 19 20 21 22 29 30 23 Analog I/O Pins Description Phone Positive Input Phone Negative Input First Mic Positive Input First Mic Negative Input Second Mic Positive Input Second Mic Negative Input Line Input Left Channel I2C + I2S Audio Codec + Voice PCM Interface Characteristic Definition Analog Input (1Vrms) Analog Input (1Vrms) Analog Input (1Vrms) Analog Input (1Vrms) Analog Input (1Vrms) Analog Input (1Vrms) Analog Input (1Vrms) 6 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet Name LINE_IN_R MONO_OUT MONO_OUTN HP_OUT_L HP_OUT_R SPK_OUT_L SPK_OUT_LN SPK_OUT_R SPK_OUT_RN 6.3. Pin 24 31 32 39 41 35 33 36 37 Description Line Input Right Channel Positive MONO Output Negative MONO Output Headphone Output Left Channel Headphone Output Right Channel Speaker Output Left Channel Negative Speaker Output Left Channel Speaker Output Right Channel Negative Speaker Output Right Channel Characteristic Definition Analog Input (1Vrms) Analog Output (1Vrms) Analog Output (1Vrms) Analog Output (1Vrms) Analog Output (1Vrms) Analog Output (1.3Vrms, SPKVDD = 4.2V) Analog Output (1.3Vrms, SPKVDD = 4.2V) Analog Output (1.3Vrms, SPKVDD = 4.2V) Analog Output (1.3Vrms, SPKVDD = 4.2V) Total: 16 Pins Filter/Reference Name MICBIAS2 MICBIAS VREF 6.4. Type I O O O O O O O O Type O O O Pin 16 28 27 Table 3. Filter/Reference Description Characteristic Definition MIC BIAS Voltage Output 2 Programmable Analog DC Output with 3mA drive MIC BIAS Voltage Output Programmable Analog DC Output with 3mA drive Internal Reference Voltage 1µf capacitor to analog ground Total: 2 Pins Power/Ground Table 4. Power/Ground Type Pin Description Characteristic Definition P 1 Digital VDD 1.8V~3.6V (IO) P 4 Digital GND P 7 Digital GND P 9 Digital VDD 1.8V~3.6V (Core) P 17 Analog VDD 2.3V~3.6V P 18 Analog GND P 25 Analog VDD 2.3V~3.6V P 26 Analog GND P 34 Analog GND for Speaker Amps P 38 Analog VDD for Speaker Amps 3.0V~5V (For Ohm loading) 2.3V~5V (For kOhm loading) HPGND P 40 Analog GND for Headphone Amps AGND2 P 42 Analog GND HPVDD P 43 Analog VDD for Headphone Amps 2.3V~3.6V LFGND P 49 Thermal Pad, Connect to SPKGND Total: 14 Pins Note: DVDD1 DVDD2, SPKVDD AVDD1, HPVDD AVDD1 = AVDD2 DVDD2 Name DVDD1 DGND1 DGND2 DVDD2 AVDD2 AGND3 AVDD1 AGND1 SPKGND SPKVDD I2C + I2S Audio Codec + Voice PCM Interface 7 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7. Functional Description 7.1. Power The ALC5620 ALC5620 has many power blocks. SPKVDD operates between 2.3V and 5V. HPVDD, AVDD2, and AVDD1 operate between 2.3V and 3.6V. DVDD1 and DVDD2 operate between 1.8V and 3.6V. The power supply limit condition are DVDD1DVDD2, SPKVDDAVDD1=AVDD2, HPVDD AVDD1= AVDD2DVDD2. Power Setting 7.2. DVDD1 3.3V Table 5. Power Setting for Best Performance DVDD2 HPVDD AVDD2 1.8V 3.3V 3.3V AVDD1 3.3V SPKVDD 4.2V Reset There are 3 types of reset operation: Power-On Reset (POR), Cold, and Register reset. Reset Type POR Cold Reset Register Reset 7.2.1. Table 6. Reset Operation Trigger Condition CODEC Response Monitor digital power supply voltage reach Reset all hardware logic and all registers to default VPOR values. Assert RESET# for a specified period Reset all hardware logic and all registers to default values except some specify control registers and logic. Write Reg-00h Reset all registers to default values except some specify control registers and logic. Power-On Reset (POR) When powered on, DVDD2 passes through the VPOR band of the ALC5620 ALC5620 (VPOR_ON ~VPOR_OFF). A Power-On Reset (POR) will generate an internal reset signal (POR reset `LOW') to reset the whole chip. Table 7. Symbol Min VPOR_ON 1.0 VPOR_OFF Note: VPOR_OFF must be below VPOR_ON. I2C + I2S Audio Codec + Voice PCM Interface Power-On Reset Voltage Typical Max 1.6 1.3 - 8 Unit V V Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.3. Clocking The Stereo_SYSCLK can be selected from MCLK or PLL. This means MCLK is always provided externally, and the driver should arrange the clock of each block and setup each divider. The voice codec clock can be selected from MCLK (Master mode), PLL (Master mode), EXTCLK (Slave mode) or VBCLK (Slave mode). The driver should arrange the clock of each block and setup each divider. In master mode of voice I2S/PCM, EXTCLK can be output by setting Extclk_dir=1. The output frequency will be determined by MCLK and the setting of Extclk_out_sel. 7.3.1. Phase-Locked Loop A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. The source of the PLL can be set to MCLK or BLCK by setting pll_sour_sel. The driver can set up the PLL to output a frequency close to the SYSCLK. The PLL transmit formula is: FOUT = (MCLK * (N+2) / (M+2) * (K+2) {Typical K=2} Table 8. MCLK 13 3.6864 2.048 4.096 12 15.36 16 19.2 19.68 N 66 78 94 70 80 81 78 80 78 Clock Setting Table for 48K (Unit: MHz) M FVCO K 7 98.222 2 1 98.304 2 0 98.304 2 1 98.304 2 8 98.4 2 11 98.068 2 11 98.462 2 14 98.4 2 14 98.4 2 I2C + I2S Audio Codec + Voice PCM Interface 9 FOUT 24.555 24.576 24.576 24.576 24.6 24.517 24.615 24.6 24.6 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet MCLK 13 3.6864 2.048 4.096 12 15.36 16 19.2 19.68 Table 9. N 68 72 86 64 66 63 66 64 67 Clock Setting Table for 44.1K (Unit: MHz) M FVCO K 8 91 2 1 90.931 2 0 90.112 2 1 90.112 2 7 90.667 2 9 90.764 2 10 90.667 2 12 90.514 2 13 90.528 2 FOUT 22.75 22.733 22.528 22.528 22.667 22.691 22.667 22.629 22.632 After a Cold Reset, PLL related Registers are reset to default values, however, they are not reset to default values after a soft-reset (write Reg00). Firmware should not power down the PLL when the PLL output is used as Stereo_SYSCLK. 7.3.2. I2C and Stereo I2S The ALC5620 ALC5620 supports I2C for the digital control interface, and I2S/PCM for the digital data interface. The I2S/PCM audio digital interface is used to input data to a stereo DAC or output data from a stereo ADC. The I2S/PCM Audio Digital Interface can be configured to Master mode or Slave mode. For the Stereo I2S Interface, the source clock is always input from MCLK. Master Mode In master mode BCLK/SDALRCK/SADLRCK are configured as output. When PLL is disabled and sel_sysclk=0, MCLK is used as Stereo SYSCLK. When PLL is enabled, MCLK is suggested to provide 13MHz, and PLL should be configured to support 44.1K and 48K base sampling rates. The driver should set each divider (Reg60 & Reg62) to arrange the clock distribution. Refer to section 12 Appendix A: Stereo I2S Clock Table, page 73, for details. Note: The ALC5620 ALC5620 supports different sample rates between SDALRCK and SADLRCK in Master mode. Slave Mode In slave mode BCLK/SDALRCK are configured as input. MCLK should provide the BCLK synchronized clock externally. Stereo_SYSCLK and the driver should set each divider to arrange the clock distribution. Refer to section 12 Appendix A: Stereo I2S Clock Table, page 73, for details. Note: In Slave mode, the ALC5620 ALC5620 does NOT support different sample rates between SDALRCK and SADLRCK. Only SDALRCK is used in slave mode. I2C + I2S Audio Codec + Voice PCM Interface 10 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.3.3. Voice_I2S/PCM Interface The ALC5620 ALC5620 supports an independent digital interface for Voice Audio. The voice audio digital interface is used to input digital data to the voice DAC, or output digital data from the voice ADC. The Voice Audio Digital Interface can be configured to Master mode or Slave mode. Whether in Master mode or Slave mode, the sample rate of the Voice ADC and Voice DAC is set via Reg64 and Reg66. Master Mode In Master mode the main clock of the Voice_I2S/PCM interface can be input selected from MCLK (with or without a PLL) or EXTCLK. VBCLK and VSLRCK will be configured as output. The driver should set each divider (Reg64 & Reg66) to arrange the clock distribution. See section 13 Appendix B: Voice PCM Interface, page 74 for details. Slave Mode In Slave mode the main clock of the Voice_I2S/PCM can be input from MCLK or EXTCLK. VBCLK is synchronized externally. VBCLK and VSLRCK should be configured as input. The driver should set each divider (Reg64 and Reg66) to arrange the clock distribution (see section 13.2 Slave Mode: (voice_port_sel=1), page 75 for more information. If VBCLK provides 64Fs, 128Fs, or 256Fs externally, the ALC5620 ALC5620 can use VBCLK input as the main clock of the Voice_I2S/PCM. See section 12 Appendix A: Stereo I2S Clock Table, page 73. 7.3.4. Voice ADC The ALC5620 ALC5620 supports Voice ADC for transmitting voice data to a Bluetooth device. The Voice ADC is implemented by sharing from the Right Channel of the Stereo ADC (by setting voice_adc_enable). When voice_adc_enable=0'b, the L/R channel stereo ADC sample rate is set according to the stereo sample rate, and is output to the Stereo I2S/PCM interface. When voice_adc_enable=1, the sample rate of the Left channel is set by the stereo sample rate (Reg60 & Reg62). The sample rate of the Right channel is set by the voice sample rate (Reg64 & Reg66). The Left channel ADC data is output to the Left frame and duplicated to the Right frame of the I2S/PCM interface. The Right channel of the Stereo ADC data is then used as a Voice ADC and is output to voice_I2S/PCM. I2C + I2S Audio Codec + Voice PCM Interface 11 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.4. Digital Data Interface 7.4.1. Stereo and Voice I2S/PCM Interface The stereo and voice I2S/PCM interface can be configured as Master mode or Slave mode. Four audio data formats are supported: · PCM mode · Left justified mode · Right justified mode · I2S mode Figure 4. PCM MONO Data Mode A Format (bclk_polarity=0) Figure 5. PCM MONO Data Mode A Format (bclk_polarity=1) I2C + I2S Audio Codec + Voice PCM Interface 12 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet Figure 6. PCM MONO Data Mode B Format (bclk_polarity=0) Figure 7. PCM Stereo Data Mode A Format (bclk_polarity=0) Figure 8. PCM Stereo Data Mode B Format (bclk_polarity=0) I2C + I2S Audio Codec + Voice PCM Interface 13 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet Figure 9. I2S Data Format (bclk_polarity=0) Figure 10. Left-Justified Data Format (bclk_polarity=0) Figure 11. Right-Justified Data Format (bclk_polarity=0) I2C + I2S Audio Codec + Voice PCM Interface 14 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.5. 7.5.1. Audio Data Path Stereo ADC and Voice ADC The Stereo ADC is used for recording stereo sound or, by setting voice_adc_enable, can be configured to MONO PCM ADC (Left channel of Stereo ADC) + voice ADC (Right channel of Stereo ADC) when using bluetooth and recording at the same time. · When voice_adc_enabl=0, the sample rate of the Stereo ADC can be configured via setting Reg60 & Reg62. · When voice_adc_enabl=1, the sample rate of the voice ADC is set by Reg64 & Reg66, and the sample rate of the MONO PCM ADC is set by Reg60 & Reg62. The sample rate of the stereo ADC is independent of the Stereo DAC sample rate. In order to save power, the left and right ADC can be powered down separately by setting Reg3C [6], [7]). The volume control of the stereo ADC is set via Reg12[11:7][4:0]. 7.5.2. Stereo DAC Stereo DAC can be configured to different sample rate by setting the stereo I2S clock divider (Reg60). Reg0C[12:8][4:0] can be used to control the volume of DAC output 7.5.3. Voice to Stereo Digital Path The ALC5620 ALC5620 supports a voice to digital stereo path for voice command through Bluetooth by setting Reg42[15]=1. The Voice data will be transferred from the voice I2S/PCM to the Main I2S/PCM directly. This function is only supported when the Voice and Stereo I2S/PCM are in Master Mode. The driver should set the same sample rate between the Voice DAC and the stereo ADC. When a voice to stereo digital path is enabled, the signal from Voice_I2S/PCM is direct output to Left frame and is duplicated to Right frame of the Voice I2S/PCM interface. The Voice to Stereo Digital Path and Voice ADC functions can exist at the same time. 7.5.4. Voice DAC The Voice DAC is dedicated to playback of received voice signals from the voice_I2S/PCM interface. Typically, it is used at an 8kHz sample rate. In Voice I2S/PCM Master mode, the sample rate is set by the VoDAC clock Divider (Reg64). In addition, Reg66[7:4][2:0] is used to set the over-sample rate clock divider of the Voice ADC/DAC filter to 128Fs. Reg66[13] must be set according to the over-sample rate clock. Performance at 128Fs is better than 64Fs, but with higher power consumption. The higher frequency will cause better performance. For best performance, the frequency of the Voice DAC Sigma Delta clock must be equal to, or higher than, the Voice DA filter over-sampling rate. The volume control of the Voice DAC is set via Reg18[12:8]. I2C + I2S Audio Codec + Voice PCM Interface 15 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.6. Mixers The ALC5620 ALC5620 supports four mixers for all audio function requirements: · Headphone mixer for 2 channels · MONO mixer · Speaker mixer · ADC record mixer 7.6.1. Headphone Mixer The headphone mixer is used to drive stereo output, including HP_OUT_L/R, SPK_OUT_L/R (SPK_OUT_LN/RN) and MONO_OUT (MONO_OUTN). The output of the Headphone mixer can be input to the ADC record mixer. The following signals can be mixed into the headphone mixer: · LINE-IN_L/R (Controlled by Reg0A) · PHONEP/N (Controlled by Reg08) · MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10) · Stereo DAC output (Controlled by Reg0C) · Voice DAC output (Controlled by Reg18) · ADC record mixer output (Controlled by Reg12 & Reg14). Note: The headphone mixer can be powered down by setting Reg3C[5][4]. 7.6.2. MONO Mixer The MONO mixer is used to drive MONO_OUT (MONO_OUTN) and SPK_OUT_L/R (SPK_OUT_LN/RN). The output of the MONO mixer can be input to the ADC record mixer. The output of the MONO mixer is two channels with the same signal. The following signals can be mixed into the MONO mixer: · LINE-IN_L/R (Controlled by Reg0A) · MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10) · Stereo DAC output (Controlled by Reg0C) · Voice DAC output (Controlled by Reg18) · ADC record mixer output (Controlled by Reg12 & Reg14). Note: The MONO mixer can be powered down by setting Reg3C[2]. I2C + I2S Audio Codec + Voice PCM Interface 16 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.6.3. Speaker Mixer The speaker mixer is the same as the MONO mixer and is used to drive MONO_OUT (MONO_OUTN) and SPK_OUT_L/R (SPK_OUT_LN/RN). The output of the speaker mixer can be input to the ADC record mixer. The output of the speaker mixer is two channels with the same signal. The following signals can be mixed into the speaker mixer: · LINE-IN_L/R (Controlled by Reg0A) · PHONEP/N (Controlled by Reg08) · MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10) · Stereo DAC output (Controlled by Reg0C) · Voice DAC output (Controlled by Reg18) Note: The speaker mixer can be powered down by setting Reg3C[3]. 7.6.4. ADC Record Mixer The ADC record mixer is used to mix analog signals as input to the Stereo ADC for recording. Output of the ADC record mixer can be input to the headphone mixer, MONO mixer, and speaker mixer. The following signals can be mixed into the ADC record mixer: · LINE-IN_L/R (Controlled by Reg0A) · PHONEP/N (Controlled by Reg08) · MIC1P/N and MIC2P/N (Controlled by Reg22 & Reg10) · Headphone mixer output · MONO mixer output · Speaker mixer output Note: The ADC record mixer can be powered down by setting Reg3C[1][0]. I2C + I2S Audio Codec + Voice PCM Interface 17 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.7. Analog Audio Input Path The ALC5620 ALC5620 supports four Analog Audio Input paths: · Line_IN_L/R · PHONEP/N · MIC1 · MIC2 7.7.1. Line Input Line_In_L and Line_In_R provide 2-channel stereo single-ended input that can be mixed into the MONO mixer, Headphone mixer, Speaker mixer, or the ADC record mixer. The Line_In_L/R volume and mute are controlled by Reg0A. Reg3E[7:6] can be used to power down the Line_In volume control. 7.7.2. Phone Input PHONEP/N provides one-channel MONO differential or single-ended input configured by Reg08[13] that can be mixed into the ADC record mixer, or any analog output mixer except for the MONO mixer. PHONEP is main input when differential mode is disabled. The PHONEP/N volume and mute are controlled by Reg08. Reg3E[5:4] can be used to power down PHONEP/N volume control and mixer. 7.7.3. Microphone Input MIC1P/N and MIC2P/N provide two-channel stereo differential or single-ended input via Reg10[12], [4], that can be mixed into the ADC record mixer, or any analog output mixer. MIC1P and MIC2P are main inputs when differential mode is disabled. The ALC5620 ALC5620 Microphone input boost provides 20/30/40dB boost, set by Reg22[11:10] (for MIC1), and by Reg22[9:8] (for MIC2). The MIC1/2 volume and mute are controlled by Reg0E. For detailed power management of MIC1/2, Reg3E[3][2] can be used to power down the MIC1/2 volume control. Reg3E[1][0] can be used to power down MIC1/2 and mixer. I2C + I2S Audio Codec + Voice PCM Interface 18 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.8. Analog Audio Output Data Path The ALC5620 ALC5620 supports three Analog Audio output paths: · SPK_OUT_L/R · HP_OUT_L/R · MONO_OUT 7.8.1. Speaker Output SPK_OUT_L/R provides two-channel differential output. The SPK_OUT_L source is set in Reg1C[15:14]. Sources are shown below: · Vmid · Headphone left mixer · Speaker mixer · MONO mixer The SPK_OUT_R source is set in Reg1C[12:11]. Sources are shown below: · Vmid · Headphone right mixer · Speaker mixer · MONO mixer The ALC5620 ALC5620 speaker supports Class AB and Class D type amplifiers (set in Reg1C[13]:spk_out_sel). As the voltage of SPKVDD is usually higher than AVDD, the driver should set the Class AB Vmid ratio in Reg40[5:3], and the Class D Vmid ratio in Reg40[7:6] in order to extend the output level. In class AB mode, for L+R MONO speaker solutions, SPK_OUT_R can select a different signal source (SPKR Volume output or SPKL Volume output by Reg1C[14]) but SPK_OUT_RN only outputs SPKR Volume Negative Output. The SPK_OUT_L/R volume and mute are controlled by Reg02. Reg3E[13]: pow_spk_r and Reg3E[12]:pow_spk_rn can be used to power down SPK output. Reg3C[14]: pow_clsab is used to power down Class AB output, and Index 46[15:12] is used to power down each output channel of Class D. SPK_OUT_L/R supports the zero-cross detect function (enabled at Reg02[6][14]: sp_l_dezero/ sp_r_dezero). I2C + I2S Audio Codec + Voice PCM Interface 19 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.8.2. Headphone Output HP_OUT_L/R provides two-channel single-ended output. The HP_OUT_L/R source is set in Reg1C[9][8]. Sources are shown below: · Vmid · Headphone mixer The HP_OUT_L/R volume and mute are controlled by Reg04. Reg3E[11]: pow_hp_l_vol and Reg3E[10]: pow_hp_r_vol can be used to power down the volume of HP output. HP_OUT supports the zero-cross detect function (enabled at Reg04[14][6]:hp_l_dezero/ hp_r_dezero). 7.8.3. MONO Output MONO_OUT provide one-channel differential or single-ended output configured by Reg08[15]. The MONO_OUT source is set in Reg1C[7:6]. Sources are shown below: · Vmid · Headphone mixer (L+R) · Speaker mixer · MONO mixer The MONO_OUT volume and mute are controlled by Reg08. Reg3E[14]: pow_MONO_out_vol can be used to power down the volume of MONO_OUT. MONO_OUT supports the zero-cross detect function (enabled at Reg08[6]:MONO_dezero). I2C + I2S Audio Codec + Voice PCM Interface 20 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.9. AVC Control The Automatic Volume Control (AVC) function dynamically adjusts the input signal quantized by the ADC to an expected sound level by setting THmax and THmin. When the average level of input signal is higher than THmax, the AVC will decrease the selected analog gain to attenuate the quantized Pulse Code Modulation (PCM) signal to a lower amplitude than THmax. When the average level of input signal is lower than THmin, the AVC will increase the selected analog gain to amplify the input signal. The quantized Pulse Code Modulation (PCM) signal is then set higher than THmin. The quantized PCM has an average level between THmin and THmax. The AVC reference source channel and target channel can be individually set by Index20[0] and Reg5E[13:12]. The AVC architecture is shown in Figure 12 below: Figure 12. Auto Volume Control Block Diagram I2C + I2S Audio Codec + Voice PCM Interface 21 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.10. Hardware Sound Effects The Sound Effect block is composed of Pseudo Stereo, Spatial 3D, and Equalizer blocks. The Pseudo Stereo block is used to convert a MONO source into virtualized stereo output. The Spatial 3D block is a surround sound generator with adjustable amplitude (Gain) and surround depth (Ratio). The Equalizer block can be used to compensate for speaker response, or to make environment sound effects, e.g., `Pub', `Live' , `Rock',. etc. 7.10.1. Equalizer Block The Equalizer block cascades 5 bands of equalizer to compensate for speaker response and to emulate environment sound. One high-pass filter cascaded in the front end is used to drop low frequency tone, which has a larger amplitude and may damage a mini speaker. The high-pass filter can also be used to adjust Treble strength with gain control. A low-pass filter with gain control can adjust the Bass strength. Three bands of bi-quad bandpass filters are used to emulate environment sounds. To avoid PCM sample saturation, the digital volume control has up to 18dB of attenuation before the equalizer. A 0~+18dB digital gain after the equalizer is used to correct PCM output to a suitable level. 7.10.2. Pseudo Stereo and Spatial 3D Sound There are two spatial effects in post-processing; the Pseudo-Stereo Effect + Spatial Effect, and the Stereo Expansion Effect. The Pseudo-Stereo Effect + Spatial Effect converts a MONO signal to a stereo signal by changing the phase and amplitude of the original signal followed by enhancing the spatial effect. The Stereo Expansion Effect enhances the spatial effect when the input signal is Stereo. I2C + I2S Audio Codec + Voice PCM Interface 22 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.11. I2C Control Interface I2C is a 2-wires half-duplex serial communication interface, supporting only slave mode. The host must support MCLK during register access. 7.11.1. Addressing Setting Table 10. Addressing Setting (MSB) BIT 0 0 1 1 0 Note: For A1: determined by external connect to VCC or GND 7.11.2. 0 A1 (LSB) R/W Complete Data Transfer Data Transfer over I2C Control Interface Figure 13. Data Transfer Over I2C Control Interface I2C + I2S Audio Codec + Voice PCM Interface 23 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet Write WORD Protocol Table 11. Write WORD Protocol Read WORD Protocol Table 12. Read WORD Protocol 1 7 S Device Address 1 1 Wr A 8 1 Register Address A 7 S 1 Device Address Rd A S: Start Condition 8 1 8 Data Byte High A Data Byte Low 1 1 NA P A: 0 for ACK, 1 for NACK Slave Address: 7-bit Device Address Data Byte: 16-bit Mixer data Wr: 0 for Write Command : Master-to-Slave Rd: 1 for Read Command : Slave-to-Master Command Code: 8-bit Register Address 7.12. Odd-Addressed Register Access The ALC5620 ALC5620 will return `0000h' when odd-addressed and unimplemented registers are read. 7.13. Power Management The ALC5620 ALC5620 supports a grouped power down control register (Reg26). More detailed Power Management control is supported in Reg 3A, 3C, and 3E. Each particular block will only be active when both Reg26 and Reg3A/3C/3E are set to `Enable'. I2C + I2S Audio Codec + Voice PCM Interface 24 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 7.14. GPIO and Interrupt The ALC5620 ALC5620 supports up to five GPIOs. Each GPIO can be configured as Input/Output by Reg4C. When GPIOs are configured as Input, the status will be indicated in Reg54. When GPIOs are configured as Output, Reg5C is used to drive GPIOs to High (1b) or Low (0b). The status can be read in Reg54. Interrupt request (IRQ) can be configured as: · Sticky by setting Reg50 · Changed polarity by setting Reg4E · Wake-up by setting Reg52 The driver can write each bit of Reg54=1 to clear each IRQ status flag. When VoPCM_En (Reg36[15])=1, GPIOs 1, 3, 4, and 5 will be dedicated as VoDAC_I2S/PCM interface, regardless of GPIO Pin Configuration (Reg4C[5:3,1]). These pins cannot be used as GPIOs in this case. GPIO pin2 can be configured and pin-shared with IRQ_Output by setting Reg56. Figure 14. GPIO Implementation There are some internal events (over-temperature, MICBIAS short detect) where GPIOs can be an interrupt source. GPIO Internal event application is located in Reg4C, Reg4E, Reg50, Reg52, and Reg54. I2C + I2S Audio Codec + Voice PCM Interface 25 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8. Mixer Registers List Accessing odd numbered registers, or reading unimplemented registers, will return a 0. 8.1. Reg-00h: Reset Default: 59B4h Table 13. Reg-00h: Reset Name Bits Read/Write Reset State Description Reserved 15 R 0'h Reserved. Read as 0 REG-00 REG-00_b14_b10 14:10 R 16'h SE[4:0]=10110b REG-00 REG-00_b9 9 R 0'h No support for 20-bit ADC REG-00 REG-00_b8 8 R 1'h Supports 16-bit ADC REG-00 REG-00_b7 7 R 1'h Supports 16-bit DAC REG-00 REG-00_b6 6 R 0'h No support for 18-bit DAC REG-00 REG-00_b5 5 R 1'h Support for Loudness REG-00 REG-00_b4 4 R 1'h Headphone output support Reserved 3 R 0'h Reserved REG-00 REG-00_b2 2 R 1'h Supports EQ Control Reserved 1 R 0'h Reserved. Read as 0 REG-00 REG-00_b0 0 R 0'h Dedicated MIC PCM input is not supported. Note: Writes to this register will reset all registers to their default values except PLL related Register. The written data will be ignored 8.2. Reg-02h: Speaker Output Volume Default: 8080h Table 14. Reg-02h: Speaker Output Volume Name Bits Read/Write Reset State Description sp_l_mute 15 R/W 1'h Mute Left Control 0: On 1: Mute Left Channel (-dB) sp_l_dezero 14 R/W 0'h Left Zero-Cross Detector Control 0: Disable 1: Enable Reserved 13 R 0'h Reserved. Read as 0 sp_l_vol 12:8 R/W 0'h Speaker Output Left Volume (SPKL[4.0]) in 1.5dB Steps sp_r_mute 7 R/W 1'h Mute Right Control 0: On 1: Mute Right Channel (-dB) sp_r_dezero 6 R/W 0'h Right Zero-Cross Detector Control 0: Disable 1: Enable Reserved 5 R 0'h Reserved. Read as 0 sp_r_vol 4:0 R/W 0'h Speaker Output Right Volume (SPKR[4.0]) in 1.5dB Steps Note: For SPKR/SPKL, 00h: 0dB attenuation 1Fh: 46.5dB attenuation I2C + I2S Audio Codec + Voice PCM Interface 26 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.3. Reg-04h: Headphone Output Volume Default: 8080h Table 15. Reg-04h: Headphone Output Volume Name Bits Read/Write Reset State Description hp_l_mute 15 R/W 1'h Mute Left Control 0: On 1: Mute Left Channel (-dB) hp_l_dezero 14 R/W 0'h Left Zero-Cross Detector Control 0: Disable 1: Enable Reserved 13 R 0'h Reserved. Read as 0 hp_l_vol 12:8 R/W 0'h Headphone Output Left Volume (HPL[4.0]) in 1.5dB Steps hp_r_mute 7 R/W 1'h Mute Right Control 0: On 1: Mute Right Channel (-dB) hp_r_dezero 6 R/W 0'h Right Zero-Cross Detector Control 0: Disable 1: Enable Reserved 5 R 0'h Reserved. Read as 0 hp_r_vol 4:0 R/W 0'h Headphone Output Right Volume (HPR[4.0]) in 1.5dB Steps Note: For HPR/HPL, 00h: 0dB attenuation 1Fh: 46.5dB attenuation 8.4. Reg-08h: Phone Input/MONO Output Volume Default: C880h Table 16. Reg-08h: Phone Input / MONO Output Volume Read/Write Reset State Description R/W 1'h Mute Phone Input to Headphone Mixer Control 0: On 1: Mute (-dB) phone2spk_mute 14 R/W 1'h Mute Phone Input to Speaker Mixer Control 0: On 1: Mute (-dB) phone_diff_ctrl 13 R/W 0'h Phone Differential Input Control 0: Disable 1: Enable phone_vol 12:8 R/W 8'h Phone Input Volume (PV[4:0]) in 1.5dB Steps (not to ADC) MONO_mute 7 R/W 1'h Mute MONO Output Control 0: On 1: Mute (-dB) MONO_dezero 6 R/W 0'h Zero-Cross Detector Control 0: Disable 1: Enable MONO_diff_ctrl 5 R/W 0'h MONO Output Differential Control 0: Disable (SE) 1: Enable (BTL) MONO_vol 4:0 R/W 0'h MONO Output Master Volume (MOV[4.0]) in 1.5dB Steps Note: For MOV, 00h: 0dB attenuation 1Fh: 46.5dB attenuation For PV, 00h: +12dB gain 08h: 0dB attenuation 1Fh: 34.5dB attenuation Name phone2hp_mute Bits 15 I2C + I2S Audio Codec + Voice PCM Interface 27 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.5. Reg-0Ah: LINE_IN Volume Default: E808h Table 17. Reg-0Ah: LINE_IN Volume Name Bits Read/Write Reset State Description li2hp_mute 15 R/W 1'h Mute Volume Output to Headphone Mixer Control 0: On 1: Mute li2spk_mute 14 R/W 1'h Mute Volume Output to Speaker Mixer Control 0: On 1: Mute li2MONO_mute 13 R/W 1'h Mute Volume Output to MONO Mixer Control 0: On 1: Mute li_l_vol 12:8 R/W 08'h LINE_IN Left Volume (NLV[4.0]) in 1.5dB Steps Reserved 7:5 R 0'h Reserved li_r_vol 4:0 R/W 8'h LINE_IN Right Volume (NRV[4.0]) in 1.5dB Steps Note: For NRV/NLV, 00h: +12dB gain 08h: 0dB attenuation 1Fh: 34.5dB attenuation 8.6. Reg-0Ch: STEREO DAC Volume Default: E808h Table 18. Reg-0Ch: STEREO DAC Volume Read/Write Reset State Description R/W 1'h Mute Volume Output to Headphone Mixer Control 0: On 1: Mute (-dB) dac2spk_mute 14 R/W 1'h Mute Volume Output to Speaker Mixer Control 0: On 1: Mute (-dB) dac2MONO_mute 13 R/W 1'h Mute Volume Output to MONO Mixer Control 0: On 1: Mute (-dB) dac_l_vol 12:8 R/W 08'h PCM Left DAC Volume (PLV[4.0]) in 1.5dB Steps Reserved 7:5 R 0'h Reserved dac_r_vol 4:0 R/W 8'h PCM Right DAC Volume (PRV[4.0]) in 1.5dB Steps Note: For PRV/PLV,: 00h: +12dB gain 08h: 0dB attenuation 1Fh: 34.5dB attenuation Name dac2hp_mute Bits 15 I2C + I2S Audio Codec + Voice PCM Interface 28 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.7. Reg-0Eh: MIC Volume Default: 0808h Table 19. Reg-0Eh: MIC Volume Name Bits Read/Write Reset State Description Reserved 15:13 R 0'h Reserved mic1_vol 12:8 R/W 08'h MIC1 Volume (M1V[4.0]) in 1.5dB Steps Reserved 7:5 R 0'h Reserved mic2_vol 4:0 R/W 8'h MIC2 Volume (M2V[4.0]) in 1.5dB Steps For M2V/M1V, 00h: +12dB gain 08h: 0dB attenuation 1Fh: 34.5dB attenuation 8.8. Reg-10h: MIC Routing Control Default: E0E0h Name mic12hp_mute Bits 15 mic12spk_mute 14 mic12MONO_mute 13 mic1_diff_ctrl 12 Reserved mic22hp_mute 11:8 7 mic22spk_mute 6 mic22MONO_mute 5 mic2_diff_ctrl 4 Reserved 3:0 Table 20. Reg-10h: MIC Routing Control Read/Write Reset State Description R/W 1'h Mute MIC1 Volume Output to Headphone Mixer 0: On 1: Mute R/W 1'h Mute MIC1 Volume Output to Speaker Mixer 0: On 1: Mute R/W 1'h Mute MIC1 Volume Output to MONO Mixer 0: On 1: Mute R/W 0'h MIC1 Differential Input Control 0: Disable 1: Enable R 0'h Reserved R/W 1'h Mute MIC2 Volume Output to Headphone Mixer 0: On 1: Mute R/W 1'h Mute MIC2 Volume Output to Speaker Mixer 0: On 1: Mute R/W 1'h Mute MIC2 Volume Output to MONO Mixer 0: On 1: Mute R/W 0'h MIC2 Differential Input Control 0: Disable 1: Enable R 0'h Reserved I2C + I2S Audio Codec + Voice PCM Interface 29 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.9. Reg-12h: ADC Record Gain Default: F58Bh Name adc2hp_l_mute Bits 15 adc2hp_r_mute 14 adc2MONO_l_ mute 13 adc2MONO_r_ mute 12 adc_l_vol 11:7 adc_l_dezero 6 adc_r_dezero 5 adc_r_vol 4:0 Table 21. Reg-12h: ADC Record Gain Read/Write Reset State Description R/W 1'h Mute Left Gain Output to Headphone Mixer Control 0: On 1: Mute (-dB) R/W 1'h Mute Right Gain Output to Headphone Mixer Control 0: On 1: Mute (-dB) R/W 1'h Mute Left Gain Output to MONO Mixer Control 0: On 1: Mute (-dB) R/W 1'h Mute Right Gain Output to MONO Mixer Control 0: On 1: Mute (-dB) R/W 0B'h ADC Record Gain Left Channel (LRG[4.0]) in 1.5dB Steps 00h: -16.5dB attenuation 0Bh: 0dB gain 1Fh: 30dB gain R/W 0'h ADC_L Zero-Cross Detector Control 0: Disable 1: Enable R/W 0'h ADC_R Zero-Cross Detector Control 0: Disable 1: Enable R/W 0B'h ADC Record Gain Right Channel (RRG[4.0]) in 1.5dB Steps 00h: -16.5dB attenuation 0Bh: 0dB gain 1Fh: 30dB gain I2C + I2S Audio Codec + Voice PCM Interface 30 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.10. Reg-14h: ADC Record Mixer Control Default: 7F7Fh Name Reserved adcrec_l_mute Bits 15 14:8 Reserved adcrec_r_mute 7 6:0 Table 22. Reg-14h: ADC Record Mixer Control Read/Write Reset State Description R 0'h Reserved R/W 7F'h Left Mixer Mute Control 0: On 1: Mute (-dB) Bit 14: MIC1 Bit 13: MIC2 Bit 12: LINE_IN_L Bit 11: PHONE Bit 10: Headphone Mixer Left Channel Bit 9: Speaker Mixer Bit 8: MONO Mixer R 0'h Reserved R/W 7F'h Right Mixer Mute Control 0: On 1: Mute (-dB) Bit 6: MIC1 Bit 5: MIC2 Bit 4: LINE_IN_R Bit 3: PHONE Bit 2: Headphone Mixer Right Channel Bit 1: Speaker Mixer Bit 0: MONO Mixer 8.11. Reg-18h: Voice DAC Output Volume Default: E800h Table 23. Reg-18h: Voice DAC Output Volume Name Bits Read/Write Reset State Description voice2hp_mute 15 R/W 1'h Mute DAC Output to Headphone Mixer Control 0: On 1: Mute (-dB) voice2spk_mute 14 R/W 1'h Mute DAC Output to Speaker Mixer Control 0: On 1: Mute (-dB) voice2MONO_mute 13 R/W 1'h Mute DAC Output to MONO Mixer Control 0: On 1: Mute (-dB) voice_vol 12:8 R/W 8'h Voice Output Volume (VV[4.0]) in 1.5dB Steps Reserved 7:0 R 0'h Reserved Note: For NRV, 00h: +12dB gain 08h: 0dB attenuation 1Fh: 34.5dB attenuation I2C + I2S Audio Codec + Voice PCM Interface 31 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.12. Reg-1Ch: Output Mixer Control Default: 0000h Name spk_l_vol_in_sel spk_l_out_sel spk_r_vol_in_sel Bits 15:14 13 12:11 Reserved hp_l_in_sel 10 9 hp_r_in_sel 8 MONO_in_sel Reserved clab_amp_source_sel Reserved 7:6 5 4 3:0 Table 24. Reg-1Ch: Output Mixer Control Read/Write Reset State Description R/W 0'h SPKL Volume Input Select 00: VMID (No input) 01: HP Left Mixer 10: Speaker Mixer 11: MONO R/W 0'h SPKL and SPKR Output Select 0: Class AB 1: Class D R/W 0'h SPKR Volume Input Select 00: VMID (No input) 01: HP Right Mixer 10: Speaker Mixer 11: MONO R 0'h Reserved R/W 0'h HPL Volume Input Select 0: VMID (No input) 1: HP Left Mixer R/W 0'h HPR Volume Input Select 0: VMID (No input) 1: HP Right Mixer R/W 0'h MONO Volume Input Select 00: VMID (No input) 01: HP Left + Right Mixer 10: Speaker Mixer 11: MONO Mixer R 0'h Reserved R/W 0'h In Class AB Mode SPK_OUT_R Output Amplifier Source Select 0: SPKR Volume Output 1: SPKL Volume Output Note: SPK_OUT_RN: SPKR Volume Negative Output R 0'h Reserved I2C + I2S Audio Codec + Voice PCM Interface 32 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.13. Reg-22h: Microphone Control Default: 0000h Name Reserved mic1_boost_ctrl Bits 15:12 11:10 mic2_boost_ctrl 9:8 Reserved mic1_bias_voltage_ctrl 7:6 5 mic2_bias_voltage_ctrl 4 Reserved mic_bias_threshold 2:3 1:0 Table 25. Reg-22h: Microphone Control Read/Write Reset State Description R 0'h Reserved R/W 0'h MIC1 Boost Control 00: Bypass 01: +20dB 10: +30dB 11: +40dB R/W 0'h MIC2 Boost Control 00: Bypass 01: +20dB 10: +30dB 11: +40dB R 0'h Reserved. Read as 0 R/W 0'h MICBIAS1 Output Voltage Control 0: 0.9 * AVDD 1: 0.75 * AVDD R/W 0'h MICBIAS2 Output Voltage Control 0: 0.9 * AVDD 1: 0.75 * AVDD R 0'h Reserved. Read as 0 R/W 0'h MICBIAS1/2 Short Current Detector Threshold 00: 600µA 01: 1200µA 1x: 1800µA 8.14. Reg-26h: Power Down Control/Status Default: EF00h Name ac_pr7 Bits 15 ac_pr6 14 ac_pr5 13 Table 26. Reg-26h: Power Down Control/Status Read/Write Reset State Description R/W 1'h PR7 0: Normal 1: Power down Speaker Amplifier R/W 1'h PR6 0: Normal 1: Power down Headphone Out and MONO Out R/W 1'h PR5 0: Normal 1: Disable internal clock I2C + I2S Audio Codec + Voice PCM Interface 33 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet Name Reserved ac_pr3 Bits 12 11 Read/Write R/W R/W ac_pr2 10 R/W ac_pr1 9 R/W ac_pr0 8 R/W 7:4 3 R R analog_mixer_status 2 R dac_status 1 R adc_status 0 R Reserved vref_status PR0=1 PR1=1 PR2=1 PR3=1 PR4=1 PR5=1 PR6=1 PR7=1 ADC PD PD PD PD - Reset State Description 0'h Reserved 1'h PR3 0: Normal 1: Power down Mixer (Vref/Vrefout off) 1'h PR2 0: Normal 1: Power down Mixer (Vref/Vrefout are still on) 1'h PR1 0: Normal 1: Power down STEREO DAC 1'h PR0 0: Normal 1: Power down STEREO ADC, and input MUX 0'h Reserved. Read as 0 0'h Vref Status 1: Vref is up to normal level 0: Not yet up to normal level 0'h Analog Mixer Status 1: Ready 0: Not yet ready 0'h DAC Status 1: Ready 0: Not yet ready 0'h ADC Status 1: Ready 0: Not yet ready Table 27. Truth Table for Power Down Mode: (PD= Power Down) DAC Mixer Vref ACLINK Int CLK HP-OUT MONO-OUT SPK-OUT PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD I2C + I2S Audio Codec + Voice PCM Interface 34 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.15. Reg-34h: Main Serial Data Port Control (Stereo I2S) Default: 0000h Name stereo_i2s_mode_sel stereo_i2s_sadlrck_ ctrl_en Reserved stereo_i2s_bclk_ polarity_ctrl i2s_da_sigma_ delta_clock_sel i2s_da_sigma_ delta_clock_div Reserved stereo_i2s_pcm_ mode_sel Reserved stereo_i2s_data_ len_sel stereo_i2s_data_ format_sel Table 28. Reg-34h: Main Serial Data Port Control (Stereo I2S) Bits Read/Write Reset State Description 15 R/W 0'h Main Serial Data Port Mode Selection 0: Master 1: Slave 14 R/W 0'h SADLRCK Control: Set to "1" when ADC and DAC are different sampling rate 0: Disable, ADC and DAC use the same Fs 1: Enable Note: frame clock have to input from SDALRCK when this bit set to"0" 13 R 0'h Reserved 12 R/W 0'h Stereo I2S BCLK Polarity Control 0: Normal 1: Invert 11 R/W 0'h I2S_DA Sigma Delta Clock Source Select 0b: From DA Filter 1b: From DA Sigma Delta Clock Divider 10:8 R/W 0'h I2S DA Sigma Delta Clock Divider 000b: ÷ 2 001b: ÷ 4 010b: ÷ 8 011b: ÷ 16 100b: ÷ 32 101b: ÷ 64 Others: Reserved 7 R/W 0'h Reserved 6 R/W 0'h PCM Mode Select 0: Mode A 1: Mode B Non PCM Mode Control 0: Normal SADLRCK / SDALRCK 1: Invert SADLRCK / SDALRCK Note: Only support when stereo_i2s_sadlrck_ctrl_en ="0" 5:4 R 0'h Reserved 3:2 R/W 0'h Data Length Selection 00: 16 bits 01: 20 bits 10: 24 bits 11: 32 bits 1:0 R/W 0'h Stereo PCM Data Format Selection 00: I2S format 01: Right justified 10: Left justified 11: PCM format I2C + I2S Audio Codec + Voice PCM Interface 35 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.16. Reg-36h: Extend Serial Data Port Control (VoDAC_I2S/PCM) Default: 0000h Table 29. Reg-36h: Extend Serial Data Port Control (VoDAC_I2S/PCM) Name Bits Read/Write Reset State Description VoPCM_En 15 R/W 0'b Enable PCM Interface on GPIO1, 3, 4, 5 0: GPIO function 1: VoPCM interface voice_port_sel 14 R/W 0'h Extend Serial Data Port Mode Selection 0: Master 1: Slave Reserved 13:9 R 00'h Reserved voice_adc_enable 8 R/W 0'b Voice ADC Enable 0b: Disable (ADC_L=ADC_R=Stereo) 1b: Enable (ADC_L=Stereo, ADC_R=Voice) voice_vbclk_polarity_ctrl 7 R/W 0'h Voice I2S VBCLK Polarity Control 0: Normal 1: Invert voice_pcm_mode_sel 6 R/W 0'h PCM Mode Select 0: Mode A 1: Mode B Non PCM Mode Control 0: Normal VSLRCK 1: Invert VSLRCK Reserved 5:4 R 0'h Reserved voice_data_len_sel 3:2 R/W 0'h Data Length Selection 00: 16 bits 01: 20 bits 10: 24 bits 11: 32 bits voice_data_format_sel 1:0 R/W 0'h Voice Data Format Selection 00: I2S format 01: Right justified 10: Left justified 11: PCM format I2C + I2S Audio Codec + Voice PCM Interface 36 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.17. Reg-3Ah: Power Management Addition 1 Default: 0000h Name depop_MONOoutb depop_hp_outb pow_zcd Reserved main_i2s_en Reserved pow_mic1_bias_det_ctrl pow_mic2_bias_det_ctrl pow_mic1_bias pow_mic2_bias pow_main_bias pow_dac_ref Table 30. Reg-3Ah: Power Management Addition 1 Bits Read/Write Reset State Description 15 R/W 0'h Depop of MONO Out 0: Enable (De-pop Enable) 1: Disable (De-pop Disable) 14 R/W 0'h Depop of HP Out 0: Enable (De-pop Enable) 1: Disable (De-pop Disable) 13 R/W 0'h All Zero-Cross Detect Power Down 0: Disable 1: Enable 12 R/W 0'h Reserved 11 R/W 0'h Main I2S Digital Interface Enable 0: Disable 1: Enable 10:6 R/W 0'h Reserved 5 R/W 0'h MICBIAS1 Short Current Detector Control 0: Disable 1: Enable 4 R/W 0'h MICBIAS2 Short Current Detector Control 0: Disable 1: Enable 3 R/W 0'h 0: Disable 1: Enable microphone1 bias 2 R/W 0'h 0: Disable 1: Enable microphone2 bias 1 R/W 0'h 0: Disable 1: Enable Main bias of the ALC5620 ALC5620 0 R/W 0'h 0: Disable 1: Enable DAC reference of the ALC5620 ALC5620 I2C + I2S Audio Codec + Voice PCM Interface 37 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.18. Reg-3Ch: Power Management Addition 2 Default: 0000h Name pow_thermal Bits 15 pow_clsab 14 pow_vref 13 pow_pll 12 Reserved pow_voice_dac 11 10 pow_dac_l 9 pow_dac_r 8 pow_adc_l 7 pow_adc_r 6 pow_hp_l 5 pow_hp_r 4 pow_spk 3 pow_MONO 2 pow_adc_rec_l 1 pow_adc_rec_r 0 Table 31. Reg-3Ch: Power Management Addition 2 Read/Write Reset State Description R/W 0'h Thermal Detect (Temp Sensor) 0: Disable 1: Enable R/W 0'h Class_AB Power (All) 0: Disable 1: Enable R/W 0'h VREF of All Analog Circuits 0: Disable 1: Enable R/W 0'h PLL 0: Disable 1: Enable PLL R/W 0'h Reserved R/W 0'h VoDAC Clock 0: Disable 1: Enable Note: Disabled includes Voice_I2S interface. R/W 0'h Left Stereo DAC Filter Clock 0: Disable 1: Enable R/W 0'h Right Stereo DAC Filter Clock 0: Disable 1: Enable R/W 0'h Left Stereo ADC Filter Clock and Input Gain 0: Disable 1: Enable R/W 0'h Right Stereo ADC Filter Clock and Input Gain 0: Disable 1: Enable R/W 0'h Left Headphone Mixer 0: Disable 1: Enable R/W 0'h Right Headphone Mixer 0: Disable 1: Enable R/W 0'h Speaker Mixer 0: Disable 1: Enable R/W 0'h MONO Mixer 0: Disable 1: Enable R/W 0'h Left ADC Record Mixer 0: Disable 1: Enable R/W 0'h Right ADC Record Mixer 0: Disable 1: Enable I2C + I2S Audio Codec + Voice PCM Interface 38 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.19. Reg-3Eh: Power Management Addition 3 Default: 0000h Name Reserved pow_MONO_out_vol pow_spk_outln pow_spk_outrn pow_hp_l_vol pow_hp_r_vol pow_spk_l pow_spk_r pow_li_l_vol pow_li_r_vol pow_phone_vol pow_phone_admixer pow_mic1_vol pow_mic2_vol pow_mic1_admixer pow_mic2_admixer Table 32. Reg-3Eh: Power Management Addition 3 Bits Read/Write Reset State Description 15 R 0'h Reserved 14 R/W 0'h MONO_OUT Volume Control (Amp) 0: Disable 1: Enable 13 R/W 0'h SPK_OUTLN Output (Enable Class AB & Class D) 0: Disable 1: Enable 12 R/W 0'h SPK_OUTRN Output (Enable Class AB & Class D) 0: Disable 1: Enable 11 R/W 0'h HP_OUT_L Volume Control (Amp) 0: Disable 1: Enable 10 R/W 0'h HP_OUT_R Volume Control (Amp) 0: Disable 1: Enable 9 R/W 0'h SPK_OUT_L Output (Enable Class AB & Class D) 0: Disable 1: Enable 8 R/W 0'h SPK_OUT_R Output (Enable Class AB & Class D) 0: Disable 1: Enable 7 R/W 0'h LINE_IN Left Volume Control 0: Disable 1: Enable 6 R/W 0'h LINE_IN Right Volume Control 0: Disable 1: Enable 5 R/W 0'h PHONE Volume Control 0: Disable 1: Enable 4 R/W 0'h PHONE AD Mixer 0: Disable 1: Enable 3 R/W 0'h MIC1 Volume Control 0: Disable 1: Enable 2 R/W 0'h MIC2 Volume Control 0: Disable 1: Enable 1 R/W 0'h MIC1 AD Mixer and Boost 0: Disable 1: Enable 0 R/W 0'h MIC2 AD Mixer and Boost 0: Disable 1: Enable I2C + I2S Audio Codec + Voice PCM Interface 39 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet Figure 15. Power Control to MIC Input 8.20. Reg-40h: General Purpose Control Register 1 Default: 0428h Name Bits sel_sysclk 15 extclk_dir 14 Reserved hp_amp_ctrl 13:10 9:8 spk_ampD_ctrl 7:6 spk_ampAB_ctrl 5:3 Reserved a1_status 2 1 Reserved 0 Table 33. Reg-40h: General Purpose Control Register 1 Read/ Reset Description Write State R/W 0'h Stereo SYSCLK Source Select 0: MCLK 1: PLL Output R/W 0'h EXTCLK Direction Control 0: Input 1: Output R/W 1'h Reserved R/W 0'h Headphone Amplifier VMID Ratio Control (Output Gain Control) 00: 1 01: 1.25 1x: 1.5 R/W 0'h Speaker Class D Amplifier VMID Ratio Control (Output Gain Control) 00: 1.75 Vdd 01: 1.5 Vdd 10: 1.25 Vdd 11: 1.0 Vdd R/W 5'h Speaker Class AB Amplifier VMID Ratio Control (Output Gain Control) 000: 2.25 Vdd 001: 2.00 Vdd 010: 1.75 Vdd 011: 1.5 Vdd 100: 1.25 Vdd 101: 1 Vdd Others: Not allowed R/W 0'h Reserved R 0'h A1 Pin Status for I2C 0: 0 1: 1 R/W 0'h Reserved I2C + I2S Audio Codec + Voice PCM Interface 40 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.21. Reg-42h: General Purpose Control Register 2 Default: 0000h Table 34. Reg-42h: General Purpose Control Register 2 Name Bits Read/Write Reset State Description voice_stereo_digitalpath_en 15 R/W 0'b Voice to Stereo Digital Path Enable 0b: Disable 1b: Enable Reserved 14 R/W 0'h Reserved se_btl_clsab 13 R/W 0'b Single End & BTL of Class AB Selection: 0: Differential Mode 1: Single-End Mode Reserved 12:1 R/W 0'h Reserved pll_pre_div 0 R/W 0'b PLL Pre-Divider 0b: ÷1 1b: ÷2 8.22. Reg-44h: PLL Control Default: 0000h Table 35. Reg-44h: PLL Control Name Bits Read/Write Reset State Description pll_n_code 15:8 R/W 00'h N[7:0] Code for Analog PLL 00000000: Div 2 00000001: Div 3 . 11111111: Div 257 pll_m_bypass 7 R/W 0'h Bypass PLL M 0b: No bypass 1b: Bypass pll_k_code 6:4 R/W 0'h K[2:0] Code for Analog PLL 000: Div 2 001: Div 3 . 111: Div 9 pll_m_code 3:0 R/W 0'h M[3:0] Code for Analog PLL 0000: Div 2 0001: Div 3 . 1111: Div 17 Note: The PLL1 transmit formula is FOUT = (MCLK * (N+2)/(M+2) * (K+2) {Typical K=2} I2C + I2S Audio Codec + Voice PCM Interface 41 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.22.1. MCLK 13 3.6864 2.048 4.096 12 15.36 16 19.2 19.68 MCLK 13 3.6864 2.048 4.096 12 15.36 16 19.2 19.68 AC-LINK PLL Clock Setting Table (Unit: MHz) Table 36. I2C+I2S Clock Setting Table for 48K: (Unit: MHz) N M FVCO K 66 7 98.222 2 78 1 98.304 2 94 0 98.304 2 70 1 98.304 2 80 8 98.4 2 81 11 98.068 2 78 11 98.462 2 80 14 98.4 2 78 14 98.4 2 Table 37 N 68 72 86 64 66 63 66 64 67 I2C+I2S Clock Setting Table for 44.1K: (Unit: MHz) M FVCO K 8 91 2 1 90.931 2 0 90.112 2 1 90.112 2 7 90.667 2 9 90.764 2 10 90.667 2 12 90.514 2 13 90.528 2 I2C + I2S Audio Codec + Voice PCM Interface 42 FOUT 24.555 24.576 24.576 24.576 24.6 24.517 24.615 24.6 24.6 FOUT 22.75 22.733 22.528 22.528 22.667 22.691 22.667 22.629 22.632 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.23. Reg-4Ch: GPIO Pin Configuration Default: 2E3Eh Name Reserved over_temp_conf Bits 15:12 11 mic1_short_det_conf 10 mic2_short_det_conf 9 Reserved gpio5_conf 8:6 5 gpio4_conf 4 gpio3_conf 3 gpio2_conf 2 gpio1_conf 1 Reserved 0 Table 38. Reg-4Ch: GPIO Pin Configuration Read/Write Reset State Description R 00'h Reserved R/W 1'h Over-temperature Status Source Configuration 0: Bypass 1: Normal R/W 1'h MICBIAS1 Short Current Status Source Configuration 0: Bypass 1: Normal R/W 1'h MICBIAS2 Short Current Status Source Configuration 0: Bypass 1: Normal R 0'h Reserved R/W 1'h GPIO5 Pin Configuration 0: Output 1: Input R/W 1'h GPIO4 Pin Configuration 0: Output 1: Input R/W 1'h GPIO3 Pin Configuration 0: Output 1: Input R/W 1'h GPIO2 Pin Configuration 0: Output 1: Input R/W 1'h GPIO1 Pin Configuration 0: Output 1: Input R 0'h Reserved. Read as 0 I2C + I2S Audio Codec + Voice PCM Interface 43 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.24. Reg-4Eh: GPIO Pin Polarity Default: 2E3Eh Name Reserved over_temp_polarity Bits 15:12 11 mic1_short_det_polarity 10 mic2_short_det_polarity 9 Reserved gpio5_polarity 8:6 5 gpio4_polarity 4 gpio3_polarity 3 gpio2_polarity 2 gpio1_polarity 1 Reserved 0 Table 39. Reg-4Eh: GPIO Pin Polarity Read/Write Reset State Description R 00'h Reserved R/W 1'h Over-temperature Polarity 0: Low Active 1: High Active R/W 1'h MICBIAS1 Short Current Detect Polarity 0: Low Active 1: High Active R/W 1'h MICBIAS2 Short Current Detect Polarity 0: Low Active 1: High Active R 0'h Reserved. Read as 0 R/W 1'h GPIO Pin Polarity 0: Low Active 1: High Active R/W 1'h GPIO Pin Polarity 0: Low Active 1: High Active R/W 1'h GPIO Pin Polarity 0: Low Active 1: High Active R/W 1'h GPIO Pin Polarity 0: Low Active 1: High Active R/W 1'h GPIO Pin Polarity 0: Low Active 1: High Active R 0'h Reserved. Read as 0 I2C + I2S Audio Codec + Voice PCM Interface 44 Track ID: JATR-1076-21 JATR-1076-21 Rev. 1.0 ALC5620 ALC5620 Datasheet 8.25. Reg-50h: GPIO Pin Sticky Default: 0000h Name Reserved over_temp_sticky_En Bits 15:12 11 mic1_short_det_sticky_En 10 mic2_short_det_sticky_En 9 Reserved gpio5_sticky_En 8:6 5 gpio4_sticky_En 4 gpio3_sticky_En 3 gpio2_sticky_En 2 gpio1_sticky_En 1 Reserved 0 Table 40. Reg-50h: GPIO Pin Sticky Read/Write Reset State Description R 00'b Reserved R/W 0'h Over-temperature Sticky Enable 0: Not sticky 1: Sticky R/W 0'h MICBIAS1 Short Current Detect Sticky Enable 0: Not sticky 1: Sticky R/W 0'h MICBIAS2 Short Current Detect Sticky Enable 0: Not sticky 1: Sticky R 0'h Reserved. Read as 0 R/W 0'h GPIO5 Pin Sticky Enable 0: Not sticky 1: Sticky R/W 0'h GPIO4 Pin Sticky Enable 0: Not sticky 1: