AL250/251 AL250 AL251 AL250-01 YUV422 RGB565 VDIN12 VDIN13 VDIN14 VDIN15 VDIN11 - Datasheet Archive

 

AL250 Contents 1.0 Features _ 3 2.0 Applications _

 

AL250/251 AL250/251 Data Sheets AL250 AL250 Contents 1.0 Features _ 3 2.0 Applications _ 3 3.0 General Description_ 4 4.0 Pinout Diagrams _ 5 5.0 Pin Definition and Description_ 6 6.0 Functional Description _ 8 6.1 Digital Input/Output Data Formats _ 8 6.2 Default Resolution _ 9 6.3 Video Timing _ 9 6.4 Border/Border Color _ 13 6.5 OSD Interface _ 14 6.6 External Overlay _ 15 6.7 Look-up Table (LUT) _ 16 6.8 I2C Programming _ 16 6.9 Video Decoding _ 18 7.0 Electrical Characteristics _ 20 7.1 Recommended Operating Conditions _ 20 7.2 Characteristics_ 20 8.0 AL250/251 AL250/251 Register Definition _ 22 8.1 Register Description _ 23 9.0 Board Design and Layout Considerations _ 29 9.1 Grounding _ 29 9.2 Power Planes and Power Supply Decoupling _ 29 9.3 Digital Signal and Clock Interconnect _ 29 9.4 Analog Signal Interconnect_ 29 10.0 Mechanical Drawing _ 30 11.0 Power Consumption _ 32 July 28, 1999 2 AL250 AL250 AL250/251 AL250/251 Video Scan Doubler 1.0 Features · · · · · · · · · · · Convert interlaced TV signal (NTSC/PAL) into non-interlaced RGB format for CRT monitors or LCD panels Highly integrated design with built-in DAC, SRAM, OSD and LUT Built-in on-screen-display with programmable bitmap Interpolated scan doubling with no tearing or jagged edge artifacts Reduced interlace flicker Auto NTSC/PAL detect Digital video input of square pixel, ITU-RBT 601 (CCIR 601), or user-defined format Analog/digital non-interlaced RGB (VGA) signal output (Scan Doubled or Deinterlaced) I2C programming interface Power-down control via I2C Internal RGB video lookup table (LUT) to provide gamma correction and special effects Overlay support for title making and complex on-screen display Self-initialization without software (Plug & Play) 3.3 or 5 volt support 16-bit digital RGB/YUV output (AL251 AL251 only) · · · · 2.0 Applications · · · · · · TV-ready Multimedia Computer Monitor TV to PC Video Scan Converter Box Progressive Scan TV Video Game Station DVD Player LCD TV Monitor On-screen Display Video Memory 16 Digital YUV or RGB output (AL251 AL251) 8-bit DAC 16 Video Formatter Video Processor and Scan Doubler R 8-bit DAC G 8-bit DAC Digital YUV or RGB input RGB Video Lookup Tables B VCLK RSET I2C Circuit VREF Mode Control COMP SQUARE SDA I2CADDR SCL GVS GHREF GHS INTYPE 2 HREF STD VIDVS Timing Control RESET VIDHS OVLCTRL VCLKX2 AL250-01 AL250-01 July 28, 1999 3 AL250 AL250 3.0 General Description The AL250/251 AL250/251 Video Scan Doubler (De-Interlacer) is a video conversion chip for consumer video and multimedia applications. It converts interlaced NTSC or PAL, ITU-RBT 601 (CCIR 601) or square pixel, YUV422 YUV422 or RGB565 RGB565 digital signals into computer monitor RGB signals for direct connection to a computer monitor or progressive scan TV. By using I2C interface control, the AL250/251 AL250/251 can also be programmed to co-ordinate with various input resolutions, adjust screen positioning and crop video noise from around the original input video boundary. The internal RGB video lookup tables (LUT), which are controlled via I2C interface, can provide gamma correction for calibrating the color accuracy of different types of CRT's and improving the contrast level to display more vivid pictures. A built-in on-screen-display (OSD) provides programmable bitmap RAM for custom design icons and on-screen control panels. Overlay function is supported to create titling or on-screen-display menus for video adjustment. The AL251 AL251 provides all the features of the AL250 AL250. Additionally, it has digital output in YUV422 YUV422 or RGB565 RGB565 format, and can convert NTSC video for VGA LCD panels. The AverLogic proprietary digital signal processing technology creates a highly stable video image without tearing effects or jagged edges. The output picture is smoother and has less flicker than the original input signal/picture. July 28, 1999 4 VREF 39 VDIN5 COMP 38 VDIN6 RSET 37 VDIN7 AVDD 36 VDIN8 AR 35 AGND 34 AG 33 AVDD 32 AB 31 AGND 30 VDIN12 VDIN12 GHS 29 VDIN13 VDIN13 GVS 28 78 VDIN14 VDIN14 GREF 27 79 VDIN15 VDIN15 D011 26 80 NC D010 25 AL251 AL251 DO9 DO8 VDD SCL VDD SDA /RESET I2CADDR TESTIN SQUARE INTYPE GND STD1 STD0 HREF DO12 NC NC NC GND OVLCTRL0 OVLCTRL1 DO0 DO1 DO2 DO3 DO4 DO5 VDD VDD DO6 DO7 GND VDIN0 VDIN1 VDIN2 VDIN3 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VIDHS VDD VCLK VIDVS GND VCLKX2 HREF STD0 STD1 GND INTYPE SQUARE TESTIN I2CADDR /RESET SDA VDD SCL VDD VDIN4 VDIN3 VDIN2 VDIN1 VDIN0 GND TESTY7 TESTY6 VDD VDD TESTY5 TESTY4 TESTY3 TESTY2 TESTY1 TESTY0 OVLCTRL1 OVLCTRL0 GND VREF COMP RSET AVDD AR AGND AG AVDD AB AGND GHS GVS GREF 24 23 22 40 VCLKX2 GND NC VDIN4 64 AL250 AL250 21 20 19 18 17 16 15 14 13 12 11 10 9 77 8 GND 76 VIDVS VDIN11 VDIN11 75 VCLK VDIN10 VDIN10 74 7 VDIN9 73 VDD VDD 72 6 71 VIDHS 70 VDIN5 VDIN6 VDIN7 VDIN8 VDD VDIN9 VDIN10 VDIN10 VDIN11 VDIN11 GND VDIN12 VDIN12 VDIN13 VDIN13 VDIN14 VDIN14 VDIN15 VDIN15 5 69 4 68 NC DO15 67 NC DO14 66 DO13 65 3 NC 52 53 54 55 56 57 58 59 60 61 62 63 64 2 1 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AL250 AL250 4.0 Pinout Diagrams 32 31 30 29 28 27 26 25 24 23 22 21 20 AL251-01 AL251-01 pinout diagram July 28, 1999 5 AL250 AL250 5.0 Pin Definition and Description Symbol Type 250 Pin # 251 Pin # Description Video Interface VDIN (15 to 0) in (CMOS) 64-61, 59- 79-76, 74- Digital video data input. Please refer to the input 57, 55-52, 72, 70-67, data format table for details 51-47 62-58 VCLK in (CMOS) 3 6 Video clock input VCLKX2 in (CMOS) 6 9 2 times of video clock input VIDHS in (CMOS) 1 4 Horizontal sync. input signal VIDVS in (CMOS) 4 7 Vertical sync. input signal HREF in (CMOS) 7 10 Horizontal reference input signal; this signal is used to indicate data on the digital YUV bus. The positive slope marks the beginning of a new active line. Graphic Interface RSET In (100 ohm) 30 37 Full Scale Current Adjust; 100 ohm pull-down VREF in (1.235V) 32 39 Voltage Reference Input COMP out (0.1µF) 31 38 Compensation pin; 0.1µF pull-up AR out (0.7V) 28 35 VGA analog red output AG out (0.7V) 26 33 VGA analog green output AB out (0.7V) 24 31 VGA analog blue output DO (15 to 0) out (CMOS) N/A 66-63, 26- Digital YUV422 YUV422 or RGB565 RGB565 output, selected by 23, 56-55, register 08h 52-47 GHS out (TTL) 22 29 VGA horizontal sync. output signal GVS out (TTL) 21 28 VGA vertical sync. output signal GHREF out (CMOS) 20 27 VGA horizontal reference output signal; it can be used to indicate blanking interval. Reset & Mode Select /RESET in (CMOSd) 15 18 Reset input; active low STD (1 to 0) in (CMOSd) 9, 8 12, 11 Video Input Standard select 00: NTSC input July 28, 1999 6 AL250 AL250 01: PAL input 10: Automatic standard detection 11: Reserved for testing INTYPE in (CMOSd) 11 14 Input video data format select 0: 422 YUV (16-bit) 1: 565 RGB (16-bit) SQUARE in (CMOSd) 12 15 Square pixel/YUV (CCIR-601 CCIR-601) input select 0: YUV (CCIR-601 CCIR-601) 1: Square pixel TESTIN in (CMOSd) 13 16 Test input pin, to be pulled high for normal applications. SCL in (CMOSsu) 18 21 I2C-bus serial clock input SDA in/out (CMOSsu) 16 19 I2C -bus serial data input/output I2CADDR in (CMOSd) 14 17 I2C -bus slave address select 0: write address = 58, read address = 59 1: write address = 5C, read address = 5D OVLCTRL in (CMOSd) 35, 34 46, 45 Overlay control 00: No overlay 01: Overlay color #1 10: Overlay color #2 11: Overlay color #3 Overlay colors can be programmed by software out (CMOS) 45-44, 41-36 N/A Test output pins, for factory test only I2C & overlay Interface (1 to 0) Test pins TESTY (7 to 0) Power & Ground Pins VDD power 2, 17, 19, 5, 20, 22, Digital power pins. Connected to +5V power 42, 43, 56 53, 54, 71 GND power 5, 10, 33, 8, 13, 44, Digital ground pins 46, 60 57, 75 AVDD power 25, 29 32, 36 Analog power pins. Connected to +5V power AGND power 23, 27 30, 34 Analog ground pins Notes: CMOSd : CMOS with internal pull-down CMOSsu : CMOS with Schmitt trigger and internal pull-up July 28, 1999 7 AL250 AL250 6.0 Functional Description 6.1 Digital Input/Output Data Formats The digital video data formats that the AL250/251 AL250/251 accepts are YUV422 YUV422 and RGB565 RGB565. The pin definition and the RGB 888 to 565 mapping is as follows: Video Data Signal Pin Number YUV 422 RGB 888565 AL250 AL250 AL251 AL251 VDIN15 VDIN15 64 79 Y7 R7 VDIN14 VDIN14 63 78 Y6 R6 VDIN13 VDIN13 62 77 Y5 R5 VDIN12 VDIN12 61 76 Y4 R4 VDIN11 VDIN11 59 74 Y3 R3 VDIN10 VDIN10 58 73 Y2 G7 VDIN9 57 72 Y1 G6 VDIN8 55 70 Y0 G5 VDIN7 54 69 U7, V7 G4 VDIN6 53 68 U6, V6 G3 VDIN5 52 67 U5, V5 G2 VDIN4 51 62 U4, V4 B7 VDIN3 50 61 U3, V3 B6 VDIN2 49 60 U2, V2 B5 VDIN1 48 59 U1, V1 B4 VDIN0 47 58 U0, V0 B3 Pixel clock - - VCLK VCLK INTYPE = 0 INTYPE = 1 INTYPE select To select YUV422 YUV422 or RGB565 RGB565 as the input format, program the Board Configuration Register #02h, or set the hardware pin "INTYPE" (AL250 AL250 pin#11, AL251 AL251 pin#14). The AL251 AL251 provides digital output in RGB565 RGB565 or YUV422 YUV422 format. The pin definition and the RGB565 RGB565 to 888 mapping is as follows: Video Data Signal DO7 DO6 AL251 AL251 Pin # 56 55 YUV 422 RGB 565888 Y7 R7 Y6 R6 July 28, 1999 8 AL250 AL250 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 OutFormat select 52 51 50 49 48 47 66 65 64 63 26 25 24 23 - Y5 R5 Y4 R4 Y3 R3 Y2 G7 Y1 G6 Y0 G5 U7, V7 G4 U6, V6 G3 U5, V5 G2 U4, V4 B7 U3, V3 B6 U2, V2 B5 U1, V1 B4 U0, V0 B3 1 0 To select YUV422 YUV422 or RGB565 RGB565 as the output format, program the Control Register #08h, i.e., OutFormat. 6.2 Default Resolution The resolution of the AL250/251 AL250/251 applications depends on the input video source, e.g., the digital video decoder. The typical resolution of the video decoder that the AL250/251 AL250/251 supports without software, and the VCLK frequency provided by the decoder to the AL250/251 AL250/251 is as follows: Square Pixel CCIR 601 NTSC PAL NTSC PAL Pixel Total 780 x 525 944 x 625 858 x 525 864 x 625 Pixel Active 640 x 480 768 x 576 720 x 480 720 x 576 VCLKx2 (MHz) 24.545454 29.5 27 27 VCLK (MHz) 12.272727 14.75 13.5 13.5 The AL250/251 AL250/251 can process up to 768 active pixels per line and 1024 lines per frame. 6.3 Video Timing The AL250/251 AL250/251 registers 20h~29h and 2Bh~2Eh are used to control the video timing. All increments are either by 8 pixels per line or by 4 lines per frame. All values (times 8 or 4) are relative to the input July 28, 1999 9 AL250 AL250 video source H-sync or V-sync. These registers need to be programmed if the input video resolution is different from the default resolution supported. The H-sync Start and End (registers 22h and 23h) define the output horizontal sync period relative to the input H-sync leading edge. The Horizontal Blank Start and End (registers 2Bh and 2Ch) define the output H-sync blanking period. The Horizontal Capture Start and End (registers 20h and 21h) define the active pixels in each line relative to the input video H-sync. These registers can also be used for adjusting the position of the output picture. The Horizontal Total High and Low (registers 24h and 29h) define the total number of pixels per line. The AL250/251 AL250/251 can detect the H-total automatically when the input data is of the typical resolution mentioned in the Default Resolution section. The V-sync Start and End (registers 27h and 28h) define the output V-sync period relative to the input V-sync start. The Vertical Blank Start and End (registers 2Dh and 2Eh) define the output V-sync blanking period. The Vertical Capture Start and End (registers 25h and 26h) define the active lines. The total number of lines per frame (Vertical Total) is detected by the AL250/251 AL250/251 automatically. To take advantage of the auto detection of the AL250/251 AL250/251, set the bit 3 of the Control register #08h (Softtime) as 0. If a user-defined input format is used, then disable the hardware default by setting this bit as 1, and write all of the parameters to the corresponding registers to define the format. The sample code the AL250EVB AL250EVB provides disables the hardware settings. The following typical parameters (as well as hardware default values) are for reference: Mode Square NTSC Square PAL CCIR NTSC CCIR PAL H(Horizontal) total 780 944 858 864 V(Vertical) total 525 625 525 625 HDE Start 120 160 72 80 HDE End 736 896 752 760 H-sync Start 776 0 792 808 H-sync End 56 72 856 16 VDE Start 48 60 48 60 VDE End 500 604 500 604 July 28, 1999 10 AL250 AL250 V-sync Start 4 4 4 4 V-sync End 8 8 8 8 Reg.#20h HDE Start 0Fh 14h 09h 0Ah Reg.#21h HDE End 5Ch 70h 5Eh 5Fh Reg.#22h H-sync Start 61h 00h 63h 65h Reg.#23h H-sync End 07h 09h 6Bh 02h Reg.#24h HTOTAL10 HTOTAL10_3 61h 76h 6Bh 6Ch Reg.#29h HTOTAL2_1 02h 00h 01h 00h Reg.#25h VDE Start 0Ch 0Fh 0Ch 0Fh Reg.#26h VDE End 7Dh 97h 7Dh 97h Reg.#27h V-sync Start 01h 01h 01h 01h Reg.#28h V-sync End 02h 02h 02h 02h Reg.#2Bh H-blank Start 5Fh 73h 61h 62h Reg.#2Ch H-blank End 0Ch 11h 06h 07h Reg.#2Dh V-blank Start 7Fh 99h 7Fh 99h Reg.#2Eh V-blank End 0Ah 0Dh 0Ah 0Dh The output timing/format is as follows: Square NTSC Square PAL CCIR NTSC CCIR PAL Resolution 640x480/616x452 768x576/736x544 720x480/680x452 720x576/680x544 Pixel rate 24.5454 MHz 29.5 MHz 27.00 MHz 27.00 MHz Interlace No No No No Video Analog-color Analog-color Analog-color Analog-color Sync on G No No No No Video level 700mV/1V* 700mV/1V* 700mV/1V* 700mV/1V* White level 700mV/1V* 700mV/1V* 700mV/1V* 700mV/1V* Black level 0 IRE 0 IRE 0 IRE 0 IRE H total 780 944 858 864 H display 616* 736* 680* 680* H F-porch 40* 48* 40* 48* H B-porch 64* 88* 74* 64* HS width 60* 72* 64* 72* July 28, 1999 11 AL250 AL250 H border 24* 24* 24* 24* V total 525 625 525 625 V display 452* 544* 452* 544* V F-porch 29* 25* 29* 25* V B-porch 40* 52* 40* 52* VS width 4* 4* 4* 4* V border 8* 8* 8* 8* HS output ON(-)* ON(-)* ON(-)* ON(-)* VS output ON(-)* ON(-)* ON(-)* ON(-)* Fh 31.4685 KHz 31.250 KHz 31.4685 KHz 31.250 KHz Fv 59.94 Hz 50 Hz 59.94 Hz 50 Hz Remark: Values with "*" are programmable (S/W) or adjustable (H/W). The horizontal video timing diagram is as follows. Reference start (0) VIDHS Output H Total (24h, 29h) GHSync HSyncStart (22h) HSyncEnd (23h) H Blank Interval (AL250 AL250) HBlankEnd (2Ch) HBlankStart (2Bh) Left Border Right Border GHREF HDEStart (20h) H Blank Interval (AL251 AL251) HDEEnd (21h) Visible Picture AL250-06 AL250-06 Horizontal timing diagram July 28, 1999 12 AL250 AL250 The vertical video timing diagram is as follows. Reference start (0) VIDVS Output V Total GVSync VSyncStart (27h) VSyncEnd (28h) V Blank Interval (AL250 AL250) VBlankEnd (2Eh) VBlankStart (2Dh) Top Border Bottom Border VDEStart (25h) VDEEnd (26h) V Blank Interval (AL251 AL251) Visible Picture AL250-26 AL250-26 Vertical timing diagram Details about the registers can be found in the Register Definition section. 6.4 Border/Border Color The AL250/251 AL250/251 displays all the active pixels from the video source resulting in a larger viewable area on a monitor than on a regular TV. This is especially advantageous for digital video sources such as DVD. However, for some other video sources such as VCR, the unwanted and untrimmed border may appear. To solve this, the AL250/251 AL250/251 provides border control by cropping the video source. In addition, the cropped border can be filled with one color (24-bit), which is defined by registers 0Ch~0Eh. Border/border color control applies to the AL250/251 AL250/251 analog output but not to the AL251 AL251 digital YUV/RGB output. July 28, 1999 13 AL250 AL250 6.5 OSD Interface The AL250/251 AL250/251 provides two ways to implement the on screen display. The internal way is to program the built-in on-screen display (OSD) bitmap, and the external way is to control the two overlay pins for showing on screen display or creating special effects onto each single pixel on screen. The AL250/251 AL250/251 provides 256 registers to implement the two internal bitmaps, which are programmable as 16x16 blocks (4x4 pixels each) and 48x16 blocks (8x8 pixels each) respectively. To program the OSD, first use LUT/OSD Control register 10h to turn on bitmap 1 or bitmap 2. Then program the overlay colors 1, 2 and 3 through registers 15h~1Dh. Select the OSD index (0~255) through register 11h, then fill the data through register 13h. The two bits of each OSD block can be used to define no overlay color (transparent) or color 1, 2 or 3. Mesh color and mesh background can be enabled by programming register 2Fh. The position of the bitmaps can be defined by registers 1Eh, 1Fh, and 2Fh. The data index of the bitmap 1 starts at bitmap address 192, and the lay-out is defined as follows: 7:6 5:4 3:2 1:0 193 194 195 192 196 200 204 252 AL250-16 AL250-16 16x16 OSD drawing 253 254 255 Each pixel is defined by 2 bits value ("00", "01", "10" and "11"). Value "00" shows the current input video data. Value "01", "10" and "11" are index to overlay color 1~3 (defined in registers 15h ~ 1Dh). The data index of bitmap 2 starts at bitmap address 0, and the lay-out is defined as follows: July 28, 1999 14 AL250 AL250 0 4 5 7:6 5:4 3:2 1:0 188 1 189 2 190 3 191 AL250-17 AL250-17 16x48 OSD drawing Similar to bitmap 1, each pixel is defined by 2 bits value ("00", "01", "10" and "11") with the same definition. The horizontal positions of the bitmaps 1 & 2 are defined by registers 1Eh and 1Fh respectively. The vertical position of both is defined by register 2Fh. For the external OSD, the overlay feature needs to be used and this will be explained in detail in the External Overlay section. OSD control applies to the AL250/251 AL250/251 analog output and the AL251 AL251 digital RGB output, but not to the AL251 AL251 digital YUV output. 6.6 External Overlay The AL250/251 AL250/251 provides two overlay pins (OVLCTRL1 and OVLCTRL0) for overlay control as well as some special effects. They can be pulled as 00 for no overlay, and 01, 10, 11 for different overlay colors or effects. The colors can be chosen from any one of 16M colors (defined by 24 bits RGB) by programming registers 15h~1Dh. The effects can be logic AND, OR, or XOR of the video source with any of the three overlay colors by programming register 14h. For instance, a negative film effect can be produced by XOR the original video source with white color. More details can be found in the Register Definition section. Using the external overlay of the AL250/251 AL250/251 for caption display is possible if the OSD or FPGA chip chosen for displaying fonts of the decoded caption has the two overlay pins compatible with the AL250 AL250. If not, then the digital or analog output of the OSD can still be multiplexed with the output of the AL250/251 AL250/251 to show captions on the video display. July 28, 1999 15 AL250 AL250 External overlay applies to the AL250/251 AL250/251 analog output and the AL251 AL251 digital RGB output, but not to the AL251 AL251 digital YUV output. 6.7 Look-up Table (LUT) Because of the different characteristics of TV's and PC monitors, direct color space conversion from TV to PC may not show the same color that the human eye sees from the original video on the TV. The contrast may not be sufficient, and the hue may not be accurate, so to resolve these issues the AL250/251 AL250/251 has a gamma correction internal LUT implemented. The AL250/251 AL250/251 provides 768 registers for implementing the LUT. The directly converted colors are sent to the LUT that then sends out the mapped, corrected colors. To program the LUT, first choose a color (R, G or B) from register 10h, select the LUT index (0~255) through register 11h, then fill the data (0~255) through register 13h. The input 8-bit R (or G or B) value is then converted to the corrected R (or G or B) value. The user can program the LUT based on his/her own experiments on specific types of monitors. The typical input-output mapping curve is usually somewhat like the following: Output Corrected Conversion Direct Conversion Input LUT control applies to the AL251/251 AL251/251 analog output but not to the AL251 AL251 digital YUV/RGB output. 6.8 I2C Programming The AL250/251 AL250/251 I2C programming interface follows the Philips standard. The I2C interface consists of the SCL (clock) and SDA (data) signals. Data can be written to or read from the AL250/251 AL250/251. For both read and write, each byte is transferred MSB first, and the SDA data bit is valid when the SCL is pulled high. July 28, 1999 16 AL250 AL250 The read/write command format is as follows: Write: Read: Following are the details: : Start signal SCL SDA High High High Low The Start signal is HIGH to LOW transition on the SDA line when SCL is HIGH. : Write Slave Address: 58h or 5Ch SDA Data bit [1] or NA SCL SDA Data bit [0] or A SCL : Read Slave Address: 59h or 5Dh SDA : Value of the AL250/251 AL250/251 register index. : Acknowledge stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) for the AL250/251 AL250/251 (slave) to pull down the SDA line during the acknowledge clock pulse. START bit [S] SCL STOP bit [P] SCL SDA Not significant : Not Acknowledge stage The acknowledge-related clock pulse is generated by the host (master). The host releases the SDA line (HIGH) during the acknowledge clock pulse, but the AL250/251 AL250/251 does not pull it down during this stage. SCL AL250-15 AL250-15 I2C drawing : Data byte write to or read from the register index. In read operation, the host must release the SDA line (high) before the first clock pulse is transmitted to the AL250 AL250. July 28, 1999 17 AL250 AL250 : Stop signal SCL SDA High Low High High The Stop signal is LOW to HIGH transition on the SDA line when SCL is HIGH. Suppose data F0h is to be written to register 0Fh using write slave address 58h, the timing is as follows: Start Slave addr = 58h Ack Index = 0Fh Ack Data = F0h Ack Stop SDA SCL AL250-24 AL250-24 I2C Write timing Suppose data is to be read from register 55h using read slave address 59h, the timing is as follows: Start Slave addr = 58h Ack Index = 55h Ack Stop Read slave addr = 59h NAck Start Ack Data read cycle Stop SDA SCL AL250-25 AL250-25 I2C Read timing 6.9 Video Decoding A video decoder (video input processor) is needed with the AL250/251 AL250/251 for S-video or composite video processing. Please note that the AL250/251 AL250/251 works only with line-locked video decoders. There are a number of video decoders available in the market; following is a selection chart. For detailed information, please consult with the decoder vendors or their distributors directly. The attached information is believed to be accurate but not guaranteed. July 28, 1999 18 AL250 AL250 Decoder Vendor Line locked NTSC/ PAL RGB565 RGB565 CCIR 601 SAA 7110 Philips V V SAA 7111 Philips V V V V SAA 7112 Philips V V V V KS0127 KS0127 Samsung V V V V VPC3211B VPC3211B ITT V V Square Pixel Closed Caption Tele text V V V V V More information on the AL250/251 AL250/251 functionality can be found in the Register Definition section. July 28, 1999 19 AL250 AL250 7.0 Electrical Characteristics 7.1 Recommended Operating Conditions Parameter Min Supply Voltage TAMB Ambient Operating Temperature Unit +3.0 VDD Max +5.5 V 0 +70 °C 7.2 Characteristics Parameter Test Conditions Min Max Unit IDD Supply current 55 110 mA P Power consumption 180 600 mW VIH Hi-level input voltage 0.7VDD VDD+0.5 V VIL Lo-level input voltage -0.5 +0.8 V VOH Hi-level output voltage 2.4 VDD V VOL Lo-level output voltage - 0.5 V IO Output current, data -0.5V