AL1402 AL1401A AL1402-0605 AL1201 GP1F33RT - Datasheet Archive

 

ADAT® Optical Decoder General Description Features Compatible with ADAT Type I and II formats 4 stereo pairs as inputs using

 

AL1402 AL1402 ADAT® Optical Decoder General Description Features Compatible with ADAT Type I and II formats 4 stereo pairs as inputs using standard ADC formats 4 user bit outputs to receive time-code, MIDI data, etc. Internal PLL generates all required clocks from optical data or wordclock Wordclock input to synchronize outputs to user's system The AL1402 AL1402 OptoRec interface decodes a single datastream of the industry-standard ADAT Optical protocol (U.S. patent number 5,297,181) and produces four stereo pairs (8 channels) of digital audio suitable for DACs or further processing. With an internal PLL to generate all needed clock signals, the AL1402 AL1402 requires no external clocks in master mode, and only wordclock (Fs) for proper operation in slave mode. A companion encoder, the OptoGenTM, is also available. AL1401A AL1401A Applications Digital Mixing Boards Use of the ADAT Optical interface (including the OptoGen and OptoRec) requires a license agreement (generally royalty-free) between the manufacturer and Wavefront Semiconductor. Details and agreement information are available upon request from Wavefront directly, or on our web site. Signal Processors Digital Effects Boxes Digital Recorders Computer Sound Boards Sound Reinforcement Products Package GND MODE0 FMT0 FMT1 MODE1 OPDIGIN SVCO WDCLK BCLK OUT 1/2 OUT 3/4 OUT 5/6 VDD LINMODE MUTE ERROR HOLDERR OPDIGTHRU DVCO USER3 USER2 USER1 USER0 OUT 7/8 24 pin SOIC 300 mils wide Wavefront Semiconductor 200 Scenic View Drive Cumberland, RI 02864 U.S.A. Tel: +1 401 658-3670 Fax: +1 401 658-3680 Email: info@wavefrontsemi.com On the web at www.wavefrontsemi.com 1 AL1402-0605 AL1402-0605 Table of Contents General Description . 1 Features . 1 Applications . 1 Package . 1 Table of Contents . 2 Pin Descriptions . 2 Electrical Characteristics . 3 Architecture Details . 3 Serial Input Interface . 3 Serial Input Format Selection . 3 Serial Input Formats . 4 Serial Input Format Timing . 4 Wordclock Selection . 5 Wordclock Mode Selection . 5 Wordclock Modes . 5 Wordclock Muting . 5 ADAT Optical Datastream . 6 Reset Circuitry . 6 Clock Generator and PLL . 6 Package Dimensions . 7 Sample Application Schematic . 8 Notice and Contact Information . 9 Pin Descriptions Pin# Name Pin Type 1 2 3 4 5 6 GND MODE0 FMT0 FMT1 MODE1 OPDIGIN Ground In In In In In 7 SVCO Out 8 9 10 11 12 13 14 15 16 17 18 19 WDCLK BCLK OUT 1/2 OUT 3/4 OUT 5/6 OUT 7/8 USER0 USER1 USER2 USER3 DVCO OPDIGTHRU I/O Out Out Out Out Out Out Out Out Out Out Out 20 HOLDERR In 21 ERROR Out 22 23 24 MUTE LINMODE VDD In In Power Description Ground connection. Mode 0, sets mode. Format 0, sets data format. Format 1, sets data format. Mode 1, sets mode. Input to optical receiver. Master mode: DVCO-derived clock (nominal 12.288MHz, 256*Fs), Slave mode: WDCLK-derived clock. Wordclock input/output (nominal 48kHz, Fs). Bitclock output (nominal 3.072MHz, 64*Fs). Channels 1&2 data output. Channels 3&4 data output. Channels 5&6 data output. Channels 7&8 data output. User 0 data bit output. Used to receive timecode. User 1 data bit output. Used to receive MIDI data. User 2 data bit output. Used to receive S/Mux indicator. User 3 data bit output. Reserved. Recovered clock from datastream (nominal 12.288MHz, 256*Fs). Regenerated OPDIGIN for daisy-chaining. If high, ERROR pin stays high until cause of error removed AND HOLDERR goes low. Indicates lack of input or failure to synchronize to datastream. If high, data outputs muted but not clock outputs. Mute select: 1=Mute outputs, 0=No muting. Tie high. VDD power pin. www.wavefrontsemi.com 2 Electrical Characteristics Symbol Description Min Typ Max Units 4.5 5.0 7.7 5.4 0 48 25 5.5 V mA mA V kHz °C Recommended Operating Conditions VDD IDD-MSTR IDD-SLAV GND Fs Temp Supply Voltage Supply Current, Master Supply Current, Slave Ground Sample rate Temperature 30 0 55 70 Inputs (WDCLK, FMT0-1, OPDIGIN, MODE0-1 LINMODE, MUTE, HOLDERR) 0.75 VDD 0.25 VDD 1 1 5 Logical "1" input voltage Logical "0" input voltage Logical "1" input current Logical "0" input current Logic input capacitance VIH VIL IIH IIL CIN V V A A pF Outputs (WDCLK, DVCO, OPDIGTHRU, SVCO, BCLK, ERROR) VOH VOL IOH IOL Logical Logical Logical Logical "1" "0" "1" "0" output output output output voltage voltage current current 0.9 VDD 0.1 VDD -8 8 V V mA mA 0.1 VDD -2 2 V V mA mA Outputs (OUT1/2-7/8, USER0-3) VOH VOL IOH IOL Logical Logical Logical Logical "1" "0" "1" "0" output output output output voltage voltage current current 0.9 VDD Architecture Details Serial Output Interface The AL1402 AL1402 OptoRec interface has been designed for ease of use and flexibility in systems designed to interface to the ADAT protocol. It supports both left and right justified data formats for ease of integration into existing devices as well as new devices. These formats allow it to operate in parallel with many standard ADCs. The specific output format to be used is selected by the format pins FMT1 and FMT0. Serial Output Format Selection FMT[1:0] Format 00 Right justified, BCLK falls on WDCLK edge. 01 Left justified, BCLK rises on WDCLK edge. 10 Chip reset. 11 Gated BCLK, BCLK rises on WCLK edge. www.wavefrontsemi.com 3 Serial Output Formats one period WordClock WDCLK Left Just 24 ADAT Type II ® ADAT Type I ® 23 23 0 MSB 0 MSB 19 19 0 MSB 0 MSB 15 15 0 MSB 0 MSB BCLK (rising) Right Just 24 ADAT Type II ADAT Type I ® ® 23 23 0 MSB 19 19 0 MSB 0 MSB 0 MSB 15 15 0 MSB 0 MSB BCLK (falling) Left Just 24 23 23 0 MSB 0 MSB Gated BCLK *Note: The most significant bit is sign-extended to the left of the frame. +Note: These diagrams represent how data would be framed from an ADAT Type I or Type II device. They are not actual modes of the OptoRec. The left justified mode is recommended for ADAT formats. Serial Output Timing WDCLK LEFT CHANNEL tDS OUT tDU USER Symbol tDS(Mstr) tDS(Slav) tDU(Mstr) tDU(Slav) VALID Description Min Typ OUT setup time relative to Master WDCLK output -10 2 OUT setup time relative to Slave WDCLK input -7 5 USER setup time relative to Master WDCLK output -10 0 USER setup time relative to Slave WDCLK input -8 2 Note: Above specifications hold after 3900 WDCLK cycles of valid input at OPDIGIN. www.wavefrontsemi.com 4 Max 27 30 25 27 Units ns ns ns ns Wordclock Selection With the use of the MODE inputs, the user may choose the source of the wordclock used to generate the output clocks for the OptoRec. When the OptoRec is in Master Mode, all outputs are derived from the input ADAT Optical datastream on the OPDIGIN pin, and WDCLK is an output. When the OptoRec is in Slave Mode, OUT1/2-7/8, USER0-3, BCLK, and SVCO are synchronous to WDCLK, which is an input. While in Slave mode, WDCLK may be at an arbitrary phase with respect to the incoming samples of OPDIGIN, but if the two frequencies are not identical, samples will be dropped, repeated, or garbled. Generally, identical frequencies are achieved by either using DVCO as the source from which WDCLK is generated, or creating OPDIGIN from a source synchronized to WDCLK. Wordclock Mode Selection MODE[1:0] Mode 00 Master Mode, WDCLK is an output. Slave Mode, WDCLK is an input. WDCLK MUST be 01 derived from the same clock supplying the source. 10 Reserved. 11 Reserved. Wordclock Modes Master Mode WDCLK SVCO DVCO 1 2 3 4 5 124 125 126 127 128 129 130 131 132 133 252 253 254 255 256 1 2 3 4 5 124 125 126 127 128 129 130 131 132 133 252 253 254 255 256 Slave Mode In Slave mode DVCO is not phase aligned with WDCLK and SVCO. Wordclock Muting The OptoRec in Master Mode can produce clock outputs running at uncontrolled frequencies if the digital input becomes unstable after stable use, due mostly to poor connection of the optical cable to the optical connector. Care should be taken when running the OptoRec with the AL1201 AL1201 DAC as the AL1201 AL1201 DAC will output noise if the OptoRec WDCLK is at an uncontrolled VCO frequency beyond the AL1201 AL1201's maximum. An external AND gate implementation may be used to correct this. The inverted ERROR pin and the desired OptoRec output clock are inputs to the AND gate and the desired mutable clock is the output, and the AND function will mute the selected OptoRec clock when the ERROR pin is high (i.e. when unstable input is present at OPDIGIN). In place of this circuit, the ERROR pin may be used as a mute select for any audio output stage muting circuitry that is present in the system. www.wavefrontsemi.com 5 ADAT Optical Datastream The AL1402 AL1402 provides support for both the ADAT Type I format (16-bit) and the ADAT Type II format (20-bit). Data lengths of up to 24 bits are supported. USER0 is used to receive the ADAT format 32-bit timecode, USER1 is used to receive MIDI data, USER2 is used to receive the S/Mux data indicator, and USER3 is reserved and should be tied low. Reset Circuitry An OptoRec reset, initiated by setting FMT[1:0]=10, is synchronous, and a minimum duration of 1 DVCO clock period is required. At a nominal 12.288MHz, this translates to 82ns. A safety margin is advised, and a pulse width of 100ns would be sufficient to reset the chip. This will reset all internal counters and state registers to their initial state and disrupt the outputs. However, PLL lock to OPDIGIN will not be disturbed. The clock and data outputs of the OptoRec are undefined after power-up until a proper datastream is well established on OPDIGIN. The clock outputs may be running at an uncontrolled frequency during that time. In this case, the ERROR pin will be high, indicating that the outputs are invalid. This may be prevented by using the FMT pins to reset the OptoRec on power-up, thus stopping the VCO clocks and muting the data output. The FMT pins may then be set to the value required in your system. Nevertheless the OptoRec will synchronize and produce proper outputs when proper and valid inputs are provided, whether this reset procedure is used or not. Clock Generator and PLL The OptoRec contains an internal PLL that locks to the embedded clock in the ADAT Optical datastream and produces all necessary high frequency clocks and timing signals to operate the device. This high quality PLL will reject any high-frequency jitter on the incoming datastream. Receiving 8 channels of ADAT Optical data on OPDIGIN, the jitter was measured to be 1.5ns typical on WDCLK. Using the extracted clock, the PLL generates the DVCO output. The datastream is also reconstructed using this PLL and outputted on OPDIGTHRU (clocked on the rising edge of DVCO), and thus the OPDIGTHRU datastream is synchronized to the PLL's wordclock, as well as to OPDIGIN. Symbol tDI tDT Description OPDIGIN setup time relative to Master WDCLK output OPDIGTHRU setup time relative to Master WDCLK output www.wavefrontsemi.com 6 Min -34 -20 Typ -53 -4 Max -72 5 Units ns ns The OptoRec contains a duplicate PLL that locks to the incoming clock signal on WDCLK when in slave mode. Receiving 8 channels of ADAT Optical data on OPDIGIN, the jitter was measured to be 1.26ns typical on BCLK. The second PLL locks onto the wordclock selected by the user via the Master/Slave Mode selection. In Master Mode, the selected wordclock comes from the first PLL, and SVCO, BCLK, and WDCLK are all synchronized to it. In Slave Mode, WDCLK is an input, and is what SVCO and BCLK are locked to. Symbol tDB Description Min 0 BCLK setup time relative to Slave WDCLK output Typ 9 Max 30 Units ns The PLL allows a simplified user interface and eliminates the need of running high frequency clocks to the part on PCB traces. This reduces unwanted RF noise and coupling problems that can occur when such clock signals are required on input pins for a device. Package Dimensions A B C D E F G H J K L A 24 1 C 13 12 B Dimensions (Typical) Inches Millimeters 0.606" 15.40 0.295" 7.50 0.406" 10.30 0.100" 2.50 0.008" 0.20 0.025" 0.64 0.050" 1.27 0.017" 0.42 0.011" 0.27 0.352" 8.94 0.033" 0.83 Note: Dimension "A" does not include mold flash, protrusions, or gate burrs. 7° nom K 4° nom D H E J G F www.wavefrontsemi.com 7 L Sample Application Schematic The following schematic shows the OptoGen and OptoRec in a typical application. The OptoGen accepts input from an ADC, then outputs data in the ADAT Optical format on the optical transmitters. The OptoRec receives ADAT Optical data on the optical receivers, then outputs data to a DAC. +5V 0.1uF 5 NC INPUT VCC C_LIMIT GND NC +5V 4 3 2 1 OPTOGEN 19 TOTX173* 6 OPTICAL OUT WDCLK RESET 0.1uF 20 VDD OPDGOUT 8.2k 4 WDCLK 5 OUTPUT VCC GND1 GND2 NC 2 NC 3 +5V 15 16 17 18 7 8 9 10 NC NC GND 1 3 MIDI DATA +5V 1 2 4 +5V 0.1uF TORX173* 1/2 3/4 5/6 7/8 TIME CODE WDCLKNEG +5V 47uH USER0 USER1 USER2 USER3 FMT0 FMT1 FMT2 FMT3 IN IN IN IN RESET 6 5 IN 1/2 IN 3/4 IN 5/6 IN 7/8 11 12 13 14 0.1uF 6 OPTOREC 6 3 4 OPTICAL IN ERROR 24 VDD OPDIGTHRU OUT 1/2 OUT 3/4 OUT 5/6 OUT 7/8 OPDIGIN FMT0 FMT1 21 20 ERROR HOLDERR 23 2 5 22 LINMODE MODE0 MODE1 MUTE GND USER0 USER1 USER2 USER3 DVCO SVCO WDCLK BCLK 19 10 11 12 13 14 15 16 17 18 7 8 9 OPDIGTHRU OUT 1/2 OUT 3/4 OUT 5/6 OUT 7/8 TIME CODE NC NC MIDI DATA DVCO SVCO 1 (Master Mode, can be MCLK) WDCLK (Slave Mode) WDCLK (Master Mode) BCLK (Master Mode) * Optical I/O parts shown are Toshiba parts. The Sharp GP1F33RT GP1F33RT or equivalent is also compatible. LEFTIN LEFTOUT RIGHTIN INL/R WDCLK BCLK MCLK RIGHTOUT OUTL/R WDCLK BCLK MCLK ADC DAC www.wavefrontsemi.com 8 NOTICE Wavefront Semiconductor reserves the right to make changes to their products or to discontinue any product or service without notice. All products are sold subject to terms and conditions of sale supplied at the time of order acknowledgement. Wavefront Semiconductor assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Information contained herein is only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, no responsibility is assumed for inaccuracies. Wavefront Semiconductor products are not designed for use in applications which involve potential risks of death, personal injury, or severe property or environmental damage or life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. All trademarks and registered trademarks are property of their respective owners. Contact Information: Wavefront Semiconductor 200 Scenic View Drive Cumberland, RI 02864 U.S.A. Tel: +1 401 658-3670 Fax: +1 401 658-3680 On the web at www.wavefrontsemi.com Email: info@wavefrontsemi.com Copyright © 2005 Wavefront Semiconductor Application note revised June, 2005 Reproduction, in part or in whole, without the prior written consent of Wavefront Semiconductor is prohibited. www.wavefrontsemi.com 9