AK4645EZ AK4645EZCODEC MS0605-J-00 AK4644 AK4645 AKD4645 AK4643/44 AK4643 32QFN - Datasheet Archive

 

AK4645EZ Stereo CODEC with MIC/HP-AMP AK4645EZCODEC AK4645EZ PLLPMP() 32pin QFN (4mm x 4mm) 1. · 4 · ( or )

 

[AK4645EZ AK4645EZ] AK4645EZ AK4645EZ Stereo CODEC with MIC/HP-AMP AK4645EZCODEC AK4645EZCODEC AK4645EZ AK4645EZ PLLPMP() 32pin QFN (4mm x 4mm) 1. · 4 · ( or ) · · (+32dB/+26dB/+20dB or 0dB) · Digital ALC (Automatic Level Control) (+36dB -54dB, 0.375dB Step, Mute) · ADC: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB) S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB) · · · Programmable EQ 2. · (tc=50/15s, fs=32kHz, 44.1kHz, 48kHz) · · · (+12dB -115.0dB, 0.5dB Step, Mute) · Digital ALC (Automatic Level Control) (+36dB -54dB, 0.375dB Step, Mute) · · Programmable EQ · - : S/(N+D): 88dB, S/N: 92dB · - HP-AMP: S/(N+D): 70dB@7.5mW, S/N: 90dB - : 70mW@16 (HVDD=5V), 62mW@16 (HVDD=3.3V) - ON/OFF · : 4 3. 4. : (1) PLL · : 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz (MCKI pin) 1fs (LRCK pin) 32fs or 64fs (BICK pin) (2) · : 256fs, 512fs or 1024fs (MCKI pin) 5. : 32fs/64fs/128fs/256fs 6. : · PLL Slave Mode (LRCK pin): 7.35kHz 48kHz · PLL Slave Mode (BICK pin): 7.35kHz 48kHz · PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz MS0605-J-00 MS0605-J-00 2007/06 -1- [AK4645EZ AK4645EZ] · PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz · EXT Master/Slave Mode: 7.35kHz 48kHz (256fs), 7.35kHz 26kHz (512fs), 7.35kHz 13kHz (1024fs) 7. P: 3, I2C (Ver 1.0, 400kHz Fast-mode) 8. 9. : MSB First, 2's complement · ADC : 16bit, I2S, DSP Mode · DAC : 16bit, 16bit, 16-24bit I2S, DSP Mode 10. Ta = -30 85°C 11. : · AVDD, DVDD: 2.6 3.6V (typ. 3.3V) · HVDD: 2.6 5.25V (typ. 3.3V/5.0V) · TVDD (Digital I/O): 1.6 3.6V (typ. 3.3V) 12. : 32pin QFN (4mm x 4mm, 0.4mm pitch) 13. AK4644 AK4644 AVDD AVSS VCOM TVDD DVDD PMMP MPWR MIC Power Supply I2C Control Register PMADL or PMMICL LIN1/IN1- CSN/CAD0 CCLK/SCL CDTI/SDA Internal MIC RIN1/IN1+ MIC-Amp LIN2/IN2+ External MIC PDN PMADL or PMADR A/D HPF Wind-Noise Stereo ALC Reduction Separation PMADR or PMMICR BICK RIN2/IN2- LRCK SDTO PMAINR2 MIN/LIN3 Line In * RIN3 Line In Audio I/F SDTI RIN4/IN4- PMAINL2 LIN4/IN4+ PMAINR3 PMAINR4 PMAINL3 PMAINL4 PMMIN PMLO PMDAC LOUT/LOP Stereo Line Out D/A Stereo DATT Bass ALC Separation SMUTE Boost HPF ROUT/LON MCKO PMPLL PMHPL PLL * VCOC HPL Headphone MCKI PMHPR HPR MUTET HVDD HVSS (VCOC pinRIN3 pin) Figure 1. MS0605-J-00 MS0605-J-00 2007/06 -2- [AK4645EZ AK4645EZ] -30 +85°C AK4645 AK4645 AK4645EZ AK4645EZ AKD4645 AKD4645 32pin QFN (0.4mm pitch) RIN4 / IN4- MUTET HPL HPR HVDD HVSS MCKO MCKI 24 23 22 21 20 19 18 17 LRCK RIN2 / IN2- 29 Top View 12 SDTO LIN2 / IN2+ 30 11 SDTI LIN1 / IN1- 31 10 CDTI / SDA RIN1 / IN1+ 32 9 CCLK / SCL 8 13 CSN / CAD0 AK4645EZ AK4645EZ 7 28 PDN MIN / LIN3 6 BICK I2C 14 5 27 VCOC / RIN3 LOUT / LOP 4 DVDD AVDD 15 3 26 AVSS ROUT / LON 2 TVDD VCOM 16 1 25 MPWR LIN4 / IN4+ AK4643/44 AK4643/44 1. Function Function Digital I/O of P I/F Analog Mixing for Playback Input Selector for Recording HP-Amp Hi-Z Setting for wired OR PLL Speaker-Amp Receiver-Amp Package AK4643 AK4643 2.6 to 3.6V 3 Stereo 3 Stereo No 11.2896/12/12.288/ 13.5/24/27MHz Yes Yes 32QFN 32QFN (5mm x 5mm, 0.5mm pitch) MS0605-J-00 MS0605-J-00 AK4644 AK4644 AK4645EZ AK4645EZ 1.6 to 3.6V 4 Stereo 4 Stereo Yes 11.2896/12/12.288/13/ 13.5/19.2/24/26/27MHz No No 32QFN 32QFN (4mm x 4mm, 0.4mm pitch) 2007/06 -3- [AK4645EZ AK4645EZ] 2. Pin Pin# 16 19 20 21 22 23 24 25 26 27 AK4643 AK4643 DVSS SPN SPP HVDD HVSS HPR HPL MUTET ROUT/RCN LOUT/RCP AK4644 AK4644 AK4645EZ AK4645EZ TVDD HVSS HVDD HPR HPL MUTET RIN4 / IN4- LIN4 / IN4+ ROUT/LON LOUT/LOP TEST1 TEST2 3. (AK4644 AK4644) Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Power Management 4 Mode Control 5 Lineout Mixing Select HP Mixing Select Reserved D7 0 HPZ 0 LOVL PLL3 PS1 DVTM 0 REF7 IVL7 DVL7 RGAIN1 IVR7 DVR7 0 0 INR1 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQA15 EQB7 0 EQC7 EQC15 EQC15 F1A7 F1AS F1B7 0 HPMTN 0 LOPS PLL2 PS0 WTM2 0 REF6 IVL6 DVL6 LMTH1 IVR6 DVR6 LOOP 0 INL1 GN0 F3A6 0 F3B6 0 EQA6 EQA14 EQA14 EQB6 0 EQC6 EQC14 EQC14 F1A6 0 F1B6 0 PMAINR4 PMAINL4 0 LOM 0 0 D6 PMVCM D5 PMMIN PMHPL 0 PLL1 FS3 ZTM1 ALC REF5 IVL5 DVL5 0 IVR5 DVR5 SMUTE 0 HPG 0 F3A5 F3A13 F3A13 F3B5 F3B13 F3B13 EQA5 EQA13 EQA13 EQB5 EQB13 EQB13 EQC5 EQC13 EQC13 F1A5 F1A13 F1A13 F1B5 F1B13 F1B13 D4 0 PMHPR DACL 0 PLL0 MSBS ZTM0 ZELMN REF4 IVL4 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3A12 F3B4 F3B12 F3B12 EQA4 EQA12 EQA12 EQB4 EQB12 EQB12 EQC4 EQC12 EQC12 F1A4 F1A12 F1A12 F1B4 F1B12 F1B12 D3 PMLO M/S 0 0 BCKO BCKP WTM1 LMAT1 REF3 IVL3 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3A11 F3B3 F3B11 F3B11 EQA3 EQA11 EQA11 EQB3 EQB11 EQB11 EQC3 EQC11 EQC11 F1A3 F1A11 F1A11 F1B3 F1B11 F1B11 D2 PMDAC 0 PMMP MINL 0 FS2 WTM0 LMAT0 REF2 IVL2 DVL2 0 IVR2 DVR2 BST0 HPM INR0 FIL3 F3A2 F3A10 F3A10 F3B2 F3B10 F3B10 EQA2 EQA10 EQA10 EQB2 EQB10 EQB10 EQC2 EQC10 EQC10 F1A2 F1A10 F1A10 F1B2 F1B10 F1B10 D1 0 MCKO 0 0 DIF1 FS1 RFST1 RGAIN0 REF1 IVL1 DVL1 VBAT IVR1 DVR1 DEM1 MINH INL0 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 0 DIF0 FS0 RFST0 LMTH0 REF0 IVL0 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL L4DIF RINR3 RINH3 0 MIX LINL3 LINH3 0 AIN3 RINR2 RINH2 0 LODIF MGAIN1 0 MICR3 MICL3 LOM3 RINR4 LINL4 HPM3 RINH4 LINH4 0 0 0 AK4645 AK4645 MS0605-J-00 MS0605-J-00 D0 PMADL PMPLL MGAIN0 LINL2 LINH2 0 2007/06 -4- [AK4645EZ AK4645EZ] No. 1 Pin Name MPWR I/O O Function , 0.45 x AVDD 2 VCOM O ADCDAC 3 AVSS 4 AVDD , 2.6 3.6V PLL(AIN3 bit = "0": PLL) VCOC O 5 AVSS RIN3 I Rch3(AIN3 bit = "1": PLL) 6 I2C I "H": I2C, "L": 3 7 PDN I "H": "L": CSN I (I2C pin = "L": 3) 8 CAD0 I 0 (I2C pin = "H" : I2C) CCLK I (I2C pin = "L": 3) 9 SCL I (I2C pin = "H": I2C) CDTI I (I2C pin = "L": 3) 10 SDA I/O (I2C pin = "H": I2C) 11 SDTI I 12 SDTO O 13 LRCK I/O 14 BICK I/O 15 DVDD , 2.6 3.6V 16 TVDD I/O, 1.6 3.6V 17 MCKI I 18 MCKO O 19 HVSS 20 HVDD 21 HPR O Rch 22 HPL O Lch 23 MUTET O HVSS pin RIN4 I Rch4(L4DIF bit = "0": ) 24 IN4- I 4(L4DIF bit = "1": ) LIN4 I Lch2(L4DIF bit = "0": ) 25 IN4+ I 4(L4DIF bit = "1": ) ROUT O Rch(LODIF bit = "0": ) 26 LON O (LODIF bit = "1": ) LOUT O Lch(LODIF bit = "0": ) 27 LOP O (LODIF bit = "1": ) MIN I (AIN3 bit = "0": PLL) 28 LIN3 I Lch3 (AIN3 bit = "1": PLL) RIN2 I Rch2(MDIF2 bit = "0": ) 29 IN2- I 2(MDIF2 bit = "1": ) LIN2 I Lch2(MDIF2 bit = "0": ) 30 IN2+ I 2(MDIF2 bit = "1": ) LIN1 I Lch1(MDIF1 bit = "0": ) 31 IN1- I 1(MDIF1 bit = "1": ) RIN1 I Rch1(MDIF1 bit = "0": ) 32 IN1+ I 1(MDIF1 bit = "1": ) Note 1. (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, LIN4, RIN4) Note 2. I2C pinAVDDAVSS MS0605-J-00 MS0605-J-00 2007/06 -5- [AK4645EZ AK4645EZ] Analog Digital MPWR, VCOC/RIN3, HPR, HPL, MUTET, RIN4/IN4-, LIN4/IN4+, ROUT/LON, LOUT/LOP, MIN/LIN3, RIN2/IN2-, LIN2/IN2+, LIN1/IN1-, RIN1/IN1+ MCKO MCKI HVSS (AVSS, HVSS=0V; Note 3, Note 4) Parameter Power Supplies: Analog Digital Digital I/O Headphone-Amp Input Current, Any Pin Except Supplies Analog Input Voltage (Note 5) Digital Input Voltage (Note 6) Ambient Temperature (powered applied) Storage Temperature Symbol AVDD DVDD TVDD HVDD IIN VINA VIND Ta Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -30 -65 max 6.0 6.0 6.0 6.0 ±10 AVDD+0.3 TVDD+0.3 85 150 Units V V V V mA V V °C °C Note 3. Note 4. AVSSHVSS Note 5. I2C, RIN4/IN4-, LIN4/IN4+, MIN/LIN3, RIN3, RIN2/IN2-, LIN2/IN2+, LIN1/IN1-, RIN1/IN1+ pins Note 6. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins SDA, SCL pins(TVDD+0.3)V : (AVSS, HVSS=0V; Note 3) Parameter Power Supplies Analog (Note 7) Digital Digital I/O HP-Amp Difference Symbol AVDD DVDD TVDD HVDD AVDD-DVDD min 2.6 2.6 1.6 2.6 -0.3 typ 3.3 3.3 3.3 3.3 / 5.0 0 max 3.6 3.6 DVDD 5.25 +0.3 Units V V V V V Note 3. Note 7. AVDD, DVDD, TVDD, HVDDPDN pin = "L"PDN pin "H" () OFFOFF OFF : MS0605-J-00 MS0605-J-00 2007/06 -6- [AK4645EZ AK4645EZ] (Ta=25°C; AVDD, DVDD, TVDD, HVDD=3.3V; AVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 20kHz; unless otherwise specified) min typ max Units Parameter MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = "1"); MDIF1=MDIF2 bits = "0" (Single-ended inputs) Input MGAIN1-0 bits = "00" 40 60 80 k Resistance MGAIN1-0 bits = "01", "10"or "11" 20 30 40 k MGAIN1-0 bits = "00" 0 dB MGAIN1-0 bits = "01" +20 dB Gain MGAIN1-0 bits = "10" +26 dB MGAIN1-0 bits = "11" +32 dB MIC Amplifier: IN1+/IN1-/IN2+/IN2- pins; MDIF1 = MDIF2 bits = "1" (Full-differential input) Input Voltage (Note 8) MGAIN1-0 bits = "01" 0.228 Vpp MGAIN1-0 bits = "10" 0.114 Vpp MGAIN1-0 bits = "11" 0.057 Vpp MIC Power Supply: MPWR pin Output Voltage (Note 9) 2.22 2.47 2.72 V Load Resistance 0.5 k Load Capacitance 30 pF ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = "1") ADC IVOL, IVOL=0dB, ALC=OFF Resolution 16 Bits (Note 11) 0.168 0.198 0.228 Vpp Input Voltage (Note 10) 1.68 1.98 2.28 Vpp (Note 12) (Note 11, LIN1/RIN1/LIN2/RIN2) 71 83 dBFS S/(N+D) (Note 11, LIN3/RIN3/LIN4/RIN4) 83 dBFS (-1dBFS) (Note 12, except for LIN3/RIN3) 88 dBFS (Note 12, LIN3/RIN3) 72 dBFS (Note 11) 76 86 dB D-Range (-60dBFS, A-weighted) 95 dB (Note 12) (Note 11) 76 86 dB S/N (A-weighted) 95 dB (Note 12) (Note 11) 75 90 dB Interchannel Isolation 100 dB (Note 12) (Note 11) 0.1 0.8 dB Interchannel Gain Mismatch 0.1 0.8 dB (Note 12) Note 8. AC MGAIN1-0 bits = "00"IN1+, IN1-, IN2+, IN2- pin AVDD = |(IN+) - (IN-)| = 0.069 x AVDD (max)@MGAIN1-0 Vin bits = "01", 0.035 x AVDD (max)@MGAIN1-0 bits = "10", 0.017 x AVDD (max)@MGAIN1-0 bits = "11". ADC Note 9. AVDDVout = 0.75 x AVDD (typ) Note 10. AVDDVin = 0.06 x AVDD (typ)@MGAIN1-0 bits = "01" (+20dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = "00" (0dB) Note 11. MGAIN1-0 bits = "01" (+20dB) Note 12. MGAIN1-0 bits = "00" (0dB) MS0605-J-00 MS0605-J-00 2007/06 -7- [AK4645EZ AK4645EZ] min typ max Units Parameter DAC Characteristics: Resolution 16 Bits Stereo Line Output Characteristics: DAC LOUT/ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = "0", LODIF bit = "0", RL=10k (Single-ended); unless otherwise specified. Output Voltage (Note 13) LOVL bit = "0" 1.78 1.98 2.18 Vpp LOVL bit = "1" 2.25 2.50 2.75 Vpp 78 88 dBFS S/(N+D) (-3dBFS) S/N (A-weighted) 82 92 dB Interchannel Isolation 80 100 dB Interchannel Gain Mismatch 0.1 0.5 dB Load Resistance 10 k Load Capacitance 30 pF Mono Line Output Characteristics: DAC LOP/LON pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = "0", LODIF bit = "1", RL=10k for each pin (Full-differential) Output Voltage (Note 14) LOVL bit = "0" 3.52 3.96 4.36 Vpp LOVL bit = "1" 5.00 Vpp 78 88 dBFS S/(N+D) (-3dBFS) S/N (A-weighted) 85 95 dB Load Resistance (LOP/LON pins, respectively) 10 k Load Capacitance (LOP/LON pins, respectively) 30 pF Note 13. AVDDVout = 0.6 x AVDD (typ)@LOVL bit = "0". Note 14. AVDDVout = (LOP) - (LON) = 1.2 x AVDD (typ)@LOVL bit = "0". MS0605-J-00 MS0605-J-00 2007/06 -8- [AK4645EZ AK4645EZ] min typ max Units Parameter Headphone-Amp Characteristics: DAC HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB; VBAT bit = "0"; unless otherwise specified. Output Voltage (Note 15) 1.58 1.98 2.38 Vpp HPG bit = "0", 0dBFS, HVDD=3.3V, RL=22.8 2.40 3.00 3.60 Vpp HPG bit = "1", 0dBFS, HVDD=5V, RL=100 HPG bit = "1", 0dBFS, HVDD=3.3V, RL=16 (Po=62mW) 1.0 Vrms HPG bit = "1", 0dBFS, HVDD=5V, RL=16 (Po=70mW) 1.06 Vrms S/(N+D) 60 70 dBFS HPG bit = "0", -3dBFS, HVDD=3.3V, RL=22.8 80 dBFS HPG bit = "1", -3dBFS, HVDD=5V, RL=100 HPG bit = "1", 0dBFS, HVDD=3.3V, RL=16 (Po=62mW) 20 dBFS HPG bit = "1", 0dBFS, HVDD=5V, RL=16 (Po=70mW) 70 dBFS (Note 16) 80 90 dB S/N (A-weighted) 90 dB (Note 17) (Note 16) 65 75 dB Interchannel Isolation 80 dB (Note 17) (Note 16) 0.1 0.8 dB Interchannel Gain Mismatch 0.1 0.8 dB (Note 17) Load Resistance 16 30 pF Figure 2C1 Load Capacitance 300 pF Figure 2C2 Note 15. AVDD Vout = 0.6 x AVDD(typ)@HPG bit = "0", 0.91 x AVDD(typ)@HPG bit = "1". Note 16. HPG bit = "0", HVDD=3.3V, RL=22.8. Note 17. HPG bit = "1", HVDD=5V, RL=100. HP-Amp HPL/HPR pin Measurement Point 47F 6.8 C1 0.22F C2 16 10 Figure 2. MS0605-J-00 MS0605-J-00 2007/06 -9- [AK4645EZ AK4645EZ] min typ Parameter Mono Input: MIN pin (AIN3 bit = "0"; External Input Resistance=20k) Maximum Input Voltage (Note 18) 1.98 Gain (Note 19) MIN LOUT/ROUT LOVL bit = "0" 0 -4.5 LOVL bit = "1" +2 MIN HPL/HPR HPG bit = "0" -24.5 -20 HPG bit = "1" -16.4 Stereo Input: LIN2/RIN2/LIN4/RIN4 pins; LIN3/RIN3 pins (AIN3 bit = "1") Maximum Input Voltage (Note 20) 1.98 Gain LIN/RIN LOUT/ROUT LOVL bit = "0" 0 -4.5 LOVL bit = "1" +2 LIN/RIN HPL/HPR HPG bit = "0" 0 -4.5 HPG bit = "1" +3.6 Full-differential Mono Input: IN4+/- pins (L4DIF bit = "1") Maximum Input Voltage (Note 21) 3.96 Gain LOVL bit = "0" IN4+/- LOUT/ROUT -10.5 -6 (LODIF bit = "0") LOVL bit = "1" -4 LOVL bit = "0" 0 IN4+/- LOP/LON -4.5 (LODIF bit = "1", Note 22) LOVL bit = "1" +2 HPG bit = "0" IN4+/- HPL/HPR -10.5 -6 HPG bit = "1" -2.4 Power Supplies: Power Up (PDN pin = "H") All Circuit Power-up: AVDD+DVDD+TVDD (Note 23) 16 HVDD: HP-Amp Normal Operation 5 No Output (Note 24) Power Down (PDN pin = "L") (Note 25) AVDD+DVDD+TVDD+HVDD 1 max Units - Vpp +4.5 -15.5 - dB dB dB dB - Vpp +4.5 +4.5 - dB dB dB dB - Vpp -1.5 +4.5 -1.5 - dB dB dB dB dB dB 24 mA 8 mA 100 A Note 18. AVDD(Rin)Vin = 0.6 x AVDD x Rin / 20k (typ). Note 19. Note 20. AVDDVin = 0.6 x AVDD (typ). Note 21. AVDDVin = (IN4+) - (IN4-) = 1.2 x AVDD (typ). IN4+, IN4- pins Note 22. Vout = (LOP) - (LON) at LODIF bit = "1". Note 23. PLL Master Mode (MCKI=12.288MHz)PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = MCKO = PMMIN = PMMP = M/S bits = "1"MPWR pin 0mA AVDD=11mA(typ), DVDD=3mA(typ), TVDD=2mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = "0"): AVDD=10mA(typ), DVDD=3mA(typ), TVDD=0.03mA(typ). Note 24. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN bits = "1" Note 25. TVDDHVSS MS0605-J-00 MS0605-J-00 2007/06 - 10 - [AK4645EZ AK4645EZ] : Ta=25°C; AVDD=DVDD=TVDD=HVDD=3.3V; AVSS=HVSS=0V; fs=44.1kHz, External Slave Mode, BICK=64fs; 1kHz, 0dBFS input; Headphone = No output. PMDAC PMADL PMHPR PMADR PMMICL PMMICR PMAINL2 PMAINR2 PMAINL3 PMAINR3 PMAINL4 PMAINR4 AVDD [mA] DVDD [mA] TVDD [mA] PMHPL HVDD [mA] Total Power [mW] 20H PMLO 10H PMMIN 01H PMVCM 00H Power Management Bit 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.4 3.8 1.9 5.5 3.5 0 1.8 1.8 0 1.6 1.5 0 0.03 0.03 0 0.03 0.03 0 0.2 5 5 0.2 0.2 0 21.2 35.1 22.8 24.2 17.3 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 8.3 2.7 0.03 5 52.9 Mode All Power-down DAC Lineout DAC HP LIN2/RIN2 HP LIN2/RIN2 ADC LIN1 (Mono) ADC LIN2/RIN2 ADC & DAC HP Table 1. Power Consumption for each operation mode (typ) MS0605-J-00 MS0605-J-00 2007/06 - 11 - [AK4645EZ AK4645EZ] (Ta=25°C; AVDD, DVDD=2.6 3.6V; TVDD=1.6 3.6V; HVDD=2.6 5.25V; fs=44.1kHz; DEM=OFF; FIL1=FIL3=EQ=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 26) PB 0 17.3 kHz ±0.16dB 19.4 kHz -0.66dB 19.9 kHz -1.1dB 22.1 kHz -6.9dB Stopband SB 26.1 kHz Passband Ripple PR dB ±0.1 Stopband Attenuation SA 73 dB Group Delay (Note 27) GD 19 1/fs Group Delay Distortion 0 GD s ADC Digital Filter (HPF): (Note 28) Frequency Response (Note 26) -3.0dB FR 0.9 Hz 2.7 Hz -0.5dB 6.0 Hz -0.1dB DAC Digital Filter (LPF): Passband (Note 26) PB 0 19.6 kHz ±0.1dB 20.0 kHz -0.7dB 22.05 kHz -6.0dB Stopband SB 25.2 kHz Passband Ripple PR dB ±0.01 Stopband Attenuation SA 59 dB Group Delay (Note 27) GD 25 1/fs DAC Digital Filter (LPF) + SCF: FR dB Frequency Response: 0 20.0kHz ±1.0 DAC Digital Filter (HPF): (Note 28) Frequency Response (Note 26) -3.0dB FR 0.9 Hz 2.7 Hz -0.5dB 6.0 Hz -0.1dB BOOST Filter: (Note 29) Frequency Response MIN FR 20Hz dB 5.76 100Hz dB 2.92 1kHz dB 0.02 MID FR 20Hz dB 10.80 100Hz dB 6.84 1kHz dB 0.13 MAX 20Hz FR dB 16.06 100Hz dB 10.54 1kHz dB 0.37 Note 26. fs () PB=20.0kHz(@-0.7dB)0.454 x fs(DAC)1kHz Note 27. ADC16 ADC16 DAC16 DAC16 PMADL=PMADR bits = "0"DACGroup Delay25/fs(typ) Note 28. PMADL bit = "1" or PMADR bit = "1"ADCHPFONDACHPFOFF PMADL=PMADR bits = "0", PMDAC bit = "1"DACHPFONADCHPFOFF Note 29. MS0605-J-00 MS0605-J-00 2007/06 - 12 - [AK4645EZ AK4645EZ] DC (Ta=25°C; AVDD, DVDD=2.6 3.6V; TVDD=1.6 3.6V; HVDD=2.6 5.25V) Parameter Symbol min High-Level Input Voltage 2.2VTVDD3.6V VIH 70%TVDD 1.6VTVDD ALC Output -6.0dBFS 0 ALC Output -6.0dBFS -6.0dBFS > ALC Output -8.5dBFS 1 ALC Output -8.5dBFS -8.5dBFS > ALC Output -12dBFS Table 28. ALC LMAT1 LMAT0 ALC ATT 0 0 1 step 0.375dB Default 0 1 2 step 0.750dB 0 1 0 4 step 1.500dB 1 1 8 step 3.000dB 1 x x 1step 0.375dB Table 29. ALC ATT (x: Don't care) ZELMN ZTM1 ZTM0 0 0 1 1 0 1 0 1 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 30. ALC MS0605-J-00 MS0605-J-00 Default 2007/06 - 43 - [AK4645EZ AK4645EZ] 2. ALC ALCWTM2-0(Table 31)ALC (Table 28)ALCALC (Table 33) ZTM1-0 bits(Table 30) RGAIN1-0 bits(Table 32)IVL, IVR(L/R)ALC WTM2-0 bitsWTM2-0 bitsZTM1-0 bits ZTM1-0 bitsALC IVL, IVR30HRGAIN1-0 IVR30HRGAIN1-0 bits = "01"(2 steps)ALC IVL, IVR32H0 IVR32H0.75dB(0.375dB x 2)IVL, IVR (REF7-0 bits)IVL, IVR ALC () Output Signal < () () > Output Signal ALCALC () RFST1-0 bits (Table 34) ALC 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms 2048/fs 256ms 128ms 46.4ms 4096/fs 512ms 256ms 92.9ms 8192/fs 1024ms 512ms 185.8ms 16384/fs 2048ms 1024ms 371.5ms Table 31. ALC WTM2 WTM1 WTM0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 RGAIN1 0 0 1 1 RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 32. ALC MS0605-J-00 MS0605-J-00 Default Default 2007/06 - 44 - [AK4645EZ AK4645EZ] REF7-0 GAIN(dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 0.375dB E1H +30.0 Default E0H +29.625 : : 03H -53.25 02H -53.625 01H -54.0 00H MUTE Table 33. ALC RFST1 bit 0 0 1 1 RFST0 bit 0 4 1 8 0 16 1 N/A Table 34. MS0605-J-00 MS0605-J-00 Default 2007/06 - 45 - [AK4645EZ AK4645EZ] 3. ALC Table 35ALC 35ALC Register Name Comment LMTH1-0 ZELMN ZTM1-0 Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM2-0 bits should be the same or longer data as ZTM1-0 bits. Maximum gain at recovery operation WTM2-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 RFST1-0 ALC Data 01 0 01 fs=8kHz Operation -4.1dBFS Enable 32ms Data 01 0 11 fs=44.1kHz Operation -4.1dBFS Enable 23.2ms Limiter ATT step Recovery GAIN step Fast Recovery Speed ALC enable 32ms 011 23.2ms E1H +30dB E1H +30dB E1H Gain of IVOL 001 +30dB E1H +30dB 1 step 1 step 4 times Enable 00 00 00 1 1 step 1 step 4 times Enable 00 00 00 1 Table 35. ALC ALC ALC(ALC bit = "0"PMADL = PMADR bits = "0") LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0 Example: Limiter = Zero crossing Enable Recovery Cycle = 32ms@8kHz Zero Crossing Timeout Period = 32ms@8kHz Limiter and Recovery Step = 1 Fast Recovery Speed = 4 step Gain of IVOL = +30dB Maximum Gain = +30.0dB Limiter Detection Level = -4.1dBFS ALC bit = "1" Manual Mode WR (ZTM1-0, WTM2-0, RFST1-0) (1) Addr=06H, Data=14H WR (REF7-0) (2) Addr=08H, Data=E1H WR (IVL/R7-0) * The value of IVOL should be (3) Addr=09H&0CH, Data=E1H the same or smaller than REF's WR (RGAIN1, LMTH1) (4) Addr=0BH, Data=00H WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= "1") (5) Addr=07H, Data=21H ALC Operation Note : WR : Write Figure 36. ALC MS0605-J-00 MS0605-J-00 2007/06 - 46 - [AK4645EZ AK4645EZ] () ALC bit = "0" 1. 2. 3. ALC(ZTM1-0, LMTH1-0 bits) ALC IVL7-0, IVR7-0 bits(Table 36)L/R ZTM1-0 bits PMADL = PMADR bits = "0"IVL7-0, IVR7-0 bitsPMADL bit = "1" or PMADR bit = "1"ADCIVOL IVL7-0 = IVR7-0 bits = "91H" (0dB) IVL7-0 GAIN (dB) Step IVR7-0 F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 0.375dB E1H +30.0 Default E0H +29.625 : : 03H -53.25 02H -53.625 01H -54 00H MUTE Table 36. MS0605-J-00 MS0605-J-00 2007/06 - 47 - [AK4645EZ AK4645EZ] IVL7-0, IVR7-0 bits ALC bit ALC Status Disable Enable IVL7-0 bits E1H(+30dB) IVR7-0 bits Disable C6H(+20dB) Internal IVL E1H(+30dB) Internal IVR C6H(+20dB) E1(+30dB) -> F1(+36dB) (1) E1(+30dB) (2) E1(+30dB) -> F1(+36dB) C6H(+20dB) Figure 37. ALCIVOL (1) ALCIVLIVRIVLALC bit = "1" IVL7-0 bitsALC (WTM2-0 bits) + (ZTM1-0 bits) (2) ALCIVL, IVR(09H, 0CH)ALCDisable ALCEnable ALC bit = "0"ALC bit = "1" MS0605-J-00 MS0605-J-00 2007/06 - 48 - [AK4645EZ AK4645EZ] IIR3(32kHz, 44.1kHz, 48kHz)(tc=50/15s) DEM1-0 bits (Table 37) DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF Default 1 0 48kHz 1 1 32kHz Table 37. BST1-0 bitsDAC(Table 38)BST1-0 bits = "01"(MIN)DC47F DC47F DAC Figure 38-20dB Boost Filter (fs=44.1kHz) 0 MAX Level [dB] -5 MID -10 MIN -15 -20 -25 10 100 1000 10000 Frequency [Hz] Figure 38. (fs=44.1kHz) BST1 BST0 Mode 0 0 OFF Default 0 1 MIN 1 0 MID 1 1 MAX Table 38. MS0605-J-00 MS0605-J-00 2007/06 - 49 - [AK4645EZ AK4645EZ] AK4645MUTE0 AK4645MUTE0.5dB 256(DATT) DAC+12dB-115dB DVOLC bit "1"DVL7-0 bitsLch, RchDVOLC bit "0"Lch, RchATT1061 256/fsDVTM bitDVTM bit = "0" 00H(+12dB)FFH(MUTE)1061/fs(24ms@fs=44.1kHz) DVL/R7-0 00H 01H 02H : 18H : FDH FEH FFH DVTM bit 0 1 Gain Step +12.0dB +11.5dB +11.0dB : 0.5dB 0dB : -114.5dB -115.0dB MUTE (-) Table 39. Digital Volume Code Table Default DVL/R7-0 bits = 00HFFH 00HFFH fs=8kHz fs=44.1kHz 1061/fs 133ms 24ms 256/fs 32ms 6ms Table 40. MS0605-J-00 MS0605-J-00 Default 2007/06 - 50 - [AK4645EZ AK4645EZ] DACSMUTE bit SMUTE bit "1"DVTM bit-("0") SMUTE bit "0"- -DVTM bit DVL/R7-0 bitsDVTM bit DVL/R7-0 bits (Figure 39) S M U T E bit D VTM bit D VL/R 7-0 bits D VTM bit (1) (3) A ttenuation - GD (2) GD A nalog O utput Figure 39. (1) DVTM bit-("0") (2) (GD) (3) DVTM bit DVL/R7-0 bits MS0605-J-00 MS0605-J-00 2007/06 - 51 - [AK4645EZ AK4645EZ] : (LIN2/RIN2/LIN4/RIN4 pins, AIN3 bit = "1": LIN3/RIN3 pins) PMAINL2=PMAINR2 bits = "1"LIN2/RIN2 pins LINH2 bitRINH2 bit "1"LINL2 bitRINR2 bit "1" PMAINL4=PMAINR4 bits = "1"LIN4/RIN4 pins LINH4 bitRINH4 bit "1"LINL4 bitRINR4 bit "1" PMADL bitPMADR bit "1"A/D LIN2/RIN2/LIN4/RIN4 pinsMGAIN1-0 bits = "00"typ. 30k MGAIN1-0 bits = "01", "10", "11"typ. 20k AIN3 bit = "1" MIN/VCOC pinsLIN3/RIN3 pins PLL PMAINL3=PMAINR3 bits = "1"LIN3/RIN3 pins PMMICL=PMMICR=MICL3=MICR3 bits = "1"LIN3/RIN3 pins MIC-AmpLINH3 bitRINH3 bit "1" LINL3 bitRINR3 bit "1" PMADL bitPMADR bit "1"A/D LIN3/RIN3 pinsMICL3=MICR3 bits = "0"MGAIN1-0 bits = "00" typ. 30kMGAIN1-0 bits = "01", "10", "11"typ. 20kMICL3=MICR3 bits = "1" MGAIN1-0 bits = "00"typ. 60kMGAIN1-0 bits = "01", "10", "11"typ. 30k (typ)Table 41, Table 42, Table 43 AK4645 AK4645 INL1-0 bits LIN1/IN1- pin ADC Lch RIN1/IN1+ pin MDIF1 bit MIC-Amp INR1-0 bits RIN2/IN2- pin ADC Rch LIN2/IN2+ pin MDIF2 bit MIC-Amp These blocks are not available at PLL mode. MIN/LIN3 pin MICL3 bit MICR3 bit PMAINR2 bit PMAINL2 bit PMAINR4 bit PMAINL4 bit RIN4/IN4- pin PMAINR3 bit LIN4/IN4+ pin PMAINL3 bit VCOC/RIN3 pin Lineout, HP-Amp Figure 40. () MS0605-J-00 MS0605-J-00 2007/06 - 52 - [AK4645EZ AK4645EZ] PMAINL2 bit PMAINR2 bit LINL2/RINR2 LOUT/LOP pin, ROUT/LON pin LIN2/RIN2 LINH2/RINH2 HPL, HPR pins Figure 41. (LIN2/RIN2) PMAINL4 bit PMAINR4 bit LINL4/RINR4 LOUT/LOP pin, ROUT/LON pin LIN4/RIN4 LINH4/RINH4 HPL, HPR pins Figure 42. (LIN4/RIN4) PMAINL3 bit PMAINR3 bit LINL3/RINR3 LOUT/LOP pin, ROUT/LON pin LIN3/RIN3 LINH3/RINH3 HPL, HPR pins Figure 43. (LIN3/RIN3: PLL) LOVL bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 LOUT/ROUT 0 0dB Default 1 +2dB Table 41. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input LOUT/ROUT Output Gain (typ) LOVL bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 LOP/LON 0 0dB Default 1 +2dB Table 42. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input LOP/LON Output Gain (typ) HPG bit LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 HPL/HPR 0 0dB Default 1 +3.6dB Table 43. LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 Input Headphone-Amp Output Gain (typ) MS0605-J-00 MS0605-J-00 2007/06 - 53 - [AK4645EZ AK4645EZ] : (L4DIF bit = "1": IN4+/IN4- pins) L4DIF bit = "1"LIN4, RIN4 pinsIN4+, IN4- pins PMAINL4 bit = "1"IN4+, IN4- pins LINH4 bitRINH4 bit "1"LINL4 bitRINR4 bit "1" (typ)Table 44, Table 45, Table 46(IN4+) - (IN4-) AK4645 AK4645 MIC-Amp Lch LIN4/IN4+ pin L4DIF bit PMAINL4 bit MIC-Amp Rch RIN4/IN4- pin PMAINR4 bit Lineout, HP-Amp Figure 44. Full-differential Mono Analog Mixing Circuit LOVL bit IN4+/IN4- LOUT/ROUT 0 Default -6dB 1 -4dB Table 44. IN4+/IN4- Input LOUT/ROUT Output Gain (typ) LOVL bit IN4+/IN4- LOP/LON 0 0dB Default 1 +2dB Table 45. IN4+/IN4- Input LOP/LON Output Gain (typ) HPG bit IN4+/IN4- HPL/HPR 0 Default -6dB 1 -2.4dB Table 46. IN4+/IN4- Input Headphone-Amp Output Gain (typ) MS0605-J-00 MS0605-J-00 2007/06 - 54 - [AK4645EZ AK4645EZ] : (AIN3 bit = "0": MIN pin) AIN3 bit = "0"MIN pinPMMIN bit = "1" MINH bit "1"MINL bit "1" RiRi = 20k (typ)Table 47, Table 48, Table 49Ri Ri MINL MIN LOUT/LOP pin, ROUT/LON pin MINH HPL, HPR pin Figure 7. Block Diagram of MIN pin LOVL bit MIN LOUT/ROUT 0 0dB Default 1 +2dB Table 47. Ri = 20k MIN LOUT/ROUT(typ) LOVL bit MIN LOP/LON 0 +6dB Default 1 +8dB Table 48. Ri = 20k MIN LOP/LON(typ) HPG bit MIN HPL/HPR 0 Default -20dB 1 -16.4dB Table 49. Ri = 20k MIN (typ) MS0605-J-00 MS0605-J-00 2007/06 - 55 - [AK4645EZ AK4645EZ] (LOUT/ROUT pins) DACL bit "1" DACLch, RchLOUT, ROUT pins DACL bit "0"OFFLOUT, ROUT pinsVCOM min. 10kPMLO=LOPS bits = "0" AVSS 100k(typ)LOPS bit = "1"LOPS bit = "1"PMLO bitON/OFF ON/OFF Figure 46C20k C=1F, AVDD=3.3V 300ms PMLO bit = "1"LOPS bit = "0" LOVL bit LOM bit = "1"DAC[(L+R)/2]LOUT, ROUT pins LOM3 bit = "1"MICL3, MICR3 bits(LIN3/RIN3MIC-Amp)[(L+R)/2] LOUT, ROUT pins "DACL" "LOVL" LOUT pin DAC ROUT pin Figure 45. LOPS 0 1 PMLO Mode LOUT/ROUT pin 0 Pull-down to AVSS 1 0 Fall down to AVSS 1 Rise up to VCOM Table 50. (x: Don't care) Default LOVL Gain (typ) 0 0dB 0.6 x AVDD Default 1 +2dB 0.757 x AVDD Table 51. LOUT ROUT 1F 220 20k Figure 46. () MS0605-J-00 MS0605-J-00 2007/06 - 56 - [AK4645EZ AK4645EZ] () (2 ) (5 ) P M L O b it (1 ) (3 ) (4 ) (6 ) L O P S b it L O U T , R O U T p in s N o r m a l O u tp u t 300 m s 300 m s Figure 47. () (1) ON LOPS bit = "1" (2) PMLO bit = "1" LOUT, ROUT pins C=1F, AVDD=3.3V200ms (max 300ms) (3) LOUT, ROUT pins LOPS bit = "0" (4) ON LOPS bit = "1" (5) PMLO bit = "0" LOUT, ROUT pins C=1F, AVDD=3.3V200ms (max 300ms) (6) LOUT, ROUT pins LOPS bit = "0" MS0605-J-00 MS0605-J-00 2007/06 - 57 - [AK4645EZ AK4645EZ] AIN3 bit = "0"ON/OFFDACL, MINL, LINL2, RINR2, LINL4, RINR4 bits MIN20k0dB(typ)@LOVL bit = "0" LIN2/RIN2/LIN4/RIN4/DAC0dB(typ)@LOVL bit = "0" LINL2 bit LIN2 pin 0dB LINL4 bit LIN4 pin M 0dB MINL bit MIN pin 0dB I LOUT pin X DACL bit DAC Lch 0dB Figure 48. LOUT(AIN3 bit = "0", LOVL bit = "0") RINR2 bit RIN2 pin 0dB RINR4 bit RIN4 pin M 0dB MINL bit MIN pin 0dB I ROUT pin X DACL bit DAC Rch 0dB Figure 49. ROUT(AIN3 bit = "0", LOVL bit = "0") MS0605-J-00 MS0605-J-00 2007/06 - 58 - [AK4645EZ AK4645EZ] AIN3 bit = "1" ON/OFFDACL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, MICL3, MICR3 bits0dB(typ) @LOVL bit = "0" LINL2 bit LIN2 pin 0dB LINL4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINL3 bit I 0dB MIC-Amp Lch M *These blocks are not available at PLL mode. LOUT pin X DACL bit DAC Lch 0dB Figure 50. LOUT(AIN3 bit = "1", LOVL bit = "0") RINR2 bit RIN2 pin 0dB RINR4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RIN1 pin RINR3 bit I 0dB MIC-Amp Rch M *These blocks are not available at PLL mode. ROUT pin X DACL bit DAC Rch 0dB Figure 51. ROUT(AIN3 bit = "1", LOVL bit = "0") MS0605-J-00 MS0605-J-00 2007/06 - 59 - [AK4645EZ AK4645EZ] (LOP/LON pins) LODIF bit = "1" LOUT/ROUT pins LOP/LON pins DAC LIN2/RIN2/LIN3/RIN3/LIN4/RIN4[(L+R)/2]LOP/LON pins min. 10kPMLO bit = "0" LOP/LON pinsHi-ZPMLO bit = "1", LOPS bit = "1" PMLO bit = "1", LOPS bit = "0"LOVL bit L4DIF=LODIF bits = "1"(LOP) - (LON) = (IN4+) - (IN4-) "DACL" "LOVL" LOP pin DAC LON pin Figure 52. Mono Line Output PMLO 0 1 LOPS Mode LOP LON x Power-down Hi-Z Hi-Z 1 Power-save Hi-Z VCOM 0 Normal Operation Normal Operation Normal Operation Table 52. Mono Line Output Mode Setting (x: Don't care) LOVL 0 1 Default Gain Output Voltage (typ) +6dB 1.2 x AVDD Default +8dB 1.5 x AVDD Table 53. Mono Line Output Volume Setting PMLO bit LOPS bit LOP pin LON pin Hi-Z Hi-Z Hi-Z VCOM VCOM Hi-Z Figure 53. Power-up/Power-down Timing for Mono Line Output MS0605-J-00 MS0605-J-00 2007/06 - 60 - [AK4645EZ AK4645EZ] AIN3 bit = "0"ON/OFFDACL, MINL, LINL2, RINR2, LINL4, RINR4 bits MIN20k+6dB(typ)@LOVL bit = "0" LIN2/RIN2/LIN4/RIN4/DAC0dB(typ)@LOVL bit = "0" LINL2 bit LIN2 pin 0dB RINR2 bit RIN2 pin 0dB LINL4 bit LIN4 pin 0dB M RINR4 bit RIN4 pin LOP/N pin I 0dB X MINL bit MIN pin +6dB DACL bit DAC Lch 0dB DACL bit DAC Rch 0dB Figure 54. (AIN3 bit = "0", LOVL bit = "0") AIN3 bit = "1" ON/OFFDACL, LINL2, RINR2, LINL3, RINR3, LINL4, RINR4, MICL3, MICR3 bits0dB(typ)@LOVL bit = "0" LINL2 bit LIN2 pin 0dB LINL4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINL3 bit 0dB MIC-Amp Lch *These blocks are not available at PLL mode. RINR2 bit RIN2 pin M 0dB RINR4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RIN1 pin I LOP/N pin X RINR3 bit 0dB MIC-Amp Rch *These blocks are not available at PLL mode. DACL bit DAC Lch 0dB DAC Rch 0dB DACL bit Figure 55. (AIN3 bit = "1", LOVL bit = "0") MS0605-J-00 MS0605-J-00 2007/06 - 61 - [AK4645EZ AK4645EZ] (HPL/HPR pins) HVDDHVDD/2@VBAT bit = "0" 16 (min)HPG bit(Table 54) HPM bit = "1"DAC[(L+R)/2]HPL, HPR pins HPM3 bit = "1"MICL3, MICR3 bits(LIN3/RIN3MIC-Amp)[(L+R)/2] HPL, HPR pins HPG bit Output Voltage [Vpp] 0 0.6 x AVDD Table 54. 1 0.91 x AVDD HPMTN bit "0"HVSSHPMTN bit "1" HVDD/2@VBAT bit = "0"MUTET pin HVDDMUTET pin : MUTET pinC=1F, HVDD=3.3V : 100ms(typ), 250ms(max) : 500ms(max) PMHPL, PMHPR bits "0" HPL, HPR pins "L" (HVSS) PMHPL bit, PMHPR bit HPMTN bit HPL pin, HPR pin (1) (2) (3) (4) Figure 56. (1) (PMHPL, PMHPR bits = "1")HVSS (2) (HPMTN bit = "1") (3) (HPMTN bit = "0") (4) (PMHPL, PMHPR bits = "0")HVSS BOOST=OFF(fc) Table 55 (fc)RL16 HVDD=3.0, 3.3, 5V0.6 x AVDD (Vpp)@HPG bit = "0", 0.91 x AVDD (Vpp)@HPG bit = "1" R12 (0.22F±20%10±20%) MS0605-J-00 MS0605-J-00 2007/06 - 62 - [AK4645EZ AK4645EZ] HP-AMP C AK4645 AK4645 0.22 R Headphone 16 10 Figure 57. HPG bit R [] 0 0 6.8 16 0 1 100 Output Power [mW]@0dBFS fc [Hz] BOOST C [F] HVDD=3.0V HVDD=3.3V HVDD=5V =MIN AVDD=3.0V AVDD=3.3V AVDD=3.3V fs=44.1kHz 220 45 17 25.3 30.6 30.6 100 100 43 100 70 28 12.5 15.1 15.1 47 149 78 100 50 19 6.3 7.7 7.7 47 106 47 62 51 220 45 17 70 (Note 42) (Note 42) 100 100 43 22 62 25 1.1 1.3 1.3 10 137 69 Table 55. Note 41. 16 Note 42. fc [Hz] BOOST =OFF PSRR HVDDRF VBAT bit = "1"HVDD PSRR0.64 x AVDD(typ)AVDD=3.3V2.1VHVDD4.2V VBAT bit 0 1 Common Voltage [V] 0.5 x HVDD 0.64 x AVDD Table 56. Wired OR PMVCM=PMHPL=PMHPR bits = "0", HPZ bit = "1"HP-AmpHPL, HPR pins 200k(typ)HVSSAK4645HP-AmpHP-AmpWired OR20A OR20A(typ) PMVCM x 0 1 1 PMHPL/R 0 0 1 1 HPMTN HPZ Mode x 0 Power-down & Mute x 1 Power-down 0 x Mute 1 x Normal Operation Table 57. HP-Amp Mode Setting (x: Don't care) MS0605-J-00 MS0605-J-00 HPL/R pins HVSS Pull-down by 200k HVSS Normal Operation Default 2007/06 - 63 - [AK4645EZ AK4645EZ] HPL pin AK4645 AK4645 Headphone HPR pin Another HP-Amp Figure 58. Wired OR AIN3 bit = "0"ON/OFFDACH, MINH, LINH2, RINH2, LINH4, RINH4 bits MIN20k-20dB(typ)@HPG bit = "0" LIN2/RIN2/LIN4/RIN4/DAC0dB(typ)@HPG bit = "0" LINH2 bit LIN2 pin 0dB LIN4 pin 0dB LINH4 bit M MINH bit -20dB MIN pin I HPL pin X DACH bit DAC Lch 0dB Figure 59. HPL(AIN3 bit = "0", HPG bit = "0") RINH2 bit RIN2 pin 0dB RIN4 pin 0dB RINH4 bit M MINH bit -20dB MIN pin I HPR pin X DACH bit DAC Rch 0dB Figure 60. HPR(AIN3 bit = "0", HPG bit = "0") MS0605-J-00 MS0605-J-00 2007/06 - 64 - [AK4645EZ AK4645EZ] AIN3 bit = "1"ON/OFFDACH, LINH2, RINH2, LINH3, RINH3, LINH4, RINH4, MICL3, MICR3 bits0dB(typ) @HPG bit = "0" LINH2 bit LIN2 pin 0dB LINH4 bit LIN4 pin 0dB MICL3 bit LIN3 pin LIN1 pin LINH3 bit I 0dB MIC-Amp Lch M *These blocks are not available at PLL mode. HPL pin X DACH bit DAC Lch 0dB Figure 61. HPL(AIN3 bit = "1", HPG bit = "0") RINH2 bit RIN2 pin 0dB RINH4 bit RIN4 pin 0dB MICR3 bit RIN3 pin RIN1 pin RINH3 bit I 0dB MIC-Amp Rch M *These blocks are not available at PLL mode. HPR pin X DACH bit DAC Rch 0dB Figure 62. HPR(AIN3 bit = "1", HPG bit = "0") MS0605-J-00 MS0605-J-00 2007/06 - 65 - [AK4645EZ AK4645EZ] (1) 3 (I2C pin = "L") 3I/F(CSN, CCLK, CDTI) I/FChip address (1bit, "1"), Read/Write (1bit, "1"), Register address (MSB first, 6bits) Control Data (MSB first, 8bits) CCLK "" "" CSN ""16CCLK 16CCLK ""1CSN "H" CCLK5MHz (max)PDN pin = "L" CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK Clock, "H" or "L" CDTI "H" or "L" Clock, "H" or "L" C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 "1" "1" C1: R/W: A5-A0: D7-D0: "H" or "L" Chip Address; Fixed to "1" READ/WRITE ("1": WRITE, "0": READ); Fixed to "1" Register Address Control data Figure 63. MS0605-J-00 MS0605-J-00 2007/06 - 66 - [AK4645EZ AK4645EZ] (2) I2C (I2C pin = "H") AK4645I2C AK4645I2C(max:400kHz)SDA, SCL pins (TVDD+0.3)V (2)-1. WRITE I2CFigure 64IC (Start Condition)SCL "H"SDA "H" "L" (Figure 70)7 8(R/W)6 "001001"1 ICCAD0 pin(Figure 65) AK4645 AK4645(Acknowledge) SDA(Figure 71)R/W bit "0" R/W bit "1" 2()8MSB first2 "0"(Figure 66)38 MSB first(Figure 67)AK4645 AK4645 (Stop Condition)SCL "H" SDA "L" "H"(Figure 70) AK46451 AK46451 "24H" "00H" "H"SDA "H" "L" SCL "L"(Figure 72)SCL "H" SDA S T A R T SDA S T O P R/W="0" Slave S Address Sub Address(n) A C K Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 64. I2C 0 0 1 0 0 1 CAD0 R/W A2 A1 A0 D1 D0 (CAD0) Figure 65. 1 0 0 A5 A4 A3 Figure 66. 2 D7 D6 D5 D4 D3 D2 Figure 67. 3 MS0605-J-00 MS0605-J-00 2007/06 - 67 - [AK4645EZ AK4645EZ] (2)-2. READ R/W bit "1"AK4645READ AK4645READ "24H" "00H" AK46452READ AK46452READ (2)-2-1. AK4645 AK4645 (READWRITE) "n" "n+1" AK4645READ AK4645READ(R/W bit = "1") 1 READ S T A R T SDA S T O P R/W="1" Slave S Address Data(n) A C K Data(n+1) Data(n+2) A C K A C K Data(n+x) A C K A C K P A C K Figure 68. (2)-2-2. READ(R/W bit = "1")WRITE WRITE(R/W bit = "0")AK4645 AK4645 READ(R/W bit= "1")AK4645 AK4645 1 READ S T A R T SDA S T A R T R/W="0" Slave S Address Slave S Address Sub Address(n) A C K A C K S T O P R/W="1" Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 69. MS0605-J-00 MS0605-J-00 2007/06 - 68 - [AK4645EZ AK4645EZ] SDA SCL S P start condition stop condition Figure 70. DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 71. I2C SDA SCL data line stable; data valid change of data allowed Figure 72. I2C MS0605-J-00 MS0605-J-00 2007/06 - 69 - [AK4645EZ AK4645EZ] Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Power Management 4 Mode Control 5 Lineout Mixing Select HP Mixing Select Reserved D7 0 HPZ 0 LOVL PLL3 PS1 DVTM 0 REF7 IVL7 DVL7 RGAIN1 IVR7 DVR7 0 0 INR1 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQA15 EQB7 0 EQC7 EQC15 EQC15 F1A7 F1AS F1B7 0 D6 PLL1 FS3 ZTM1 ALC REF5 IVL5 DVL5 0 IVR5 DVR5 SMUTE 0 HPG 0 F3A5 F3A13 F3A13 F3B5 F3B13 F3B13 EQA5 EQA13 EQA13 EQB5 EQB13 EQB13 EQC5 EQC13 EQC13 F1A5 F1A13 F1A13 F1B5 F1B13 F1B13 D4 0 PMHPR DACL 0 PLL0 MSBS ZTM0 ZELMN REF4 IVL4 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3A12 F3B4 F3B12 F3B12 EQA4 EQA12 EQA12 EQB4 EQB12 EQB12 EQC4 EQC12 EQC12 F1A4 F1A12 F1A12 F1B4 F1B12 F1B12 D3 PMLO M/S 0 0 BCKO BCKP WTM1 LMAT1 REF3 IVL3 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3A11 F3B3 F3B11 F3B11 EQA3 EQA11 EQA11 EQB3 EQB11 EQB11 EQC3 EQC11 EQC11 F1A3 F1A11 F1A11 F1B3 F1B11 F1B11 D2 PMDAC 0 PMMP MINL 0 FS2 WTM0 LMAT0 REF2 IVL2 DVL2 0 IVR2 DVR2 BST0 HPM INR0 FIL3 F3A2 F3A10 F3A10 F3B2 F3B10 F3B10 EQA2 EQA10 EQA10 EQB2 EQB10 EQB10 EQC2 EQC10 EQC10 F1A2 F1A10 F1A10 F1B2 F1B10 F1B10 D1 0 MCKO 0 0 DIF1 FS1 RFST1 RGAIN0 REF1 IVL1 DVL1 VBAT IVR1 DVR1 DEM1 MINH INL0 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 HPMTN 0 LOPS PLL2 PS0 WTM2 0 REF6 IVL6 DVL6 LMTH1 IVR6 DVR6 LOOP 0 INL1 GN0 F3A6 0 F3B6 0 EQA6 EQA14 EQA14 EQB6 0 EQC6 EQC14 EQC14 F1A6 0 F1B6 0 0 DIF0 FS0 RFST0 LMTH0 REF0 IVL0 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 PMAINR4 0 LOM 0 0 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 0 LOM3 HPM3 0 MICR3 RINR4 RINH4 0 MICL3 LINL4 LINH4 0 L4DIF RINR3 RINH3 0 MIX LINL3 LINH3 0 AIN3 RINR2 RINH2 0 LODIF PMVCM D5 PMMIN PMHPL 0 MGAIN1 D0 PMADL PMPLL MGAIN0 LINL2 LINH2 0 Note 43. PDN pin "L" Note 44. "0" "1" MS0605-J-00 MS0605-J-00 2007/06 - 70 - [AK4645EZ AK4645EZ] Addr 00H Register Name Power Management 1 Default D7 0 0 D6 PMVCM 0 D5 PMMIN 0 D4 0 0 D3 PMLO 0 D2 PMDAC 0 D1 0 0 D0 PMADL 0 PMADL: MIC-Amp Lch, ADC Lch 0: Power down (Default) 1: Power up PMADLPMADR bit "0" "1"(1059/fs=24ms@44.1kHz) ADC PMDAC: DAC 0: Power down (Default) 1: Power up PMLO: 0: Power down (Default) 1: Power up PMMIN: 0: Power down (Default) 1: Power up PMMIN or PMAINL3 bit = "1" PMVCM: VCOM 0: Power down (Default) 1: Power up PMVCM bit"1"PMVCM bit "0" 00H, 01H, 02H, 10H, 20H MCKO bit"0" ON/OFF ("1"/"0") PDN pin"L" 00H, 01H, 02H, 10H, 20HMCKO 20HMCKO bit"0" 20A(typ)(typ. 1A)PDN pin = "L" ADCDAC ADCDAC MS0605-J-00 MS0605-J-00 2007/06 - 71 - [AK4645EZ AK4645EZ] Addr 01H Register Name Power Management 2 Default D7 HPZ 0 D6 HPMTN 0 D5 PMHPL 0 D4 PMHPR 0 D3 M/S 0 D2 0 0 D1 MCKO 0 D4 DACL 0 D3 0 0 D2 PMMP 0 D1 0 0 D0 PMPLL 0 PMPLL: PLL 0: EXT Mode and Power Down (Default) 1: PLL Mode and Power up MCKO: MCKO 0: Disable: MCKO pin = "L" (Default) 1: Enable: Output frequency is selected by PS1-0 bits. M/S: Master / Slave Mode 0: Slave Mode (Default) 1: Master Mode PMHPR: Rch 0: Power down (Default) 1: Power up PMHPL: Lch 0: Power down (Default) 1: Power up HPMTN: 0: Mute (Default) 1: Normal operation HPZ: HP-Amp 0: (Default) 1: 200k(typ) Addr 02H Register Name Signal Select 1 Default D7 0 0 D6 0 0 D5 0 0 D0 MGAIN0 1 MGAIN1-0: (Table 23) MGAIN1 bit03HD5 bit PMMP: MPWR pin 0: Power down: Hi-Z (Default) 1: Power up DACL: DAC 0: OFF (Default) 1: ON PMLO bit = "1"PMLO bit = "0"LOUT, ROUT pinsAVSS MS0605-J-00 MS0605-J-00 2007/06 - 72 - [AK4645EZ AK4645EZ] Addr 03H Register Name Signal Select 2 Default D7 LOVL 0 D6 LOPS 0 D5 D4 0 0 MGAIN1 0 D3 0 0 D2 MINL 0 D1 0 0 D0 0 0 MINL: MIN 0: OFF (Default) 1: ON PMLO bit = "1"PMLO bit = "0"LOUT, ROUT pinsAVSS MGAIN1: (Table 23) LOPS: 0: Normal Operation (Default) 1: Power Save Mode LOVL: /(Table 51, Table 53) 0: 0dB/+6dB (Default) 1: +2dB/+8dB Addr 04H Register Name Mode Control 1 Default D7 PLL3 0 D6 PLL2 0 D5 PLL1 0 D4 PLL0 0 D3 BCKO 0 D2 0 0 D1 DIF1 1 D0 DIF0 0 D4 MSBS 0 D3 BCKP 0 D2 FS2 0 D1 FS1 0 D0 FS0 0 DIF1-0: (Table 17) Default: "10" () BCKO: BICK (Table 11) PLL3-0: PLL(Table 5) Default: "0000" (LRCK pin) Addr 05H Register Name Mode Control 2 Default D7 PS1 0 D6 PS0 0 D5 FS3 0 FS3-0: (Table 6 and Table 7)MCKI(Table 12) PLLEXTMCKI BCKP: DSP ModeBICK (Table 18) "0": ""SDTO, ""SDTI(Default) "1": ""SDTO, ""SDTI MSBS: DSP ModeLRCK (Table 18) "0": LRCK ""BICK (Default) "1": LRCK ""BICK 1 PS1-0: MCKO(Table 10) Default: "00" (256fs) MS0605-J-00 MS0605-J-00 2007/06 - 73 - [AK4645EZ AK4645EZ] Addr 06H Register Name Timer Select Default D7 DVTM 0 D6 WTM2 0 D5 ZTM1 0 D4 ZTM0 0 D3 WTM1 0 D2 WTM0 0 D1 RFST1 0 D0 RFST0 0 RFST1-0: ALC(Table 34) Default: "00"(4) WTM2-0: ALC(Table 31) ALC "000" (128/fs) ZTM1-0: ALC(Table 30) ALC "00" (128/fs) DVTM: Digital Volume(Table 40) 0: 1061/fs (Default) 1: 256/fs DVL7-0, DVR7-0 bits 00HFFH 00HFFH Addr 07H Register Name ALC Mode Control 1 Default D7 0 0 D6 0 0 D5 ALC 0 D4 ZELMN 0 D3 LMAT1 0 D2 LMAT0 0 D1 0 D0 LMTH0 0 D1 REF1 0 D0 REF0 1 RGAIN0 LMTH1-0: ALC/(Table 28) Default: "00" LMTH1 bit0BHD6 bit RGAIN1-0: ALC(Table 32) Default: "00" RGAIN1 bit0BHD7 bit LMAT1-0: ALCATT(Table 29) Default: "00" ZELMN: ALC 0: Enable (Default) 1: Disable ALC: ALC 0: ALC Disable (Default) 1: ALC Enable Addr 08H Register Name ALC Mode Control 2 Default D7 REF7 1 D6 REF6 1 D5 REF5 1 D4 REF4 0 D3 REF3 0 D2 REF2 0 REF7-0: ALC0.375dB step, 242 Level (Table 33) Default: "E1H" (+30.0dB) MS0605-J-00 MS0605-J-00 2007/06 - 74 - [AK4645EZ AK4645EZ] Addr 09H 0CH Register Name Lch Input Volume Control Rch Input Volume Control Default D7 IVL7 IVR7 1 D6 IVL6 IVR6 1 D5 IVL5 IVR5 1 D4 IVL4 IVR4 0 D3 IVL3 IVR3 0 D2 IVL2 IVR2 0 D1 IVL1 IVR1 0 D0 IVL0 IVR0 1 IVL7-0, IVR7-0: ; 0.375dB step, 242 Level (Table 36) Default: "E1H" (+30.0dB) Addr 0AH 0DH Register Name Lch Digital Volume Control Rch Digital Volume Control Default D7 DVL7 DVR7 0 D6 DVL6 DVR6 0 D5 DVL5 DVR5 0 D4 DVL4 DVR4 1 D3 DVL3 DVR3 1 D2 DVL2 DVR2 0 D1 DVL1 DVR1 0 D0 DVL0 DVR0 0 D4 0 0 D3 0 0 D2 0 0 D1 VBAT 0 D0 0 0 D1 DEM1 0 D0 DEM0 1 DVL7-0, DVR7-0: (Table 39) Default: "18H" (0dB) Addr 0BH Register Name ALC Mode Control 3 Default D7 RGAIN1 0 D6 LMTH1 0 D5 0 0 VBAT: (Table 56) 0: 0.5 x HVDD (Default) 1: 0.64 x AVDD LMTH1: ALC/(Table 28) RGAIN1: ALC(Table 32) Addr 0EH Register Name Mode Control 3 Default D7 0 0 D6 LOOP 0 D5 SMUTE 0 D4 DVOLC 1 D3 BST1 0 D2 BST0 0 DEM1-0: (Table 37) Default: "01" (OFF) BST1-0: (Table 38) Default: "00" (OFF) DVOLC: 0: Independent 1: Dependent (Default) DVOLC bit = "1"DVL7-0 bit DVR7-0 bitDVL7-0 bit SMUTE: 0: Normal Operation (Default) 1: DAC outputs soft-muted LOOP: 0: SDTI DAC (Default) 1: SDTO DAC MS0605-J-00 MS0605-J-00 2007/06 - 75 - [AK4645EZ AK4645EZ] Addr 0FH Register Name Mode Control 4 Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 IVOLC 1 D2 HPM 0 D1 MINH 0 D0 DACH 0 DACH: DAC 0: OFF (Default) 1: ON MINH: MIN pin 0: OFF (Default) 1: ON HPM: 0: (Default) 1: HPM bit = "1"DAC(L+R)/2 IVOLC: IVOL 0: Independent 1: Dependent (Default) IVOLC bit = "1"IVL7-0 bitIVOLIVR7-0 bitIVL7-0 bit Addr 10H Register Name Power Management 3 Default D7 INR1 0 D6 INL1 0 D5 HPG 0 D4 MDIF2 0 D3 MDIF1 0 D2 INR0 0 D1 INL0 0 D0 PMADR 0 PMADR: MIC-Amp Rch, ADC Rch 0: Power down (Default) 1: Power up INL1-0: ADC Lch(Table 20) Default: 00 (LIN1 pin) INR1-0: ADC Rch(Table 20) Default: 00 (RIN1 pin) MDIF1: /1 0: (LIN1/RIN1 pin: Default) 1: (IN1+/IN1- pin) Pin#32#31 MDIF2: /2 0: (LIN2/RIN2 pin: Default) 1: (IN2+/IN2- pin) Pin#30#29 HPG: (Table 54) 0: 0dB (Default) 1: +3.6dB MS0605-J-00 MS0605-J-00 2007/06 - 76 - [AK4645EZ AK4645EZ] Addr 11H Register Name Digital Filter Select Default D7 GN1 0 D6 GN0 0 D5 0 0 D4 FIL1 0 D3 EQ 0 D2 FIL3 0 D1 0 0 D0 0 0 GN1-0: Gain(Table 26) Default: "00" (0dB) FIL3: FIL3 0: (Default) 1: FIL3 bit = "1"F3A13-0 F3A13-0, F3B13-0 F3B13-0 bitFIL3 bit = "0"FIL3 OFF(MUTE) EQ: 0: (Default) 1: EQ bit = "1"EQA15-0 EQA15-0, EQB13-0 EQB13-0, EQC15-0 EQC15-0 bitEQ bit = "0" EQ(0dB) FIL1: FIL1 0: (Default) 1: FIL1 bit = "1"F1A13-0 F1A13-0, F1B13-0 F1B13-0 bitFIL1 bit = "0"FIL1 (0dB) Addr 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Default D7 F3A7 F3AS F3B7 0 EQA7 EQA15 EQA15 EQB7 0 EQC7 EQC15 EQC15 F1A7 F1AS F1B7 0 0 D6 F3A6 0 F3B6 0 EQA6 EQA14 EQA14 EQB6 0 EQC6 EQC14 EQC14 F1A6 0 F1B6 0 0 D5 F3A5 F3A13 F3A13 F3B5 F3B13 F3B13 EQA5 EQA13 EQA13 EQB5 EQB13 EQB13 EQC5 EQC13 EQC13 F1A5 F1A13 F1A13 F1B5 F1B13 F1B13 0 D4 F3A4 F3A12 F3A12 F3B4 F3B12 F3B12 EQA4 EQA12 EQA12 EQB4 EQB12 EQB12 EQC4 EQC12 EQC12 F1A4 F1A12 F1A12 F1B4 F1B12 F1B12 0 D3 F3A3 F3A11 F3A11 F3B3 F3B11 F3B11 EQA3 EQA11 EQA11 EQB3 EQB11 EQB11 EQC3 EQC11 EQC11 F1A3 F1A11 F1A11 F1B3 F1B11 F1B11 0 D2 F3A2 F3A10 F3A10 F3B2 F3B10 F3B10 EQA2 EQA10 EQA10 EQB2 EQB10 EQB10 EQC2 EQC10 EQC10 F1A2 F1A10 F1A10 F1B2 F1B10 F1B10 0 D1 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 0 D0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 0 F3A13-0 F3A13-0, F3B13-0 F3B13-0: FIL3(14bit x 2) Default: "0000H 0000H" F3AS: FIL3 0: HPF (Default) 1: LPF EQA15-0 EQA15-0, EQB13-0 EQB13-0, EQC15-C0 EQC15-C0: (14bit x 2 + 16bit x 1) Default: "0000H 0000H" F1A13-0 F1A13-0, F1B13-B0 F1B13-B0: FIL1(14bit x 2) Default: "0000H 0000H" F1AS: FIL1 0: HPF (Default) 1: LPF MS0605-J-00 MS0605-J-00 2007/06 - 77 - [AK4645EZ AK4645EZ] Addr 20H Register Name Power Management 4 Default D7 D6 D5 D4 D3 D2 D1 D0 PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 0 0 0 0 0 0 0 0 PMMICL: MIC-Amp Lch 0: Power down (Default) 1: Power up PMMICR: MIC-Amp Rch 0: Power down (Default) 1: Power up PMAINL2: LIN2 0: Power down (Default) 1: Power up PMAINR2: RIN2 0: Power down (Default) 1: Power up PMAINL3: LIN3 0: Power down (Default) 1: Power up PMMIN or PMAINL3 bit = "1" PMAINR3: RIN3 0: Power down (Default) 1: Power up PMAINL4: LIN4 0: Power down (Default) 1: Power up PMAINR4: RIN4 0: Power down (Default) 1: Power up MS0605-J-00 MS0605-J-00 2007/06 - 78 - [AK4645EZ AK4645EZ] Addr 21H Register Name Mode Control 5 Default D7 0 0 D6 0 0 D5 MICR3 0 D4 MICL3 0 D3 L4DIF 0 D2 MIX 0 D1 AIN3 0 D0 LODIF 0 LODIF: 0: (LOUT/ROUT pins) (Default) 1: (LOP/LON pins) AIN3: 0: (MIN pin) (Default) 1: (LIN3/RIN3 pins): PLL MIX: 0: (Default) 1: : (L+R)/2 L4DIF: 0: : LIN4/RIN4 pins (Default) 1: : IN4+/- pins MICL3: 0: LIN3 pin (Default) 1: MIC-Amp Lch MICR3: 0: RIN3 pin (Default) 1: MIC-Amp Rch MS0605-J-00 MS0605-J-00 2007/06 - 79 - [AK4645EZ AK4645EZ] Addr 22H Register Name Lineout Mixing Select Default D7 LOM 0 D6 LOM3 0 D5 RINR4 0 D4 LINL4 0 D3 RINR3 0 D2 LINL3 0 D1 RINR2 0 D0 LINL2 0 LINL2: LIN2(MIC-Amp) 0: OFF (Default) 1: ON RINR2: RIN2(MIC-Amp) 0: OFF (Default) 1: ON LINL3: LIN3 (or MIC-Amp Lch) 0: OFF (Default) 1: ON RINR3: RIN3 (or MIC-Amp Rch) 0: OFF (Default) 1: ON LINL4: LIN4(MIC-Amp) 0: OFF (Default) 1: ON RINR4: RIN4(MIC-Amp) 0: OFF (Default) 1: ON LOM3: MIC-Amp (or LIN3/RIN3) 0: Stereo Mixing (Default) 1: Mono Mixing LOM: DAC 0: Stereo Mixing (Default) 1: Mono Mixing MS0605-J-00 MS0605-J-00 2007/06 - 80 - [AK4645EZ AK4645EZ] Addr 23H Register Name HP Mixing Select Default D7 0 0 D6 HPM3 0 D5 RINH4 0 D4 LINH4 0 D3 RINH3 0 D2 LINH3 0 D1 RINH2 0 D0 LINH2 0 LINH2: LIN2(MIC-Amp) 0: OFF (Default) 1: ON RINH2: RIN2(MIC-Amp) 0: OFF (Default) 1: ON LINH3: LIN3 (or MIC-Amp Lch) 0: OFF (Default) 1: ON RINH3: RIN3 (or MIC-Amp Rch) 0: OFF (Default) 1: ON LINH4: LIN4(MIC-Amp) 0: OFF (Default) 1: ON RINH4: RIN4(MIC-Amp) 0: OFF (Default) 1: ON HPM3: MIC-Amp (or LIN3/RIN3) 0: Stereo Mixing (Default) 1: Mono Mixing MS0605-J-00 MS0605-J-00 2007/06 - 81 - [AK4645EZ AK4645EZ] Figure 73Figure 74(AKD4645 AKD4645) Headphone 47u 10 10 0.22u 6.8 47u 10u 6.8 Power Supply 2.6 3.6V Power Supply 1.6 3.6V 10 0.22u 17 18 MCKO 0.1u MCKI 19 HVSS 20 HVDD 0.1u 21 22 HPR Line In MUTET 23 RIN4 External SPK-Amp HPL 24 1u 25 LIN4 TVDD 16 26 ROUT DVDD 15 27 LOUT BICK 14 Speaker 0.1u DSP 28 MIN LRCK 13 Top View SDTO 12 30 LIN2 SDTI 11 31 LIN1 CDTI 10 32 RIN1 External MIC AK4645EZ AK4645EZ 29 RIN2 Mono In CCLK 9 I2C PDN CSN 7 8 5 6 VCOC AVDD 4 P Rp AVSS 3 2.2u 0.1u VCOM 2 MPWR 1 0.1u 2.2k 2.2k 2.2k 2.2k Internal MIC Cp Analog Ground Digital Ground : - AK4645AVSS AK4645AVSS, HVSS - - EXT(PMPLL bit = "0") VCOC/RIN3 pin - PLL(PMPLL bit = "1") CpRpTable 5 - M/S bit "1"AK4645LRCK AK4645LRCK, BICK pin AK4645LRCK AK4645LRCK, BICK pin100k - 0.1F - AVDD10DVDDDVDD AVDD10DVDDDVDD 0.1F Figure 73. (AIN3 bit = "0", ) MS0605-J-00 MS0605-J-00 2007/06 - 82 - [AK4645EZ AK4645EZ] Headphone 47u 10 10 0.22u 6.8 47u 10u 6.8 Power Supply 2.6 3.6V Power Supply 1.6 3.6V 10 0.22u 17 18 MCKO 0.1u MCKI 19 20 HVDD HVSS 21 HPR 22 MUTET 23 Line In HPL RIN4 24 20k 20k 0.1u 1u 25 LIN4 200 Line Out 1u 200 1u TVDD 16 26 ROUT DVDD 15 27 LOUT BICK 14 0.1u DSP 10 9 0.1u VCOM 2 2.2u 0.1u 1 P 8 CCLK CSN 32 RIN1 PDN CDTI 7 31 LIN1 I2C 11 6 SDTI RIN3 30 LIN2 5 12 AVDD SDTO 4 Top View AVSS 13 MPWR LRCK 29 RIN2 Line In AK4645EZ AK4645EZ 3 28 LIN3 Analog Ground Digital Ground : - AK4645AVSS AK4645AVSS, HVSS - - M/S bit "1"AK4645LRCK AK4645LRCK, BICK pin AK4645LRCK AK4645LRCK, BICK pin100k - 0.1F - AVDD10DVDDDVDD AVDD10DVDDDVDD 0.1F Figure 74. (AIN3 bit = "1": PLL, ) MS0605-J-00 MS0605-J-00 2007/06 - 83 - [AK4645EZ AK4645EZ] 1. AVDD, DVDD, TVDD, HVDD AVDD, DVDD, TVDD, HVDD PDN pin = "L" PDN pin "H" 1) PDN pin = "L" PDN pin = "L"150ns PDN pin = "H" TVDDDVDD HVDDDVDD 2) PDN pin = "L" TVDDDVDD HVDDDVDD AVSS, HVSS PC 2. VCOM2.2F 0.1FAVSS VCOM pin VCOM pin 3. MIN (0.45 x AVDD)0.06 x AVDD Vpp(typ)@MGAIN1-0 bits = "01", 0.03 x AVDD Vpp(typ)@MGAIN1-0 bits = "10", 0.015 x AVDD Vpp(typ)@MGAIN1-0 bits = "11"0.6 x AVDD Vpp(typ)@MGAIN1-0 bits = "00"MIN(0.45 x AVDD) 0.6 x AVDD Vpp(typ)DC fc=1/(2RC)AK4645AVSSAVDD AK4645AVSSAVDD 4. DAC2's7FFFH(@16bit) 8000H 8000H(@16bit)0000H 0000H(@16bit)VCOMVCOM 0.45 x AVDD (typ)HVDD/2 MS0605-J-00 MS0605-J-00 2007/06 - 84 - [AK4645EZ AK4645EZ] ADCDACPower-up 1. PLL Example: Power Supply Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D6) (4) (1) Power Supply & PDN pin = "L" MCKO bit "H" (Addr:01H, D1) PMPLL bit (2)Addr:01H, Data:08H Addr:04H, Data:4AH Addr:05H, Data:27H (Addr:01H, D0) (5) MCKI pin Input M/S bit (3)Addr:00H, Data:40H (Addr:01H, D3) 40msec(max) (6) BICK pin LRCK pin Output (4)Addr:01H, Data:0BH Output MCKO, BICK and LRCK output 40msec(max) (8) MCKO pin (7) Figure 75. Clock Set Up Sequence (1) (1) PDN pin "L" "H"AK4645150ns "L" () (2) DIF1-0, PLL3-0, FS3-0, BCKO, M/S bits (3) VCOM: PMVCM bit = "0" "1" VCOM (4) MCKO: MCKO bit = "1" MCKO: MCKO bit = "0" (5) PMPLL bit "0" "1"MCKI pinPLL PLL40ms(max) (6) PLLBICK, LRCK (7) MCKO bit = "1"MCKO pin (8) MCKO bit = "1"PLLMCKO pin MS0605-J-00 MS0605-J-00 2007/06 - 85 - [AK4645EZ AK4645EZ] 2. PLL(LRCK or BICK pin) Example: Power Supply Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 44.1kHz (1) PDN pin (2) 4fs ofPower Supply & PDN pin = "L" (1) (3) PMVCM bit "H" (Addr:00H, D6) PMPLL bit (2) Addr:04H, Data:32H Addr:05H, Data:27H (Addr:01H, D0) LRCK pin BICK pin Input (3) Addr:00H, Data:40H (4) Internal Clock (5) (4) Addr:01H, Data:01H Figure 76. Clock Set Up Sequence (2) (1) PDN pin "L" "H"AK4645150ns "L" () (2) DIF1-0, FS3-0, PLL3-0 bits (3) VCOM: PMVCM bit = "0" "1" VCOM (4) PMPLL bit "0" "1"PLL(LRCK or BICK pin)PLL PLLLRCKPLL160ms(max), BICKPLL 2ms(max) (5) PLL MS0605-J-00 MS0605-J-00 2007/06 - 86 - [AK4645EZ AK4645EZ] 3. PLL(MCKI pin) Example: Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz Power Supply (1) Power Supply & PDN pin = "L" (1) "H" PDN pin (2) (3) (2)Addr:04H, Data:4AH Addr:05H, Data:27H PMVCM bit (Addr:00H, D6) (4) MCKO bit (Addr:01H, D1) (3)Addr:00H, Data:40H PMPLL bit (Addr:01H, D0) (5) MCKI pin (4)Addr:01H, Data:03H Input 40msec(max) (7) MCKO pin MCKO output start Output (6) (8) BICK pin LRCK pin Input BICK and LRCK input start Figure 77. Clock Set Up Sequence (3) (1) PDN pin "L" "H"AK4645150ns "L" () (2) DIF1-0, PLL3-0, FS3-0 bits (3) VCOM PMVCM bit = "0" "1" VCOM (4) MCKO : MCKO bit = "1" (5) PMPLL bit "0" "1"MCKI pinPLL PLL40ms(max) (6) MCKO pin (7) PLLMCKO pin (8) MCKOBICK, LRCK MS0605-J-00 MS0605-J-00 2007/06 - 87 - [AK4645EZ AK4645EZ] 4. () Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable Power Supply (1) Power Supply & PDN pin = "L" "H" (1) PDN pin (2) (2) Addr:04H, Data:02H Addr:05H, Data:00H (3) PMVCM bit (Addr:00H, D6) (4) MCKI pin Input (3) Addr:00H, Data:40H (4) LRCK pin BICK pin Input MCKI, BICK and LRCK input Figure 78. Clock Set Up Sequence (4) (1) PDN pin "L" "H"AK4645150ns "L" () (2) DIF1-0, FS1-0 bits (3) VCOM PMVCM bit = "0" "1" VCOM (4) MCKI, LRCK, BICK MS0605-J-00 MS0605-J-00 2007/06 - 88 - [AK4645EZ AK4645EZ] 5. () Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable (1) Power Supply & PDN pin = "L" Power Supply "H" (1) PDN pin (2) MCKI input (4) PMVCM bit (Addr:00H, D6) (3) Addr:04H, Data:02H Addr:05H, Data:00H Addr:01H, Data:08H (2) MCKI pin Input (3) M/S bit BICK and LRCK output (Addr:01H, D3) LRCK pin BICK pin Output (4) Addr:00H, Data:40H Figure 79. Clock Set Up Sequence (5) (1) PDN pin "L" "H"AK4645150ns "L" () (2) MCKI (3) DIF1-0, FS1-0 bitsM/S bit "1"LRCKBICK (4) VCOM PMVCM bit = "0" "1" VCOM MS0605-J-00 MS0605-J-00 2007/06 - 89 - [AK4645EZ AK4645EZ] () Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 PLL Master Mode Audio I/F Format: MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Pre MIC AMP: +20dB MIC Power On ALC setting: Refer to Table 34 ALC bit="1" 1,111 (1) MIC Control (Addr:02H, D2-0) ALC Control 1 (Addr:06H) ALC Control 2 (Addr:08H) (1) Addr:05H, Data:27H 001 101 (2) Addr:02H, Data:05H (2) 00H 3CH (3) Addr:06H, Data:3CH E1H (4) Addr:08H, Data:E1H (3) E1H (4) (5) Addr:0BH, Data:00H ALC Control 3 (Addr:0BH) 00H 00H (6) Addr:07H, Data:21H (5) ALC Control 4 (Addr:07H) 07H 21H 01H (6) ALC State (9) ALC Disable ALC Enable ALC Disable (7) Addr:00H, Data:41H Addr:10H, Data:01H Recording PMADL/R bits (Addr:00H&10H, D0) 1059 / fs (8) (7) ADC Internal State Power Down (8) Addr:00H, Data:40H Addr:10H, Data:00H Initialize Normal State Power Down (9) Addr:07H, Data:01H Figure 80. MIC Input Recording Sequence fs=44.1kHzALC ALC"Figure 36. " (1) (FS3-0 bits)PLL PLL(7)ADC (2) ( 02H) (3) ALC Timer ( 06H) (4) ALC REF( 08H) (5) LMTH1, RGAIN1 bits( 0BH) (6) LMTH0, RGAIN0, LMAT1-0, ALC bits( 07H) (7) ADC : PMADL = PMADR bits = "0" "1" ADC1059/fs=24ms@fs=44.1kHz ALC(IVL/R7-0 bits)(+30dB) HPFPMVCM bit = "1"PMMP bit = "1" AC60k(typ) 4ADCPower-up (8) ADC: PMADL = PMADR bits = "1" "0" ADCALCDisable ALC(ALC bit = "0") ADC (PMADL = PMADR bits = "0")PMADL = PMADR bits = "0" (IVL/R7-0 bits) (9) ALC Disable: ALC bit = "1" "0" MS0605-J-00 MS0605-J-00 2007/06 - 90 - [AK4645EZ AK4645EZ] E x a m p le : FS3-0 bits (Addr:05H, D5&D2-0) 0,000 P L L M a s te r M o d e S a m p lin g F r e q u e n c y : 4 4 . 1 k H z D V O L C b it = " 1 " ( d e fa u lt ) D ig it a l V o lu m e L e v e l: - 8 d B B a s s B o o s t L e v e l: M id d le D e -e m p h a s e s re s p o n s e : O F F S o f t M u t e T im e : 2 5 6 /f s 1,111 (1) ( 1 ) A d d r : 0 5 H , D a ta : 2 7 H DACH bit (2) (Addr:0FH, D0) (13) ( 2 ) A d d r : 0 F H , D a ta 0 9 H BST1-0 bits (Addr:0EH, D3-2) IVL/R7-0 bits (Addr:09H&0CH, D7-0) 00 10 00 (3) E1H (4 ) A d d r:0 9 H & 0 C H , D a ta 9 1 H 91H (4) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (3 ) A d d r:0 E H , D a ta 1 9 H (12) ( 5 ) A d d r : 0 A H & 0 D H , D a ta 2 8 H 18H 28H ( 6 ) A d d r : 0 0 H , D a ta 6 4 H (5) PMDAC bit ( 7 ) A d d r : 0 1 H , D a ta 3 9 H (Addr:00H, D2) (6) (11) PMMIN bit ( 8 ) A d d r : 0 1 H , D a ta 7 9 H P la y b a c k (Addr:00H, D5) ( 9 ) A d d r : 0 1 H , D a ta 3 9 H PMHPL/R bits (7) (10) (Addr:01H, D5-4) HPMTN bit ( 1 0 ) A d d r :0 1 H , D a t a 0 9 H (8) (9) (Addr:01H, D6) ( 1 1 ) A d d r :0 0 H , D a t a 4 0 H ( 1 2 ) A d d r :0 E H , D a t a 1 1 H HPL/R pins Normal Output ( 1 3 ) A d d r :0 F H , D a t a 0 8 H Figure 81. Headphone-Amp Output Sequence (1) (FS3-0 bits)PLL PLL(5)DAC (2) DAC HP-Amp: DACH bit = "0" "1" (3) (BST1-0 bits) (4) (09H&0CH) PMADL = PMADR bits = "0"IVL7-0 = IVR7-0 bits = "91H"(0dB) (5) (0AH&0DH) DVOLC bit = "1"(default)DVL7-0bits(0AH)LchRch DACDefault(0dB) (6) DACMIN-Amp: PMDAC = PMMIN bits = "0" "1" (1059/fs=24ms@fs=44.1kHz)DAC2's "0" DAC(25/fs =0.5ms@fs=44.1kHz) DAC PMADL bitPMADR bit "1" DACALC bit = "1"(1059/fs = 24ms @fs=44.1kHz)ALC(ALCIVL/R7-0 bits) ALCIVL/R7-0 bits (7) : PMHPL = PMHPR bits = "0" "1" HVSS (8) : HPMTN bit = "0" "1" MUTET pinHVDDMUTET pinC = 1F, HVDD=3.3Vr =100ms(typ), 250ms(max) (9) : HPMTN bit = "1" "0" MUTET pinHVDDMUTET pinC = 1F, HVDD=3.3Vf =100ms(typ), 250ms(max) HVSS HVSS2 (10) : PMHPL = PMHPR bits = "1" "0" (11) DACMIN-Amp: PMDAC = PMMIN bits = "1" "0" (12) OFF: BST1-0 bits = "00" (13) DAC HP-AmpDisable: DACH bit = "1" "0" MS0605-J-00 MS0605-J-00 2007/06 - 91 - [AK4645EZ AK4645EZ] Example: FS3-0 bits (Addr:05H, D5&D2-0) 0,000 PLL, Master Mode Audio I/F Format: MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: -8dB LOVL=MINL bits = "0" 1,111 (1) (1) Addr:05H, Data:27H (10) DACL bit (2) (2) Addr:02H, Data:10H (Addr:02H, D4) IVL/R7-0 bits (Addr:09H&0CH, D7-0) E1H (3) Addr:09H&0CH, Data:91H 91H (3) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (4) Addr:0AH&0DH, Data:28H 18H 28H (5) Addr:03H, Data:40H (4) LOPS bit (6) Addr:00H, Data:6CH (Addr:03H, D6) (5) (7) (8) (11) PMDAC bit (Addr:00H, D2) Playback PMMIN bit (8) Addr:03H, Data:40H (Addr:00H, D5) (6) (9) (9) Addr:00H, Data:40H PMLO bit (Addr:00H, D3) (7) Addr:03H, Data:00H >300 ms (10) Addr:02H, Data:00H LOUT pin ROUT pin >300 ms Normal Output (11) Addr:03H, Data:00H Figure 82. Stereo Lineout Sequence (1) (FS3-0 bits)PLL PLL(5)DAC (2) DAC : DACL bit = "0" "1" (3) (09H&0CH) PMADL = PMADR bits = "0"IVL7-0 = IVR7-0 bits = "91H"(0dB) (4) (0AH&0DH) DVOLC bit = "1"(default)DVL7-0bits(0AH)LchRch DACDefault(0dB) (5) : LOPS bit = "0" "1" (6) DAC, MIN-Amp : PMDAC = PMMIN = PMLO bits = "0" "1" (1059/fs=24ms@fs=44.1kHz)DAC2's "0" DAC(25/fs=0.5ms@fs=44.1kHz) DACPMADL bitPMADR bit "1" DACALC bit = "1"(1059/fs = 24ms @fs=44.1kHz)ALC(ALCIVL/R7-0 bits) ALCIVL/R7-0 bits PMLO bit = "1"LOUT, ROUT pinsC = 1F, AVDD=3.3V max. 300ms (7) : LOPS bit = "1" "0" LOUT, ROUT pinsLOUT, ROUT pins (8) : LOPS bit: "0" "1" (9) DAC, MIN-Amp: PMDAC = PMMIN = PMLO bits = "1" "0" LOUT, ROUT pinsC = 1F, AVDD=3.3Vmax. 300ms (10) DAC Disable: DACL bit = "1" "0" (11) : LOPS bit = "1" "0" LOUT, ROUT pins MS0605-J-00 MS0605-J-00 2007/06 - 92 - [AK4645EZ AK4645EZ] ADCDAC 1. PLL Example: Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz Sampling Frequency: 44.1kHz (1) PMPLL bit (Addr:01H, D0) (2) MCKO bit "1" or "0" (1) (2) Addr:01H, Data:08H (Addr:01H, D1) (3) External MCKI Input (3) Stop an external MCKI Figure 83. Clock Stopping Sequence (1) (1) PLL: PMPLL bit = "1" "0" (2) MCKO: MCKO bit = "1" "0" (3) 2. PLLPLL(LRCK, BICK pin) Example Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 44.1kHz (1) PMPLL bit (Addr:01H, D0) (2) External BICK Input (1) Addr:01H, Data:00H (2) External LRCK Input (2) Stop the external clocks Figure 84. Clock Stopping Sequence (2) (1) PLL: PMPLL bit = "1" "0" (2) 3. PLL(MCKI pin) Example (1) Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 44.1kHz PMPLL bit (Addr:01H, D0) (1) MCKO bit (1) Addr:01H, Data:00H (Addr:01H, D1) (2) External MCKI Input (2) Stop the external clocks Figure 85. Clock Stopping Sequence (3) (1) PLL: PMPLL bit = "1" "0" MCKO: MCKO bit = "1" "0" (2) MS0605-J-00 MS0605-J-00 2007/06 - 93 - [AK4645EZ AK4645EZ] 4. (1) External MCKI Input Example (1) External BICK External LRCK Audio I/F Format: MSB justified (ADC & DAC) Input MCKI frequency: 1024fs Sampling Frequency: 44.1kHz Input Input (1) (1) Stop the external clocks Figure 86. Clock Stopping Sequence (4) (1) 5. (1) External MCKI Input Example BICK Output "H" or "L" LRCK Output Audio I/F Format: MSB justified (ADC & DAC)