AGX51004-2 PRBS31 IEEE802 SMPTE292M SMPTE424M 8B/10B EP1AGX20/35 EP1AGX50/60 - Datasheet Archive

 

AGX51004-2.0 Operating Conditions Arria® GX devices are offered in both commercial and industrial grades. Both commercial and

 

4. DC and Switching Characteristics AGX51004-2 AGX51004-2.0 Operating Conditions Arria® GX devices are offered in both commercial and industrial grades. Both commercial and industrial devices are offered in ­6 speed grade only. This chapter contains the following sections: "Operating Conditions" "Power Consumption" on page 4­25 "I/O Timing Model" on page 4­26 "Typical Design Performance" on page 4­32 "Block Performance" on page 4­84 "IOE Programmable Delay" on page 4­86 "Maximum Input and Output Clock Toggle Rate" on page 4­87 "Duty Cycle Distortion" on page 4­95 "High-Speed I/O Specifications" on page 4­100 "PLL Timing Specifications" on page 4­103 "External Memory Interface Specifications" on page 4­105 "JTAG Timing Specifications" on page 4­106 Table 4­1 through Table 4­42 on page 4­25 provide information on absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for Arria GX devices. Absolute Maximum Ratings Table 4­1 contains the absolute maximum ratings for the Arria GX device family. Table 4­1. Arria GX Device Absolute Maximum Ratings Symbol Parameter (Note 1), (2), (3) (Part 1 of 2) Conditions Minimum Maximum Units VCCINT Supply voltage With respect to ground ­0.5 1.8 V VCCIO Supply voltage With respect to ground ­0.5 4.6 V VCCPD Supply voltage With respect to ground ­0.5 4.6 V VI DC input voltage (4) ­0.5 4.6 V IOUT DC output current, per pin ­25 40 mA TSTG Storage temperature ­65 150 C © December 2009 Altera Corporation - - No bias Arria GX Device Handbook, Volume 1 4­2 Chapter 4: DC and Switching Characteristics Operating Conditions Table 4­1. Arria GX Device Absolute Maximum Ratings Symbol Parameter TJ (Note 1), (2), (3) (Part 2 of 2) Conditions Junction temperature Minimum Maximum Units ­55 125 C BGA packages under bias Notes to Table 4­1: (1) For more information about operating requirements for Altera® devices, refer to the Arria GX Device Family Data Sheet chapter. (2) Conditions beyond those listed in Table 4­1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. (4) During transitions, the inputs may overshoot to the voltage shown in Table 4­2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to ­2.0 V for input currents less than 100 mA and periods shorter than 20 ns. Table 4­2. Maximum Duty Cycles in Voltage Transitions Symbol Parameter (Note 1) Condition Maximum Duty Cycles (%) VI = 4.0 V 100 VI = 4.1 V VI = 4.3 V 30 17 VI = 4.5 V Maximum duty cycles in voltage transitions 50 VI = 4.4 V VI 90 VI = 4.2 V 10 Note to Table 4­2: (1) During transition, the inputs may overshoot to the voltages shown based on the input duty cycle. The DC case is equivalent to 100% duty cycle. Recommended Operating Conditions Table 4­3 lists the recommended operating conditions for the Arria GX device family. Table 4­3. Arria GX Device Recommended Operating Conditions (Part 1 of 2) Symbol Parameter Conditions (Note 1) (Part 1 of 2) Minimum Maximum Units 1.15 1.25 V Supply voltage for internal logic and input buffers Rise time 100 ms (3) Supply voltage for output buffers, 3.3-V operation Rise time 100 ms (3), (6) 3.135 (3.00) 3.465 (3.60) V Supply voltage for output buffers, 2.5-V operation Rise time 100 ms (3) 2.375 2.625 V Supply voltage for output buffers, 1.8-V operation Rise time 100 ms (3) 1.71 1.89 V Supply voltage for output buffers, 1.5-V operation Rise time 100 ms (3) 1.425 1.575 V Supply voltage for output buffers, 1.2-V operation Rise time 100 ms (3) 1.15 1.25 V Supply voltage for pre-drivers as well as configuration and JTAG I/O buffers. 100 s rise time 100 ms (4) 3.135 3.465 V VCCPD VI Input voltage (refer to Table 4­2) (2), (5) ­0.5 4.0 V VO Output voltage 0 VCCIO V VCCINT VCCIO Arria GX Device Handbook, Volume 1 - © December 2009 Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­3 Table 4­3. Arria GX Device Recommended Operating Conditions (Part 2 of 2) Symbol Parameter TJ Operating junction temperature (Note 1) (Part 2 of 2) Conditions Minimum Maximum Units 0 85 C ­40 100 C For commercial use For industrial use Notes to Table 4­3: (1) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. (2) During transitions, the inputs may overshoot to the voltage shown in Table 4­2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to ­2.0 V for input currents less than 100 mA and periods shorter than 20 ns. (3) Maximum VCC rise time is 100 ms, and VCC must rise monotonically from ground to VCC . (4) VCCPD must ramp-up from 0 V to 3.3 V within 100 s to 100 ms. If VCCPD is not ramped up within this specified time, the Arria GX device will not configure successfully. If the system does not allow for a V CCPD ramp-up time of 100 ms or less, hold nCONFIG low until all power supplies are reliable. (5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, can be driven before VCCINT, VCCPD, and VCCIO are powered. (6) VCCIO maximum and minimum conditions for PCI and PCI-X are shown in parentheses. Transceiver Block Characteristics Table 4­4 through Table 4­6 on page 4­4 contain transceiver block specifications. Table 4­4. Arria GX Transceiver Block Absolute Maximum Ratings Symbol Parameter (Note 1) Conditions Minimum Maximum Units VCCA Transceiver block supply voltage Commercial and industrial ­0.5 4.6 V VCCP Transceiver block supply voltage Commercial and industrial ­0.5 1.8 V VCCR Transceiver block supply voltage Commercial and industrial ­0.5 1.8 V VCCT_B Transceiver block supply voltage Commercial and industrial ­0.5 1.8 V VCCL_B Transceiver block supply voltage Commercial and industrial ­0.5 1.8 V VCCH_B Transceiver block supply voltage Commercial and industrial ­0.5 2.4 V Note to Table 4­4: (1) The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is not violated. Table 4­5. Arria GX Transceiver Block Operating Conditions Symbol Parameter Conditions Minimum Typical Maximum Units VCCA Transceiver block supply voltage Commercial and industrial 3.135 3.3 3.465 V VCCP Transceiver block supply voltage Commercial and industrial 1.15 1.2 1.25 V VCCR Transceiver block supply voltage Commercial and industrial 1.15 1.2 1.25 V VCCT_B Transceiver block supply voltage Commercial and industrial 1.15 1.2 1.25 V VCCL_B Transceiver block supply voltage Commercial and industrial 1.15 1.2 1.25 V 1.15 1.2 1.25 V 1.425 1.5 1.575 V 2K - 1% 2K 2K +1% VCCH_B Transceiver block supply voltage Commercial and industrial RREFB (1) Reference resistor Commercial and industrial Note to Table 4­5: (1) The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin. © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 4­4 Chapter 4: DC and Switching Characteristics Operating Conditions Table 4­6. Arria GX Transceiver Block AC Specification (Part 1 of 3) Symbol / Description Conditions ­6 Speed Grade Commercial and Industrial Min Typ Units Max Reference clock Input reference clock frequency - 50 - 622.08 MHz Absolute VM A X for a REFCLK Pin - - - 3.3 V Absolute VMIN for a REFCLK Pin - ­0.3 - - V Rise/Fall time - - 0.2 - UI Duty cycle - 45 - 55 % Peak to peak differential input voltage VID (diff p-p) - 200 - 2000 mV Spread spectrum clocking (1) 0 to ­0.5% 30 - 33 kHz On-chip termination resistors - 115 ± 20% VICM (AC coupled) - 1200 ± 5% mV VICM (DC coupled) (2) RREFB PCI Express (PIPE) mode 0.25 - - 0.55 V 2000 +/-1% Transceiver Clocks Calibration block clock frequency - 10 - 125 MHz Calibration block minimum power-down pulse width - 30 - - ns fixedclk clock frequency (3) reconfig clock frequency - 125 ±10% MHz SDI mode 2.5 - 50 MHz - 100 - - ns Data rate - 600 - 3125 Mbps Absolute VMAX for a receiver pin (4) - - - 2.0 V Absolute VMIN for a receiver pin - ­0.4 - - V Maximum peak-to-peak differential input voltage VID (diff p-p) Vicm = 0.85 V - - 3.3 V Minimum peak-to-peak differential input voltage VID (diff p-p) DC Gain = 3 dB 160 - - mV Transceiver block minimum power-down pulse width Receiver On-chip termination resistors VICM (15) - 100±15% Vicm = 0.85 V setting 850 ± 10% 850 ± 10% 850 ± 10% mV 1200 ± 10% 1200 ± 10% - 30 - BW = Med - 40 - BW = High Arria GX Device Handbook, Volume 1 1200 ± 10% BW = Low Bandwidth at 3.125 Gbps Vicm = 1.2 V setting - 50 - © December 2009 mV MHz Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­5 Table 4­6. Arria GX Transceiver Block AC Specification (Part 2 of 3) Symbol / Description Conditions ­6 Speed Grade Commercial and Industrial Min - 35 - - 50 - BW = High Return loss differential mode BW = Low - 60 Units Max BW = Med Bandwidth at 2.5 Gbps Typ - 50 MHz to 1.25 GHz (PCI Express) MHz ­10 dB ­6 dB 100 MHz to 2.5 GHz (XAUI) Return loss common mode 50 MHz to 1.25 GHz (PCI Express) 100 MHz to 2.5 GHz (XAUI) Programmable PPM detector (5) - ± 62.5, 100, 125, 200, 250, 300, 500, 1000 PPM Run length (6) - 80 UI Programmable equalization - - - 5 dB Signal detect/loss threshold (7) - 65 - 175 mV CDR LTR TIme (8), (9) - - - 75 us CDR Minimum T1b (9), (10) - 15 - - us LTD lock time (9), (11) - 0 100 4000 ns Data lock time from rx_freqlocked (9), (12) - - - 4 us Programmable DC gain - 0, 3, 6 dB Output Common Mode voltage (Vocm) - 580 ± 10% mV On-chip termination resistors - 108±10% Transmitter Buffer 50 MHz to 1.25 GHz (PCI Express) Return loss differential mode dB ­10 312 MHz to 625 MHz (XAUI) 625 MHz to 3.125GHz (XAUI) Return loss common mode ­10 ­6 50 MHz to 1.25 GHz (PCI Express) dB -decade slope dB Rise time - 35 - 65 ps Fall time - 35 - 65 ps VOD = 800 mV - - 15 ps - - - 100 ps Intra differential pair skew Intra-transceiver block skew (×4) (13) © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 4­6 Chapter 4: DC and Switching Characteristics Operating Conditions Table 4­6. Arria GX Transceiver Block AC Specification (Part 3 of 3) Symbol / Description Conditions ­6 Speed Grade Commercial and Industrial Units Min Typ Max - 500 - 1562.5 BW = Low - 3 - BW = Med - 5 - BW = High - 9 - BW = Low - 1 - BW = Med - 2 - BW = High - 4 - - - - 100 us Interface speed per mode - 25 - 156.25 MHz Digital Reset Pulse Width - Transmitter PLL VCO frequency range Bandwidth at 3.125 Gbps Bandwidth at 2.5 Gbps TX PLL lock time from gxb_powerdown de-assertion (9), (14) MHz MHz MHz PCS Minimum is 2 parallel clock cycles - Notes to Table 4­6: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) Spread spectrum clocking is allowed only in PCI Express (PIPE) mode if the upstream transmitter and the receiver share the same clock source. The reference clock DC coupling option is only available in PCI Express (PIPE) mode for the HCSL I/O standard. The fixedclk is used in PIPE mode receiver detect circuitry. The device cannot tolerate prolonged operation at this absolute maximum. The rate matcher supports only up to ± 300 PPM for PIPE mode and ± 100 PPM for GIGE mode. This parameter is measured by embedding the run length data in a PRBS sequence. Signal detect threshold detector circuitry is available only in PCI Express (PIPE mode). Time taken for rx_pll_locked to go high from rx_analogreset deassertion. Refer to Figure 4­1. For lock times specific to the protocols, refer to protocol characterization documents. Time for which the CDR needs to stay in LTR mode after rx_pll_locked is asserted and before rx_locktodata is asserted in manual mode. Refer to Figure 4­1. Time taken to recover valid data from GXB after the rx_locktodata signal is asserted in manual mode. Measurement results are based on PRBS31 PRBS31, for native data rates only. Refer to Figure 4­1. Time taken to recover valid data from GXB after the rx_freqlocked signal goes high in automatic mode. Measurement results are based on PRBS31 PRBS31, for native data rates only. Refer to Figure 4­2. This is applicable only to PCI Express (PIPE) ×4 and XAUI ×4 mode. Time taken to lock TX PLL from gxb_powerdown deassertion. The 1.2 V RX VICM settings is intended for DC-coupled LVDS links. Figure 4­1 shows the lock time parameters in manual mode. Figure 4­2 shows the lock time parameters in automatic mode. 1 LTD = Lock to data LTR = Lock to reference clock Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­7 Figure 4­1. Lock Time Parameters for Manual Mode r x_analogreset CDR status LTR LTD r x_pll_locked r x_locktodata Invalid Data Valid data r x_dataout CDR LTR Time LTD lock time CDR Minimum T1b Figure 4­2. Lock Time Parameters for Automatic Mode CDR status LTR LTD r x_freqlocked r x_dataout Invalid Valid data data Data lock time from rx_freqlocked © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 4­8 Chapter 4: DC and Switching Characteristics Operating Conditions Figure 4­3 and Figure 4­4 show differential receiver input and transmitter output waveforms, respectively. Figure 4­3. Receiver Input Waveform Single-Ended Waveform Positive Channel (p) VID Negative Channel (n) VCM Ground Differential Waveform VID (diff peak-peak) = 2 x VID (single-ended) VID p-n=0V VID Figure 4­4. Transmitter Output Waveform Single-Ended Waveform Positive Channel (p) VOD Negative Channel (n) VCM Ground Differential Waveform VOD (diff peak-peak) = 2 x VOD (single-ended) VOD p-n=0V VOD Table 4­7 lists the Arria GX transceiver block AC specification. Table 4­7. Arria GX Transceiver Block AC Specification (Note 1), (2), (3) (Part 1 of 4) Description Condition ­6 Speed Grade Commercial & Units Industrial XAUI Transmit Jitter Generation (4) REFCLK = 156.25 MHz Total jitter at 3.125 Gbps Pattern = CJPAT VOD = 1200 mV 0.3 UI No Pre-emphasis Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­9 Table 4­7. Arria GX Transceiver Block AC Specification (Note 1), (2), (3) (Part 2 of 4) Description Condition ­6 Speed Grade Commercial & Units Industrial REFCLK = 156.25 MHz Deterministic jitter at 3.125 Gbps Pattern = CJPAT VOD = 1200 mV 0.17 UI > 0.65 UI > 0.37 UI No Pre-emphasis XAUI Receiver Jitter Tolerance (4) Pattern = CJPAT Total jitter No Equalization DC Gain = 3 dB Pattern = CJPAT Deterministic jitter No Equalization DC Gain = 3 dB Peak-to-peak jitter Jitter frequency = 22.1 KHz > 8.5 UI Peak-to-peak jitter Jitter frequency = 1.875 MHz > 0.1 UI Peak-to-peak jitter Jitter frequency = 20 MHz > 0.1 UI < 0.25 UI p-p > 0.6 UI p-p < 0.279 UI p-p < 0.14 UI p-p > 0.66 UI p-p > 0.4 UI p-p < 0.35 UI p-p < 0.17 UI p-p PCI Express (PIPE) Transmitter Jitter Generation (5) Total Transmitter Jitter Generation Compliance Pattern; VOD = 800 mV; Pre-emphasis = 49% PCI Express (PIPE) Receiver Jitter Tolerance (5) Total Receiver Jitter Tolerance Compliance Pattern; DC Gain = 3 db Gigabit Ethernet (GIGE) Transmitter Jitter Generation (7) Total Transmitter Jitter Generation (TJ) Deterministic Transmitter Jitter Generation (DJ) CRPAT: VOD = 800 mV; Pre-emphasis = 0% CRPAT; VOD = 800 mV; Pre-emphasis = 0% Gigabit Ethernet (GIGE) Receiver Jitter Tolerance Total Jitter Tolerance Deterministic Jitter Tolerance CJPAT Compliance Pattern; DC Gain = 0 dB CJPAT Compliance Pattern; DC Gain = 0 dB Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Transmitter Jitter Generation (6) CJPAT Compliance Pattern; Total Transmitter Jitter Generation (TJ) VOD = 800 mV; Pre-emphasis = 0% CJPAT Compliance Pattern; Deterministic Transmitter Jitter Generation (DJ) VOD = 800 mV; Pre-emphasis = 0% © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 4­10 Chapter 4: DC and Switching Characteristics Operating Conditions Table 4­7. Arria GX Transceiver Block AC Specification (Note 1), (2), (3) (Part 3 of 4) Description Condition ­6 Speed Grade Commercial & Units Industrial Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Receiver Jitter Tolerance (6) Total Jitter Tolerance CJPAT Compliance Pattern; Sinusoidal Jitter Tolerance > 0.55 UI p-p > 0.37 UI p-p > 8.5 UI p-p Jitter Frequency = 200 KHz > 1.0 UI p-p Jitter Frequency = 1.875 MHz > 0.1 UI p-p Jitter Frequency = 20 MHz Deterministic Jitter Tolerance (JD) UI p-p Jitter Frequency = 22.1 KHz Combined Deterministic and Random Jitter Tolerance (JDR) > 0.65 > 0.1 UI p-p Data Rate = 1.485 Gbps (HD) REFCLK = 74.25 MHz Pattern = Color Bar Vod = 800 mV No Pre-emphasis Low-Frequency Roll-Off = 100 KHz 0.2 UIv Data Rate = 2.97 Gbps (3G) REFCLK = 148.5 MHz Pattern = Color Bar Vod = 800 mV No Pre-emphasis Low-Frequency Roll-Off = 100 KHz 0.3 UI DC Gain = 0 dB CJPAT Compliance Pattern; DC Gain = 0 dB CJPAT Compliance Pattern; DC Gain = 0 dB SDI Transmitter Jitter Generation (8) Alignment Jitter (peak-to-peak) Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­11 Table 4­7. Arria GX Transceiver Block AC Specification Description (Note 1), (2), (3) (Part 4 of 4) ­6 Speed Grade Commercial & Units Industrial Condition SDI Receiver Jitter Tolerance (8) Jitter Frequency = 15 KHz Data Rate = 2.97 Gbps (3G) REFCLK = 148.5 MHz Pattern = Single Line Scramble Color Bar No Equalization DC Gain = 0 dB Sinusoidal Jitter Tolerance (peak-to-peak) UI Jitter Frequency = 100 KHz Data Rate = 2.97 Gbps (3G) REFCLK = 148.5 MHz Pattern = Single Line Scramble Color Bar No Equalization DC Gain = 0 dB > 0.3 UI Jitter Frequency = 148.5 MHz Data Rate = 2.97 Gbps (3G) REFCLK = 148.5 MHz Pattern = Single Line Scramble Color Bar No Equalization DC Gain = 0 dB Sinusoidal Jitter Tolerance (peak-to-peak) >2 > 0.3 UI Jitter Frequency = 20 KHz Data Rate = 1.485 Gbps (HD) REFCLK = 74.25 MHz Pattern = 75% Color Bar No Equalization DC Gain = 0 dB >1 UI Jitter Frequency = 100 KHz Data Rate = 1.485 Gbps (HD) REFCLK = 74.25 MHz Pattern = 75% Color Bar No Equalization DC Gain = 0 dB > 0.2 UI Notes to Table 4­7: (1) (2) (3) (4) (5) (6) (7) (8) Dedicated REFCLK pins were used to drive the input reference clocks. Jitter numbers specified are valid for the stated conditions only. Refer to the protocol characterization documents for detailed information. The jitter numbers for XAUI are compliant to the IEEE802 IEEE802.3ae-2002 Specification. The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0. The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3. The jitter numbers for GIGE are compliant to the IEEE802 IEEE802.3-2002 Specification. The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M SMPTE292M and SMPTE424M SMPTE424M specifications. © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 4­12 Chapter 4: DC and Switching Characteristics Operating Conditions Table 4­8 and Table 4­9 list the transmitter and receiver PCS latency for each mode, respectively. Table 4­8. PCS Latency (Note 1) Transmitter PCS Latency Functional Mode Configuration TX PIPE TX Phase Comp FIFO Byte Serializer TX State Machine 8B/10B 8B/10B Encoder Sum (2) - 2­3 1 0.5 0.5 4­5 ×1, ×4, ×8 8-bit channel width 1 3­4 1 - 1 6­7 ×1, ×4, ×8 16-bit channel width 1 3­4 1 - 0.5 6­7 - 2­3 1 - 1 4­5 1.25 Gbps, 2.5 Gbps, 3.125 Gbps - 2­3 1 - 0.5 4­5 HD10-bit channel width - 2­3 1 - 1 4­5 XAUI - PIPE GIGE - Serial RapidIO SDI HD, 3G 20-bit channel width 2­3 1 - 0.5 4­5 - 2­3 1 - 1 4­5 16-bit/20-bit channel width BASIC Single Width - 8-bit/10-bit channel width - 2­3 1 - 0.5 4­5 Notes to Table 4­8: (1) The latency numbers are with respect to the PLD-transceiver interface clock cycles. (2) The total latency number is rounded off in the Sum column. Table 4­9. PCS Latency (Part 1 of 2) (Part 1 of 2) 8B/10B 8B/10B Decoder Receiver State Machine Byte Deserializer Byte Order Receiver Phase Comp FIFO Receiver PIPE Sum (2) Serial RapidIO Rate Matcher (3) GIGE Deskew FIFO PIPE Word Aligner XAUI 2­2.5 2­2.5 5.5­6.5 0.5 1 1 1 1­2 - 14­17 ×1, ×4 8-bit channel width 4­5 - 11­13 1 - 1 1 2­3 1 21­25 ×1, ×4 16-bit channel width 2­2.5 - 5.5­6.5 0.5 - 1 1 2­3 1 13­16 4­5 - 11­13 1 - 1 1 1­2 - 19­23 2­2.5 - - 0.5 - 1 1 1­2 - 6­7 5 - - 1 - 1 1 1­2 - 9­10 2.5 - - 0.5 - 1 1 1­2 - 6­7 Configuration Functional Mode Receiver PCS Latency - - 1.25 Gbps, 2.5 Gbps, 3.125 Gbps HD 10-bit channel width SDI HD, 3G 20-bit channel width Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­13 Table 4­9. PCS Latency (Part 2 of 2) (Part 2 of 2) Deskew FIFO Rate Matcher (3) 8B/10B 8B/10B Decoder Receiver State Machine Byte Deserializer Byte Order Receiver Phase Comp FIFO Receiver PIPE Sum (2) 8/10-bit channel width; with Rate Matcher 4­5 - 11­13 1 - 1 1 1­2 1 19­23 8/10-bit channel width; without Rate Matcher 4­5 - - 1 - 1 1 1­2 - 8­10 16/20-bit channel width; with Rate Matcher 2­2.5 - 5.5­6.5 0.5 - 1 1 1­2 - 11­14 16/20-bit channel width; without Rate Matcher 2­2.5 - - 0.5 - 1 1 1­2 - 6­7 BASIC Single Width Configuration Functional Mode Word Aligner Receiver PCS Latency Notes to Table 4­9: (1) The latency numbers are with respect to the PLD-transceiver interface clock cycles. (2) The total latency number is rounded off in the Sum column. (3) The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set gap allowed by the protocol, actual PPM difference between the reference clocks, and so forth. Table 4­10 through Table 4­13 show the typical VOD for data rates from 600 Mbps to 3.125 Gbps. The specification is for measurement at the package ball. Table 4­10. Typical VOD Setting, TX Term = 100 Vcc HTX = 1.5 V VOD Typical (mV) VOD Setting (mV) 400 600 800 1000 1200 430 625 830 1020 1200 Table 4­11. Typical VOD Setting, TX Term = 100 Vcc HTX = 1.2 V VOD Typical (mV) VOD Setting (mV) 320 480 640 800 960 344 500 664 816 960 Table 4­12. Typical Pre-Emphasis (First Post-Tap), (Note 1) Vcc HTX = 1.5 V VOD Setting (mV) First Post Tap Pre-Emphasis Level 1 2 3 4 5 TX Term = 100 400 62% 112% 184% - 600 - 31% 56% 86% 122% 800 © December 2009 24% - 20% 35% 53% 73% Altera Corporation Arria GX Device Handbook, Volume 1 4­14 Chapter 4: DC and Switching Characteristics Operating Conditions Table 4­12. Typical Pre-Emphasis (First Post-Tap), (Note 1) Vcc HTX = 1.5 V VOD Setting (mV) First Post Tap Pre-Emphasis Level 1 2 3 4 5 1000 - - 23% 36% 49% 1200 - - 17% 25% 35% Note to Table 4­12: (1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball. Table 4­13. Typical Pre-Emphasis (First Post-Tap), (Note 1) Vcc HTX = 1.2 V VOD Setting (mV) First Post Tap Pre-Emphasis Level 1 2 3 4 5 TX Term = 100 320 24% 61% 114% - - 480 - 31% 55% 86% 121% 640 - 20% 35% 54% 72% 800 - - 23% 36% 49% 960 - - 18% 25% 35% Note to Table 4­13: (1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball. DC Electrical Characteristics Table 4­14 lists the Arria GX device family DC electrical characteristics. Table 4­14. Arria GX Device DC Operating Conditions (Part 1 of 2) Symbol Parameter (Note 1) Conditions Device Min Typ Max Units II Input pin leakage current VI = VCCIOmax to 0 V (2) All ­10 - 10 A IOZ Tri-stated I/O pin leakage current VO = VCCIOmax to 0 V (2) All ­10 - 10 A - 0.30 (3) A ICCINT0 VI = ground, no load, no toggling inputs EP1AGX20/35 EP1AGX20/35 VCCINT supply current (standby) EP1AGX50/60 EP1AGX50/60 - 0.50 (3) A TJ = 25 °C EP1AGX90 EP1AGX90 - 0.62 (3) A VI = ground, no load, no toggling inputs EP1AGX20/35 EP1AGX20/35 - 2.7 (3) mA EP1AGX50/60 EP1AGX50/60 - 3.6 (3) mA TJ = 25 °C, VCCPD = 3.3V EP1AGX90 EP1AGX90 - 4.3 (3) mA VI = ground, no load, no toggling inputs EP1AGX20/35 EP1AGX20/35 - 4.0 (3) mA EP1AGX50/60 EP1AGX50/60 - 4.0 (3) mA TJ = 25 °C EP1AGX90 EP1AGX90 - 4.0 (3) mA ICCPD0 ICCI00 ICCI00 VCCPD supply current (standby) VCCIO supply current (standby) Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­15 Table 4­14. Arria GX Device DC Operating Conditions (Part 2 of 2) Symbol Parameter Min Typ Max Units - 10 25 50 k Vi = 0, VCCIO = 2.5 V - 15 35 70 k Vi = 0, VCCIO = 1.8 V - 30 50 100 k Vi = 0, VCCIO = 1.5 V - 40 75 150 k Vi = 0, VCCIO = 1.2 V RCONF (4) Device Vi = 0, VCCIO = 3.3 V Value of I/O pin pull-up resistor before and during configuration Conditions (Note 1) - 50 90 170 k - - 1 2 k Recommended value of I/O pin external pull-down resistor before and during configuration - Notes to Table 4­14: (1) Typical values are for TA = 25 °C, VCCINT = 1.2 V, and VCCIO = 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V. (2) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, 1.5, and 1.2 V). (3) Maximum values depend on the actual TJ and design utilization. For maximum values, refer to the Excel-based PowerPlay Early Power Estimator (available at PowerPlay Early Power Estimators (EPE) and Power Analyzer) or the Quartus® II PowerPlay Power Analyzer feature for maximum values. For more information, refer to "Power Consumption" on page 4­25. (4) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO. I/O Standard Specifications Table 4­15 through Table 4­38 show the Arria GX device family I/O standard specifications. Table 4­15. LVTTL Specifications Symbol Parameter Conditions Minimum Maximum Units - 3.135 3.465 V VCCIO (1) Output supply voltage VIH High-level input voltage - 1.7 4.0 V VIL Low-level input voltage - ­0.3 0.8 V VOH High-level output voltage IOH = ­4 mA (2) 2.4 - V VOL Low-level output voltage IOL = 4 mA (2) - 0.45 V Notes to Table 4­15: (1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. (2) This specification is supported across all the programmable drive strength settings available for this I/O standard. Table 4­16. LVCMOS Specifications Symbol Parameter Conditions Minimum Maximum Units VCCIO (1) Output supply voltage - 3.135 3.465 V VIH High-level input voltage - 1.7 4.0 V VIL Low-level input voltage - ­0.3 0.8 V VOH High-level output voltage VCCIO = 3.0, IOH = ­0.1 mA (2) VCCIO ­ 0.2 - V VOL Low-level output voltage VCCIO = 3.0, IOL = 0.1 mA (2) - 0.2 V Notes to Table 4­16: (1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. (2) This specification is supported across all the programmable drive strength available for this I/O standard. © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 4­16 Chapter 4: DC and Switching Characteristics Operating Conditions Table 4­17. 2.5-V I/O Specifications Symbol Parameter Conditions Minimum Maximum Units VCCIO (1) Output supply voltage - 2.375 2.625 V VIH High-level input voltage - 1.7 4.0 V VIL Low-level input voltage - ­0.3 0.7 V VOH High-level output voltage I OH = ­1 mA (2) 2.0 - V VOL Low-level output voltage I OL = 1 mA (2) - 0.4 V Notes to Table 4­17: (1) The Arria GX device VCCIO voltage level support of 2.5 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard. (2) This specification is supported across all the programmable drive settings available for this I/O standard. Table 4­18. 1.8-V I/O Specifications Symbol Parameter Conditions Minimum Maximum Units VCCIO (1) Output supply voltage - 1.71 1.89 V VIH High-level input voltage - 0.65 × VCCIO 2.25 V VIL Low-level input voltage - ­0.3 0.35 × VCCIO V VOH High-level output voltage I OH = ­2 mA (2) VCCIO ­ 0.45 - V VOL Low-level output voltage I OL = 2 mA (2) - 0.45 V Notes to Table 4­18: (1) The Arria GX device VCCIO voltage level support of 1.8 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard. (2) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in Arria GX Architecture chapter. Table 4­19. 1.5-V I/O Specifications Symbol Parameter Conditions Minimum Maximum Units VCCIO (1) Output supply voltage - 1.425 1.575 V VIH High-level input voltage - 0.65 VCCIO VCCIO + 0.3 V VIL Low-level input voltage - ­0.3 0.35 VCCIO V VOH High-level output voltage IOH = ­2 mA (2) 0.75 VCCIO - V VOL Low-level output voltage IOL = 2 mA (2) - 0.25 VCCIO V Notes to Table 4­19: (1) The Arria GX device VCCIO voltage level support of 1.5 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard. (2) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture chapter. Figure 4­5 and Figure 4­6 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS and LVPECL). Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­17 Figure 4­5. Receiver Input Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID VID (Peak-to-Peak) Figure 4­6. Transmitter Output Waveforms for Differential I/O Standards Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD Table 4­20. 2.5-V LVDS I/O Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO I/O supply voltage for left and right I/O banks (1, 2, 5, and 6) - 2.375 2.5 2.625 V VID Input differential voltage swing (single-ended) - 100 350 900 mV VICM Input common mode voltage - 200 1,250 1,800 mV VOD Output differential voltage (single-ended) RL = 100 250 - 450 mV VOCM Output common mode voltage RL = 100 1.125 - 1.375 V RL Receiver differential input discrete resistor (external to Arria GX devices) - 90 100 110 © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 4­18 Chapter 4: DC and Switching Characteristics Operating Conditions Table 4­21. 3.3-V LVDS I/O Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO (1) I/O supply voltage for top and bottom PLL banks (9, 10, 11, and 12) - 3.135 3.3 3.465 V VID Input differential voltage swing (single-ended) - 100 350 900 mV VICM Input common mode voltage - 200 1,250 1,800 mV VOD Output differential voltage (single-ended) RL = 100 250 - 710 mV VOCM Output common mode voltage RL = 100 840 - 1,570 mV RL Receiver differential input discrete resistor (external to Arria GX devices) 90 100 110 - Note to Table 4­21: (1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V CCINT, not VCCIO. The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V. Table 4­22. 3.3-V PCML Specifications Symbol Parameter Minimum Typical Maximum Units 3.135 3.3 3.465 V 300 - 600 mV VCCIO I/O supply voltage VID Input differential voltage swing (single-ended) VICM Input common mode voltage 1.5 - 3.465 V VOD Output differential voltage (single-ended) 300 370 500 mV VOD Change in VO D between high and low - - 50 mV VOCM Output common mode voltage 2.5 2.85 3.3 V VOCM Change in VO C M between high and low - - 50 mV VT Output termination voltage - VC C I O - V R1 Output external pull-up resistors 45 50 55 R2 Output external pull-up resistors 45 50 55 Table 4­23. LVPECL Specifications Parameter Conditions Minimum Typical Maximum Units Parameter VCCIO (1) I/O supply voltage - 3.135 3.3 3.465 V VID Input differential voltage swing (single-ended) - 300 600 1,000 mV VICM Input common mode voltage - 1.0 - 2.5 V VOD Output differential voltage (single-ended) RL = 100 525 - 970 mV VOCM Output common mode voltage RL = 100 1,650 - 2,250 mV RL Receiver differential input resistor - 90 100 110 Note to Table 4­23: (1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO . The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V. Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­19 Table 4­24. 3.3-V PCI Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage - 3.0 3.3 3.6 V VIH High-level input voltage - 0.5 VCCIO - VCCIO + 0.5 V VIL Low-level input voltage - ­0.3 - 0.3 VCCIO V VOH High-level output voltage IOUT = ­500 A 0.9 VCCIO - - V VOL Low-level output voltage IOUT = 1,500 A - - 0.1 VCCIO V Table 4­25. PCI-X Mode 1 Specifications Symbol Parameter Conditions Minimum Maximum Units VCCIO Output supply voltage - 3.0 3.6 V VIH High-level input voltage - 0.5 VCCIO VCCIO + 0.5 V VIL Low-level input voltage - ­0.3 0.35 VCCIO V VIPU Input pull-up voltage - 0.7 VCCIO - V VOH High-level output voltage I OUT = ­500 A 0.9 VCCIO - V VOL Low-level output voltage I OUT = 1,500 A - 0.1 VCCIO V Table 4­26. SSTL-18 SSTL-18 Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage - 1.71 1.8 1.89 V VREF Reference voltage - 0.855 0.9 0.945 V VTT Termination voltage - VREF ­ 0.04 VREF VREF + 0.04 V VIH (DC) High-level DC input voltage - VREF + 0.125 - - V VIL (DC) Low-level DC input voltage - - - VREF ­ 0.125 V VIH (AC) High-level AC input voltage - VREF + 0.25 - - V VIL (AC) Low-level AC input voltage - - - VREF ­ 0.25 V VOH High-level output voltage I OH = ­6.7 mA (1) VTT + 0.475 - - V VOL Low-level output voltage I OL = 6.7 mA (1) - - VTT ­ 0.475 V Note to Table 4­26: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter. Table 4­27. SSTL-18 SSTL-18 Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage - 1.71 1.8 1.89 V VREF Reference voltage - 0.855 0.9 0.945 V VTT Termination voltage - VREF ­ 0.04 VREF VREF + 0.04 V VIH (DC) High-level DC input voltage - VREF + 0.125 - - V VIL (DC) Low-level DC input voltage - - - VREF ­ 0.125 V VIH (AC) High-level AC input voltage - VREF + 0.25 - - V VIL (AC) Low-level AC input voltage - - - VREF ­ 0.25 V © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 4­20 Chapter 4: DC and Switching Characteristics Operating Conditions Table 4­27. SSTL-18 SSTL-18 Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VOH High-level output voltage I OH = ­13.4 mA (1) VCCIO ­ 0.28 - - V VOL Low-level output voltage I OL = 13.4 mA (1) - - 0.28 V Note to Table 4­27: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter. Table 4­28. SSTL-18 SSTL-18 Class I & II Differential Specifications Symbol Parameter Minimum Typical Maximum Units VCCIO Output supply voltage 1.71 1.8 1.89 V VSWING (DC) DC differential input voltage 0.25 - - V VX (AC) AC differential input cross point voltage (VCCIO/2) ­ 0.175 - (VCCIO/2) + 0.175 V VSWING (AC) AC differential input voltage 0.5 - - V VISO Input clock signal offset voltage - 0.5 VCC IO - V VISO Input clock signal offset voltage variation - 200 - mV VOX (AC) AC differential cross point voltage (VCCIO/2) ­ 0.125 - (VCCIO/2) + 0.125 V Table 4­29. SSTL-2 Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage - 2.375 2.5 2.625 V VTT Termination voltage - VREF ­ 0.04 VREF VREF + 0.04 V VREF Reference voltage - 1.188 1.25 1.313 V VIH (DC) High-level DC input voltage - VREF + 0.18 - 3.0 V VIL (DC) Low-level DC input voltage - ­0.3 - VREF ­ 0.18 V VIH (AC) High-level AC input voltage - VREF + 0.35 - - V VIL (AC) Low-level AC input voltage - - - VREF ­ 0.35 V VOH High-level output voltage IOH = ­8.1 mA (1) VTT + 0.57 - VOL Low-level output voltage IOL = 8.1 mA (1) - - V VTT ­ 0.57 V Note to Table 4­29: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter. Table 4­30. SSTL-2 Class II Specifications (Part 1 of 2) Symbol Parameter Conditions Minimum Typical Maximum Units VCC IO Output supply voltage - 2.375 2.5 2.625 V VTT Termination voltage - VREF ­ 0.04 VREF VREF + 0.04 V VREF Reference voltage - 1.188 1.25 1.313 V VIH (DC) High-level DC input voltage - VREF + 0.18 - VCCIO + 0.3 V Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­21 Table 4­30. SSTL-2 Class II Specifications (Part 2 of 2) Symbol Parameter Conditions Minimum Typical Maximum Units VIL (DC) Low-level DC input voltage - ­0.3 - VREF ­ 0.18 V VIH (AC) High-level AC input voltage - VREF + 0.35 - - V VIL (AC) Low-level AC input voltage - - - VREF ­ 0.35 V VOH High-level output voltage IOH = ­16.4 mA (1) VTT + 0.76 - - V VOL Low-level output voltage I OL = 16.4 mA (1) - - VTT ­ 0.76 V Note to Table 4­30: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter. Table 4­31. SSTL-2 Class I & II Differential Specifications Symbol (Note 1) Parameter Minimum Typical Maximum Units VCCIO Output supply voltage 2.375 2.5 2.625 V VSWING (DC) DC differential input voltage 0.36 - - V VX (AC) AC differential input cross point voltage (VCCIO/2) ­ 0.2 - (VCCIO /2) + 0.2 V VSWING (AC) AC differential input voltage 0.7 - - V VISO Input clock signal offset voltage - 0.5 VCCIO - V VISO Input clock signal offset voltage variation - 200 - mV VOX (AC) AC differential output cross point voltage (VCCIO/2) ­ 0.2 - (VCCIO /2) + 0.2 V Note to Table 4­31: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter. Table 4­32. 1.2-V HSTL Specifications Symbol Parameter Minimum Typical Maximum Units 1.14 1.2 1.26 V VCCIO Output supply voltage VREF Reference voltage 0.48 VCCIO 0.5 VCCIO 0.52 VCCIO V VIH (DC) High-level DC input voltage VREF + 0.08 - VCCIO + 0.15 V VIL (DC) Low-level DC input voltage ­0.15 - VREF ­ 0.08 V VIH (AC) High-level AC input voltage VREF + 0.15 - VCCIO + 0.24 V VIL (AC) Low-level AC input voltage ­0.24 - VREF ­ 0.15 V VOH High-level output voltage VREF + 0.15 - VCCIO + 0.15 V VOL Low-level output voltage ­0.15 - VREF ­ 0.15 V © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 4­22 Chapter 4: DC and Switching Characteristics Operating Conditions Table 4­33. 1.5-V HSTL Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage - 1.425 1.5 1.575 V VREF Input reference voltage - 0.713 0.75 0.788 V VTT Termination voltage - 0.713 0.75 0.788 V VIH (DC) DC high-level input voltage - VREF + 0.1 - - V VIL (DC) DC low-level input voltage - ­0.3 - VREF ­ 0.1 V VIH (AC) AC high-level input voltage - VREF + 0.2 - - V VIL (AC) AC low-level input voltage - - - VREF ­ 0.2 V VOH High-level output voltage IOH = 8 mA (1) VCCIO ­ 0.4 - - V VOL Low-level output voltage IOH = ­8 mA (1) - - 0.4 V Note to Table 4­33: (1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture chapter. Table 4­34. 1.5-V HSTL Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage - 1.425 1.50 1.575 V VREF Input reference voltage - 0.713 0.75 0.788 V VTT Termination voltage - 0.713 0.75 0.788 V VIH (DC) DC high-level input voltage - VREF + 0.1 - - V VIL (DC) DC low-level input voltage - ­0.3 - VREF ­ 0.1 V VIH (AC) AC high-level input voltage - VREF + 0.2 - - V VIL (AC) AC low-level input voltage - - - VREF ­ 0.2 V VOH High-level output voltage IOH = 16 mA (1) VCCIO ­ 0.4 - - V VOL Low-level output voltage I OH = ­16 mA (1) - - 0.4 V Note to Table 4­34: (1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture chapter. Table 4­35. 1.5-V HSTL Class I & II Differential Specifications Symbol Parameter Minimum Typical Maximum Units 1.425 1.5 1.575 V VCCIO I/O supply voltage VDIF (DC) DC input differential voltage 0.2 - - V VCM (DC) DC common mode input voltage 0.68 - 0.9 V VDIF (AC) AC differential input voltage 0.4 - - V VOX (AC) AC differential cross point voltage 0.68 - 0.9 V Arria GX Device Handbook, Volume 1 © December 2009 Altera Corporation Chapter 4: DC and Switching Characteristics Operating Conditions 4­23 Table 4­36. 1.8-V HSTL Class I Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage - 1.71 1.80 1.89 V VREF Input reference voltage - 0.85 0.90 0.95 V VTT Termination voltage - 0.85 0.90 0.95 V VIH (DC) DC high-level input voltage - VREF + 0.1 - - V VIL (DC) DC low-level input voltage - ­0.3 - VREF ­ 0.1 V VIH (AC) AC high-level input voltage - VREF + 0.2 - - V VIL (AC) AC low-level input voltage - - - VREF ­ 0.2 V VOH High-level output voltage IOH = 8 mA (1) VCCIO ­ 0.4 - - V VOL Low-level output voltage IOH = ­8 mA (1) - - 0.4 V Note to Table 4­36: (1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture chapter. Table 4­37. 1.8-V HSTL Class II Specifications Symbol Parameter Conditions Minimum Typical Maximum Units VCCIO Output supply voltage - 1.71 1.80 1.89 V VREF Input reference voltage - 0.85 0.90 0.95 V VTT Termination voltage - 0.85 0.90 0.95 V VIH (DC) DC high-level input voltage - VREF + 0.1 - - V VIL (DC) DC low-level input voltage - ­0.3 - VREF ­ 0.1 V VIH (AC) AC high-level input voltage - VREF + 0.2 - - V VIL (AC) AC low-level input voltage - - - VREF ­ 0.2 V VOH High-level output voltage I OH = 16 mA (1) VCCIO ­ 0.4 - - V VOL Low-level output voltage IOH = ­16 mA (1) - - 0.4 V Note to Table 4­37: (1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook. Table 4­38. 1.8-V HSTL Class I & II Differential Specifications Symbol Parameter Minimum Typical Maximum Units VCCIO I/O supply voltage 1.71 1.80 1.89 V VDIF (DC) DC input differential voltage 0.2 - - V VCM (DC) DC common mode input voltage 0.78 - 1.12 V VDIF (AC) AC differential input voltage 0.4 - - V VOX (AC) AC differential cross point voltage 0.68 - 0.9 V © December 2009 Altera Corporation Arria GX Device Handbook, Volume 1 4­24 Chapter 4: DC and Switching Characteristics Operating Conditions Bus Hold Specifications Table 4­39 shows the Arria GX device family bus hold specifications. Table 4­39. Bus Hold Parameters VC CIO Level Parameter 1.2 V Conditions 1.5 V 1.8 V 2.5 V 3.3 V Units Min Max Min Max Min Max Min Max Min Max Low sustaining current VIN > VIL (maximum) 22.5 - 25 - 30 - 50 - 70 - A High sustaining current VIN < VIH (minimum) ­22.5 - ­25 - ­30 - ­50 - ­70 - A Low overdrive current 0V