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Part Manufacturer Description Datasheet BUY
SN74ACT1071 Texas Instruments DIODE BUS TERMINATION ARRAY, PDSO14, DSO-14 visit Texas Instruments
SN65220YZBT Texas Instruments 60W, UNIDIRECTIONAL, 2 ELEMENT, SILICON, TVS DIODE, GREEN, BGA-4 visit Texas Instruments
SN65220YZBR Texas Instruments 60W, UNIDIRECTIONAL, 2 ELEMENT, SILICON, TVS DIODE, GREEN, BGA-4 visit Texas Instruments
SN74F1018DWR Texas Instruments 18-LINE 50ohm DIODE BUS TERMINATION ARRAY, PDSO24, SOIC-24 visit Texas Instruments
SN74F1056SC Texas Instruments 8-LINE DIODE BUS TERMINATION ARRAY, PSIP10, PLASTIC, SIP-10 visit Texas Instruments
SN74ACT1071DE4 Texas Instruments 10-LINE DIODE BUS TERMINATION ARRAY, PDSO14, GREEN, PLASTIC, SOIC-14 visit Texas Instruments

AE21 ARRAY DIODE

Catalog Datasheet MFG & Type PDF Document Tags

AD 149 AE9

Abstract: AA23 Distributed Networks · Two array clock/control networks available to the logic cell flip-flop clock, set , 3 4 8 10 11 tACK Array Clock Delay 1.2 1.2 1.3 1.3 1.5 1.6 , Global Clock Buffer Delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 a. The array distributed , array clock has up to eight loads per half column. The global clock has up to 11 loads per half column , improperly. An internal diode is present in-between VCC and VCCIO, as shown in Figure 6. V CC Internal
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AE21 ARRAY DIODE

Abstract: QL3060 Distributed Networks · Two array clock/control networks available to the logic cell flip-flop clock, set , 3 4 8 10 11 tACK Array Clock Delay 1.2 1.2 1.3 1.3 1.5 1.6 , Global Clock Buffer Delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 a. The array distributed , array clock has up to eight loads per half column. The global clock has up to 11 loads per half column , improperly. An internal diode is present in-between VCC and VCCIO, as shown in Figure 6. V CC Internal
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diode t25 4 H9

Abstract: diode t25 4 B8 AB22 AF25 AF24 AG24 AE25 AE24 AG23 AD22 AD23 AF23 AB21 AH23 AE22 AE21 AG21 AC22 , AC14 AK25 AL25 AC21 AL26 AK24 AG23 AM25 AD21 AM26 AJ23 AE21 AF21 AH25 AL24 AH22 AF22 , AF21 AB8 AF6 AG7 AC7 AH7 AF7 DQ1B3 DQS1B DQ1B0 AC20 AA21 AB21 AE21 AD20 AD21 AC21 AC20 AA21 AB21 AE21 AD20 AD21 AC21 AD6 AE7 AD5 AH6 AG6 AD7 AE6 Y9 DQ0B7 , -V, 2.5-V, 3.3-V PCI, and 3.3-V PCI-X I/O standards. These are internal logic array voltage supply pins
Altera
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diodes t25 4 l9

Abstract: EPF10K30AB356 integration in a single device ­ Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions ­ Dual-port capability up to 16-bit width per embedded array block (EAB) ­ Logic array for general logic functions Replaces FLEX® 10KB family High density ­ 30,000 to 250 , ), plastic quad flat pack (PQFP), pin-grid array (PGA), and ball-grid array (BGA). Devices in the same , Element MatriX (FLEX) architecture incorporates all features necessary to implement common gate array
Altera
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altera an33 configuring FLEX 8000

Abstract:   â  â  system integration in a single device Enhanced em bedded array for im plem enting , idth per em bedded array block (e a b ) - Logic array for general logic functions Replaces FLEXÂ , array (PGA), and ball-grid array (BGA). (3) Devices in the same package are pin-compatible, although , ) architecture incorporates all features necessary to im plem ent com m on gate array m egafunctions. W ith up , array designs; FLEX 10KE devices can be configured on the board for the specific functionality required
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OCR Scan

Diode D25 N12

Abstract: diode t25 4 H9 AE23 AF22 AH22 AG22 AF20 AD21 AE21 AG21 AF21 AE20 AG20 AB18 AH21 V18 AH20 AE19 AD19 AF19 AG19 AB19 AC21 , AB6 AB5 W5 Y5 AA5 R7 N7 P7 AA4 AB4 Y2 Y4 AA3 AA2 W3 W4 Y3 T7 V4 V3 B672 AF21 AC20 AA21 AE21 AD20 AC21 AB18 F672 AF21 AC20 AA21 AE21 AD20 AC21 AB18 F780 AF7 AD6 AE7 AH6 AG6 AE6 AD9 V11 Y11 AF5 AH5 AF4 AG4 , internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVDS , temperature sensing diode (bias-high input) inside the Stratix device. If the temperature sensing diode is not
Altera
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diode t25 4 L9

Abstract: diode t25 4 H9 AB20 AD21 AE21 DQ9B7 DQ9B6 DQ9B5 DQ9B4 Configuration Function DQS for x16 DQS for x32 , AB20 AF21 AC20 AA21 AE21 AE20 AA20 AB20 AF21 AC20 AA21 AE21 DQ0B15 DQ0B14 DQ0B13 , , 1.5-V, 1.8-V, 2.5-V, 3.3-V PCI, and 3.3-V PCI-X I/O standards. These are internal logic array voltage , . Pin used in conjunction with the temperature sensing diode (bias-high input) inside the Stratix device. If the temperature sensing diode is not used then connect this pin to GND. Pin used in conjunction
Altera
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diode t25 4 L9 diode t25 4 H9 diode t25 4 G9 diode t25 4 j3 diode t25 4 k8 diode t25 4 k6 EP1S20 PT-EP1S20-3

diode t25 4 H9

Abstract: diode t25 4 L9 AD21 AE21 AG21 AF21 AE20 AG20 AB18 AH21 V18 AH20 AE19 AD19 AF19 AG19 AB19 AC21 AC19 , x32 DIFFIO AB19 AB19 AE20 AE20 AA20 AA20 AB20 AF21 AC20 AA21 AE21 AD20 AC21 AB18 AB20 AF21 AC20 AA21 AE21 AD20 AC21 AB18 AE25 AF22 AF24 AE22 AB22 AE23 AC23 , I/O standards. These are internal logic array voltage supply pins. VCCINT also supplies power to , conjunction with the temperature sensing diode (bias-high input) inside the Stratix device. If the
Altera
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diode t25 4 F8 diode t25 4 g8 diode t25 4 B9 diode t25 4 F7 diode t25 4 L8 diode t25 4 e9 EP1S10 PT-EP1S10-3 EP1S10F484

aj24 diode

Abstract: AK19 diode AE25 AE24 AH24 AD24 AG23 AD22 AD23 AF23 AB21 AH23 AE22 AE23 AF22 AB20 AH22 AG22 Y20 AD21 AE21 AG21 AC22 , AB21 AH22 AK22 AC19 AG21 AF24 AH21 AA19 AJ22 AL22 AE21 AJ21 AK21 AE23 AG25 AG20 AE19 AH20 AK20 AD19 AL20 AG23 AG19 AE18 AJ20 AH19 AF20 AJ19 AK19 F1020 AG22 AM25 AB21 AM26 AJ23 AE21 AF21 AH25 AL24 AH22 , , and 3.3-V PCI-X I/O standards. These are internal logic array voltage supply pins. VCCINT also , device. Pin used in conjunction with the temperature sensing diode (bias-high input) inside the Stratix
Altera
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aj24 diode AK19 diode Ak12 diode Diode ak21 AE27 diode ak27 diode EP1S30 PLL10

diode t25 4 k8

Abstract: diode t25 4 L9 AE21 AG21 AF21 AE20 AG20 AF20 AE19 AH21 AD19 AH20 AF19 AD20 AG19 AH19 AF18 AB19 AC21 , AB5 W5 AE20 AA20 AB20 AF21 AC20 AA21 AE21 AE20 AA20 AB20 AF21 AC20 AA21 AE21 , . Dedicated & Configuration/JTAG Pins I/O standards. These are internal logic array voltage supply pins , . Pin used in conjunction with the temperature sensing diode (bias-high input) inside the Stratix TEMPDIODEp Input device. If the temperature sensing diode is not used then connect this pin to GND
Altera
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Diode D25 N12 diode ab24 u25 diode diode t25 4 d7 diode t25 4 j6 diode t25 4 F6

Diode D25 N12

Abstract: diode AA17 AF23 AD22 AH23 AE22 AE23 AF22 AH22 AG22 AF20 AD21 AE21 AG21 AF21 AE20 AG20 AB18 AH21 , Function B672 F672 AB20 AF21 AC20 AA21 AE21 AD20 AC21 AB18 AB20 AF21 AC20 AA21 AE21 , are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for , sensing diode (bias-high input) inside the Stratix device. If the temperature sensing diode is not used then connect this pin to GND. Pin used in conjunction with the temperature sensing diode (bias-low
Altera
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diode AA17 diode AA19 AA12 diode diode M21 DIODE AE12 AF12 diode

diode AA19

Abstract: diode t25 4 g8 AD21 AE21 AG21 AF21 AE20 AG20 AF20 AE19 AH21 AD19 AH20 AF19 AD20 AG19 AH19 AF18 AB19 AC21 AC19 AD18 , AE20 AA20 AB20 AF21 AC20 AA21 AE21 AD20 AE25 AC21 AF22 AD21 F672 AE17 W18 AB17 AA18 AF20 AC17 AD17 AB18 AF18 AE18 AF19 Y20 AA19 AB19 AD19 AC19 AE19 AE20 AA20 AB20 AF21 AC20 AA21 AE21 AD20 AE25 AC21 AF22 AD21 , -V, 3.3-V PCI, and 3.3-V PCI-X I/O standards. These are internal logic array voltage supply pins. VCCINT , device. Pin used in conjunction with the temperature sensing diode (bias-high input) inside the Stratix
Altera
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diode AA16 T4 w4 DIODE diode v6 N9 DSAUTAZ001023.txt EP1S25

diode t25 4 k8

Abstract: diode t25 4 B9 AB14 AA14 AB13 AA13 AF22 AH22 AG22 AF20 AD21 AE21 AG21 AF21 AE20 AG20 AB18 AH21 V18 , AA20 AA20 AB20 AF21 AC20 AA21 AE21 AD20 AC21 AB18 AB20 AF21 AC20 AA21 AE21 AD20 , /JTAG Pins I/O standards. These are internal logic array voltage supply pins. VCCINT also supplies , with the temperature sensing diode (bias-high input) inside the Stratix TEMPDIODEp Input device. If the temperature sensing diode is not used then connect this pin to GND. Pin used in
Altera
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diode t25 4 k5 aa7 diode

QL4058-1PQ240C

Abstract: aldec g2 high-drive input/distributed network pins Eight Low-Skew Distributed Networks · Two array clock/control , Propagation Delays (ns) Fanouta Parameter 1 2 3 4 8 10 11 tACK Array Clock Delay , Global Clock Buffer Delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 a. The array distributed networks consist of , independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has , to VCC/VCCIO earlier than 400 µs can cause the device to behave improperly. An internal diode is
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QL4058 QL4058-1PQ240C aldec g2 PQ208 PQ240 QL4058-1PB456C

CQFP 240

Abstract: aldec g2 high-drive input/distributed network pins Eight Low-Skew Distributed Networks · Two array clock/control , Parameter 1 2 3 4 8 10 11 tACK Array Clock Delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 , 0.8 0.8 0.9 0.9 1.1 1.2 1.3 a. The array distributed networks consist of 40 half columns and the , of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half , behave improperly. An internal diode is present in-between VCC and VCCIO, as shown in Figure 8. V CC
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QL4090 CQFP 240 AD 149 AE9 QL4090-1PB456C QL4090-1PQ208C QL4090-1PQ240C

FIR FILTER implementation in c language

Abstract: PCIH ), providing System-on-a-Programmable-ChipTM integration in a single device ­ Enhanced embedded array for , with up to 16-bit width per embedded array block (EAB) ­ Logic array for general logic functions , flat pack (TQFP), plastic quad flat pack (PQFP), pin-grid array (PGA), and ball-grid array (BGA , array megafunctions. With up to 200,000 gates, FLEX 10KE devices provide the density, speed, and , management for gate array designs and generation of test vectors for fault coverage. Table 5 shows FLEX
Altera
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FIR FILTER implementation in c language PCIH data sheet of preset 10k IBM T21 Data Sheet bga 529 FIR Filter verilog code EPF10K10A EPF10K30A EPF10K50V EPF10K100A EPF10K200E EPF10K200S
Abstract: 10,000 Gate Array Equivalent Gates (up to 25,000 equivalent PLD Gates) P ro d u c t F a m ily P ro file Device A14V15A Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL , 100 200 D rain C u rre n t lo (A ) Forward Voltage of Free Wheeling Diode 5 200 Job , Capacitance, Forward Voltage of Free Wheeling Diode S o u rce - D rain V o ltag e V s d s (V , make up the bulk of the array. This arrangement allows the placement software to support two-module -
OCR Scan
A14V25A A14V40A A14V60A A14V100A

EPF10K50S

Abstract: EPF10K100B system-on-a-programmable-chip integration in a single device ­ Enhanced embedded array for implementing megafunctions such as , embedded array block (EAB) ­ Logic array for general logic functions High density ­ 30,000 to 200,000 , flat pack (PQFP), power quad flat pack (RQFP), pin-grid array (PGA), and ball-grid array (BGA , elements, the FLEX architecture incorporates all features necessary to implement common gate array , array designs and generation of test vectors for fault coverage. Table 5 shows FLEX 10KE performance
Altera
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EPF10K30E EPF10K50E EPF10K50S EPF10K100B EPF10K100E EPF10K130E 800-EPLD

uart verilog code

Abstract: implementation of 8-tap fir filter vhdl System-on-a-Programmable-ChipTM integration in a single device ­ Enhanced embedded array for implementing megafunctions such as , array block (EAB) ­ Logic array for general logic functions High density ­ 30,000 to 200,000 typical , types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), pin-grid array (PGA), and ball-grid array (BGA) packages. Devices in the same package are pin-compatible, although some devices have , features necessary to implement common gate array megafunctions. With up to 200,000 gates, FLEX 10KE
Altera
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uart verilog code implementation of 8-tap fir filter vhdl 256-P 484-P 672-P

em 513 diode

Abstract: , p ro v id in g system integration in a single device E nhanced em b ed d ed array for im p lem , up to 16-bit w id th p er em b ed d ed array block (EAB) Logic array for general logic functions , age ty p es in clu d e thin quad flat pack (TQFP), p lastic quad flat pack (PQFP), p in -grid array (PG A ), and ball-grid array (BGA). D e v ic e s in the sam e p ack age are p in -com p atib le, alth , incorporates all features necessary to im plem ent com m on gate array m egafunctions. W ith u p to 250,000
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OCR Scan
em 513 diode
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