16-BIT DIODE30 ADUC7032-8L SYSSER11 0XFFFF0700 0XFFFF0780 VREF/136 - Datasheet Archive

 

for Automotive System ADuC7032-8L FEATURES Memory 96 kB Flash/EE memory, 6 kB SRAM 10k-cycle Flash/EE endurance, 20-year Flash/EE

 

Integrated Precision Battery Sensor for Automotive System ADuC7032-8L FEATURES Memory 96 kB Flash/EE memory, 6 kB SRAM 10k-cycle Flash/EE endurance, 20-year Flash/EE retention In-circuit download via JTAG and LIN 64 × 16-bit result FIFO for current and voltage ADC On-chip peripherals LIN 1.3- and 2.0-compatible (slave) support via UART with hardware synchronization Flexible wake-up I/O pin, master/slave SPI serial I/O 9-pin GPIO port, 2× general-purpose timers Wake-up and watchdog timers Power supply monitor, on-chip power-on reset Power Operates directly from 12 V battery supply Current consumption Normal mode: 10 mA at 10 MHz Low power monitor mode: 175 A Package and temperature range 48-lead, 7 mm × 7 mm LQFP Fully specified for -40°C to +105°C operation High precision analog-to-digital converters (ADCs) Dual channel, simultaneous sampling, 16-bit - ADCs Third independent ADC for temperature sensing Programmable ADC throughput from 1 Hz to 8 kHz On-chip 5 ppm/°C voltage reference Current channel Fully differential, buffered input Programmable gain: 1 to 512 ADC input range: -200 mV to +300 mV Digital comparators, with current accumulator feature Voltage channel Buffered, on-chip attenuator for 12 V battery inputs Temperature channel External and on-chip temperature sensor options Microcontroller ARM7TDMI core, 16-/32-bit RISC architecture 20.48 MHz PLL with programmable divider PLL input source On-chip precision oscillator On-chip low power oscillator External (32.768 kHz) watch crystal JTAG port supports code download and debug APPLICATIONS Battery sensing/management for automotive systems FUNCTIONAL BLOCK DIAGRAM TCK TDI TDO NTRST TMS PRECISION ANALOG ACQUISITION ADuC7032-8L 16-BIT 16-BIT - ADC PGA IIN­ 2.6V LDO PSM POR MEMORY 96kB FLASH 6kB SRAM 128B ADC FIFO ARM7TDMI ® MCU 20MHz PRECISION OSC (1%) LOW POWER OSC ON-CHIP PLL 2× TIMERS WDT W/U TIMER GPIO PORT UART PORT SPI PORT LIN VBAT RESULT ACCUMULATOR DIGITAL COMPARATOR 16-BIT 16-BIT - ADC BUF VTEMP GPIO_8 GPIO_7 GPIO_6 GPIO_5 GPIO_4 GPIO_0 IO_VSS VSS PRECISION REFERENCE DGND AGND REG_DVDD VDD REG_AVDD VREF TEMPERATURE SENSOR GPIO_3 GND_SW GPIO_2 16-BIT 16-BIT - ADC BUF GPIO_1 MUX RESET XTAL1 XTAL2 WU LIN 05986-001 IIN+ Figure 1. Rev.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. ADuC7032-8L TABLE OF CONTENTS Features . 1 ADuC7032-8L Low Power Clock Calibration. 64 Applications. 1 Processor Reference Peripherals. 66 Functional Block Diagram . 1 Interrupt System . 66 Revision History . 2 Timers . 68 Specifications. 3 Timer0-Lifetime Timer. 69 Electrical Specifications. 3 Timer1. 71 Timing Specifications . 8 Timer2-Wake-Up Timer. 73 Absolute Maximum Ratings. 14 Timer3-Watchdog Timer. 75 ESD Caution. 14 General-Purpose I/O . 77 Pin Configuration and Function Descriptions. 15 High Voltage Peripheral Control Interface . 87 Terminology . 18 WU (Wake-Up) Pin . 93 Theory of Operation . 19 Overview of the ARM7TDMI® Core . 19 Handling Interrupts from the High Voltage Peripheral Control Interface . 94 Memory Organization . 21 Low Voltage Flag (LVF). 94 Reset . 23 High Voltage Diagnostics. 94 Flash/EE Memory and the ADuC7032-8L . 24 UART Serial Interface . 95 Flash/EE Control Interface. 24 Baud Rate Generation. 95 Flash/EE Memory Security . 27 UART Register Definitions . 95 Flash/EE Memory Reliability. 30 Serial Peripheral Interface . 99 Code Execution Time from SRAM and Flash/EE . 30 MISO (Master In, Slave Out Data I/O Pin) . 99 ADuC7032-8L Kernel . 31 MOSI (Master Out, Slave In Pin). 99 Memory Mapped Registers . 33 SCLK (Serial Clock I/O Pin). 99 Complete MMR Listing. 34 Chip Select (SS) Input Pin. 99 16-Bit, Sigma-Delta Analog-to-Digital Converters . 38 SPI Registers Definitions. 99 Current Channel ADC (I-ADC) . 38 LIN (Local Interconnect Network) Interface. 102 Voltage Channel ADC (V-ADC). 39 LIN MMR Description . 102 Temperature Channel ADC (T-ADC). 39 LIN Hardware Interface . 106 ADC Ground Switch. 40 ADuC7032-8L On-Chip Diagnostics . 110 ADC Noise Performance Tables. 41 ADC Diagnostics. 110 ADC MMR Interface . 42 High Voltage I/O Diagnostics. 110 ADC Power Modes of Operation. 53 Part Identification. 111 ADC Diagnostics. 58 ADuC7032-8L Example Schematic . 114 Power Supply Support Circuits. 59 Outline Dimensions . 115 ADuC7032-8L System Clocks . 60 Ordering Guide . 115 REVISION HISTORY 8/07-Revision 0: Initial Version Rev.0 | Page 2 of 116 ADuC7032-8L SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.5 V to 18 V, VREF = 1.2 V internal reference; fCORE = 10.24 MHz, driven from external 32.768 kHz watch crystal or on-chip precision oscillator. All specifications TA = -40°C to +105°C, unless otherwise noted. Table 1. Parameter ADC SPECIFICATIONS Conversion Rate 1 Offset Error1, 3 Offset Error Drift6 Offset Error Drift6 Offset Error Drift6 Total Gain Error1, 3, 7 , 8 , 9 Total Gain Error1, 3, 7, 9, 10 Total Gain Error1, 3, 7, 9 Gain Drift PGA Gain Mismatch Error Output Noise1, 11 Voltage Channel 12 No Missing Codes1 Integral Nonlinearity1 Offset Error1, 3, 5 Offset Error1, 3 Offset Error Drift Total Gain Error1, 3, 7, 13 , 14 Total Gain Error1, 3, 7, 13, 14 Gain Drift Output Noise1, 15 Min Chop off, ADC normal operating mode Chop on, ADC normal operating mode Chop on, ADC low power mode Current Channel No Missing Codes1 Integral Nonlinearity1, 2 Offset Error1, 2 , 3 , 4 , 5 Offset Error2, 3, 4, 6 Offset Error1, 3, 6 Offset Error1, 3 Test Conditions/Comments 4 4 1 Valid for all ADC update rates and ADC modes 16 Chop off, 1 LSB = (36.6/gain) V, after initial offset calibration Chop off, 1 LSB = (36.6/gain) V Chop on Chop on, low power mode or low power plus mode, MCU powered down Chop on, normal mode, CD = 1 Chop off, valid for ADC gains of 4 to 64, normal mode Chop off, valid for ADC gains of 128 to 512, normal mode Chop on Normal mode Low power mode Low power plus mode, using precision VREF -10 -15 -2 0 0 -0.5 -4 -1 4 Hz update rate, gain = 512, chop enabled 10 Hz update rate, gain = 512, chop enabled 1 kHz update rate, gain = 512 1 kHz update rate, gain = 32 1 kHz update rate, gain = 4 8 kHz update rate, gain = 32 8 kHz update rate, gain = 4 ADC low power mode, fADC = 10 Hz, gain = 128 ADC low power mode, fADC = 1 Hz, gain = 128 ADC low power plus mode, fADC = 1 Hz, gain = 512 Valid at all ADC update rates Typ ±0.5 -200 -1.5 0.03 30 10 ±0.1 ±0.2 ±0.2 3 ±0.1 60 100 0.6 0.8 2.0 2.5 14 1.25 0.35 0.1 Unit 8000 2600 650 ±10 ±3 Max Hz Hz Hz ±60 +10 +35 +2 Bits ppm of FSR LSB LSB V -650 -5 +0.5 +4 +1 90 150 0.9 1.2 2.8 3.5 21 1.9 0.5 0.15 16 nV V LSB/°C nV/°C nV/°C % % % ppm/°C % nV rms nV rms V rms V rms V rms V rms V rms V rms V rms V rms ±10 ±1 0.3 0.03 ±60 +10 1 Bits ppm of FSR LSB LSB LSB/°C Chop off, 1 LSB = 439.5 V Chop on Chop off -10 Includes resistor mismatch -0.25 ±0.06 +0.25 % Temperature range = -25°C to +65°C Includes resistor mismatch drift 4 Hz update rate 10 Hz update rate 1 kHz update rate 8 kHz update rate -0.15 ±0.03 3 60 60 180 1600 +0.15 % ppm/°C V rms V rms V rms V rms Rev.0 | Page 3 of 116 90 90 270 2400 ADuC7032-8L Parameter Temperature Channel No Missing Codes1 Integral Nonlinearity1 Offset Error1, 3, 5, 16 , 17 , 18 Offset Error1, 3 Offset Error Drift Total Gain Error1, 3, 14, 17, 18 Gain Drift Output Noise1 ADC SPECIFICATIONS, ANALOG INPUT Current Channel Absolute Input Voltage Range Input Voltage Range 19 , 20 Input Leakage Current1 Input Offset Current1, 22 Voltage Channel Absolute Input Voltage Range Input Voltage Range VBAT Input Current Temperature Channel Absolute Input Voltage Range Input Voltage Range VTEMP Input Current1 VOLTAGE REFERENCE ADC Precision Reference Internal VREF Power-Up Time1 Initial Accuracy1 Internal VREF Temperature Coefficient1, 23 Long-Term Stability 24 External Reference Input Range 25 VREF Divide-by-2 Initial Error1 ADC Low Power Reference Internal VREF Initial Accuracy Initial Accuracy10 Temperature Coefficient1, 23 RESISTIVE ATTENUATOR Divider Ratio Resistor Mismatch Drift ADC GROUND SWITCH Resistance Test Conditions/Comments Min Valid at all ADC update rates 16 Max Unit ±10 ±60 Bits ppm of FSR -10 -5 ±3 1 0.03 +10 +5 LSB LSB LSB/°C -0.25 Chop off, 1 LSB = 19.84 V Chop on Typ ±0.06 3 7.5 +0.25 11.25 % ppm/°C V rms +300 mV +3 1.5 V mV mV mV mV mV mV mV mV mV nA nA 18 V 8 V A 1300 mV 100 V nA +0.15 +20 V ms % ppm/°C 1.3 ppm/ 1000 hr V 0.3 % 1 kHz update rate Internal VREF = 1.2 V Applies to both IIN+ and IIN- -200 Gain = 1 21 Gain = 221 Gain = 421 Gain = 8 Gain = 16 Gain = 32 Gain = 64 Gain = 128 Gain = 256 Gain = 512 ±1.2 ±600 ±300 ±150 ±75 ±37.5 ±18.75 ±9.375 ±4.68 ±2.3 -3 0.5 4 VBAT = 18 V 3 0 to 28.8 5.5 100 0 to VREF 2.5 1.2 0.5 Measured at TA = 35°C -0.15 -20 ±5 100 0.1 0.1 1.2 Measured at TA = 35°C Using ADCREF, measured at TA = 35°C -5 +5 0.1 -300 +300 24 3 Direct path to ground 20 k resistor selected 10 Input Current Rev.0 | Page 4 of 116 10 20 V % % ppm/°C ppm/°C 30 6 k mA ADuC7032-8L Parameter TEMPERATURE SENSOR1, 26 Accuracy POWER-ON RESET (POR) POR Trip Level POR Hysteresis Reset Timeout from POR LOW VOLTAGE FLAG (LVF) LVF Level POWER SUPPLY MONITOR (PSM) PSM Trip Level WATCHDOG TIMER (WDT) Timeout Period1 Timeout Step Size FLASH/EE MEMORY1 Endurance 27 Data Retention 28 DIGITAL INPUTS Input Leakage Current Input Pull-Up Current Input Capacitance Input Leakage Current Input Pull-Down Current LOGIC INPUTS1 Input Low Voltage (VINL) Input High Voltage (VINH) CRYSTAL OSCILLATOR1 Logic Inputs, XTAL1 Only Input Low Voltage (VINL) Input High Voltage (VINH) XTAL1 Capacitance XTAL2 Capacitance ON-CHIP OSCILLATORS Low Power Oscillator Accuracy 29 Precision Oscillator Accuracy MCU CLOCK RATE MCU START-UP TIME At Power-On After Reset Event From MCU Power-Down Oscillator Running Wake-Up from Interrupt Wake-Up from LIN Crystal Powered Down Wake-Up from Interrupt Internal PLL Lock Time Test Conditions/Comments Min MCU in power-down or standby mode; temperature range = -40°C to -30°C MCU in power-down or standby mode; temperature range = -30°C to -16°C MCU in power-down or standby mode; temperature range = -16°C to +40°C MCU in power-down or standby mode; temperature range = +40°C to +70°C MCU in power-down or standby mode; temperature range = +70°C to +85°C MCU in power-down or standby mode; temperature range = +85°C to +105°C Refers to voltage at VDD pin 2.85 Refers to voltage at VDD pin 1.9 Max Unit -4 +4 °C -3 +3 °C -2 +2 °C -4 +4 °C -8 +8 °C -12 +12 °C 3.0 300 20 3.15 V mV ms 2.1 2.3 V Refers to voltage at VDD pin Typ 6.0 32.768 kHz clock, 256 prescale 0.008 V 512 7.8 10,000 20 All digital inputs except NTRST Input (high) = REG_DVDD Input (low) = 0 V -10 -80 NTRST only: input (low) = 0 V NTRST only: input (high) = REG_DVDD All logic inputs -10 30 sec ms Cycles Years ±1 -20 10 ±1 55 +10 -10 +10 100 A A pF A A 0.4 V V 0.8 V V pF pF 2.0 1.7 12 12 131.072 Includes drift data from 1000 hr life test -3 Includes drift data from 1000 hr life test Eight programmable core clock selections within this range (binary divisions 1, 2, 4, 8. . .64, 128) -1 0.160 +3 131.072 Includes kernel power-on execution time Includes kernel power-on execution time 10.24 +1 20.48 kHz % kHz % MHz ms ms 2 2 ms ms 500 1 Rev.0 | Page 5 of 116 25 5 ms ms ADuC7032-8L Parameter LIN I/O GENERAL Baud Rate VDD Input Capacitance LIN Comparator Response Time1 ILIN DOM MAX Test Conditions/Comments Min Supply voltage range at which the LIN interface is functional Typ 1000 7 Unit 20,000 18 5.5 38 Using 22 resistor Max 90 Bits/sec V pF s 40 200 mA ILIN_PAS_REC Current limit for driver when LIN bus is in dominant state; VBAT = VBAT(MAX) Driver off; 7.0 V < VBUS < 18 V; VDD = VLIN - 0.7 V -20 +20 A ILIN_PAS_DOM1 Input leakage VLIN = 0 V -1 Control unit disconnected from ground, GND = VDD; 0 V < VLIN < 18 V; VBAT = 12 V LIN receiver dominant state, VDD > 7.0 V -1 VLIN_REC1 LIN receiver recessive state, VDD > 7.0 V 0.6 VDD VLIN_CNT1 LIN receiver center voltage, VDD > 7.0 V 0.475 VDD VHYS1 LIN receiver hysteresis voltage VLIN_DOM_DRV_LOSUP1 LIN dominant output voltage; VDD = 7.0 V ILIN_NO_GND VLIN_DOM 30 1 mA +1 0.4 VDD 0.5 VDD V V 1.2 V 0.6 V LIN dominant output voltage; VDD = 18 V RL 500 2 RL 1000 VLIN_RECESSIVE 0.525 VDD 0.175 VDD RL 1000 V V V RL 500 1 LIN_DOM_DRV_HISUP mA V 0.8 VBAT Shift30 V 0.8 VDD LIN recessive output voltage V 0 30 GND Shift 0.1 VDD 0 V 0.1 VDD RSLAVE Slave termination resistance 20 29 VSERIAL DIODE30 DIODE30 Voltage drop at the serial diode, DSer_Int 0.4 0.7 Transmit Propagation Delay1 VDDMIN = 7 V V 47 k 1 V 4 s Bus load conditions (CBUS||RBUS): 1 nF||1 k; 6.8 nF||660 ; 10 nF||500 Symmetry of Transmit Propagation Delay1 VDDMIN = 7 V Receive Propagation Delay1 VDDMIN = 7 V -2 +2 s 6 s +2 s 3 V/s 3 +5 +4 V/s s s Symmetry of Receive Propagation Delay1 LIN v.1.3 SPECIFICATION dV dt dV dt 1 1 tSYM1 LIN 2.0 SPECIFICATION D1 D2 VDDMIN = 7 V -2 Bus load conditions (CBUS||RBUS): 1 nF||1 k ; 6.8 nF||660 ; 10 nF||500 Slew rate Dominant and recessive edges, VBAT = 18 V 1 2 Slew rate Dominant and recessive edges, VBAT = 7 V Symmetry of rising and falling edge, VBAT = 18 V Symmetry of rising and falling edge, VBAT = 7 V Bus load conditions ( CBUS||RBUS ): 1 nF||1 k; 6.8 nF||660 ; 10 nF||500 Duty Cycle 1 THREC(MAX) = 0.744 × VBAT, THDOM(MAX) = 0.581 × VBAT, VSUP = 7.0 V.18 V; tBIT = 50 s, D1 = tBUS_REC(MIN)/(2 × tBIT) Duty Cycle 2 THREC(MIN) = 0.284 × VBAT, THDOM(MIN) = 0.422 × VBAT, VSUP = 7.0 V.18 V; tBIT = 50 s, D2 = tBUS_REC(MAX)/(2 × tBIT ) Rev.0 | Page 6 of 116 0.5 -5 -4 0.396 0.581 ADuC7032-8L Parameter PACKAGE THERMAL SPECIFICATIONS Thermal Shutdown 31 Thermal Impedance (JA) 32 POWER REQUIREMENTS Power Supply Voltages VDD (Battery Supply) REG_DVDD, REG_AVDD 33 Power Consumption IDD (MCU Normal Mode) 34 IDD (MCU Powered Down)1 IDD (Current ADC) IDD (Voltage/Temperature ADC) IDD (Precision Oscillator) Test Conditions/Comments Min Typ Max Unit 140 150 160 °C 48-lead LQFP, stacked die Top die Bottom die 50 25 3.5 2.5 MCU clock rate = 10.24 MHz, ADC off MCU clock rate = 20.48 MHz, ADC off ADC low power mode, measured over an ambient temperature range of -10°C to +40°C (continuous ADC conversion) ADC low power mode, measured over an ambient temperature range of -40°C to +85°C (continuous ADC conversion) ADC low power plus mode, measured over an ambient temperature range of -10°C to +40°C (continuous ADC conversion) Average current, measured with wake-up and watchdog timer clocked from low power oscillator (-40°C to +85°C) Average current, measured with wake-up and watchdog timer clocked from low power oscillator over an ambient temperature range of -10°C to +40°C °C/W °C/W 2.6 18 2.7 V V 10 20 300 20 30 400 mA mA A 300 500 A 520 700 A 120 300 A 120 175 A 1.7 0.5 1 mA mA 400 Per ADC A Not guaranteed by production test, but by design and/or characterization data at production release. Valid for current ADC gain setting of PGA = 4 to 64. These numbers include temperature drift. 4 Tested at gain range = 4; self-offset calibration removes this error. 5 Measured with an internal short after an initial offset calibration. 6 Measured with an internal short. 7 Includes internal reference temperature drift. 8 Factory calibrated at gain = 1. 9 System calibration at specific gain range removes the error at this gain range at that temperature. 10 Valid when used in conjunction with the ADCREF (the low power mode reference error) MMR. 11 Typical noise in low power modes is measured with chop enabled. 12 Voltage channel specifications include resistive attenuator input stage. 13 Includes an initial system calibration. 14 System calibration removes this error at that temperature. 15 RMS noise is referred to voltage attenuator input. For example, at fADC = 1 kHz, typical rms noise at the ADC input is 7.5 V, which, when scaled by the attenuator (24), yields these input referred noise figures. 16 ADC self-offset calibration removes this error. 17 Valid after an initial self-calibration. 18 Factory calibrated for the internal temperature sensor during final production test. 19 In ADC low power mode, the input range is fixed at ±9.375 mV. In ADC low power plus mode, the input range is fixed at ±2.34375 mV. 20 It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. This approach can also be used to reduce the ADC input range (LSB size). 21 Limited by minimum/maximum absolute input voltage range. 22 Valid for a differential input less than 10 mV. 23 Measured using box method. 24 The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period. 25 References of up to REG_AVDD can be accommodated by enabling an internal divide-by-2. 26 Die temperature. 27 Endurance is qualified to 10,000 cycles, as per JEDEC Std. 22 Method A117, and measured at -40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles. 28 Retention lifetime equivalent at junction temperature (TJ) = 85°C, as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature. 29 Low power oscillator can be calibrated against either the precision oscillator or the external 32.768 kHz crystal in user code. 30 These numbers are not production tested but are supported by LIN compliance testing. 31 The MCU core is not shut down, but an interrupt is generated, if enabled. 32 Thermal impedance can be used to calculate the thermal gradient from ambient to die temperature. 33 Internal regulated supply available at REG_DVDD (ISOURCE = 5 mA) and REG_AVDD (ISOURCE = 1 mA). 34 Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively. 2 3 Rev.0 | Page 7 of 116 ADuC7032-8L TIMING SPECIFICATIONS SPI Timing Specifications Table 2. SPI Master Mode Timing (PHASE Mode = 1) Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF 2 Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max (2 × tUCLK) + (2 × tHCLK) 0 3 × tUCLK 3.5 3.5 3.5 3.5 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDF MSB MOSI MISO tDR MSB IN tDSU BITS[6:1] BITS[6:1] LSB LSB IN 05986-002 1 Description SCLK low pulse width 1 SCLK high pulse width1 Data output valid after SCLK edge 2 Data input setup time before SCLK edge Data input hold time after SCLK edge2 Data output fall time Data output rise time SCLK rise time SCLK fall time tDHD Figure 2. SPI Master Mode Timing (PHASE Mode = 1) Rev.0 | Page 8 of 116 Unit ns ns ns ns ns ns ns ns ns ADuC7032-8L Table 3. SPI Master Mode Timing (PHASE Mode = 0) Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF 2 Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max (2 × tUCLK) + (2 × tHCLK) ½ tSL 0 3 × tUCLK 3.5 3.5 3.5 3.5 tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDF tDOSU MSB MOSI MISO MSB IN tDSU tDR BITS[6:1] BITS[6:1] LSB LSB IN 05986-003 1 Description SCLK low pulse width 1 SCLK high pulse width1 Data output valid after SCLK edge 2 Data output setup time before SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge2 Data output fall time Data output rise time SCLK rise time SCLK fall time tDHD Figure 3. SPI Master Mode Timing (PHASE Mode = 0) Rev.0 | Page 9 of 116 Unit ns ns ns ns ns ns ns ns ns ns ADuC7032-8L Table 4. SPI Slave Mode Timing (PHASE Mode = 1) Parameter tSS Description SS to SCLK edge tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS SCLK low pulse width1 SCLK high pulse width1 Data output valid after SCLK edge2 Data input setup time before SCLK edge Data input hold time after SCLK edge2 Data output fall time Data output rise time SCLK rise time SCLK fall time SS high after SCLK edge 2 Typ ½ tSL Max Unit ns (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK (3 × tUCLK) + (2 × tHCLK) 0 4 × tUCLK 3.5 3.5 3.5 3.5 ½ tSL tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. SS tSFS tCS SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDF MISO MOSI tDR MSB MSB IN tDSU BITS[6:1] BITS[6:1] tDHD Figure 4. SPI Slave Mode Timing (PHASE Mode = 1) Rev.0 | Page 10 of 116 LSB LSB IN 05986-004 1 Min ns ns ns ns ns ns ns ns ns ns ADuC7032-8L Table 5. SPI Slave Mode Timing (PHASE Mode = 0) Parameter tSS Description SS to SCLK edge tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS SCLK low pulse width1 SCLK high pulse width1 Data output valid after SCLK edge2 Data input setup time before SCLK edge Data input hold time after SCLK edge2 Data output fall time Data output rise time SCLK rise time SCLK fall time Data output valid after SS edge2 SS high after SCLK edge 2 Typ ½ tSL Max Unit ns (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK (3 × tUCLK) + (2 × tHCLK) 0 4 × tUCLK 3.5 3.5 3.5 3.5 (3 × tUCLK) + (2 × tHCLK) ½ tSL tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. tUCLK = 48.8 ns. It corresponds to the 20.48 MHz internal clock from the PLL before the clock divider. SS tSFS tSS SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDOCS tDF MSB MISO MOSI MSB IN tDSU tDR BITS[6:1] BITS[6:1] LSB LSB IN 05986-005 1 Min tDHD Figure 5. SPI Slave Mode Timing (PHASE Mode = 0) Rev.0 | Page 11 of 116 ns ns ns ns ns ns ns ns ns ns ns ADuC7032-8L LIN Timing Specifications TxD (INPUT TO TRANSCEIVER FROM CONTROLLER) tTRANS_PDF tTRANS_PDR BUS SIGNAL RECEIVING THRESHOLD tREC_PDF (MEASURED FROM POINT WHEN THE tREC_PDR SWITCHING THRESHOLD IS SURPASSED) RxD (OUTPUT OF TRANSCEIVER TO CONTROLLER) tFALL_60% tFALL_40% tRISE_40% tRISE_60% VSUP VBUSREC 60% VSWING 40% GND TIME tSLOPE_FALL tSLOPE_RISE Figure 6. LIN v.1.3 Timing Specifications Rev.0 | Page 12 of 116 05986-006 VBUSDOM ADuC7032-8L RECESSIVE tBIT tBIT tBIT TRANSMIT INPUT TO TRANSMITTING NODE DOMINANT tLIN_DOM (MAX) tLIN_REC (MIN) THRESHOLDS OF RECEIVING NODE 1 THREC (MAX) THDOM (MAX) VSUP LIN BUS (TRANSCEIVER SUPPLY OF TRANSMITTING NODE) THRESHOLDS OF RECEIVING NODE 2 THREC (MIN) THDOM (MIN) tLIN_DOM (MIN) tLIN_REC (MAX) RxD (OUTPUT OF RECEIVING NODE 1) tRX_PDF tRX_PDR tRX_PDR Figure 7. LIN 2.0 Timing Specifications Rev.0 | Page 13 of 116 tRX_PDF 05986-007 RxD (OUTPUT OF RECEIVING NODE 2) ADuC7032-8L ABSOLUTE MAXIMUM RATINGS TA = -40°C to +105°C, unless otherwise noted. Table 6. Parameter AGND to DGND to VSS to IO_VSS VBAT to AGND VDD to VSS VDD to VSS for 1 sec LIN to IO_VSS WU to IO_VSS WU Continuous Current High Voltage I/O Pins Short-Circuit Current Digital I/O Voltage to DGND VREF to AGND ADC Inputs to AGND Storage Temperature Junction Temperature (Transient) Junction Temperature (Continuous) Lead Temperature Soldering Reflow (15 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating -0.3 V to +0.3 V -22 V to +40 V -0.3 V to +33 V -0.3 V to +40 V -16 V to +40 V -3 V to +33 V 50 mA 100 mA ESD CAUTION -0.3 V to REG_DVDD + 0.3 V -0.3 V to REG_AVDD + 0.3 V -0.3 V to REG_AVDD + 0.3 V 130°C 150°C 130°C 260°C Rev.0 | Page 14 of 116 ADuC7032-8L RESET 1 GPIO_5/IRQ1/RxD 2 37 XTAL2 38 NC 39 NC 40 NC 41 WU 42 VDD 43 NC 44 VSS 45 NC 46 RESERVED 47 IO_VSS 48 LIN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 IDENTIFIER 36 XTAL1 35 DGND GPIO_6/TxD 3 34 DGND GPIO_7/IRQ4 4 33 REG_DVDD GPIO_8/IRQ5 5 32 NC ADuC7032-8L TCK 6 31 GPIO_4/ECLK TOP VIEW (Not to Scale) TDI 7 DGND 8 30 GPIO_3/MOSI 29 GPIO_2/MISO NC 9 28 GPIO_1/SCLK TDO 10 27 GPIO_0/IRQ0/SS 05986-008 NC = NO CONNECT REG_AVDD 24 NC 23 AGND 22 AGND 21 IIN­ 20 IIN+ 19 VTEMP 18 NC 17 NC 16 GND_SW 15 25 NC VREF 14 26 NC TMS 12 VBAT 13 NTRST 11 Figure 8. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic RESET Type 1 I 2 GPIO_5/IRQ1/RxD I/O 3 GPIO_6/TxD I/O 4 GPIO_7/IRQ4 I/O 5 GPIO_8/IRQ5 I/O Description Reset Input Pin, Active Low. This pin has an internal, weak, pull-up resistor to REG_DVDD. When not in use, this pin remains unconnected. For added security and robustness, it is recommended that this pin be strapped, via a resistor, to REG_DVDD. General-Purpose Digital Input/Output 5, External Interrupt Request 1, or Receive Data. By default and after power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it can be left unconnected. This multifunction pin can be configured in one of three states, namely General-Purpose Digital I/O 5. External Interrupt Request 1, active high. Receive data for UART serial port. This pin can also be used as a clock input to Timer1. General-Purpose Digital Input/Output 6 or Transmit Data. By default and after power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it can be left unconnected. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 6. Transmit data for UART serial port. General-Purpose Digital Input/Output 7 or External Interrupt Request 4. By default and after power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it can be left unconnected. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 7. External Interrupt Request 4, active high. General-Purpose Digital Input/Output 8 or External Interrupt Request 5. By default and after power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it can be left unconnected. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 8. External Interrupt Request 5, active high. This pin can also be used as a clock input to Timer1. Rev.0 | Page 15 of 116 ADuC7032-8L Pin No. 6 Mnemonic TCK Type 1 I 7 TDI I 8, 34, 35 9, 16, 17, 23, 25, 26, 32, 38, 39, 40, 43, 45 10 DGND NC S TDO O 11 NTRST I 12 TMS I 13 14 VBAT VREF I I 15 GND_SW S 18 19 20 21, 22 24 27 VTEMP IIN+ IIN- AGND REG_AVDD GPIO_0/IRQ0/SS I I I S S I/O 28 GPIO_1/SCLK I/O 29 GPIO_2/MIS0 I/O 30 GPIO_3/MOSI I/O 31 GPIO_4/ECLK I/O 33 REG_DVDD S Description JTAG Test Clock. This clock input pin is one of the standard 5-pin JTAG debug ports on the part. It is an input pin only, and it has an internal, weak, pull-up resistor. When not in use, this pin remains unconnected. JTAG Test Data Input. This data input pin is one of the standard 5-pin JTAG debug ports on the part. It is an input pin only, and it has an internal, weak, pull-up resistor. When not in use, this pin remains unconnected. Ground Reference for On-Chip Digital Circuits. No Connect. This pin is not connected internally but is reserved for possible future use. Therefore, this pin should not be connected externally. NC pins can be grounded, if required. JTAG Test Data Output. This data output pin is one of the standard 5-pin JTAG debug ports on the part. It is an output pin only. At power-on, this output is disabled and pulled high via an internal, weak, pull-up resistor. When not in use, this pin remains unconnected. JTAG Test Reset. This reset input pin is one of the standard 5-pin JTAG debug ports on the part. It is an input pin only, and it has an internal, weak, pull-down resistor. When not in use, this pin remains unconnected. It is also monitored by the on-chip kernel to enable LIN boot load mode. JTAG Test Mode Select. This mode select input pin is one of the standard 5-pin JTAG debug ports on the part. It is an input pin only, and it has an internal, weak, pull-up resistor. When not in use, this pin remains unconnected. Battery Voltage Input to Resistor Divider. External Reference Input Terminal. If this input is not used, connect it directly to the AGND system ground. Switch to Internal Analog Ground Reference. Negative input for external temperature channel and external reference. If this input is not used, connect it directly to the AGND system ground. External Pin for NTC/PTC Temperature Measurement. Positive Differential Input for Current Channel. Negative Differential Input for Current Channel. Ground Reference for On-Chip Precision Analog Circuits. Nominal 2.6 V Output from On-Chip Regulator. General-Purpose Digital I/O 0, External Interrupt Request 0, or SPI Interface. By default and after power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it remains unconnected. This multifunction pin can be configured in one of three states, namely General-Purpose Digital I/O 0. External Interrupt Request 0, active high. SPI interface, slave select input. General-Purpose Digital I/O 1 or SPI Interface. By default and after power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it remains unconnected. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 1. SPI interface, serial clock input. General-Purpose Digital I/O 2 or SPI Interface. By default and after power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it remains unconnected.This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 2. SPI interface, master input/slave output pin. General-Purpose Digital I/O 3 or SPI Interface. By default and after power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it remains unconnected. This multifunction pin can be configured in one of two states, namely General-Purpose Digital I/O 3. SPI interface, master output/slave input pin. General-Purpose Digital I/O 4 or Clock Output. By default and after power-on reset, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, it remains unconnected. This programmable digital I/O pin can also be configured to output a 2.56 MHz clock. Nominal 2.6 V Output from the On-Chip Regulator. Rev.0 | Page 16 of 116 ADuC7032-8L Pin No. 36 37 Mnemonic XTAL1 XTAL2 Type 1 O I 41 42 44 46 WU VDD VSS RESERVED O S S 47 48 IO_VSS LIN S I/O 1 Description Crystal Oscillator Output. If an external crystal is not in use, this pin remains unconnected. Crystal Oscillator Input. If an external crystal is not in use, connect this pin to the DGND system ground. High Voltage Wake-Up Transmit Pin. When not in use, this pin remains unconnected. Battery Power Supply to On-Chip Regulator. Ground Reference for the Internal Voltage Regulators. Reserved for High Voltage Output Only Functionality. This pin should be connected externally to the IO_VSS ground reference. Ground Reference for High Voltage Input/Output Pins. LIN Serial Interface Input/Output Pin. I = input, O = output, S = supply. Rev.0 | Page 17 of 116 ADuC7032-8L TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, once the ADC has settled. The - conversion techniques used on this part mean that while the ADC front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is employed to decimate the output to give a valid 16-bit data conversion result at output rates from 1 Hz to 8 kHz. Note that when software switches from one input to another (on the same ADC), the digital filter must first be cleared and then allowed to average a new result. Depending on the configuration of the ADC and the type of filter, this can take multiple conversion cycles. Integral Nonlinearity (INL) Integral nonlinearity is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition; and full scale, a point 0.5 LSB above the last code transition (111 . . . 110 to 111 . . . 111). The error is expressed as a percentage of full scale. No Missing Codes No missing codes is a measure of the differential nonlinearity of the ADC. The error is expressed in bits and specifies the number of codes (ADC results) as 2N bits, where N = no missing codes, guaranteed to occur through the full ADC input range. Offset Error Offset error is the deviation of the first code transition ADC input voltage from the ideal first code transition. Offset Error Drift Offset error drift is the variation in absolute offset error with respect to temperature. This error is expressed as LSBs per °C. Gain Error Gain error is a measure of the span error of the ADC. It is a measure of the difference between the measured span and the ideal span between any two points in the transfer function. Output Noise Output noise is the standard deviation (or 1 × ) of ADC output codes distribution collected when the ADC input voltage is at a dc voltage. It is expressed as micro root mean square ( rms). The output or rms noise can be used to calculate the effective resolution of the ADC, as defined by the following equation: Effective Resolution = log2(Full-Scale Range/rms Noise) bits The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 × of the distribution of ADC output codes collected when the ADC input voltage is at dc. The peak-topeak noise is, therefore, calculated as 6.6 × the rms noise. The peak-to-peak noise can be used to calculate the ADC (noise free, code) resolution for which there is no code flicker within a 6.6 sigma limit, as defined by the following equation: Noise Free Code Resolution = log2(Full-Scale Range/ Peak-to-Peak Noise) bits Table 8. Data Sheet Acronyms Acronym ADC ARM ECU JTAG LDO LIN LSB LVF MAC MCU MMR MSB PID PLL POR PSM rms Rev.0 | Page 18 of 116 Definition analog-to-digital converter advanced RISC machine electronic control unit joint test action group low dropout local interconnect network least significant byte/bit low voltage flag multiplication accumulation microcontroller memory mapped register most significant byte/bit protected identifier phase-locked loop power-on reset power supply monitor root mean square ADuC7032-8L THEORY OF OPERATION The ADuC7032-8L is a complete system solution for battery monitoring in 12 V automotive applications. The device integrates all of the required features to precisely and intelligently monitor, process, and diagnose 12 V battery parameters, including battery current, voltage, and temperature, over a wide range of operating conditions. Minimizing external system components, the device is powered directly from the 12 V battery. An on-chip, low dropout (LDO) regulator generates the supply voltage for the three integrated 16-bit ADCs. The ADCs precisely measure battery current, voltage, and temperature, which can be used to characterize the state of health and charge of a car battery. A Flash/EE memory-based ARM7TM microcontroller (MCU) is also integrated on-chip and is used both to preprocess the acquired battery variables and to manage communications from the ADuC7032-8L to the main electronic control unit (ECU) via a local interconnect network (LIN) interface, which is integrated on-chip. Both the MCU and the ADC subsystem can be individually configured to operate in normal or flexible power saving modes of operation. In its normal operating mode, the MCU is clocked indirectly from an on-chip oscillator via the phase-locked loop (PLL) at a maximum clock rate of 20.48 MHz. In its power-saving operating modes, the MCU can be totally powered down, waking up only in response to an ADC conversion result ready, digital comparators, the wake-up timer, a power-on reset (POR), or an external serial communication event. The ADC can be configured to operate in a normal (full-power) mode of operation, interrupting the MCU after various sample conversion events. The current channel features two low power modes: low power and low power plus, generating conversion results to a lower performance specification. On-chip factory firmware supports in-circuit Flash/EE memory reprogramming via the LIN or JTAG serial interface ports, and nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStartTM Plus development system supporting the ADuC7032-8L. The ADuC7032-8L operates directly from the 12 V battery supply and is fully specified over a temperature range of -40°C to +105°C. The ADuC7032-8L is functional, with degraded performance, at temperatures from 105°C to 125°C. OVERVIEW OF THE ARM7TDMI® CORE The ARM7 core is a 32-bit reduced instruction set computer (RISC), developed by ARM Ltd. The ARM7TDMI is a von Neumann-based architecture, which means that it uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16, or 32 bits; and the length of the instruction word is either 16 bits or 32 bits, depending on the mode in which the core is operating. The ARM7TDMI is an ARM7 core with four additional features, as listed in Table 9. Table 9. ARM7TDMI Features Feature T D M I Description Support for the Thumb® (16-bit) instruction set Support for debug Enhanced multiplier Includes the EmbeddedICETM module to support embedded system debugging Thumb Mode (T) An ARM® instruction is 32 bits long. The ARM7TDMI processor supports the Thumb instruction set, which has been compressed into 16 bits. Faster code execution from 16-bit memory and greater code density can be achieved by using the Thumb instruction set, which makes the ARM7TDMI core particularly suited for embedded applications. However, Thumb mode has three limitations. · · · Relative to ARM, Thumb code usually requires more instructions to perform that same task. Therefore, in most applications ARM code is best used for maximizing the performance of time-critical code. The Thumb instruction set does not include some instructions that are needed for exception handling. Therefore, ARM code may be required for exception handling. When an interrupt occurs, the core vectors to the interrupt location in memory and executes the code present at this address. It is required that the first command be in ARM code. Multiplier (M) The ARM7TDMI instruction set includes an enhanced multiplier, with four extra instructions that perform 32-bit × 32-bit multiplication with a 64-bit result and 32-bit × 32-bit multiplication-accumulation (MAC) with a 64-bit result. Rev.0 | Page 19 of 116 ADuC7032-8L EmbeddedICE (I) ARM Registers The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers, which allow nonintrusive user code debugging. These registers are controlled through the JTAG test port. The ARM7TDMI has 16 standard registers. R0 to R12 are used for data manipulation, R13 is the stack pointer, R14 is the link register, and R15 is the program counter that indicates the instruction currently being executed. The link register contains the address from which the user has branched, if the branch and link command was used, or the command during which an exception occurred. ARM7 Exceptions The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions follow: · · · · · Normal interrupt or IRQ. It is provided to service generalpurpose interrupt handling of internal and external events. Fast interrupt or FIQ. It is provided to service data transfer or a communication channel with low latency. FIQ has priority over IRQ. Memory abort (prefetch and data). Attempted execution of an undefined instruction. Software interrupt (SWI) instruction. It can be used to make a call to an operating system. Typically, the programmer defines interrupts as IRQ; but for higher priority interrupts, the programmer can define interrupts as being of the FIQ type. The priority of the above exceptions and vector addresses are shown in Table 10. Table 10. Exception Priority Priority 1 2 3 4 5 6 6 1 Exception Hardware reset Memory abort (data) FIQ IRQ Memory abort (prefetch) Software interrupt1 Undefined instruction1 The stack pointer (R13) contains the current location of the stack. Typically on an ARM7TDMI, the stack starts at the top of the available RAM area and descends, using the area as required. A separate stack is defined for each exception. The size of each stack is user configurable and is dependent on the target application. On the ADuC7032-8L, the stack begins at 0x000417FC and descends. When programming using a high level language such as C, it is necessary to ensure that the stack does not overflow. This is dependent on the performance of the compiler that is used. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14), as represented in Figure 9. The FIQ mode has more registers (R8 to R12), supporting faster interrupt processing. With the increased number of noncritical registers, the interrupt can be processed without the need to save or restore these registers, reducing the response time of the interrupt handling process. More information relative to the programmer's model and the ARM7TDMI core architecture can be found in ARM7TDMI technical and ARM architecture manuals available directly from ARM Ltd. Vector Address 0x00 0x10 0x1C 0x18 0x0C 0x04 0x04 R0 USABLE IN USER MODE R1 SYSTEM MODES ONLY R2 R3 R4 R5 R6 R7 R8 R9 A software interrupt and an undefined instruction exception have the same priority and are mutually exclusive. R10 R11 The exceptions in Table 10 are located from Address 0x00 to Address 0x1C, with a reserved location at 0x14. This location is required to be written with either 0x27011970 or the checksum of Page 0, excluding Location 0x14. If this is not done, user code is not executed, and LIN download mode is entered. R12 R13 R14 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_IRQ R13_ABT R14_IRQ R14_ABT R13_UND R14_UND R15 (PC) CPSR USER MODE SPSR_FIQ FIQ MODE SPSR_SVC SVC MODE SPSR_ABT SPSR_IRQ ABORT MODE Figure 9. Register Organization Rev.0 | Page 20 of 116 IRQ MODE SPSR_UND UNDEFINED MODE 05986-009 When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers may be interrogated, as well as the Flash/EE, the SRAM, and the memory mapped registers. ADuC7032-8L Interrupt Latency RESERVED The worst-case latency for an FIQ consists of the following: · · At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, or just over 2.44 s in a system using a continuous 20.48 MHz processor clock. The maximum IRQ latency calculation is similar, but it must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used; some compilers have an option to compile without using this command. Another option is to run the part in Thumb mode, where the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is five cycles. It consists of the shortest time the request can take through the synchronizer, plus the time to enter the exception mode. RESERVED 0x00097FFF FLASH/EE 0x00080000 RESERVED 0x00417FF 0x00040000 SRAM RESERVED 0x0017FFF REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM) 0x00000000 Figure 10. ADuC7032-8L Memory Map Memory Format The ADuC7032-8L memory organization is configured in little endian format: the least significant byte is located in the lowest byte address, and the most significant byte is located in the highest byte address. BIT 31 BIT 0 BYTE 3 . . . BYTE 2 . . . BYTE 1 . . . BYTE 0 . . . B A 9 8 7 6 5 4 0x00000004 3 Note that the ARM7TDMI initially (first instruction) runs in ARM (32-bit) mode when an exception occurs. The user can immediately switch from ARM mode to Thumb mode, if required (for example, when executing interrupt service routines). 2 1 0 0x00000000 0xFFFFFFFF 32 BITS Figure 11. Little Endian Format MEMORY ORGANIZATION The ARM7 (a von Neumann architecture) MCU core sees memory as a linear array of 232 byte locations. As shown in Figure 10, the ADuC7032-8L maps this memory into four distinct user areas, namely · · · · MMRs 05986-011 · 0xFFFF0FFF 0xFFFF0000 The longest time the request can take to pass through the synchronizer Plus the time for the longest instruction to complete (the longest instruction is an LDM that loads all the registers, including the PC) Plus the time for the data abort entry Plus the time for FIQ entry 05986-010 · A remappable memory area An SRAM area A Flash/EE area A memory mapped register (MMR) area SRAM The ADuC7032-8L features 6 kB of SRAM available to the user, organized as 1536 bits × 32 bits, that is, 1536 words, that are located at 0x00040000. RAM space can be used as data memory and as a volatile program space. ARM code can run directly from SRAM at full clock speed, given that the SRAM array is configured as a 32-bit wide memory array. The first 96 kB of this memory space is used as an area into which the on-chip Flash/EE or SRAM can be remapped. A second 4 kB area at the top of the memory map is used to locate the memory mapped registers (MMR), through which all on-chip peripherals are configured and monitored. The remaining two areas of memory are constituted as 6 kB of SRAM and 96 kB of on-chip Flash/EE memory. There are 94 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are reserved for the on-chip kernel. These areas are described in more detail in the sections that follow. SRAM is read/write in 8-, 16-, and 32-bit segments. Any access, either read or write, to an area not defined in the memory map results in a data abort exception. Rev.0 | Page 21 of 116 ADuC7032-8L Remap The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020. By default, after a reset, the Flash/EE memory is logically mapped to Address 0x00000000. It is possible to logically remap the SRAM to Address 0x00000000 by setting Bit 0 of the SYSMAP0 MMR, which is located at 0xFFFF0220. To revert Flash/EE to Address 0x00000000, Bit 0 of SYSMAP0 is cleared. It may be desirable to remap RAM to Address 0x00000000 to optimize the interrupt latency of the ADuC7032-8L, as code can be run in full 32-bit ARM mode and at the maximum core speed. It should be noted that when an exception occurs, the core defaults to ARM mode. Remap Operation When a reset occurs on the ADuC7032-8L, execution starts automatically in the factory-programmed internal configuration code. This so-called kernel is hidden and cannot be accessed by user code. If the ADuC7032-8L is in normal mode, it executes the poweron configuration routine of the kernel and then jumps to the reset vector, Address 0x00000000, to execute the user reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset routine must always be written in Flash/EE. Precautions must be taken to execute the remap command from the absolute Flash/EE address, and not from the mirrored, remapped segment of memory, because this segment may be replaced by the SRAM. If a remap operation is executed while operating code from the mirrored location, prefetch/data aborts may occur; or the user may observe abnormal program operation. This operation is reversible. The Flash/EE can be remapped to Address 0x00000000 by clearing Bit 0 of the SYSMAP0 MMR. Precautions must again be taken to execute the remap function from outside the mirrored area. Any kind of reset logically remaps the Flash/EE memory to the bottom of the memory array. SYSMAP0 Register Name: SYSMAP0 Address: 0xFFFF0220 Default Value: Updated by the kernel Access: Read/write Function: This 8-bit register allows user code to remap either RAM or Flash/EE space into the bottom of the ARM memory space, starting at Address 0x00000000. Table 11. SYSMAP0 MMR Bit Designations Bit 7 to 1 0 Description Reserved. These bits are reserved and should be written as 0 by user code. Remap Bit. Set by the user to remap the SRAM to 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to 0x00000000. Rev.0 | Page 22 of 116 ADuC7032-8L RESET There are four kinds of reset: external reset, power-on reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can also be written by user code to initiate a software reset event. The bits in this register can be cleared to 0 by writing to the RSTCLR MMR at 0xFFFF0234. The bit designations in RSTCLR mirror those of RSTSTA. These registers can be used during a reset exception service routine to identify the source of the reset. The implications of all four kinds of reset event are listed in Table 12. Table 12. Device Reset Implications Reset External Pins to Default State Yes Yes Yes Yes Impact/Reset POR1 Watchdog Reset Software Reset External Reset Pin 1 2 Kernel Executed Yes Yes Yes Yes Reset All External MMRs (Excluding RSTSTA) Yes Yes Yes Yes Reset All High Voltage Indirect Registers Yes Yes Yes Yes Peripherals Reset Yes Yes Yes Yes RAM Valid1 Yes/No2 Yes Yes Yes RSTSTA (Status After Reset Event) RSTSTA[0] = 1 RSTSTA[1] = 1 RSTSTA[2] = 1 RSTSTA[3] = 1 RAM is valid except in the case of a reset following a LIN download. The impact of RAM is dependent on the contents of HVSTA[6] if LVF is enabled. When LVF is enabled using (HVCFG0[2]), RAM has not been corrupted by the POR reset mechanism if the LVF Status Bit HVSTA[6] = 1. See the Low Voltage Flag (LVF) section for more information. RSTCLR Register Name: RSTCLR Address: 0xFFFF0234 Default Value: 0x00 Access: Write only Function: This 8-bit write-only register clears the corresponding bit in RSTSTA. RSTSTA Register Name: RSTSTA Address: 0xFFFF0230 Default Value: 0x01 Access: Read/write Function: This 8-bit register indicates the source of the last reset event and can also be written by user code to initiate a software reset. Table 13. RSTCLR/RSTSTA MMR Bit Designations Bit 7 to 4 3 2 1 0 1 Description Not Used. These bits are not used and always read as 0. External Reset. Set to 1 automatically when an external reset occurs. Cleared by setting the corresponding bit in RSTCLR. Software Reset. 1 Set to 1 by user code to generate a software reset. Cleared by setting the corresponding bit in RSTCLR. Watchdog Timeout. Set to 1 automatically when a watchdog timeout occurs. Cleared by setting the corresponding bit in RSTCLR. Power-On Reset. Set automatically when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR. If the software reset bit in RSTSTA is set, any write to RSTCLR that does not clear this bit generates a software reset. Rev.0 | Page 23 of 116 ADuC7032-8L FLASH/EE MEMORY AND THE ADUC7032-8L ADUC7032-8L The ADuC7032-8L incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at the byte level, although it must first be erased, the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC7032-8L, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes. Flash/EE Memory The total 96 kB of Flash/EE memory is organized as 48 kB × 16 bits. Of the 96 kB, 94 kB is user space, and 2 kB is reserved for boot loader/kernel space. The page size of this Flash/EE memory is 512 bytes. Typically, it takes the Flash/EE controller 20 ms to erase a page, and 50 s to write a 16-bit word. These Flash/EE timings are independent of the MCU core clock. There is 94 kB of Flash/EE memory available to the user as code and nonvolatile data memory. There is no distinction between data and program, because ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, which means that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. When operating at speeds less than 20.48 MHz, the Flash/EE memory controller can transparently fetch the second 16-bit halfword (part of the 32-bit ARM operation code) within a single core clock period. Therefore, for speeds less than 20.48 MHz (that is, CD > 0), it is recommended that ARM mode be used. For 20.48 MHz operation (that is, CD = 0), it is recommended that Thumb mode be used. The Flash/EE memory is physically located at Address 0x80000. Upon a hard reset, it is logically mapped to 0x00000000. The factory default contents of all Flash/EE memory locations is 0xFF. Flash/EE can be read in 8-, 16-, and 32-bit segments and written in segments of 16 bits. The Flash/EE is rated for 10,000 endurance cycles. This rating is based on the number of times that each individual halfword (16-bit location) is cycled, that is, erased and programmed. A redundancy scheme can be implemented in software to ensure greater than 10,000 cycles of endurance. It is possible to write to a single 16-bit location only twice between erases; that is, it is possible to walk bytes, not bits. If a location is written to more than twice, the contents of the Flash/EE page may be corrupted. The 94 kB of Flash/EE memory can be programmed in-circuit, using a serial download mode via the LIN interface or the integrated JTAG port. Serial Downloading (In-Circuit Programming) The ADuC7032-8L facilitates code download via the LIN pin. JTAG Access The ADuC7032-8L features an on-chip JTAG debug port to facilitate code download and debug. FLASH/EE CONTROL INTERFACE The access to and control of the Flash/EE memory on the ADuC7032-8L is managed by an on-chip memory controller. The controller manages the Flash/EE memory as two separate blocks (Block 0 and Block 1). Block 0 consists of the 32 kB Flash/EE memory mapped from 0x00090000 to 0x00097FFF (including the 2 kB kernel space that is reserved at the top of this block). Block 1 consists of the 6 kB Flash/EE memory mapped from 0x00080000 to 0x0008FFFF. Note that the MCU core can continue to execute code from one memory block while an active erase or program cycle is being carried out on the other block. If a command operates on the same block as the code currently executing, the core is halted until the command is completed. This also applies to code execution. User code, LIN, and JTAG programming use the Flash/EE control interface, which consists of the following MMRs: · · · · · · The user can also write data variables to the Flash/EE memory during run-time code execution, for example, for storing diagnostic battery parameter data. Rev.0 | Page 24 of 116 FEExSTA (x = 0 or 1): read-only register that reflects the status of the Flash/EE memory control interface FEExMOD (x = 0 or 1): sets the operating mode of the Flash/EE memory control interface FEExCON (x = 0 or 1): 8-bit command register; the commands are interpreted as described in Table 14. FEExDAT (x = 0 or 1): 16-bit data register FEExADR (x = 0 or 1): 16-bit address register FEExSIG (x = 0 or 1): holds the 24-bit code signature as a result of the signature command being initiated ADuC7032-8L · · FEExHID (x = 0 or 1) is a protection MMR that controls read- and write-protection of the Flash/EE memory code space. If previously configured via the FEExPRO register, FEExHID may require a software key to enable access. FEExPRO (x = 0 or 1) is a buffer of the FEExHID register, which is used to store the FEExHID value so it is automatically downloaded to the FEExHID registers on subsequent reset and power-on events. Note that user software must ensure that the Flash/EE controller has completed any erase or write cycle before the PLL is powered down. If the PLL is powered down before an erase or write cycle has completed, the Flash/EE page or byte may be corrupted. The following sections describe in detail the bit designations of each of the Flash/EE control MMRs. FEE0CON and FEE1CON Registers Name: FEE0CON and FEE1CON Address: 0xFFFF0E08 and 0xFFFF0E88 Default Value (Both Registers): 0x07 Access: Read/write Function: These 8-bit registers are written by user code to control the operating modes of the Flash/EE memory controllers for Block 0 (32 kB) and Block 1 (64 kB). Table 14. Command Codes in FEE0CON and FEE1CON Code 0x00 2 0x012 0x022 0x032 Command Reserved Single read Single write Erase-write 0x042 Single verify 0x052 0x062 Single erase Mass erase 0x07 0x08 0x09 0x0A 0x0B Reserved Reserved Reserved Signature 0x0C Protect 0x0D 0x0E 0x0F Reserved Reserved Ping 1 2 Description 1 Reserved. This command should not be written by user code. Load FEExDAT with the 16-bit data indexed by FEExADR. Write FEExDAT at the address pointed by FEExADR. This operation takes 50 s. Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms. Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is returned in FEExSTA Bit 1. Erase the page indexed by FEExADR. Erase Block 0 (30 kB) or Block 1 (64 kB) of user space. The 2 kB kernel is protected. This operation takes 1.2 sec. To prevent accidental execution, a command sequence is required to execute this instruction. This sequence is described in the Command Sequence for Executing a Mass Erase section. Default command. Reserved. This command should not be written by user code. Reserved. This command should not be written by user code. Reserved. This command should not be written by user code. FEE0CON. This command results in a 24-bit LFSR-based signature being generated and loaded into FEE0SIG. If FEE0ADR is less than 0x97800, this command results in a 24-bit LFSR-based signature of the user code space from the page specified in FEE0ADR upwards, including the kernel, security bits, and Flash/EE key. If FEE0ADR is greater than 0x97800, the kernel and manufacturing data are signed. FEE1CON. This command results in a 24-bit LFSR-based signature being generated, beginning at FEE1ADR and ending at the end of the 64 kB block, and loaded into FEE1SIG. The last page of this block is not included in the sign generation. This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06) or with the software protection key. Reserved. This command should not be written by user code. Reserved. This command should not be written by user code. No operation, interrupt generated. x in the register names designates 0 or 1 for Flash/EE Block 0 or Flash/EE Block 1. The FEExCON always reads 0x07 immediately after execution of any of these commands. Rev.0 | Page 25 of 116 ADuC7032-8L Command Sequence for Executing a Mass Erase To run the mass-erase command via FEE0CON, write protection on the lower 64 kB must be disabled; that is, FEE1HID and FEE1PRO are set to 0xFFFFFFFF. This is accomplished by first removing the protection or by erasing the lower 64 kB first. Because of the significance of the mass erase command, a specific code sequence must be executed to initiate this operation. 1. 2. 3. 4. Set Bit 3 in FEExMOD. Write 0xFFC3 in FEExADR. Write 0x3CFF in FEExDAT. Run the mass erase command 0x06 in FEExCON. Command Sequence Example The command sequence for executing a mass erase is illustrated in the following example: Int a = FEExSTA; FEExMOD = 0x08; FEExADR = 0xFFC3; FEExDAT = 0x3CFF; FEExCON = 0x06; while (FEExSTA & 0x04){} // Ensure FEExSTA is cleared // Mass-Erase command // Wait for command to finish FEE0STA and FEE1STA Registers Name: FEE0STA and FEE1STA Address: 0xFFFF0E00 and 0xFFFF0E80 Default Value (Both Registers): 0x20 Access: Read only Function: These 8-bit read-only registers can be read by user code and reflect the current status of the Flash/EE memory controllers. Table 15. FEE0STA and FEE1STA MMR Bit Designations Bit 15 to 4 3 2 1 0 1 Description 1 Not Used. These bits are not used and are always read as 0. Flash Interrupt Status Bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set. Cleared automatically when the FEExSTA register is read by user code. Flash/EE Controller Busy. Set automatically when the Flash/EE controller is busy. Cleared automatically when the controller is not busy. Command Fail. Set automatically when a command written to FEExCON completes unsuccessfully. Cleared automatically when the FEExSTA register is read by user code. Command Successful. Set automatically by MCU when a command is completed successfully. Cleared automatically when the FEExSTA register is read by user code. x is 0 or 1 to designate Flash/EE Block 0 or Flash/EE Block 1. FEE0ADR and FEE1ADR Registers Name: FEE0ADR and FEE1ADR Address: 0xFFFF0E10 and 0xFFFF0E90 Default Value: Nonzero (FEE0ADR), 0x0000 (FEE1ADR) Access: Read/write Function: This 16-bit register dictates the address acted upon by any Flash/EE command executed via FEExCON. FEE0DAT and FEE1DAT Registers Name: FEE0DAT and FEE1DAT Address: 0xFFFF0E0C and 0xFFFF0E8C Default Value (Both Registers): 0x0000 Access: Read/write Function: This 16-bit register contains the data either read from or to be written to the Flash/EE memory controllers. Rev.0 | Page 26 of 116 ADuC7032-8L FEE0MOD and FEE1MOD Registers Name: FEE0MOD and FEE1MOD Address: 0xFFFF0E04 and 0xFFFF0E84 Default Value (Both Registers): 0x00 Access: Read/write Function: These registers are written by user code to configure the mode of operation of the Flash/EE memory controllers. Table 16. FEE0MOD and FEE1MOD MMR Bit Designations Bit 15 to 7 6 to 5 4 3 2 1 0 1 Description 1 Not Used. These bits are reserved for future functionality and should be written as 0 by user code. Flash/EE Security Lock Bits. These bits must be written as [6:5] = 10 to complete the Flash security protect sequence. Flash/EE Controller Command Complete Interrupt Enable. Set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command. Cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command. Flash/EE Erase/Write Enable. Set by user code to enable the Flash/EE erase and write access via FEExCON. Cleared by user code to disable the Flash/EE erase and write access via FEExCON. Reserved. Should be written as 0. Flash/EE Controller Abort Enable. Set to 1 by user code to enable the Flash/EE controller abort functionality. Reserved. Should be written as 0. x is 0 or 1 to designate Flash/EE Block 0 or Flash/EE Block 1. The 94 kB of Flash/EE memory available to the user can be read-protected and write-protected using the FFE0HID and FEE1HID registers. This flexibility allows the user to set and test protection settings temporarily using the FEE0HID MMR and subsequently lock the required protection configuration (using FEE0PRO) when shipping protection systems into the field. In Block 0, the FEE0HID MMR protects the 30 kB of Flash/EE memory. Bit 0 to Bit 28 of this register protect Page 0 to Page 57 from writing. Each bit protects two pages, that is, 1 kB. Bit 29 to Bit 30 protect Page 58 and Page 59, respectively; that is, each bit write-protects a single page of 512 bytes. The MSB of this register (Bit 31) protects Block 0 from being read through JTAG. In Block 1 (64 kB), the FEE1HID MMR protects the 64 kB of Flash/EE memory. Bit 0 to Bit 29 of this register protect Page 0 to Page 119 from writing. Each bit protects four pages, that is, 2 kB. Bit 30 protects Page 120 to Page 127; that is, Bit 30 write-protects eight pages of 512 bytes. The MSB of this register (Bit 31) protects Flash/EE Block 1 from being read through JTAG. The FEE0PRO register mirrors the bit definitions of the FEE0HID MMR. The FEE0PRO MMR allows user code to lock the protection or security configuration of the Flash/EE memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. As with Block 0, the FEE1PRO register mirrors the bit definitions of the FEE1HID MMR. The FEE1PRO MMR allows user code to lock the protection or security configuration of the Flash/EE memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. FLASH/EE MEMORY SECURITY Rev.0 | Page 27 of 116 ADuC7032-8L Block 0, Flash/EE Memory Protection Registers Name: FEE0HID and FEE0PRO Address: 0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C (for FEE0PRO) Default Value (Both Registers): 0xFFFFFFFF (for FEE0HID) and 0x00000000 (for FEE0PRO) Access: Read/write Function: These registers are written by user code to configure the protection of the Flash/EE memory. Table 17. FEE0HID and FEE0PRO MMR Bit Designations Bit 31 30 29 28 to 0 Description Read Protection Bit. Cleared by the user to protect the 32 kB Flash/EE block code via JTAG read access. Set by the user to allow reading of the 32 kB Flash/EE block code via JTAG read access. Write-Protection Bit. Set by user code to unprotect Page 59. Cleared by user code to write-protect Page 59. Write-Protection Bit. Set by user code to unprotect Page 58. Cleared by user code to write-protect Page 58. Write-Protection Bits. When set by user code, these bits unprotect Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit write-protects two pages, and each page consists of 512 bytes. When cleared by user code, these bits write-protect Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit writeprotects two pages, and each page consists of 512 bytes. Block 1, Flash/EE Memory Protection Registers Name: FEE1HID and FEE1PRO Address: 0xFFFF0EA0 (for FEE1HID) and 0xFFFF0E9C (for FEE1PRO) Default Value (Both Registers): 0xFFFFFFFF (for FEE1HID) and 0x00000000 (for FEE1PRO) Access: Read/write Function: These registers are written by user code to configure the protection of the Flash/EE memory. Table 18. FEE1HID and FEE1PRO MMR Bit Designations Bit 31 30 29 to 0 Description Read-Protection Bit. Cleared by the user to protect the 64 kB Flash/EE block code via JTAG read access. Set by the user to allow reading of the 64 kB Flash/EE block code via JTAG read access. Write-Protection Bit. When set by user code, this bit protects Page 120 to Page 127 of the 64 kB Flash/EE code memory. This bit write-protects eight pages, and each page consists of 512 bytes. When cleared by user code, this bit write-protects Page 120 to Page 127 of the 64 kB Flash/EE code memory. This bit writeprotects eight pages, and each page consists of 512 bytes. Write-Protection Bits. When set by user code, these bits unprotect Page 0 to Page 119 of the 64 kB Flash/EE code memory. Each bit write-protects four pages, and each page consists of 512 bytes. When cleared by user code, these bits write-protect Page 0 to Page 119 of the 64 kB Flash/EE code memory. Each bit writeprotects two pages, and each page consists of 512 bytes. Rev.0 | Page 28 of 116 ADuC7032-8L In summary, there are three levels of memory protection: Sequence to Write the Key and Set Permanent Protection · 1. · · Temporary protection can be set and removed by writing directly into the FEExHID MMR. This register is volatile; therefore, protection is in place only while the part remains powered on. Protection is not reloaded after a power cycle. Keyed permanent protection can be set via FEExPRO, which is used to lock the protection configuration. The software key used at the start of the required FEExPRO write sequence is saved once and must subsequently be used for any subsequent access to the FEExHID or FEExPRO MMRs. A mass erase sets the key back to 0xFFFF but also erases the entire user code space. Permanent protection can be set via FEExPRO, similarly to keyed permanent protection. The only difference is that the software key used is 0xDEADDEAD. Once the FEExPRO write sequence is saved, only a mass erase sets the key back to 0xFFFFFFFF. This mass erase also erases the entire user code space. 2. 3. 4. Write in FEExPRO corresponding to the pages to be protected. Write the new (user-defined) 32-bit key in FEExADR Bits[31:16] and FEExDAT Bits[15:0]. Write 1,0 in FEExMOD Bits[6:5] and set FEExMOD Bit 3. Run the write key command 0x0C in FEExCON. Sequence Example The sequence to write the key and set permanent protection is illustrated in the following example, which protects writing Page 4 and Page 5 of the Flash/EE: FEExPRO = 0xFFFFFFFB; // Protect Page 4 and Page 5 FEExADR = 0x66BB; // 32-bit key value Bits[31:16] FEExDAT = 0xAA55; // 32-bit key value Bits[15:0] FEExMOD = 0x0048; // Lock security sequence FEExCON = 0x0C; // Write key command while (FEExSTA & 0x04){} // Wait for command to finish Rev.0 | Page 29 of 116 ADuC7032-8L FLASH/EE MEMORY RELIABILITY CODE EXECUTION TIME FROM SRAM AND FLASH/EE The Flash/EE memory array on the part is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. This section describes SRAM and Flash/EE memory access times during execution for applications where execution time is critical. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events, defined as follows: Fetching instructions from SRAM takes one clock cycle. However, if the instruction involves reading or writing data to memory, one or two extra cycles must be added. If the data is in SRAM, one extra cycle is needed. If the data is in Flash/EE, two extra cycles are needed to get the 32-bit data from Flash/EE. 1. 2. 3. 4. Initial page erase sequence Read/verify sequence Byte program sequence Second read/verify sequence A control flow instruction (for example, a branch instruction) takes one cycle to fetch and two cycles to fill the pipeline with the new instructions. In reliability qualification, every halfword (16-bits wide) location of the three pages (top, middle, and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to 0xFFFF. As shown in Table 1, the Flash/EE memory endurance qualification of the parts is carried out in accordance with JEDEC Retention Lifetime Specification A117. The results allow the specification of a minimum endurance figure over supply and temperature of 10,000 cycles. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the parts are qualified in accordance with the formal JEDEC Retention Lifetime Specification A117 at a specific junction temperature (TJ = 85°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time the Flash/EE memory is reprogrammed. Also note that retention lifetime, based on an activation energy of 0.6 eV, derates with TJ, as shown in Figure 12. 450 300 In Thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction. In ARM mode, with CD = 0, two cycles are needed to fetch the 32-bit instructions. With CD > 0, no extra cycles are required for the fetch because the Flash/EE memory continues to be clocked at full speed. In addition, some dead time is needed before accessing data for any value of CD bits. Timing is identical in both modes when executing instructions that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter, and then four cycles are needed to fill the pipeline if CD = 0. A data processing instruction involving only the core register does not require any extra clock cycles. Data transfer instructions are more complex and are summarized in Table 19. Table 19. Typical Execution Cycles in ARM/Thumb Mode Fetch Cycle 2/1 2/1 2/1 2/1 2/1 2/1 Dead Time 1 1 N 1 1 N Data Access 2 1 2×N 2 × 50 s 50 s 2 × N × 50 s With 1 < N 16, N is the number of registers to load or store in the multiple load/store instruction. 150 30 40 55 70 85 100 125 135 JUNCTION TEMPERATURE (°C) Figure 12. Flash/EE Memory Data Retention 150 05986-012 RETENTION (Years) Execution from Flash/EE Instruction LD LDH LDM/POP STR STRH STM/PUSH 600 0 Execution from SRAM By default, Flash/EE code execution is suspended during any Flash/EE erase or write cycle. A page (512 bytes) erase cycle takes 20 ms, and a write (16 bits) word command takes 50 s. However, the Flash/EE memory controller allows erase/write cycles to be aborted if the ARM core receives an enabled interrupt during the current Flash/EE erase/write cycle. The ARM7 can, therefore, immediately service the interrupt and then return to repeat the Flash/EE command. The abort operation typically takes 10 clock cycles. If the abort operation is not feasible, it is possible to run Flash/EE memory programming code and the relevant interrupt routines from SRAM, allowing the core to service the interrupt immediately. Rev.0 | Page 30 of 116 ADuC7032-8L ADUC7032-8L ADUC7032-8L KERNEL The ADuC7032-8L also features an on-chip LIN downloader. The ADuC7032-8L features an on-chip kernel resident in the top 2 kB of the Flash/EE code space. After any reset event, this kernel copies the factory-calibrated data from the manufacturing data space into the various on-chip peripherals. The peripherals calibrated by the kernel are Figure 13 is a flow chart showing the execution of the kernel. The current revision of the kernel can be derived from SYSSER1, as described in Table 96. · · · · · · · · · PSM (power supply monitor) Precision oscillator Low power oscillator REG_AVDD/REG_DVDD Low power voltage reference Normal mode voltage reference Current ADC (offset and gain) Voltage ADC (offset and gain) Temperature ADC (offset and gain) Normal kernel execution time, excluding LIN download, is approximately 5 ms. It is possible to enter and leave LIN download mode only via a reset. SRAM is not modified during normal kernel execution. SRAM is modified during LIN download kernel execution. User MMRs that can be modified by the kernel and differ from their POR default values are · · · · · · · · R0 to R15 GP0CON/GP2CON SYSCHK ADCMDE/ADC0CON FEE0ADR/FEE0CON/FEE0SIG HVDAT/HVCON HVCFG0/HVCFG1 T3LD For the duration of kernel execution, the watchdog timer is active with a timeout period of 30 ms, which ensures that the ADuC7032-8L is reset if an error occurs in the kernel. The watchdog timer is disabled once the kernel code is exited. Note that, even with NTRST = 0, user code is not executed unless Address 0x14 contains either 0x27011970 or the checksum of Page 0, excluding Address 0x14. If Address 0x14 does not contain this information, user code is not executed and LIN download mode is entered. With NTRST = 1, user code is always executed. During kernel execution, JTAG access is disabled. Rev.0 | Page 31 of 116 ADuC7032-8L INITIALIZE ON-CHIP PERIPHERALS TO FACTORY CALIBRATED STATE SOFTWARE RESET NO PAGE ERASED? (0x14 = 0xFFFFFFFF) YES JTAG MODE? (NTRST = 1) NO YES KEY PRESENT? (0x14 = 0x27011970) NO YES EXECUTE USER CODE CHECKSUM PRESENT? (0x14 = CHECKSUM) NO FLAG PAGE 0 ERROR KICK WDT NO 1 HOUR PASSED? LIN RECEIVED? YES NO YES POWER DOWN RESET 1 HOUR TIMER RESET COMMAND YES Figure 13. ADuC7032-8L Kernel Flow Chart Rev.0 | Page 32 of 116 NO 05986-013 HANDLE LIN COMMAND ADuC7032-8L 0xFFFFFFFF MEMORY MAPPED REGISTERS The memory mapped register (MMR) space is mapped into the top 4 kB of the MCU memory space and accessed by indirect addressing, load, and store commands through the ARM7 banked registers. An outline of the memory mapped register bank of the ADuC7032-8L is shown in Figure 14. 0xFFFF1000 0xFFFF0E00 FLASH CONTROL INTERFACE 0xFFFF0D50 GPIO 0xFFFF0D00 0xFFFF0A14 SPI The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the ARM7 core registers (described in the ARM Registers section) reside in the MMR area. 0xFFFF0A00 As seen in the Complete MMR Listing section (Table 20 to Table 30), the MMR data widths vary from one byte (eight bits) to four bytes (32 bits). The ARM7 core can access any of the MMRs (single-byte or multiple-byte width registers) with a 32-bit read or write access. 0xFFFF079C The resultant read, for example, is aligned per the little endian format described in the Memory Format section. However, errors result if the ARM7 core tries to access 4-byte (32-bit) MMRs with a 16-bit access. In the case of a (16-bit) write access to a 32-bit MMR, the (upper) 16 most significant bits are written as 0s. More obviously, in the case of a 16-bit read access to a 32-bit MMR, only 16 of the MMR bits can be read. 0xFFFF0810 HV INTERFACE 0xFFFF0800 0xFFFF0780 LIN HARDWARE 0xFFFF0730 UART 0xFFFF0700 0xFFFF0568 ADC 0xFFFF0500 0xFFFF044C 0xFFFF0400 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 PLL AND OSCILLATOR CONTROL WATCHDOG TIMER3 WAKE-UP TIMER2 GENERAL-PURPOSE TIMER1 0xFFFF0318 TIMER0 0xFFFF0300 0xFFFF0220 0xFFFF0110 0xFFFF0000 REMAP AND SYSTEM CONTROL INTERRUPT CONTROLLER Figure 14. Top Level MMR Map Rev.0 | Page 33 of 116 05986-014 0xFFFF0244 ADuC7032-8L COMPLETE MMR LISTING Table 20. IRQ Address Base = 0xFFFF0000 Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0100 0x0104 0x0108 0x010C 1 Name IRQSTA IRQSIG 1 IRQEN IRQCLR SWICFG FIQSTA FIQSIG1 FIQEN FIQCLR Byte 4 4 4 4 4 4 4 4 4 Access Type R R RW W W R R RW W Default Value 0x00000000 0x00000000 0x00000000 0x00000000 Description Active IRQ Source. Current State of All IRQ Sources (Enabled and Disabled). Enabled IRQ Sources. MMR Used to Disable IRQ Sources. Software Interrupt Configuration MMR. Active IRQ Source. Current State of All IRQ Sources (Enabled and Disabled). Enabled IRQ Sources. MMR Used to Disable IRQ Sources. Depends on the level on the GP0, GP5, GP7, and GP8 external interrupt pins. Table 21. System Control Address Base = 0xFFFF0200 Address 0x0220 0x0230 0x0234 0x0238 0x023C 0x0240 1 Name SYSMAP0 RSTSTA RSTCLR SYSSER0 1 SYSSER11 SYSSER11 SYSCHK1 Byte 1 1 1 4 4 4 Access Type RW RW W RW RW RW Default Value 0x01 Description REMAP Control Register. Reset Status MMR. RSTSTA Clear MMR. SYSTEM Serial Number 0. SYSTEM Serial Number 1. Kernel Checksum. Updated by kernel. Table 22. Timer Address Base = 0xFFFF0300 Address 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 1 Name T0LD T0VAL0 T0VAL1 T0CON T0CLRI T0CAP T1LD T1VAL T1CON T1CLRI T1CAP T2LD T2VAL T2CON T2CLRI T3LD 1 T3VAL1 T3CON1 T3CLRI Byte 2 2 4 4 1 2 4 4 4 1 4 4 4 2 1 2 2 2 1 Access Type RW R R RW W RW RW R RW W RW RW R RW W RW R RW W Default Value 0x0000 0x0000 0x00000000 0x00000000 0x0000 0x00000000 0xFFFFFFFF 0x01000000 0xFF 0x00000000 0x00000000 0xFFFFFFFF 0x0000 Description Timer0 Load Register. Timer0 Value Register 0. Timer0 Value Register 1. Timer0 Control MMR. Timer0 Interrupt Clear Register. Timer0 Capture Register. Timer1 Load Register. Timer1 Value Register. Timer1 Control MMR. Timer1 Interrupt Clear Register. Timer1 Capture Register. Timer2 Load Register. Timer2 Value Register. Timer2 Control MMR. Timer2 Interrupt Clear Register. Timer3 Load Register. Timer3 Value Register. Timer3 Control MMR. Timer3 Interrupt Clear Register. Updated by kernel. Rev.0 | Page 34 of 116 ADuC7032-8L Table 23. PLL Base Address = 0xFFFF0400 Address 0x0400 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 0x042C 0x0440 0x0444 0x0448 0x044C Name PLLSTA POWKEY0 POWCON POWKEY1 PLLKEY0 PLLCON PLLKEY1 OSC0TRM OSC0CON OSC0STA OSC0VAL0 OSC0VAL1 Byte 4 4 1 4 4 1 4 1 1 1 2 2 Access Type R W RW W W RW W RW RW R R R Default Value 0x79 0x00 0xX8 0x00 0x00 0x0000 0x0000 Description PLL Status MMR. POWCON Prewrite Key. Power Control and Core Speed Control Register. POWCON Postwrite Key. PLLCON Prewrite Key. PLL Clock Source Selection MMR. PLLCON Postwrite Key. Low Power Oscillator Trim Bits MMR. Low Power Oscillator Calibration Control MMR. Low Power Oscillator Calibration Status MMR. Low Power Oscillator Calibration Counter 0 MMR. Low Power Oscillator Calibration Counter 1 MMR. Table 24. ADC Base Address = 0xFFFF0500 Address 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0518 0x051C 0x0520 0x0524 0x0528 0x052C 0x0530 0x0534 0x0538 0x053C 0x0540 0x0544 0x0548 0x054C 0x0550 0x0554 0x0558 0x055C 0x0560 0x057C 1 Name ADCSTA ADCMSKI ADCMDE ADC0CON ADC1CON ADC2CON ADCFLT ADCCFG ADC0DAT ADC1DAT ADC2DAT ADCFIFO ADC0OF 1 ADC1OF1 ADC2OF1 ADC0GN1 ADC1GN1 ADC2GN1 ADC0RCL ADC0RCV ADC0TH ADC0TCL ADC0THV ADC0ACC ADC0ATH ADCREF1 Byte 2 1 1 2 2 2 2 1 2 2 2 4 2 2 2 2 2 2 2 2 2 1 1 4 4 2 Access Type R RW RW RW RW RW RW RW R R R R RW RW RW RW RW RW RW R RW RW R R RW RW Default Value 0x0000 0x00 0x00 0x0002 0x0000 0x0000 0x0007 0x00 0x0000 0x0000 0x0000 0x0001 0x0000 0x0000 0x01 0x00 0x00000000 0x00000000 Updated by kernel. Rev.0 | Page 35 of 116 Description ADC Status MMR. ADC Interrupt Source Enable MMR. ADC Mode Register. Current ADC Control MMR. Voltage ADC Control MMR. Temperature ADC Control MMR. ADC Filter Control MMR. ADC Configuration MMR. Current ADC Result MMR. Voltage ADC Result MMR. Temperature ADC Result MMR. Current/Voltage Result FIFO. Current ADC Offset MMR. Voltage ADC Offset MMR. Temperature ADC Offset MMR. Current ADC Gain MMR. Voltage ADC Gain MMR. Temperature ADC Gain MMR. Current ADC Result Count Limit. Current ADC Result Count Value. Current ADC Result Threshold. Current ADC Result Threshold Count Limit. Current ADC Result Threshold Count Limit Value. Current ADC Result Accumulator. Current ADC Result Accumulator Threshold. Low Power Mode Voltage Reference Scaling Factor. ADuC7032-8L Table 25. UART Base Address = 0XFFFF0700 0XFFFF0700 Address 0x0700 0x0704 0x0708 0x070C 0x0710 0x0714 0x072C Name COMTX COMRX COMDIV0 COMIEN0 COMDIV1 COMIID0 COMCON0 COMCON1 COMSTA0 COMDIV2 Byte 1 1 1 1 1 1 1 1 1 2 Access Type W R RW RW RW R RW RW R RW Default Value 0x00 0x00 0x01 0x00 0x00 0x60 0x0000 Description UART Transmit Register. UART Receive Register. UART Standard Baud Rate Generator Divisor Value 0. UART Interrupt Enable MMR 0. UART Standard Baud Rate Generator Divisor Value 1. UART Interrupt Identification 0. UART Control Register 0. UART Control Register 1. UART Status Register 0. UART Fractional Divider MMR. Table 26. LIN Hardware Sync Base Address = 0XFFFF0780 0XFFFF0780 Address 0x0780 0x0784 0x0788 0x078C 0x0790 Name LHSSTA LHSCON0 LHSVAL0 LHSCON1 LHSVAL1 Byte 1 2 2 1 1.5 Access Type R RW RW RW RW Default Value 0x00 0x0000 0x0000 0x32 0x0000 Description LHS Status MMR. LHS Control MMR 0. LHS Timer0 MMR. LHS Control MMR 1. LHS Timer1 MMR. Table 27. High Voltage Interface Base Address = 0xFFFF0800 Address 0x0804 0x080C 1 Name HVCON 1 HVDAT1 Byte 1 2 Access Type RW RW Default Value Description High Voltage Interface Control MMR. High Voltage Interface Data MMR. Default Value 0x00 0x00 0x00 0x1B 0x0000 Description SPI Status MMR. SPI Receive MMR. SPI Transmit MMR. SPI Baud Rate Select MMR. SPI Control MMR. Default Value 0x11100000 0x10000000 0x01000000 0x000000XX Description GPIO Port 0 Control MMR. GPIO Port 1 Control MMR. GPIO Port 2 Control MMR. GPIO Port 0 Data Control MMR. GPIO Port 0 Data Set MMR. GPIO Port 0 Data Clear MMR. GPIO Port 1 Data Control MMR. GPIO Port 1 Data Set MMR. GPIO Port 1 Data Clear MMR. GPIO Port 2 Data Control MMR. GPIO Port 2 Data Set MMR. GPIO Port 2 Data Clear MMR. Updated by kernel. Table 28. SPI Base Address = 0xFFFF0A00 Address 0x0A00 0x0A04 0x0A08 0x0A0C 0x0A10 Name SPISTA SPIRX SPITX SPIDIV SPICON Byte 1 1 1 1 2 Access Type R R W RW RW Table 29. GPIO Base Address = 0xFFFF0D00 Address 0x0D00 0x0D04 0x0D08 0x0D20 0x0D24 0x0D28 0x0D30 0x0D34 0x0D38 0x0D40 0x0D44 0x0D48 1 Name GP0CON GP1CON GP2CON GP0DAT 1 GP0SET1 GP0CLR1 GP1DAT1 GP1SET1 GP1CLR1 GP2DAT1 GP2SET1 GP2CLR1 T Byte 4 4 4 4 4 4 4 4 4 4 4 4 Access Type RW RW RW RW W W RW W W RW W W 0x000000XX 0x000000XX Depends on the level on the external GPIO pins. Rev.0 | Page 36 of 116 ADuC7032-8L Table 30. Flash/EE Base Address = 0xFFFF0300 Address 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 0x0E80 0x0E84 0x0E88 0x0E8C 0x0E90 0x0E98 0x0E9C 0x0EA0 Name FEE0STA FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SIG FEE0PRO FEE0HID FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SIG FEE1PRO FEE1HID Byte 1 2 1 2 2 3 4 4 1 2 1 2 2 3 4 4 Access Type R RW RW RW RW R RW RW R RW RW RW RW R RW RW Default Value 0x20 0x00 0x07 0x0000 0xFFFFFF 0x00000000 0xFFFFFFFF 0x20 0x00 0x07 0x0000 0x0000 0xFFFFFFFF 0x00000000 0xFFFFFFFF Rev.0 | Page 37 of 116 Description Flash/EE Status MMR. Flash/EE Control MMR. Flash/EE Control MMR. Flash/EE Data MMR. Flash/EE Address MMR. Flash/EE LFSR MMR. Flash/EE Protection MMR. Flash/EE Protection MMR. Flash/EE Status MMR. Flash/EE Control MMR. Flash/EE Control MMR. Flash/EE Data MMR. Flash/EE Address MMR. Flash/EE LFSR MMR. Flash/EE Protection MMR. Flash/EE Protection MMR. ADuC7032-8L 16-BIT 16-BIT, SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS The ADuC7032-8L incorporates three independent - analog-to-digital converters (ADCs), namely, the current channel ADC (I-ADC), the voltage channel ADC (V-ADC), and the temperature channel ADC (T-ADC). These precision measurement channels integrate on-chip buffering; programmable gain amplifiers; 16-bit, - modulators; and digital filtering and are intended for the precision measurement of current, voltage, and temperature variables in 12 V automotive battery systems. The modulator converts the sampled input signal into a digital pulse train, whose duty cycle contains the digital information. A modified Sinc3 programmable low-pass filter is then employed to decimate the modulator output data stream to give a valid 16-bit data conversion result at programmable output rates from 4 Hz to 8 kHz in normal mode and 1 Hz to 2 kHz in low power mode. The I-ADC also incorporates counter, comparator, and accumulator logic. This allows the I-ADC result to generate an interrupt after a predefined number of conversions has elapsed or if the I-ADC result exceeds a programmable threshold value. A fast ADC overrange feature is also supported. Once enabled, a 32-bit accumulator automatically sums the 16-bit I-ADC results. CURRENT CHANNEL ADC (I-ADC) This ADC is intended to convert battery current sensed through an external 100 shunt resistor. On-chip programmable gain means that the I-ADC can be configured to accommodate battery current levels from ±1 A to ±1500 A. The time to a first valid (fully settled) result on the current channel is three ADC conversion cycles with chop mode turned off and two ADC conversion cycles with chop mode turned on. As shown in Figure 15, the I-ADC employs a - conversion technique to realize 16 bits of no missing codes performance. ANALOG INPUT DIAGNOSTIC CURRENT SOURCES TWO 50µA IIN+ AND IIN­ CURRENT SOURCES. PROGRAMMABLE GAIN AMPLIFIER ANALOG INPUT PROGRAMMABLE CHOPPING THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE. THE PROGRAMMABLE GAIN AMPLIFIER ALLOWS EIGHT BIPOLAR INPUT RANGES FROM ±2.3mV TO ±1.2V (INT VREF = +1.2V). - MODULATOR - ADC OUTPUT AVERAGE THE MODULATOR PROVIDES A HIGH FREQUENCY 1-BIT DATA STREAM (THE OUTPUT OF WHICH IS ALSO CHOPPED) TO THE DIGITAL FILTER, THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED ANALOG INPUT VOLTAGE. THE - ARCHITECTURE ENSURES 16 BITS NO MISSING CODES. AS PART OF THE CHOPPING IMPLEMENTATION, EACH DATA-WORD OUTPUT FROM THE FILTER IS SUMMED AND AVERAGED WITH ITS PREDECESSOR. REG_AVDD REG_AVDD IIN+ ADC FAST OVERRANGE - ADC IIN­ GND ANALOG INPUT DIAGNOSTIC VOLTAGE SOURCE VREF/136 VREF/136 VOLTAGE INPUT. BUF - MODULATOR PROGRAMMABLE DIGITAL FILTER CHOP GENERATES AN ADC INTERRUPT IF THE CURRENT INPUT IS GROSSLY OVERRANGED. CHOP BUFFER AMPLIFIER INTERNAL REFERENCE THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE PGA DRIVING THE - MODULATOR. VREF THE INTERNAL 5ppm/°C REFERENCE IS ROUTED TO THE ADC BY DEFAULT. AN EXTERNAL REFERENCE ON THE VREF PIN CAN ALSO BE SELECTED. ACCUMULATES THE ADC RESULT. OFFSET COEFFICIENT ADC RESULT ACCUMULATOR ADC INTERRUPT GENERATOR GAIN COEFFICIENT OUTP