ADV7192 PAL-60 BT656 10-BIT 16-BIT IDAC10 Y7/P15 ADV7192KST ST-80 CCIR-601/656 - Datasheet Archive

 

Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs ADV7192 APPLICATIONS DVD Playback Systems PC

 

a Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs ADV7192 ADV7192 APPLICATIONS DVD Playback Systems PC Video/Multimedia Playback Systems Progressive Scan Playback Systems FEATURES Six High-Quality 10-Bit Video DACs 10-Bit Internal Digital Video Processing Multistandard Video Input Multistandard Video Output 4 Oversampling with Internal 54 MHz PLL Programmable Video Control Includes: Digital Noise Reduction Gamma Correction Black Burst LUMA Delay CHROMA Delay Multiple Luma and Chroma Filters Luma SSAFTM (Super Subalias Filter) Average Brightness Detection Field Counter Macrovision Rev. 7.1 CGMS (Copy Generation Management System) WSS (Wide Screen Signaling) Closed Captioning Support. Teletext Insertion Port (PAL-WST) 2-Wire Serial MPU Interface (I2C®-Compatible and Fast I2C) 2 I C Interface Supply Voltage 5 V and 3.3 V Operation 80-Lead LQFP Package GENERAL DESCRIPTION The ADV7192 ADV7192 is part of the new generation of video encoders from Analog Devices. The device builds on the performance of previous video encoders and provides new features like interfacing progressive scan devices, Digital Noise Reduction, Gamma Correction, 4× Oversampling and 54 MHz operation, Average Brightness Detection, Black Burst Signal Generation, Chroma Delay, an additional Chroma Filter, and other features. The ADV7192 ADV7192 supports NTSC-M, NTSC-N (Japan), PAL N, PAL M, PAL-B/D/G/H/I and PAL-60 PAL-60 standards. Input standards supported include ITU-R.BT656 BT656 4:2:2 YCrCb in 8-Bit or 16-Bit format and 3× 10-Bit YCrCb progressive scan format. The ADV7192 ADV7192 can output Composite Video (CVBS), S-Video (Y/C), Component YUV or RGB and analog progressive scan in YPrPb format. The analog component output is also compatible with Betacam, MII, and SMPTE/EBU N10 levels, SMPTE 170 M NTSC, and ITU­R.BT 470 PAL. Please see Detailed Description of Features for more information about the ADV7192 ADV7192. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM DIGITAL INPUT 27MHz CLOCK VIDEO INPUT PROCESSING 8-BIT YCrCb IN 4:2:2 FORMAT ANALOG OUTPUT PLL AND 54MHz CHROMA LPF DEMUX ITU­R.BT 656/601 VIDEO OUTPUT PROCESSING VIDEO SIGNAL PROCESSING AND YCrCbTOYUV MATRIX COLOR CONTROL DNR GAMMA CORRECTION VBI TELETEXT CLOSED CAPTION CGMS/WSS 10-BIT 10-BIT DAC 2 OVERSAMPLING SSAF LPF LUMA LPF 10-BIT 10-BIT DAC 10-BIT 10-BIT DAC OR 10-BIT 10-BIT DAC 4 OVERSAMPLING COMPOSITE VIDEO Y [S-VIDEO] C [S-VIDEO] RGB YUV YPrPb TV SCREEN OR PROGRESSIVE SCAN DISPLAY 10-BIT 10-BIT DAC 10-BIT 10-BIT DAC I2C INTERFACE ADV7192 ADV7192 SSAF is a trademark of Analog Devices Inc. This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). I2C is a registered trademark of Philips Corporation. Throughout the document YUV refers to digital or analog component video. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 ADV7192 ADV7192 MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 28 REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 29 MODE REGISTERS 0­9 . . . . . . . . . . . . . . . . . . . . . . . 30­35 TIMING REGISTERS 0­17 . . . . . . . . . . . . . . . . . . . . . . . 36 SUBCARRIER FREQUENCY AND PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . 37 NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TELETEXT CONTROL REGISTER . . . . . . . . . . . . . . . . 38 CGMS_WSS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 38 CONTRAST CONTROL REGISTERS . . . . . . . . . . . . . . . 39 HUE ADJUST CONTROL REGISTER (HCR) . . . . . . . . 40 HCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 40 BRIGHTNESS CONTROL REGISTER (BCR) . . . . . . . . 40 BCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 40 SHARPNESS RESPONSE REGISTER (PR) . . . . . . . . . . . 41 PR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DNR REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DNR BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 41 GAMMA CORRECTION REGISTERS . . . . . . . . . . . . . . 43 BRIGHTNESS DETECT REGISTER . . . . . . . . . . . . . . . . 44 OUTPUT CLOCK REGISTER . . . . . . . . . . . . . . . . . . . . . 44 OCR BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 44 APPENDIX 1 Board Design and Layout Considerations . . . . . . . . . . . . 45 APPENDIX 2 Closed Captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 APPENDIX 3 Copy Generation Management System (CGMS) . . . . . . . 48 APPENDIX 4 Wide Screen Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 APPENDIX 5 Teletext Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 APPENDIX 6 Optional Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 APPENDIX 7 DAC Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 APPENDIX 8 Recommended Register Values . . . . . . . . . . . . . . . . . . . . 53 APPENDIX 9 NTSC Waveforms (With Pedestal) . . . . . . . . . . . . . . . . . 57 NTSC Waveforms (Without Pedestal) . . . . . . . . . . . . . . . 58 PAL Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Video Measurement Plots . . . . . . . . . . . . . . . . . . . . . . . . 60 UV Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 APPENDIX 10 Vector Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 69 CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1 SPECIFICATIONS Static Performance 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Static Performance 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dynamic Specifications 5 V . . . . . . . . . . . . . . . . . . . . . . . . 5 Dynamic Specifications 3.3 V . . . . . . . . . . . . . . . . . . . . . . . 5 Timing Characteristics 5 V . . . . . . . . . . . . . . . . . . . . . . . . 6 Timing Characteristics 3.3 V . . . . . . . . . . . . . . . . . . . . . . . 7 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10 DETAILED DESCRIPTION OF FEATURES . . . . . . . . . 11 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 11 DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 12 INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 13 FEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17 BLACK BURST OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . 17 BRIGHTNESS DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CHROMA/LUMA DELAY . . . . . . . . . . . . . . . . . . . . . . . . 17 CLAMP OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CSO, HSO AND VSO OUTPUTS . . . . . . . . . . . . . . . . . . . 17 COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 17 COLOR BURST SIGNAL CONTROL . . . . . . . . . . . . . . . 17 COLOR CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CHROMINANCE CONTROL . . . . . . . . . . . . . . . . . . . . . 17 UNDERSHOOT LIMITER . . . . . . . . . . . . . . . . . . . . . . . . 18 DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . . . . . . 18 DOUBLE BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 GAMMA CORRECTION CONTROL . . . . . . . . . . . . . . . 18 NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 18 POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PROGRESSIVE SCAN INPUT . . . . . . . . . . . . . . . . . . . . . 18 REAL-TIME CONTROL, SUBCARRIER RESET, AND TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SCH PHASE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SLEEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VERTICAL BLANKING DATA INSERTION AND BLANK INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 YUV LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16-BIT 16-BIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4× OVERSAMPLING AND INTERNAL PLL . . . . . . . . . 20 VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 20 RESET SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ­2­ REV. 0 ADV7192 ADV7192 SPECIFICATIONS 1 (VAA = 5 V, VREF = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All specifications TMIN to TMAX 2 5 V SPECIFICATIONS unless otherwise noted.) Parameter Min Typ Max 10 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN Input Leakage Current4 Input Leakage Current5 DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current6 Three-State Leakage Current7 Three-State Output Capacitance ANALOG OUTPUTS Output Current (Max) Output Current (Min) DAC-to-DAC Matching3 Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Reference Range, VREF8 POWER REQUIREMENTS VAA Normal Power Mode IDAC (Max)9 ICCT (2× Oversampling) 10, 11 ICCT (4× Oversampling)10, 11 IPLL Sleep Mode IDAC ICCT Bits 1.0 1.0 STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity3 Differential Nonlinearity3 Unit LSB LSB 2.0 0.8 ±1 10 0 6 1 200 VIN = 0.4 V or 2.4 V ISOURCE = 400 µA ISINK = 3.2 mA 4.625 mA mA RL = 300 RL = 600 RSET1, RSET2 = 2400 2.5 1.4 % V k pF 0.8 10 200 6 0.4 4.33 2.16 0.4 10 0 100 6 1.112 1.235 1.359 V 4.75 5.0 5.25 V 29 80 120 6 35 120 170 10 mA mA mA mA µA µA 0.01 85 NOTES 1 All measurements are made in 4× Oversampling Mode unless otherwise specified. 2 Temperature range T MIN to TMAX: 0°C to 70°C. 3 Guaranteed by characterization. 4 For all inputs but PAL_NTSC and ALSB. 5 For PAL_NTSC and ALSB inputs. 6 For all outputs but VSO/TTX/CLAMP. 7 For VSO/TTX/CLAMP output. 8 Measurement made in 2× Oversampling Mode. 9 IDAC is the total current required to supply all DACs including the V REF Circuitry. 10 All six DACs ON. 11 ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL. Specifications subject to change without notice. REV. 0 Guaranteed Monotonic V V µA µA pF 2.4 4.125 V V µA pF µA µA Test Conditions ­3­ IOUT = 0 mA ADV7192 ADV7192­SPECIFICATIONS 1.235 V, R (V = 3.3 V, V = 1 3.3 V SPECIFICATIONS AA REF SET1,2 = 1200 unless otherwise noted. All specifications TMIN to TMAX2 unless otherwise noted.) Parameter Min Typ Max Unit 10 Bits 1.0 1.0 LSB LSB ±1 10 V V µA µA µA pF ISOURCE = 400 µA ISINK = 3.2 mA 10 V V µA µA pF RL = 300 RL = 600 , RSET1,2 = 2400 100 6 mA mA % V k pF IOUT = 0 mA 1.235 V IVREFOUT = 20 µA STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current3 Input Leakage Current4 Input Current, IIN Input Capacitance, CIN 2 0.8 1 200 6 DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current5 Three-State Leakage Current6 Three-State Output Capacitance ANALOG OUTPUTS Output Current (Max) Output Current (Min) DAC-to-DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT 2.4 0.4 10 200 6 4.125 VOLTAGE REFERENCE Reference Range, VREF7 POWER REQUIREMENTS VAA Normal Power Mode IDAC (Max)8 ICCT (2× Oversampling)9, 10 ICCT (4× Oversampling)9, 10 IPLL Sleep Mode IDAC10 IDAC10 ICCT 3.15 4.33 2.16 0.4 4.625 2.5 1.4 3.3 3.6 54 86 Guaranteed Monotonic VIN = 0.4 V or 2.4 V V 29 42 68 6 Test Conditions mA mA mA mA µA µA 0.01 85 NOTES 1 All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. In 2 × Oversampling Mode, power requirement for the ADV7192 ADV7192 is typically 3.0 V. 2 Temperature range T MIN to TMAX: 0°C to 70°C. 3 For all inputs but PAL_NTSC and ALSB. 4 For PAL_NTSC and ALSB inputs. 5 For all outputs but VSO/TTX/CLAMP. 6 For VSO/TTX/CLAMP output. 7 Measurement made in 2× Oversampling Mode. 8 IDAC is the total current required to supply all DACs including the V REF Circuitry. 9 All six DACs ON. 10 ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL. Specifications subject to change without notice. ­4­ REV. 0 ADV7192 ADV7192 1 (VAA = 5 V 250 mV, VREF2 = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.) 5 V DYNAMIC­SPECIFICATIONS Parameter Min Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Chroma/Luma Gain Ineq Chroma/Luma Delay Ineq Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Differential Gain3 Differential Phase3 SNR (Pedestal)3 Typ 0.5 0.7 0.7 0.5 0.1 1.7 2.2 0.6 82 72 0.1 0.4 78.5 78 61.7 62 SNR (Ramp)3 Max 0.9 0.7 (0.4) (0.15) (78) (78) (61.7) (63) 0.3 (0.5) 0.5 (0.3) Unit Degrees % ±% ± Degrees ±% ±% ns ±% dB dB % Degrees dB rms dB p-p dB rms dB p-p Test Conditions Referenced to 40 IRE RMS Peak Periodic RMS Peak Periodic NOTES 1 All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. 2 Temperature range T MIN to TMAX: 0°C to 70°C. 3 Values in parentheses apply to 2× Oversampling Mode. Specifications subject to change without notice. (VAA = 3.3 V 150 mV, VREF = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All 2 MIN to TMAX unless otherwise noted.) 3.3 V DYNAMIC­SPECIFICATIONS1 specifications T Parameter Hue Accuracy Color Saturation Accuracy Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Differential Gain3 Differential Phase3 SNR (Pedestal)3 SNR (Ramp)3 Min Typ 0.5 0.8 0.6 83 71 0.7 0.5 0.1 0.2 0.5 78.5 78 62.3 61 Max (0.5) (0.2) (78) (78) (62) (62.5) Unit Degrees % ±% dB dB ±% ± Degrees ±% % Degrees dB rms dB p-p dB rms dB p-p NOTES 1 All measurements are made in 4× Oversampling Mode unless otherwise specified and are guaranteed by characterization. 2 Temperature range T MIN to TMAX: 0°C to 70°C. 3 Values in parentheses apply to 2× Oversampling Mode. Specifications subject to change without notice. REV. 0 ­5­ Test Conditions Referenced to 40 IRE RMS Peak Periodic RMS Peak Periodic ADV7192 ADV7192 5 V TIMING CHARACTERISTICS Parameter Min (VAA = 5 V 250 mV, VREF = 1.235 V, RSET1,2 = 1200 V unless otherwise noted. All specifications TMIN to TMAX1 unless otherwise noted.) Typ Max Unit 400 kHz µs µs µs µs ns ns ns µs Test Conditions 2 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 0 0.6 1.3 0.6 0.6 100 300 300 0.6 After This Period the First Clock Is Generated Relevant for Repeated Start Condition 2 ANALOG OUTPUTS Analog Output Delay DAC Analog Output Skew 8 0.1 ns ns 27 2 3 2.5 2.0 13 12 57 67 MHz ns ns ns ns ns ns ns ns Clock Cycles Clock Cycles TELETEXT PORT4 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 11 3 6 ns ns ns RESET CONTROL RESET Low Time 3 CLOCK CONTROL AND PIXEL PORT3 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 (2× Oversampling) Pipeline Delay, t15 (4× Oversampling) 8 8 6 5 6 4 20 ns 2 PLL PLL Output Frequency 54 MHz NOTES 1 Temperature range T MIN to TMAX: 0°C to 70°C. 2 Guaranteed by characterization. 3 Pixel Port consists of: Data: P7­P0, Y0/P8­Y7/P15 Y7/P15 Pixel Inputs Control: HSYNC, VSYNC, BLANK Clock: CLKIN 4 Teletext Port consists of: Digital Output: TTXRQ Data: TTX Specifications subject to change without notice. ­6­ REV. 0 ADV7192 ADV7192 (VAA = 3.3 V 150 mV, VREF = 1.235 V, RSET1,2 = 1200 unless otherwise noted. All 1 2 MIN to TMAX unless otherwise noted.) 3.3 V TIMING CHARACTERISTICS specifications T Parameter Max Unit 400 2 kHz µs µs µs µs ns ns ns µs 8 0.1 ns ns 27 2 3 4 2.0 13 12 37 MHz ns ns ns ns ns ns ns ns Clock Cycles TELETEXT PORT4 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 11 3 6 ns ns ns RESET CONTROL RESET Low Time 3 PLL PLL Output Frequency 54 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 Min 0 0.6 1.3 0.6 0.6 100 300 300 0.6 ANALOG OUTPUTS Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT 3 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 (2× Oversampling) Typ 8 8 6 4 2, 5 3 20 ns MHz NOTES 1 Temperature range T MIN to TMAX: 0°C to 70°C. 2 Guaranteed by characterization. 3 Pixel Port consists of: Data: P7­P0, Y0/P8­Y7/P15 Y7/P15 Pixel Inputs Control: HSYNC, VSYNC, BLANK Clock: CLKIN 4 Teletext Port consists of: Digital Output: TTXRQ Data: TTX Specifications subject to change without notice. REV. 0 ­7­ Test Conditions After This Period the First Clock Is Generated Relevant for Repeated Start Condition ADV7192 ADV7192 t5 t3 t3 SDA t6 t1 SCL t2 t7 t4 t8 Figure 1. MPU Port Timing Diagram CLOCK t9 CONTROL I/PS PIXEL INPUT DATA CONTROL O/PS t12 t10 HSYNC, VSYNC, BLANK Cb Y Cr Y Cb t11 HSYNC, VSYNC, BLANK, CSO_HSO, VSO, CLAMP Y t13 t14 Figure 2. Pixel and Control Data Timing Diagram TXTREQ t16 CLOCK t17 t18 TXT 4 CLOCK CYCLES 4 CLOCK CYCLES 4 CLOCK CYCLES 3 CLOCK CYCLES 4 CLOCK CYCLES Figure 3. Teletext Timing Diagram CLOCK PROGRESSIVE SCAN INPUT Y0­Y9 INCLUDING SYNC INFORMATION t9 t 12 t 10 Y0 Y1 Y2 Y3 Y4 Y5 Cb0­Cb9 Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 Cr0­Cr9 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 t 11 Figure 4. Progressive Scan Input Timing ­8­ REV. 0 ADV7192 ADV7192 ABSOLUTE MAXIMUM RATINGS 1 PACKAGE THERMAL PERFORMANCE VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on any Digital Input Pin . . GND ­ 0.5 V to VAA + 0.5 V Storage Temperature (TS) . . . . . . . . . . . . . . ­65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 220°C Analog Outputs to GND2 . . . . . . . . . . . . GND ­ 0.5 V to VAA The 80-lead package is used for this device. The junction-toambient (JA) thermal resistance in still air on a four-layer PCB is 24.7°C. To reduce power consumption when using this part the user can run the part on a 3.3 V supply, turn off any unused DACs. The user must at all times stay below the maximum junction temperature of 110°C. The following equation shows how to calculate this junction temperature: NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. Junction Temperature = (VAA × (IDAC + ICCT) × JA + 70°C TAMB IDAC = 10 mA + (sum of the average currents consumed by each powered-on DAC) Average current consumed by each powered-on DAC = (VREF × K )/RSET VREF = 1.235 V K = 4.2146 CSO_HSO VSO/ TTX/CLAMP Cr[0] Cr[3] Cr[2] Cr[1] DGND VDD Cr[4] Cr[5] Cr[6] Cr[8] Cr[7] Cb[0] Cr[9] Cb[2] Cb[1] VDD Cb[3] DGND PIN CONFIGURATION 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NC 1 NC 2 60 RESET PIN 1 IDENTIFIER 59 PAL_NTSC P0 3 P1 4 58 RSET1 57 V REF 56 COMP 1 P2 5 P3 6 P4 7 55 DAC A 54 DAC B P5 8 53 VAA 52 AGND ADV7192 ADV7192 LQFP P6 9 P7 10 Y[0]/P8 11 51 DAC C TOP VIEW (Not to Scale) 50 DAC D Y[1]/P9 12 Y[2]/P10 13 49 AGND 48 VAA 47 DAC E Y[3]/P11 14 Y[4]/P12 15 Y[5]/P13 16 46 DAC F Y[6]/P14 17 44 RSET2 43 DGND 45 COMP 2 Y[7]/P15 18 Y[8] 19 42 ALSB Y[9] 20 41 SCRESET/RTC/TR SCL SDA AGND CLKIN CLKOUT VAA DGND VDD TTXREQ Cb[9] Cb[8] Cb[7] Cb[6] Cb[5] VSYNC BLANK Cb[4] HSYNC VDD NC = NO CONNECT DGND 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ORDERING GUIDE Model Temperature Range Package Description Package Option ADV7192KST ADV7192KST 0°C to 70°C 80-Lead Quad Flatpack ST-80 ST-80 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7192 ADV7192 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 ­9­ WARNING! ESD SENSITIVE DEVICE ADV7192 ADV7192 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Input/ Output 1, 2 3­10 NC P0­P7 I 11­18 Y0/P8­Y7/P15 Y7/P15 I 19, 20 21, 34, 68, 79 22, 33, 43, 69, 80 23 Y8­Y9 VDD DGND P G HSYNC I/O 24 VSYNC I/O 25 BLANK I/O 26­31, 75­78 32 35, 49, 52 36 Cb4­Cb9, Cb0­Cb3 I TTXREQ O AGND G CLKIN I 37 38, 48, 53 39 40 41 42 44 CLKOUT VAA SCL SDA SCRESET/ RTC/TR ALSB RSET2 I I 45 COMP 2 O 46 47 50 DAC F DAC E DAC D O O O 51 54 55 DAC C DAC B DAC A O O O 56 57 COMP 1 VREF O I/O 58 RSET1 I 59 60 PAL_NTSC RESET I I 61 62 CSO_HSO VSO/TTX/CLAMP O I/O 63­67, 70­74 Cr0­Cr4, Cr5­Cr9 I O P I I/O I Function No Connect. 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on Pin P0 (Pin Number 3). 16-Bit 4:2:2 Multiplexed YCrCb Pixel Port (Bits 8­15). 1 × 10-bit progressive scan input for Ydata (Bits 0­7). 1 × 10-bit progressive scan input is Ydata (Bits 8 and 9). Digital Power Supply (3.3 V to 5 V). Digital Ground. HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be configured to be an output (Master Mode) or an input (Slave Mode) and accept Sync Signals. VSYNC Control Signal. This pin may be configured as an output (Master Mode) or as an input (Slave Mode) and accept VSYNC as a Control Signal. Video Blanking Control Signal. This signal is optional. For further information see Vertical Blanking and Data Insertion Blanking Input section. 1 × 10-Bit Progressive Scan Input Port for Cb data. Teletext Data Request Output Signal, used to control teletext data transfer. Analog Ground. TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation. Clock Output pin. Analog Power Supply (3.3 V to 5 V). MPU Port Serial Interface Clock Input. MPU Port Serial Data Input/Output. Multifunctional Input: Real Time Control (RTC) input, Timing Reset input, Subcarrier Reset input. TTL Address Input. This signal sets up the LSB of the MPU address. A 1200 resistor connected from this pin to GND is used to control full-scale amplitudes of the Video Signals from the DAC D, E, F. Compensation Pin for DACs D, E, and F. Connect a 0.1 µF Capacitor from COMP2 to VAA. S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output. S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output. Composite/Y (progressive scan)/Y/Green Analog Output. This DAC is capable of providing 4.33 mA output. S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output. S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output. Composite/Y(progressive scan)/Y/Green Analog Output. This DAC is capable of providing 4.33 mA output. Compensation Pin for DACs A, B, and C. Connect a 0.1 µF Capacitor from COMP1 to VAA. Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external VREF cannot be used in 4× Oversampling Mode. A 1200 resistor connected from this pin to GND is used to control full-scale amplitudes of the Video Signals from the DAC A, B, C. Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL. The input resets the on-chip timing generator and sets the ADV7192 ADV7192 into default mode. See Appendix 8 for Default Register settings. Dual function CSO or HSO Output Sync Signal at TTL Level. Multifunctional Pin. VSO Output Sync Signal at TTL level. Teletext Data Input pin. CLAMP TTL output signals can be used to drive external circuitry to enable clamping of all video signals. 1 × 10-Bit progressive scan input port for Cr data. ­10­ REV. 0 ADV7192 ADV7192 to input video data in 3 10-bit YCrCb progressive scan format to facilitate interfacing devices such as progressive scan systems. DETAILED DESCRIPTION OF FEATURES Clocking: Single 27 MHz Clock Required to Run the Device 4 Oversampling with Internal 54 MHz PLL Square Pixel Operation Advanced Power Management Programmable Video Control Features: Digital Noise Reduction Black Burst Signal Generation Pedestal Level Hue, Brightness, Contrast, and Saturation Clamping Output Signal VBI (Vertical Blanking Interval) Subcarrier Frequency and Phase LUMA Delay CHROMA Delay Gamma Correction Luma And Chroma Filters Luma SSAF (Super Subalias Filter) Average Brightness Detection Field Counter Interlaced/Noninterlaced Operation Complete On-Chip Video Timing Generator Programmable Multimode Master/Slave Operation Macrovision Rev 7.1 CGMS (Copy Generation Management System) WSS (Wide Screen Signaling) Closed Captioning Support Teletext Insertion Port (PAL-WST) 2-Wire Serial MPU Interface (I2C-Compatible And Fast I 2C) I2C Registers Synchronized to VSYNC Six DACs are available on the ADV7192 ADV7192, each of which is capable of providing 4.33 mA of current. In addition to the composite output signal there is the facility to output S-Video (Y/C Video), RGB Video and YUV Video. All YUV formats (SMPTRE/EBU N10, MII or Betacam) are supported. The on-board SSAF (Super Subalias Filter) with extended luminance frequency response and sharp stopband attenuation enables studio quality video playback on modern TVs, giving optimal horizontal line resolution. An additional sharpness control feature allows high-frequency enhancement on the luminance signal. DNR MODE DNR CONTROL NOISE SIGNAL PATH HSYNC VSYNC BLANK DNR CONTROL TTX 10 10 YCrCb- Y TO10 YUV U MATRIX 10 DNR Y AND 10 GAMMA U CORRECTION 10 V V 10 10 10 P0 BRIGHTNESS CONTROL AND ADD SYNC AND INTERPOLATOR SATURATION CONTROL AND ADD BURST AND INTERPOLATOR INPUT FILTER BLOCK FILTER OUTPUT >THRESHOLD? Y DATA INPUT FILTER OUTPUT< THRESHOLD MAIN SIGNAL PATH ADV7192 ADV7192 SCL SDA ALSB Cr0­Cr9 I2C MPU PORT PROGRAMMABLE LUMA FILTER AND SHARPNESS FILTER PROGRAMMABLE CHROMA FILTER YUV-TO-RGB MATRIX AND YUV LEVEL CONTROL BLOCK MODULATOR AND HUE CONTROL REAL-TIME CONTROL CIRCUIT SIN/COS DDS BLOCK CLKOUT SCRESET/RTC/TR Figure 5. Detailed Functional Block Diagram REV. 0 DNR OUT Figure 6. Block Diagram for DNR Mode and DNR Sharpness Mode DEMUX PLL ADD SIGNAL ABOVE THRESHOLD RANGE TO ORIGINAL SIGNAL NOISE SIGNAL PATH P15 CLKIN GAIN BLOCK SIZE CONTROL CORING GAIN DATA BORDER AREA CORING GAIN BORDER BLOCK OFFSET RESET TTXRQ DNR OUT DNR SHARPNESS MODE CGMS/WSS AND CLOSED CAPTIONING CONTROL TELETEXT INSERTION BLOCK FILTER OUTPUT> THRESHOLD MAIN SIGNAL PATH CSO_HSO VIDEO TIMING GENERATOR FILTER OUTPUT