ADT7490 ADT7473/ADT7475/ ADT7476/ADT7476A ADT7490/D ADT7476A 12VIN 10-BIT - Datasheet Archive

 

Controller with PECI Interface ADT7490 FEATURES GENERAL DESCRIPTION Temperature measurement 1 local on-chip temperature sensor 2

 

dBCool® Remote Thermal Monitor and Fan Controller with PECI Interface ADT7490 ADT7490 FEATURES GENERAL DESCRIPTION Temperature measurement 1 local on-chip temperature sensor 2 remote temperature sensors 3-current external temperature sensors with series resistance cancellation (SRC) PECI interface for CPU thermal information and support of up to 4 PECI inputs on one pin Fan drive and fan speed control 3 high frequency or low frequency PWM outputs for use with 3-wire or 4-wire fans 4 TACH inputs to measure fan speed OS independent automatic fan speed control based on thermal information Dynamic TMIN control mode to optimize system acoustics Default startup at 100% PWM for all fans for robust operation Bidirectional THERM/SMBALERT pin to flag out-of-limit and overtemperature conditions GPIO functionality to support extra features Can be used for loadline setting for voltage regulation, LED control, or other functions IMON monitoring for CPU current and power information Footprint and register compatible with ADT7473/ADT7475/ ADT7473/ADT7475/ ADT7476/ADT7476A ADT7476/ADT7476A family of fan controllers SMBus interface with addressing capability for up to 3 devices The ADT7490 ADT7490 is a dBCool thermal monitor and multiple PWM fan controller for noise-sensitive or power-sensitive applications requiring active system cooling. The ADT7490 ADT7490 includes a local temperature sensor, two remote temperature sensors including series resistance cancellation, and monitors CPU temperature with a PECI interface. The ADT7490 ADT7490 can drive a fan using either a low or high frequency drive signal, and measure and control the speed of up to four fans so they operate at the lowest possible speed for minimum acoustic noise. The automatic fan speed control loop optimizes fan speed for a given temperature using the PECI, remote, or local temperature information. The effectiveness of the system's thermal solution can be monitored using the THERM input. The ADT7490 ADT7490 also provides critical thermal protection to the system using the bidirectional THERM/SMBALERT pin as an output to prevent system or component overheating. APPLICATIONS Personal computers Servers ©2008 SCILLC. All rights reserved. February 2008 ­ Rev. 1 Publication Order Number: ADT7490/D ADT7490/D ADT7490 ADT7490 TABLE OF CONTENTS Features.1 Limits, Status Registers, and Interrupts .26 Applications .1 Limit Values .26 General Description.1 Interrupt Status Registers.27 Revision History.2 THERM Timer.29 Functional Block Diagram.3 Fan Drive Using PWM Control .32 Specifications .4 Laying Out 3-Wire Fans.33 Absolute Maximum Ratings .7 Programming TRANGE .37 Thermal Characteristics.7 Programming the Automatic Fan Speed Control loop.38 ESD Caution .7 Manual Fan Control Overview .38 Pin Configuration and Function Descriptions .8 THERM Operation in Manual Mode .38 Typical Performance Characteristics.10 Automatic Fan Control Overview .38 Theory of Operation.13 Step 1: Hardware Configuration .39 Feature Comparisons Between the ADT7490 ADT7490 and ADT7476A ADT7476A.13 Step 2: Configuring the Muxtiplexer.39 Start-Up Operation.14 Serial Bus Interface .14 Write Operations.15 Read Operations.16 SMBus Timeout.17 Voltage Measurement Input .17 Additional ADC Functions for Voltage Measurements.18 Temperature Measurement.20 Thermal Diode Temperature Measurement Method.22 Series Resistance Cancellation .23 Factors Affecting Diode Accuracy.23 Step 3: TMIN Settings for Thermal Calibration Channels .40 Step 4: PWMMIN for Each PWM (Fan) Output .42 Step 5: PWMMAX for PWM (Fan) Outputs .42 Step 6: TRANGE for Temperature Channels .43 Step 7: TTHERM for Temperature Channels .45 Step 8: THYST for Temperature Channels .46 Programming the GPIOs .48 XNOR Tree Test Mode .48 Register Tables .49 Outline Dimensions.78 Ordering Guide .78 Additional ADC Functions for Temperature Measurement.24 REVISION HISTORY 02/08-Rev 1: Preliminary Datasheet Status Change 02/08-Rev P2: Conversion to ON Semiconductor 12/07-Rev. 0 to Rev. A Changes to Table 3 .6 Changes to Local Temperature Measurement Section.20 Changes to Table 22 .27 Changes to Configuring the Relevant THERM Behavior Section .29 07/07-Revision 0: Initial Version Rev.1 | Page 2 of 78 | www.onsemi.com ADT7490 ADT7490 FUNCTIONAL BLOCK DIAGRAM ADDR SELECT SCL SDA ADT7490 ADT7490 SMBus ADDRESS SELECTION GPIO1 SERIAL BUS INTERFACE GPIO REGISTER GPIO2 PERFORMANCE MONITORING THERM/ SMBALERT THERMAL PROTECTION FAN SPEED COUNTER TACH1 TACH2 TACH3 TACH4 PWM2 PWM3 PWM REGISTERS AND CONTROLLERS (HF AND LF) PECI PWM CONFIGURATION REGISTERS ACOUSTIC ENHANCEMENT AUTOMATIC FAN SPEED CONTROL INTERRUPT MASKING DYNAMIC TMIN CONTROL PECI INTERFACE VTT ACOUSTIC ENHANCEMENT CONTROL VCC VCCP +12VIN 12VIN INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER +5VIN +2.5VIN IMON D1+ 10-BIT 10-BIT ADC BAND GAP REFERENCE D1­ D2+ D2­ INTERRUPT STATUS REGISTERS LIMIT COMPARATORS VALUE AND LIMIT REGISTERS BAND GAP TEMP. SENSOR GND Figure 1. Rev. 1 | Page 3 of 78 | www.onsemi.com 06789-001 PWM1 ADDRESS POINTER REGISTER ADT7490 ADT7490 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and represent a parametric norm. Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge. Table 1. Parameter POWER SUPPLY Supply Voltage Supply Current, ICC TEMPERATURE-TO-DIGITAL CONVERTER Local Sensor Accuracy Min Typ Max Unit Test Conditions/Comments 3.0 3.3 1.5 3.6 5 V mA Interface inactive, ADC active ±0.5 ±1.5 ±2.5 1.5 °C °C °C °C °C °C A A k ±2 ±1.5 % % ±1 LSB %/V 13 14 14 43 193 ms ms ms ms ms ms k k Averaging enabled, all channels excluding VTT2 Averaging enabled Averaging enabled Averaging enabled Averaging enabled Averaging disabled For +12VIN 12VIN channel For all other channels ±10 ±14 65,535 % % 0°C TA 85°C -40°C TA +125°C RPM RPM RPM RPM Fan count = 0xBFFF Fan count = 0x3FFF Fan count = 0x0438 Fan count = 0x021C mA V A IOUT = -8.0 mA VOUT = VCC Resolution Remote Diode Sensor Accuracy 0.25 ±0.5 Resolution Remote Sensor Source Current 0.25 12 72 192 Series Resistance Cancellation1 ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENTUATORS) Total Unadjusted Error (TUE) Differential Nonlinearity (DNL) Power Supply Sensitivity Conversion Times1 Voltage Inputs VTT Voltage Input2 Local Temperature Remote Temperature Total Monitoring Cycle Time Input Resistance ±0.1 150 70 11 12 12 38 169 19 200 100 FAN RPM-TO-DIGITAL CONVERTER Accuracy Full-Scale Count Nominal Input RPM OPEN-DRAIN DIGITAL OUTPUTS, PWM1 TO PWM3, XTO Current Sink, IOL Output Low Voltage, VOL High Level Output Current, IOH ±1.5 ±2.5 109 329 5000 10,000 0.1 8.0 0.4 20 Rev.1 | Page 4 of 78 | www.onsemi.com 0°C TA 85°C -40°C TA +125°C 0°C TA 85°C -40°C TA +125°C Low level Mid level High level The ADT7490 ADT7490 cancels up to 2 k in series with the remote thermal sensor For all channels: -40°C TA +125°C For all other channels except +12VIN 12VIN: 0°C TA +125°C 8 bits ADT7490 ADT7490 Parameter OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Current, IOH SMBus DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis Digital I/O (PECI PIN)1 VTT, Supply Voltage Input High Voltage , VIH Input Low Voltage, VIL Hysteresis1 High Level Output Source Current, ISOURCE Low Level Output Sink Current, ISINK Signal Noise Immunity, VNOISE DIGITAL INPUT LOGIC LEVELS (TACH1 to TACH3) Input High Voltage, VIH Min Typ Max Unit Test Conditions/Comments 0.1 0.4 1.0 V A IOUT = -4.0 mA VOUT = VCC 2.0 0.4 500 0.95 1.26 0.55 × VTT2 0.5 × VTT2 0.1 × VTT2 6 1.0 0.5 300 2.0 5.5 Input Low Voltage, VIL 0.8 -0.3 Hysteresis DIGITAL INPUT LOGIC LEVELS (THERM) Input High Voltage, VIH Input Low Voltage, VIL DIGITAL INPUT CURRENT Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN SERIAL BUS TIMING1 Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU;DAT Detect Clock Low Timeout, tTIMEOUT 1 2 0.5 0.75 × VCC 0.4 ±1 ±1 5 V V mV V V V mV mA mA mV p-p V V V V V p-p Hysteresis between input switching levels VOH = 0.75 × VTT VOL = 0.25 × VTT Noise glitches from 10 MHz to 100 MHz, width up to 50 ns Maximum input voltage Minimum input voltage V V A A pF VIN = VCC VIN = 0 See Figure 2 10 4.7 4.7 4.0 250 15 400 50 50 1000 300 35 kHz ns s s s ns s ns ms Guaranteed by design, not production tested. VTT is the voltage input on Pin 8. The VTT voltage is determined by the processor installed on the system. Rev. 1 | Page 5 of 78 | www.onsemi.com Can be optionally disabled ADT7490 ADT7490 tLOW tR tF tHD;STA SCL SDA tBUF P S tHD;DAT tHIGH tSU;STA tSU;DAT S Figure 2. SMBus Timing Diagram Rev.1 | Page 6 of 78 | www.onsemi.com tSU;STO P 06789-002 tHD;STA ADT7490 ADT7490 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Positive Supply Voltage (VCC) Maximum Voltage on +12VIN 12VIN Pin Maximum Voltage on +5VIN Pin Maximum Voltage on All Open-Drain Outputs Maximum Voltage on TACHx/PWMx Pins Voltage on Remaining Input or Output Pins Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJ max) Storage Temperature Range Lead Temperature, Soldering IR Reflow Peak Temperature Pb-Free Peak Temperature Lead Temperature (Soldering, 10 sec) ESD Rating HBM FICDM Rating 3.6 V 16 V 6.25 V 3.6 V +5.5 V -0.3 V to +4.2 V ±5 mA ±20 mA 150°C -65°C to +150°C THERMAL CHARACTERISTICS Table 3. Thermal Resistance Package Type 24-lead QSOP ESD CAUTION 220°C 260°C 300°C 2 kV 0.5 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 1 | Page 7 of 78 | www.onsemi.com JA 122 JC 31.25 Unit °C/W ADT7490 ADT7490 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SDA 1 24 PWM1/XTO SCL 2 23 VCCP GND 3 22 +2.5VIN/THERM VCC 4 21 +12V IN GPIO1 5 20 +5VIN GPIO2 6 PECI 7 ADT7490 ADT7490 IMON TOP VIEW (Not to Scale) 18 D1+ 19 17 D1­ 16 D2+ 10 15 D2­ TACH1 11 14 TACH4/THERM/SMBALERT/ADDR SELECT TACH2 12 13 PWM3/ADDREN PWM2/SMBALERT 06789-003 VTT 8 TACH3 9 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic SDA SCL GND VCC GPIO1 Type Digital I/O Digital Input Ground Power Supply Digital Input/Output 6 GPIO2 Digital Input/Output 7 PECI Digital Input 8 VTT Analog Input 9 10 TACH3 PWM2/ Digital Input Digital Output SMBALERT 11 12 13 TACH1 TACH2 PWM3/ Digital Input Digital Input Digital Output ADDREN 14 TACH4/ THERM/ Digital Input/Output Fan Tachometer Input to Measure Speed of Fan 4 (Open-Drain Digital Input). May be reconfigured as a bidirectional THERM pin. Can be connected to the PROCHOT output of the processor, to time and monitor PROCHOT assertions. Can be used as an output to signal overtemperature conditions or for clock modulation purposes. Active Low Digital Output. The SMBALERT pin is used to signal out-of-limit comparisons of temperature, voltage, and fan speed. This is compatible with SMBus alert. Can also be used at device power-up to assign SMBus address. Analog Input Analog Input Analog Input Analog Input Negative Connection for Remote Temperature Sensor 2. Positive Connection to Remote Temperature Sensor 2. Negative Connection for Remote Temperature Sensor 1. Positive Connection to Remote Temperature Sensor 1. SMBALERT/ ADDR SELECT 15 16 17 18 D2- D2+ D1- D1+ Description SMBus Bidirectional Serial Data. Open drain, requires SMBus pull-up. SMBus Serial Clock Input. Open drain, requires SMBus pull-up. Ground Pin. 3.3 V ± 10%. General-Purpose Open-Drain Digital Input/Output. Frequently used for switching loadline resistors into VR loadline circuitry or for switching LEDs using external FETs. General-Purpose Open-Drain Digital Input/Output. Frequently used for switching loadline resistors into VR loadline circuitry or for switching LEDs using external FETs. PECI Input to Report CPU Thermal Information. PECI voltage level is referenced on the VTT input. Voltage Reference for PECI. This is the supply voltage for the PECI interface and must be present to measure temperature over the PECI interface. This voltage is also monitored and presented in Register 0x1E. Fan Tachometer Input to Measure Speed of Fan 3 (Open-Drain Digital Input). Pulse-Width Modulated Output to Control Fan 2 Speed. Open drain requires 10 k typical pull-up. Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. Fan Tachometer Input to Measure Speed Of Fan 1 (Open-Drain Digital Input). Fan Tachometer Input To Measure Speed Of Fan 2 (Open-Drain Digital Input). Pulse-Width Modulated Output to Control Fan 3 Speed. Open drain requires 10 k typical pull-up. If pulled low on power-up, the ADT7490 ADT7490 enters address select mode, and the state of Pin 14 (ADDR SELECT) determines the ADT7490 ADT7490 slave address. Rev.1 | Page 8 of 78 | www.onsemi.com ADT7490 ADT7490 Pin No. 19 Mnemonic IMON Type Analog Input 20 21 22 +5VIN +12VIN 12VIN +2.5VIN/ THERM Analog Input Analog Input Analog Input 23 VCCP Analog Input 24 PWM1/ Digital Output XTO Description Monitors Current Output of Analog Devices ADP319x family of VRD10/VRD11 VRD10/VRD11 controllers. Monitors 5 V Supply Using Internal Resistor Dividers. Monitors 12 V Supply Using Internal Resistor Dividers. Monitors 2.5 V Supply Using Internal Resistor Dividers. Alternatively, this pin can be reconfigured as a bidirectional THERM pin. Can be connected to the PROCHOT output of the processor to time and monitor PROCHOT assertions. Can be used as an output to signal overtemperature conditions or for clock modulation purposes. Monitors CPU VCC Voltage (to maximum of 3.0 V). All voltage inputs can have their resistor dividers removed allowing for full-scale input of 2.25 V of the ADC channel. Pulse-Width Modulated Output to Control Fan 1 Speed. Open drain requires 10 k typical pull-up. Also functions as the output for the XNOR tree test enable mode. Table 5. Comparison of ADT7490 ADT7490 and ADT7476A ADT7476A Configurations Pin Number ADT7490 ADT7490 ADT7476A ADT7476A 1 SDA SDA 2 SCL SCL 3 GND GND 4 VCC VCC 5 GPIO1 VID0/GPIO0 6 GPIO2 VID1/GPIO1 7 PECI VID2/GPIO2 8 VTT VID3/GPIO3 9 TACH3 TACH3 10 PWM2/SMBALERT PWM2/SMBALERT 11 TACH1 TACH1 12 TACH2 TACH2 13 PWM3/ADDREN PWM3/ADDREN 14 TACH4/THERM/SMBALERT/ADDR SELECT TACH4/THERM/SMBALERT/GPIO6/ADDR SELECT 15 D2- D2- 16 D2+ D2+ 17 D1- D1- 18 D1+ D1+ 19 IMON VID4/GPIO4 20 +5VIN +5VIN 21 +12VIN 12VIN +12VIN/VID5 12VIN/VID5 22 +2.5VIN/THERM +2.5VIN/THERM 23 VCCP VCCP 24 PWM1/XTO PWM1/XTO Rev. 1 | Page 9 of 78 | www.onsemi.com ADT7490 ADT7490 3.0 4.7 DEV 1 DEV 2 DEV 3 DEV 4 DEV 5 DEV 6 DEV 7 DEV 8 DEV 9 DEV 10 DEV 11 DEV 12 DEV 13 DEV 14 DEV 15 DEV 16 DEV 17 DEV 18 DEV 19 DEV 20 DEV 21 DEV 22 DEV 23 DEV 24 DEV 25 DEV 26 DEV 27 DEV 28 DEV 29 DEV 30 DEV 31 DEV 32 MEAN LOW SPEC HIGH SPEC 2.5 DEV 1 DEV 3 4.1 DEV 2 3.9 3.7 2.0 1.5 1.0 0.5 0 ­0.5 ­1.0 ­1.5 3.1 3.2 3.3 3.4 3.5 3.6 VDD (V) ­2.0 ­40 06789-006 3.5 3.0 ­20 0 25 40 60 70 85 100 125 TEMPERATURE (°C) Figure 7. Remote 1 Temperature Sensor Error Figure 4. Supply Current vs. Supply Voltage 4.24 3.0 DEV 1 DEV 2 DEV 3 DEV 4 DEV 5 DEV 6 DEV 7 DEV 8 DEV 9 DEV 10 DEV 11 DEV 12 DEV 13 DEV 14 DEV 15 DEV 16 DEV 17 DEV 18 DEV 19 DEV 20 DEV 21 DEV 22 DEV 23 DEV 24 DEV 25 DEV 26 DEV 27 DEV 28 DEV 29 DEV 30 DEV 31 DEV 32 MEAN LOW SPEC HIGH SPEC 2.5 4.22 TEMPERATURE ERROR (°C) NORMAL IDD (mA) DEV 2 4.20 4.18 DEV 1 4.16 4.14 DEV 3 2.0 1.5 1.0 0.5 0 ­0.5 ­1.0 ­1.5 ­20 0 20 40 60 80 100 120 TEMPERATURE (°C) ­2.0 ­40 06789-007 4.12 ­40 ­20 1.5 1.0 0.5 0 ­0.5 ­1.0 40 60 70 85 100 TEMPERATURE (°C) 70 85 100 125 125 EXTERNAL 2 EXTERNAL 1 100 LOCAL 80 60 40 20 0 06789-072 2.0 25 60 120 MEASURED TEMPERATURE (°C) TEMPERATURE ERROR (°C) 2.5 140 06789-008 DEV 1 DEV 2 DEV 3 DEV 4 DEV 5 DEV 6 DEV 7 DEV 8 DEV 9 DEV 10 DEV 11 DEV 12 DEV 13 DEV 14 DEV 15 DEV 16 DEV 17 DEV 18 DEV 19 DEV 20 DEV 21 DEV 22 DEV 23 DEV 24 DEV 25 DEV 26 DEV 27 DEV 28 DEV 29 DEV 30 DEV 31 DEV 32 MEAN LOW SPEC HIGH SPEC 0 40 Figure 8. Remote 2 Temperature Sensor Error 3.0 ­20 25 TEMPERATURE (°C) Figure 5. Supply Current vs. Temperature ­1.5 ­40 0 0 10 20 30 40 50 TIME (s) Figure 9. ADT7490 ADT7490 Response to Thermal Shock Figure 6. Local Temperature Sensor Error Rev.1 | Page 10 of 78 | www.onsemi.com 60 06789-010 NORMAL IDD (mA) 4.3 TEMPERATURE ERROR (°C) 4.5 06789-009 TYPICAL PERFORMANCE CHARACTERISTICS ADT7490 ADT7490 8 20 DEV 1 15 TEMPERATURE ERROR (°C) 4 2 0 DEV 3 ­2 ­4 10 400 600 800 1000 1200 1400 1600 SERIES RESISTANCE () ­10 200 300 500 600 160 100mV 250mV 140 TEMPERATURE ERROR (°C) 3.0 2.5 2.0 1.5 1.0 0.5 0 120 100 80 60 100mV 40 60mV 20 0 ­1.0 ­20 0 100 200 300 400 500 600 POWER SUPPLY NOISE FREQUENCY (MHz) 06789-011 ­0.5 Figure 11. Local Temperature Error vs. Power Supply Noise Frequency 40mV 0 100 200 300 400 500 600 DIFFERENTIAL MODE NOISE FREQUENCY (MHz) 06789-014 3.5 Figure 14. Temperature Error vs. Differential Mode Noise Frequency 5 0.6 100mV 250mV 0.4 0 TEMPERATURE ERROR (°C) 0.2 0 ­0.2 ­0.4 ­0.6 ­0.8 DEV 3 ­5 DEV 2 ­10 ­15 DEV 1 ­20 ­25 ­30 0 100 200 300 400 500 POWER SUPPLY NOISE FREQUENCY (MHz) 600 06789-012 ­1.0 ­1.2 400 Figure 13. Temperature Error vs. Common-Mode Noise Frequency 4.0 TEMPERATURE ERROR (°C) 100 COMMON-MODE NOISE FREQUENCY (MHz) Figure 10. Temperature Error vs. Series Resistance TEMPERATURE ERROR (°C) 0 06789-013 ­5 06789-071 200 40mV 0 DEV 2 0 60mV 5 ­6 ­8 100mV Figure 12. Remote Temperature Error vs. Power Supply Noise Frequency ­35 0 2 4 6 8 10 12 14 16 18 20 22 CAPACITANCE (nF) Figure 15. Temperature Error vs. Capacitance Between D+ and D- Rev. 1 | Page 11 of 78 | www.onsemi.com 06789-015 TEMPERATURE ERROR (°C) 6 ADT7490 ADT7490 1.5 8 DEV 2 1.0 ACCURACY (%) 0 ­0.5 ­1.0 DEV 1 2 DEV 2 0 ­2 ­4 ­1.5 3.1 3.2 3.3 3.4 3.5 VDD (V) 3.6 ­8 ­40 Figure 16. TACH Accuracy vs. Supply Voltage ­20 0 20 40 60 80 TEMPERATURE (°C) Figure 17. TACH Accuracy vs. Temperature Rev.1 | Page 12 of 78 | www.onsemi.com 100 120 06789-070 ­6 06789-069 ­2.0 3.0 DEV 3 4 DEV 3 0.5 ACCURACY (%) 6 DEV 1 ADT7490 ADT7490 THEORY OF OPERATION The ADT7490 ADT7490 is a complete thermal monitor and multiple fan controller for any system requiring thermal monitoring and cooling. The device communicates with the system via a serial system management bus. The serial bus controller has a serial data line for reading and writing addresses and data (Pin 1), and an input line for the serial clock (Pin 2). All control and programming functions for the ADT7490 ADT7490 are performed over the serial bus. In addition, Pin 14 can be reconfigured as an SMBALERT output to signal out-of-limit conditions. Temperature Data REPLACE Mode FEATURE COMPARISONS BETWEEN THE ADT7490 ADT7490 AND ADT7476A ADT7476A Fan Control Using PECI Information PECI Input CPU thermal information is provided through the PECI input. The ADT7490 ADT7490 has PECI master capabilities and can read the CPU thermal information through the PECI interface. Each CPU address can have up to two PECI domains. The ADT7490 ADT7490 has the ability to record four PECI temperature readings corresponding to the four PECI addresses of 0x30 to 0x33. The hotter of the two domains at any given address is stored in the PECI value registers. A PECI reading is a negative value, in degrees Celsius, which represents the offset from the thermal control circuit (TCC) activation temperature. PECI information is not converted to absolute temperature reading. PECI information is in a 16-bit twos complement value; however, the ADT7490 ADT7490 records the sign bit as well as the bits from 12:6 in the 16-bit PECI payload. See the Platform Environment Control Interface (PECI) Specification from Intel® for more details on the PECI data format. The PECI format is represented in Table 6. Table 6. PECI Data Format MSB Upper Nibble S x Sign Bit x PWM = 100% PWMMAX PECI = 0 PWMMIN TCC TRANGE PWM = 0% PECIMIN (TMIN) (TMAX) TCONTROL Figure 18. Overview of Automatic Fan Speed Control Using PECI Thermal Information Dynamic TMIN Fan Control Mode MSB Lower Nibble x x x x Integer value (0°C to 127°C) x There are associated high and low limits for each PECI reading that can be programmed. The limit values take the same format as the PECI reading. Therefore, the programmed limits are not absolute temperatures but a relative offset in degrees Celcius from the TCC activation temperature. An out-of-limit event is recorded as follows: · · The CPU thermal information from PECI can be used in the existing automatic fan control algorithms. This temperature reading remains relative to TCC activation temperature and the associated AFC control parameters are programmed in relative temperatures as opposed to absolute temperatures, and are in the same format as detailed in Table 6. PECIMIN, TRANGE, and TCONTROL are user defined. 06789-005 The ADT7490 ADT7490 is pin and register map compatible with the ADT7476A ADT7476A. The new or additional features are detailed in the following sections. The REPLACE mode is configured by setting Bit 4 of Register 0x36. In this mode, the data in the existing Remote 1 registers are replaced by PECI0 data and vice versa. This is a legacy mode that allows the thermal data from CPU1 to be stored in the same registers as in the ADT7476A ADT7476A. This reduces the software changes in systems transitioning from CPUs with thermal diodes to CPUs with a PECI interface. See the PECI Temperature Measurement section for more details. High Limit > comparison performed Low Limit comparison performed The automatic fan speed control incorporates a feature called dynamic TMIN control. This intelligent fan control feature reduces the design effort required to program the automatic fan speed control loop and improves the system acoustics. VTT Input The VTT voltage is monitored on Pin 8. This voltage is also used as the reference voltage for the PECI interface. The VTT voltage must be connected to the ADT7490 ADT7490 in order for the PECI interface to be operational. IMON Monitoring An out-of-limit event is recorded in the associated status register and can be used to assert the SMBALERT pin. The IMON input on Pin 19 can be used to monitor the IMON output of the Analog Devices ADP319x family of VR10/VR11 VR10/VR11 controllers. IMON is a voltage representation of the CPU current. Using the IMON value and the measured VCCP value on Pin 23, the Rev. 1 | Page 13 of 78 | www.onsemi.com ADT7490 ADT7490 CPU power consumption can be calculated. See the appropriate Analog Devices flex mode data sheet for calculations. The IMON information can be considered as an early indication of an increase in CPU temperature. START-UP OPERATION At startup, the ADT7490 ADT7490 turns the fans on to 100% PWM. This allows the most robust operation at turn-on. SERIAL BUS INTERFACE Control of the ADT7490 ADT7490 is carried out using the serial system management bus (SMBus). The ADT7490 ADT7490 is connected to this bus as a slave device, under the control of a master controller. The ADT7490 ADT7490 has a 7-bit serial bus address. When the device is powered up with Pin 13 (PWM3/ADDREN) high, the ADT7490 ADT7490 has a default SMBus address of 0101110 or 0x2E. The read/write bit must be added to obtain the 8-bit address. If more than one ADT7490 ADT7490 is to be used in a system, each ADT7490 ADT7490 is placed in address select mode by strapping Pin 13 low on power-up. The logic state of Pin 14 then determines the device's SMBus address. The logic of these pins is sampled on power-up. read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as no acknowledge. The master takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the ADT7490 ADT7490, write operations contain either one or two bytes, and read operations contain one byte. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed. Then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation must contain a second data byte that is written to the register selected by the address pointer register. The device address is sampled on power-up and latched on the first valid SMBus transaction, more precisely on the low-tohigh transition at the beginning of the eighth SCL pulse, when the serial bus address byte matches the selected slave address. The selected slave address is chosen using the ADDREN/ ADDR SELECT pins. Any attempted changes in the address have no effect after this. This write operation is shown in Figure 19. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. Table 7. Hardwiring the ADT7490 ADT7490 SMBus Device Address · Pin 13 State 0 0 1 Pin 14 State Low (10 k to GND) High (10 k pull-up) Don't care When reading data from a register, there are two possibilities: Address 0101100 (0x2C) 0101101 (0x2D) 0101110 (0x2E) Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In If the ADT7490 ADT7490 address pointer register value is unknown or not the desired value, it must first be set to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7490 ADT7490 as before, but only the data byte containing the register address is sent because no data is written to the register. This is shown in Figure 20. A read operation is then performed consisting of the serial bus address, R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 21. · If the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, as shown in Figure 21. Rev.1 | Page 14 of 78 | www.onsemi.com ADT7490 ADT7490 1 9 9 1 SCL SDA 0 1 0 START BY MASTER 1 1 1 0 D6 D7 R/W ACK. BY ADT7490 ADT7490 FRAME 1 SERIAL BUS ADDRESS BYTE D4 D5 D2 D3 D1 D0 ACK. BY ADT7490 ADT7490 FRAME 2 ADDRESS POINTER REGISTER BYTE 1 9 SCL (CONTINUED) D4 D5 D6 D2 D3 D1 D0 ACK. BY ADT7490 ADT7490 FRAME 3 DATA BYTE STOP BY MASTER 06789-016 D7 SDA (CONTINUED) Figure 19. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register 1 9 9 1 SCL 0 1 START BY MASTER 0 1 1 1 0 D6 D7 R/W ACK. BY ADT7490 ADT7490 FRAME 1 SERIAL BUS ADDRESS BYTE D4 D5 D3 D2 D1 D0 ACK. BY ADT7490 ADT7490 FRAME 2 ADDRESS POINTER REGISTER BYTE STOP BY MASTER 06789-017 SDA Figure 20. Writing to the Address Pointer Register Only 1 9 9 1 SCL START BY MASTER 0 1 0 1 1 1 0 R/W D6 D7 ACK. BY ADT7490 ADT7490 FRAME 1 SERIAL BUS ADDRESS BYTE D5 D4 D3 D2 D1 FRAME 2 DATA BYTE FROM ADT7490 ADT7490 D0 NO ACK. BY STOP BY MASTER MASTER 06789-018 SDA Figure 21. Reading Data from a Previously Selected Register It is possible to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register because the first data byte of a write is always written to the address pointer register. In addition to supporting the send byte and receive byte protocols, the ADT7490 ADT7490 also supports the read byte protocol (see System Management Bus Specifications Rev. 2 for more information; this document is available from the SMBus organization). If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7490 ADT7490 are discussed here. The following abbreviations are used in the diagrams: · · · · · · S: Start P: Stop R: Read W: Write A: Acknowledge A: No acknowledge The ADT7490 ADT7490 uses the following SMBus write protocols. Rev. 1 | Page 15 of 78 | www.onsemi.com ADT7490 ADT7490 Send Byte READ OPERATIONS In this operation, the master device sends a single command byte to a slave device, as follows: The ADT7490 ADT7490 uses the following SMBus read protocols. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master asserts a stop condition on SDA and the transaction ends. 3 4 5 6 REGISTER ADDRESS A P 06789-019 2 SLAVE S W A ADDRESS This operation is useful when repeatedly reading a single register. The register address must be previously set up. In this operation, the master device receives a single byte from a slave device, as follows: Figure 22. Setting a Register Address for Subsequent Read If the master is required to read data from the register immediately after setting up the address, it can assert a repeat start condition immediately after the final ACK and carry out a single-byte read without asserting an intermediate stop condition. 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts ACK on SDA. 4. The master receives a data byte. 5. The master asserts NO ACK on SDA. 6. For the ADT7490 ADT7490, the send byte protocol is used to write a register address to RAM for a subsequent single-byte read from the same address. This operation is illustrated in Figure 22. 1 Receive Byte The master asserts a stop condition on SDA, and the transaction ends. In the ADT7490 ADT7490, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. This operation is illustrated in Figure 24. 1 2 3 SLAVE S ADDRESS R A 4 5 6 DATA A P 06789-021 1. 2. Figure 24. Single-Byte Read from a Register Write Byte In this operation, the master device sends a command byte and one data byte to the slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). Alert Response Address Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The SMBALERT output can be used as either an interrupt output or an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device's SMBALERT line goes low, the following events occur: 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 1. SMBALERT is pulled low. 8. The master asserts a stop condition on SDA, and the transaction ends. 2. The master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known and can be interrogated in the usual way. If more than one device's SMBALERT output is low, the one with the lowest device address has priority in accordance with normal SMBus arbitration. The byte write operation is illustrated in Figure 23. 2 3 SLAVE S ADDRESS W A 4 5 6 REGISTER ADDRESS A DATA A P 3. 7 8 06789-020 1 Figure 23. Single Byte Write to a Register 4. 5. Once the ADT7490 ADT7490 has responded to the alert response address, the master must read the status registers, and the SMBALERT is cleared only if the error condition is gone. Rev.1 | Page 16 of 78 | www.onsemi.com ADT7490 ADT7490 SMBus TIMEOUT Register 0x23, +5VIN Reading = 0x00 default The ADT7490 ADT7490 includes an SMBus timeout feature. If there is no SMBus activity for 35 ms, the ADT7490 ADT7490 assumes the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot work with the SMBus timeout feature, so it can be disabled. Register 0x24, +12VIN 12VIN Reading = 0x00 default +12V IN 120k 20k 47k 30pF 71k 30pF 94k +5VIN 30pF 30pF 93k Configuration Register 7 (Register 0x11) VCC 68k Bit 4 (TODIS) = 1, SMBus timeout disabled. VOLTAGE MEASUREMENT INPUT +2.5VIN The ADT7490 ADT7490 has six external voltage measurement channels. It can also measure its own supply voltage, VCC. Pin 20 to Pin 23 can measure 5 V, 12 V, and 2.5 V supplies, and the processor core voltage VCCP (0 V to 3 V input). The 2.5 V input can be used to monitor a chipset supply voltage in computer systems. The VCC supply voltage measurement is carried out through the VCC pin (Pin 4). Pin 8 measures the VTT voltage of the processor and is the dedicated reference voltage for the PECI circuitry. The IMON input on Pin 19 can be used to monitor the IMON output of the Analog Devices ADP319x family of VR10/VR11 VR10/VR11 controllers. IMON is a voltage representation of the CPU current. VCCP 45k 17.5k 52.5k IMON 35pF 45k 94k 30pF 45k VTT MUX 30pF 45k 06789-025 Bit 4 (TODIS) = 0, SMBus timeout enabled (default). Figure 25. Analog Inputs structure Voltage Limit Registers Analog-to-Digital Converter All analog inputs are multiplexed into the on-chip, successiveapproximation, analog-to-digital converter. This ADC has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the inputs have built-in attenuators to allow measurement of 2.5 V, 3.3 V, 5 V, 12 V, and the processor core voltage VCCP without any external components. To allow the tolerance of these supply voltages, the ADC produces an output of ¾ full scale (768 decimal or 0x300 hexadecimal) for the nominal input voltage, and therefore, has adequate headroom to cope with overvoltages. Associated with each voltage measurement channel is a high and low limit register. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Register 0x85, IMON Low Limit = 0x00 default Register 0x87, IMON High Limit = 0xFF default Register 0x84, VTT Low Limit = 0x00 default Register 0x86, VTT High Limit = 0xFF default Register 0x44, +2.5VIN Low Limit = 0x00 default Input Circuitry Register 0x45, +2.5VIN High Limit = 0xFF default The internal structure for the analog inputs is shown in Figure 25. The input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order low-pass filter that gives input immunity to high frequency noise. Register 0x46, VCCP Low Limit = 0x00 default Register 0x47, VCCP High Limit = 0xFF default Voltage Measurement Registers Register 0x49, VCC High Limit = 0xFF default Register 0x1D, IMON Reading = 0x00 default Register 0x4A, +5VIN Low Limit = 0x00 default Register 0x1E, VTT Reading = 0x00 default Register 0x4B, +5VIN High Limit = 0xFF default Register 0x20, +2.5VIN Reading = 0x00 default Register 0x4C, +12VIN 12VIN Low Limit = 0x00 default Register 0x21, VCCP Reading = 0x00 default Register 0x4D, +12VIN 12VIN High Limit = 0xFF default Register 0x48, VCC Low Limit = 0x00 default Register 0x22, VCC Reading = 0x00 default Rev. 1 | Page 17 of 78 | www.onsemi.com ADT7490 ADT7490 When the ADC is running, it samples and converts a voltage input in 0.7 ms and averages 16 conversions to reduce noise; a measurement takes nominally 11 ms. Extended Resolution Registers Voltage measurements can be made with higher accuracy using the extended resolution registers (0x1F, 0x76, and 0x77). Whenever the extended resolution registers are read, the corresponding data in the voltage measurement registers (0x1D, 0x1E, and 0x20 to 0x24) is locked until their data is read. That is, if extended resolution is required, the extended resolution register must be read first, immediately followed by the appropriate voltage measurement register. ADDITIONAL ADC FUNCTIONS FOR VOLTAGE MEASUREMENTS A number of other functions are available on the ADT7490 ADT7490 to offer the system designer increased flexibility. The functions described in the following sections are enabled by setting the appropriate bit in Configuration Register 2. Configuration Register 2 (Register 0x73) Setting Bit 5 of Configuration Register 2 (0x73) removes the attenuation circuitry from the 2.5 VIN, VCCP, VCC, 5 VIN, and 12 VIN inputs. This allows the user to directly connect external sensors or rescale the analog voltage measurement inputs for other applications. The input range of the ADC without the attenuators is 0 V to 2.25 V. Bypass Individual Voltage Input Attenuators Bits [7:4] of Configuration Register 4 (0x7D) can be used to bypass individual voltage channel attenuators. Table 9. Bypassing Individual Voltage Input Attenuators Configuration Register 4 (0x7D) Bit No. 4 5 6 7 Channel Attenuated Bypass +2.5VIN attenuator Bypass VCCP attenuator Bypass +5VIN attenuator Bypass +12VIN 12VIN attenuator Single-Channel ADC Conversion While single-channel mode is intended as a test mode that can be used to increase sampling times for a specific channel, therefore helping to analyze that channel's performance in greater detail, it can also have other applications. Bit 4 (AVG) = 1, averaging off. Bit 5 (ATTN) = 1, bypass input attenuators. Bit 6 (CONV) = 1, single-channel convert mode. Turn-Off Averaging For each voltage/temperature measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. When faster conversions are needed, setting Bit 4 (AVG) of Configuration Register 2 (0x73) turns averaging off. This effectively gives a reading that is 16 times faster, but the reading can be noisier. The default round-robin cycle time takes 146.5 ms. Table 8. Conversion Time with Averaging Disabled Channel Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature Bypass All Voltage Input Attenuators Measurement Time (ms) 0.7 7 7 1.3 When Bit 7 (ExtraSlow) of Configuration Register 6 (0x10) is set, the default round-robin cycle time increases to 240 ms. Setting Bit 6 of Configuration Register 2 (0x73) places the ADT7490 ADT7490 into single-channel ADC conversion mode. In this mode, the ADT7490 ADT7490 can read a single voltage channel only. The selected voltage input is read every 0.7 ms. The appropriate ADC channel is selected by writing to Bits [7:4] of the TACH1 minimum high byte register (0x55). Table 10. Programming Single-Channel ADC Mode Bits [7:4], Register 0x55 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1 Channel Selected1 +2.5VIN VCCP VCC +5VIN +12VIN 12VIN Remote 1 temperature Local temperature Remote 2 temperature VTT IMON In the process of configuring single-channel ADC conversion mode, the TACH1 minimum high byte is also changed, possibly trading off TACH1 minimum high byte functionality with single-channel mode functionality. Rev.1 | Page 18 of 78 | www.onsemi.com ADT7490 ADT7490 Table 11. 10-Bit ADC Output Code vs. VIN Input Voltage +12VIN 12VIN 15.9843 +5VIN 6.6634 VCC (3.3 VIN) 4.3957 +2.5VIN 3.3267 ADC Output VCCP 2.9970 Rev. 1 | Page 19 of 78 | www.onsemi.com VTT/IMON 2.2522 Decimal 0 1 Binary (10 Bits) 00000000 00 00000000 01 2 00000000 10 3 00000000 11 4 00000001 00 5 00000001 01 6 00000001 10 7 00000001 11 8 00000010 00 . 256 (¼ scale) . 512 (½ scale) . 768 (¾ scale) . 1013 . 01000000 00 1014 11111101 10 1015 11111101 11 1016 11111110 00 1017 11111110 01 1018 11111110 10 1019 11111110 11 1020 11111111 00 1021 11111111 01 1022 11111111 10 1023 11111111 11 . 10000000 00 . 11000000 00 . 11111101 01 ADT7490 ADT7490 TEMPERATURE MEASUREMENT PECI Offset Registers The ADT7490 ADT7490 has four temperature measurement channels: one local, two remote thermal diodes, and a PECI. The local and thermal diode readings are analog temperature measurements, whereas PECI is a digital temperature reading. Each PECI reading has a dedicated offset register to calibrate the PECI measurement and account for errors in the temperature reading. The LSBs add a 1°C offset to the temperature reading so that the 8-bit register effectively allows temperature offsets of up to ±128°C with a resolution of 1°C. PECI Temperature Measurement The PECI interface is a dedicated thermal interface. The CPU temperature measurement is carried out internally in the CPU. This information is digitized and transferred to the ADT7490 ADT7490 via the PECI interface. The ADT7490 ADT7490 is a PECI host device and therefore, polls the CPU for thermal information. The PECI measurement differs from traditional thermal diode temperature measurements in that the measurement is a relative value instead of an absolute value. The PECI reading is a negative value that indicates how close the CPU temperature is from the thermal throttling or TCC point of the CPU. The ADT7490 ADT7490 records and uses the PECI measurement for fan control in its relative format. Therefore, care must be taken in programming the relevant limits and fan control parameters in the PECI format. Refer to the PECI Input section and Table 6 for further PECI information. PECI monitoring is enabled on the ADT7490 ADT7490 by setting the PECI monitoring bit in Configuration Register 1 (Register 0x40, Bit 4). The ADT7490 ADT7490 can measure the temperature of up to four dual-core CPUs. The number of CPUs in the system that provide PECI information is set in Bits [7:6] of Register 0x88. Each CPU is distinguished by the PECI address. The number of domains, or domain count, per CPU address must also be programmed into the ADT7490 ADT7490. The ADT7490 ADT7490 reads the temperature of both domains per CPU, however, only the PECI value of the hottest domain is recorded in the PECI value register. Register 0x94, PECI0 Offset Register 0x95, PECI1 Offset Register 0x96, PECI2 Offset Register 0x97, PECI3 Offset PECI Data Smoothing The PECI smoothing interval is programmed in PECI Configuration Register 1 (0x36). Bits [2:0] of Register 0x36 set the duration over which the PECI data being read by the ADT7490 ADT7490 is averaged. These bits set the duration over which smoothing is carried out on the PECI data read. The refresh rate in the PECI value registers is the same as the smoothing interval programmed. The smoothing interval is calculated using the following formula: Smoothing Interval = # reads × (t BIT × 67 × # CPU + t IDLE ) where: #reads is the number of readings defined in Register 0x36, Bits [2:0]. tBIT is the negotiated bit rate. 67 is the number of bits in each PECI reading. #CPU is the number of CPUs providing PECI data (1 to 4). tIDLE = 14 s, the delay between consecutive reads. PECI0 domains: Register 0x36, Bit 3 For example, #reads = 4096 tBIT = 1 s (1 MHz speed) #CPU = 1 Smoothing Interval = 331 ms = PECI reading refresh rate PECI1 domains: Register 0x88, Bit 5 PECI Error Codes PECI2 domains: Register 0x88, Bit 4 Register 0x34, PECI Low Limit = 0x81 default There are two different error conditions for PECI data, PECI data errors, and PECI bus communications errors. Table 12 describes the two different error conditions. If the ADT7490 ADT7490 reads an error code (0x8000 to 0x8003) from the CPU over the PECI interface, Bit 1 is set in Interrupt Status 3 register (0x43), indicating a data error. The value of the error code is not included in the PECI value averaging sum. This means that a value of 0x00 is added to the PECI sum when an error code is recorded. The error code is not reported in the appropriate PECI value register. If an invalid FCS is recorded by the ADT7490 ADT7490, Bit 2 is set in the Interrupt Status 3 register (0x43), indicating a communications error. An alert is generated on the SMBALERT pin when either or both of these status bits are Register 0x35, PECI High Limit = 0x00 default asserted. PECI3 domains: Register 0x88, Bit 3 PECI Reading Registers Register 0x33, PECI0: PECI reading from CPU Address 0x30 Register 0x1A, PECI1: PECI reading from CPU Address 0x31 Register 0x1B, PECI2: PECI reading from CPU Address 0x32 Register 0x1C, PECI3: PECI reading from CPU Address 0x33 PECI Limit Registers Each PECI measurement shares the same high and low limits. Rev.1 | Page 20 of 78 | www.onsemi.com ADT7490 ADT7490 Table 12. PECI Error Indicators PECI Data 0x8000 to 0x8003 Invalid FCS Description PECI data error PECI communications error Action Bit 1 of Register 0x43 is set to 1 Bit 2 of Register 0x43 is set to 1 Each PECI channel also has an associated status bit to indicate if the PECI high or low limits have been exceeded. An alert is generated on the SMBALERT pin when these status bits are asserted. Table 13. PECI Status Bits Channel PECI0 PECI1 PECI2 PECI3 Register 0x43 0x81 0x81 0x81 Bit 0 3 4 5 Temperature Data REPLACE Mode The REPLACE mode is configured by setting Bit 4 of Register 0x36. In this mode, the data in the existing Remote 1 registers are replaced by PECI0 data. This is a legacy mode that allows the thermal data from CPU1 to be stored in the same registers as in the ADT7476A ADT7476A. This reduces the software changes in systems transitioning from CPUs with thermal diodes to CPUs with a PECI interface. However, note that even though the associated registers are swapped, the correct data format (PECI vs. absolute temperature, see Table 6) must be written to and interpreted from these registers. Notes In Table 14, registers listed under the Remote 1 Default column are in absolute temperature format by default and are in PECI format in REPLACE mode. Registers listed under the PECI0 Default column are in PECI format by default and in absolute temperature format in REPLACE mode. In REPLACE mode, the temperature zone controlling the relevant PWM output are also swapped from Remote 1 to PECI0. The swap of control only occurs if the default behavior setting for Register 0x5C Bits [7:5], Register 0x5D Bits [7:5] or Register 0x5E Bits [7:5] is 000. Local Temperature Measurement The ADT7490 ADT7490 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip 10-bit ADC. The 8-bit MSB temperature data is stored in the local temperature register (Address 0x26). Because both positive and negative temperatures can be measured, the temperature data is stored in Offset 64 format or twos complement format, as shown in Table 15 and Table 16. Theoretically, the temperature sensor and ADC can measure temperatures from -128°C to +127°C (or -64°C to +191°C in the extended temperature range) with a resolution of 0.25°C. However, this exceeds the operating temperature range of the device, so local temperature measurements outside the ADT7490 ADT7490 operating temperature range are not possible. Table 15. Twos Complement Temperature Data Format Temperature Digital Output (10-Bit)1 ­128°C ­63°C ­50°C ­25°C ­10°C 0°C 10.25°C 25.5°C 50.75°C 75°C 100°C 125°C 127°C 1000 0000 00 (diode fault) 1100 0001 00 1100 1110 00 1110 0111 00 1111 0110 00 0000 0000 00 0000 1010 01 0001 1001 10 0011 0010 11 0100 1011 00 0110 0100 00 0111 1101 00 0111 1111 00 1 Table 14. Replace Mode Temperature Registers Register Name Value Register Low Limit High Limit TMIN TRANGE Enhanced Acoustics Enhanced Acoustics Enable THERM TCONTROL Remote 1 Default Reg. 0x25 Reg. 0x4E Reg. 0x4F Reg. 0x67 Reg. 0x5F, Bits [7:4] Reg. 0x62, Bits [2:0] Reg. 0x62, Bit 3 Reg. 0x6A Reg. 0x3D TMIN Hysteresis Reg. 0x6D, Bits [7:4] Reg. 0x6D, Bits [3:0]1 Reg. 0x70 Reg. 0x8B Reg. 0x6E, Bits [3:0] Reg. 0x6E, Bits [7:4]1 Reg. 0x94 Reg. 0x8A Temperature offset Operating Point for Dynamic TMIN 1 PECI0 Default Reg. 0x33 Reg. 0x34 Reg. 0x35 Reg. 0x3B Reg. 0x3C, Bits [7:4] Reg. 0x3C, Bits [2:0] Reg. 0x3C, Bit 3 Table 16. Offset 64 Data Format Temperature Digital Output (10-Bit)1 ­64°C ­63°C ­1°C 0°C 1°C 10°C 25°C 50°C 75°C 100°C 125°C 191°C 0000 0000 00 (diode fault) 0000 0001 00 0011 1111 00 0100 0000 00 0100 0001 00 0100 1010 00 0101 1001 00 0111 0010 00 1000 1001 00 1010 0100 00 1011 1101 00 1111 1111 00 1 In REPLACE mode, the Remote 2 and local temperature hysteresis values are swapped. Bold numbers denote 2 LSBs of measurement in the Extended Resolution 2 register (Register 0x77) with 0.25°C resolution. Bold numbers denote 2 LSBs of measurement in the Extended Resolution 2 register (Register 0x77) with 0.25°C resolution. Rev. 1 | Page 21 of 78 | www.onsemi.com ADT7490 ADT7490 THERMAL DIODE TEMPERATURE MEASUREMENT METHOD A simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the baseemitter voltage (VBE) of a transistor operated at constant current. Unfortunately, this technique requires calibration to null out the effect of the absolute value of VBE, which varies from device to device. The technique used in the ADT7490 ADT7490 is to measure the change in VBE when the device is operated at three different currents. Previous devices have used only two operating currents, but the use of a third current allows automatic cancellation of resistances in series with the external temperature sensor. Figure 29 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, but it could equally be a discrete transistor, such as a 2N3904/2N3906 2N3904/2N3906. If a discrete transistor is used, the collector is not grounded and should be linked to the base. If a PNP transistor is used, the base is connected to the D­ input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D­ input and the base to the D+ input. Figure 26 and Figure 27 show how to connect the ADT7490 ADT7490 to an NPN or PNP transistor for temperature measurement. ADT7490 ADT7490 D+ D­ 06789-027 2N3904 2N3904 NPN Figure 26. Measuring Temperature Using an NPN Transistor ADT7490 ADT7490 D­ 06789-028 D+ 2N3906 2N3906 PNP Figure 27. Measuring Temperature Using a PNP Transistor To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D- input. C1 can optionally be added as a noise filter (recommended maximum value of 1000 pF). However, a better option in noisy environments is to add a filter, as described in the Series Resistance Cancellation section. Remote Temperature Measurement The ADT7490 ADT7490 can measure the temperature of two remote diode sensors or diode-connected transistors connected to Pin 10 and Pin 11, or Pin 12 and Pin 13. The forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about -2 mV/°C. Unfortunately, the absolute value of VBE varies from device to device, and individual calibration is required to null this out. Therefore, the technique is unsuitable for mass production. The technique used in the ADT7490 ADT7490 is to measure the change in VBE when the device is operated at three different currents. This is given by V BE = kT × ln(N ) q where: k is the Boltzmann constant. q is the charge on the carrier. T is the absolute temperature in Kelvin. N is the ratio of the two currents. To measure VBE, the operating current through the sensor is switched among three related currents. N1 × I and N2 × I are different multiples of the current I, as shown in Figure 28. The currents through the temperature diode are switched between I and N1 × I, giving VBE1, and then between I and N2 × I, giving VBE2. The temperature can then be calculated using the two VBE measurements. This method can also cancel the effect of any series resistance on the temperature measurement. The resulting VBE waveforms are passed through a 65 kHz low-pass filter to remove noise and then to a chopper-stabilized amplifier. This amplifies and rectifies the waveform to produce a dc voltage proportional to VBE. The ADC digitizes this voltage, and a temperature measurement is produced. To reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. The results of remote temperature measurements are stored in 10-bit, twos complement format, as listed in Table 15. The extra resolution for the temperature measurements is held in the Extended Resolution Register 2 (0x77). This gives temperature readings with a resolution of 0.25°C. Rev.1 | Page 22 of 78 | www.onsemi.com ADT7490 ADT7490 VDD I N2 × I N1 × I IBIAS REMOTE SENSING TRANSISTOR D+ LPF VOUT+ TO ADC D­ VOUT­ 06789-023 fC = 65kHz Figure 28. Signal Conditioning for Remote Diode Temperature Sensors 100 Parasitic resistance to the ADT7490 ADT7490 D+ and D- inputs (seen in series with the remote diode) is caused by a variety of factors, including PCB track resistance and track length. This series resistance appears as a temperature offset in the remote sensor's temperature measurement. This error typically causes a 0.5°C offset per ohm of parasitic resistance in series with the remote diode. The ADT7490 ADT7490 automatically cancels out the effect of this series resistance on the temperature reading, giving a more accurate result without the need for user characterization of this resistance. The ADT7490 ADT7490 is designed to automatically cancel, typically up to 1.5 k of resistance. By using an advanced temperature measurement method, this is transparent to the user. This feature allows resistances to be added to the sensor path to produce a filter, allowing the part to be used in noisy environments. REMOTE TEMPERATURE SENSOR R = 100 , C = 1 nF This filtering reduces both common-mode noise and differential noise. D­ FACTORS AFFECTING DIODE ACCURACY Remote Sensing Diode The ADT7490 ADT7490 is designed to work with either substrate transistors built into processors or discrete transistors. Substrate transistors are generally PNP types with the collector connected to the substrate. Discrete types can be either PNP or NPN transistors connected as a diode (base-shorted to the collector). To reduce the error due to variations in both substrate and discrete transistors, a number of factors should be taken into consideration: · For temperature sensors operating in noisy environments, previous practice was to place a capacitor across the D+ pin and the D- pin to help combat the effects of noise. However, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pF. This capacitor reduces the noise, but does not eliminate it, which makes using the sensor difficult in a very noisy environment. The construction of a filter allows the ADT7490 ADT7490 and the remote temperature sensor to operate in noisy environments. Figure 29 shows a low-pass RC filter with the following values: 1nF 100 Figure 29. Filter Between Remote Sensor and ADT7490 ADT7490 Noise Filtering The ADT7490 ADT7490 has a major advantage over other devices for eliminating the effects of noise on the external sensor. Using the series resistance cancellation feature, a filter can be constructed between the external temperature sensor and the part. The effect of any filter resistance seen in series with the remote sensor is automatically canceled from the temperature result. D+ 06789-024 SERIES RESISTANCE CANCELLATION The ideality factor, nf, of the transistor is a measure of the deviation of the thermal diode from ideal behavior. The ADT7490 ADT7490 is trimmed for an nf value of 1.008. Use the following equation to calculate the error introduced at a temperature T (°C) when using a transistor whose nf does not equal 1.008. Refer to the data sheet for the related CPU to obtain the nf values. T = (nf - 1.008)/1.008 × (273.15 K + T) To factor this in, the user can write the T value to the offset register. The ADT7490 ADT7490 automatically adds it to or subtracts it from the temperature measurement. · Some CPU manufacturers specify the high and low current levels of the substrate transistors. The high current level of the ADT7490 ADT7490, IHIGH, is 192 A and the low level current, ILOW, is 12 A. If the ADT7490 ADT7490 current levels do not match the current levels specified by the CPU manufacturer, it may be necessary to remove an offset. The CPU's data sheet advises whether this offset needs to be removed and how to calculate it. This offset can be programmed to the offset register. It is important to note that if more than one offset must be considered, the algebraic sum of these offsets must be programmed to the offset register. Rev. 1 | Page 23 of 78 | www.onsemi.com ADT7490 ADT7490 resolution of 1°C. For the PECI offset registers, the resolution is always 1°C. If a discrete transistor is used with the ADT7490 ADT7490, the best accuracy is obtained by choosing devices according to the following criteria: Temperature Offset Registers · Register 0x70, Remote 1 Temperature Offset = 0x00 (0°C default) · · · Base-emitter voltage greater than 0.25 V at 12 A at the highest operating temperature. Base-emitter voltage less than 0.95 V at 192 A at the lowest operating temperature. Base resistance less than 100 . Small variation in hFE (such as 50 to 150) that indicates tight control of VBE characteristics. Transistors, such as 2N3904 2N3904, 2N3906 2N3906, or equivalents in SOT-23 packages, are suitable devices to use. Register 0x71, Local Temperature Offset = 0x00 (0°C default) Register 0x72, Remote 2 Temperature Offset = 0x00 (0°C default) Register 0x94, PECI0 Temperature Offset = 0x00 (0°C default) Register 0x95, PECI1 Temperature Offset = 0x00 (0°C default) Register 0x96, PECI2 Temperature Offset = 0x00 (0°C default) Register 0x97, PECI3 Temperature Offset = 0x00 (0°C default) Reading Temperature from the ADT7490 ADT7490 Temperature Measurement Limit Registers It is important to note that temperature can be read from the ADT7490 ADT7490 as an 8-bit value (with 1°C resolution) or as a 10-bit value (with 0.25°C resolution). If only 1°C resolution is required, the temperature readings can be read back at any time and in no particular order. Associated with each temperature measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts (depending on the way the interrupt mask register is programmed and assuming that SMBALERT is set as an output on the appropriate pin). If the 10-bit measurement is required, it involves a 2-register read for each measurement. The Extended Resolution 2 register (0x77) should be read first. This causes all temperature reading registers to be frozen until all temperature reading registers have been read from. This prevents an MSB reading from being updated while its two LSBs are being read and vice versa. ADDITIONAL ADC FUNCTIONS FOR TEMPERATURE MEASUREMENT A number of other functions are available on the ADT7490 ADT7490 to offer the system designer increased flexibility. Nulling Out Temperature Errors Turn-Off Averaging As CPUs run faster, it becomes more difficult to avoid high frequency clocks when routing the D+/D- traces around a system board. Even when recommended layout guidelines are followed, some temperature errors may still be attributable to noise coupled onto the D+/D- lines. Constant high frequency noise usually attenuates or increases temperature measurements by a linear, constant value. For each temperature measurement read from a value register, 16 readings have actually been made internally, and the results averaged, before being placed into the value register. Sometimes it is necessary to take a very fast measurement. Setting Bit 4 of Configuration Register 2 (0x73) turns averaging off. The default round-robin cycle time with averaging off is a maximum of 23 ms. The ADT7490 ADT7490 has temperature offset registers at Address 0x70, Address 0x71, and Address 0x72 for the Remote 1, local, and Remote 2 temperature channels, respectively. By performing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it out using the offset registers. The offset registers automatically add a twos complement 8-bit reading to every temperature measurement. The temperature offset range and resolution is selected by setting Bit 1 of Register 0x7C. This ensures that the readings in the temperature measurement registers are as accurate as possible. Setting this bit to 0 means the LSBs add 0.5°C offset to the temperature reading, so the 8-bit register effectively allows temperature offsets from -63°C to +64°C with a resolution of 0.5°C. Setting this bit to 1 means the LSBs add 1°C offset to the temperature reading, so the 8-bit register effectively allows temperature offsets of up to -63°C to +127°C with a Table 17. Conversion Time with Averaging Disabled Channel Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature Measurement Time (ms) 0.7 7 7 1.3 When Bit 7 of Configuration Register 6 (0x10) is set, the default round-robin cycle time increases to a maximum of 193 ms. Table 18. Conversion Time with Averaging Enabled Channel Voltage Channels Remote Temperature Local Temperature Rev.1 | Page 24 of 78 | www.onsemi.com Measurement Time (ms) 11 39 12 ADT7490 ADT7490 Single-Channel ADC Conversions Setting Bit 6 of Configuration Register 2 (Register 0x73) places the ADT7490 ADT7490 into single-channel ADC conversion mode. In this mode, the ADT7490 ADT7490 can be made to read a single temperature channel only. The appropriate ADC channel is selected by writing to Bits [7:4] of the TACH1 Minimum High Byte register (0x55). Table 19. Programming Single-Channel ADC Mode for Temperatures Bits [7:4], Register 0x55 0101 0110 0111 Channel Selected Remote 1 temperature Local temperature Remote 2 temperature PWM outputs run at 100% duty cycle (default). This can be changed to maximum PWM duty cycle as programmed in Register 0x38, Register 0x39, and Register 0x3A, by setting Bit 3 of Register 0x7D. The fans run at this speed until the temperature drops below THERM minus hysteresis. This can be disabled by setting the BOOST bit in Configuration Register 3, Bit 2 (0x78). The hysteresis value for the THERM temperature limit is the value programmed into the hysteresis registers (0x6D and 0x6E). The default hysteresis value is 4°C. THERM LIMIT HYSTERESIS (°C) TEMPERATURE Bit 4 (AVG) = 1, averaging off. FANS 100% Bit 6 (CONV) = 1, single-channel convert mode. Figure 30. THERM Temperature Limit Operation Overtemperature Events Overtemperature events on any of the temperature channels can be detected and dealt with automatically in automatic fan speed control mode. Register 0x6A to Register 0x6C are the THERM temperature limits for the local and remote diode temperature channels. The equivalent PECI limit is TCONTROL in Register 0x3D. When a temperature exceeds its THERM temperature limit, all THERM can be disabled by setting Bit 2 of Configuration Register 4 (0x7D). THERM can also be disabled by: · · In Offset 64 mode, writing -64°C to the appropriate THERM temperature limit. In twos complement mode, writing -128°C to the appropriate THERM temperature limit. Rev. 1 | Page 25 of 78 | www.onsemi.com 06789-029 Configuration Register 2 (Register 0x73) ADT7490 ADT7490 LIMITS, STATUS REGISTERS, AND INTERRUPTS LIMIT VALUES THERM Timer Limit Register Associated with each measurement channel on the ADT7490 ADT7490 are high and low limits. These can form the basis of system status monitoring; a status bit can be set for any out-of-limit condition and is detected by polling the device. Alternatively, SMBALERT interrupts can be generated to flag out-of-limit conditions to a processor or microcontroller. Register 0x7A, THERM Timer Limit = 0x00 default The following is a list of 8-bit limits on the ADT7490 ADT7490. 16-Bit Limits The fan TACH measurements are 16-bit results. The fan TACH limits are also 16 bits, consisting of a high byte and low byte. Only high limits exist for fan TACHs because fans running under speed or stalled are normally the only conditions of interest. Because the fan TACH period is actually being measured, exceeding the limit indicates a slow or stalled fan. Voltage Limit Registers Fan Limit Registers Register 0x44, +2.5VIN Low Limit = 0x00 default Register 0x54, TACH1 Minimum Low Byte = 0xFF default Register 0x45, +2.5VIN High Limit = 0xFF default Register 0x55, TACH1 Minimum High Byte = 0xFF default Register 0x46, VCCP Low Limit = 0x00 default Register 0x56, TACH2 Minimum Low Byte = 0xFF default Register 0x47, VCCP High Limit = 0xFF default Register 0x57, TACH2 Minimum High Byte = 0xFF default Register 0x48, VCC Low Limit = 0x00 default Register 0x58, TACH3 Minimum Low Byte = 0xFF default Register 0x49, VCC High Limit = 0xFF default Register 0x59, TACH3 Minimum High Byte = 0xFF default Register 0x4A, +5VIN Low Limit = 0x00 default Register 0x5A, TACH4 Minimum Low Byte = 0xFF default Register 0x4B, +5VIN High Limit = 0xFF default Register 0x5B, TACH4 Minimum High Byte = 0xFF default Register 0x4C, +12VIN 12VIN Low Limit = 0x00 default Out-of-Limit Comparisons Once all limits have been programmed, the ADT7490 ADT7490 can be enabled for monitoring. The ADT7490 ADT7490 measures all voltage and temperature measurements in round-robin format and sets the appropriate status bit to indicate out-of-limit conditions. TACH measurements are not part of this round-robin cycle. Comparisons are done differently depending on whether the measured value is being compared to a high or low limit. High Limit > Comparison Performed 8-Bit Limits Register 0x4D, +12VIN 12VIN High Limit = 0xFF default Register 0x84, VTT Low Limit = 0x00 default Register 0x86, VTT High Limit = 0xFF default Register 0x85, IMON Low Limit = 0x00 default Register 0x87, IMON High = 0xFF default Temperature Limit Registers Register 0x4E, Remote 1 Temperature Low Limit = 0x81 default Register 0x4F, Remote 1 Temperature High Limit = 0x7F default Register 0x6A, Remote 1 THERM Temperature Limit = 0x64 default Register 0x50, Local Temperature Low Limit = 0x81 default Register 0x51, Local Temperature High Limit = 0x7F default Register 0x6B, Local THERM Temperature Limit = 0x64 default Register 0x52, Remote 2 Temperature Low Limit = 0x81 default Register 0x53, Remote 2 Temperature High Limit = 0x7F default Register 0x6C, Remote 2 THERM Temperature Limit = 0x64 default Register 0x34, PECI Low Limit = 0x81 default Register 0x35, PECI High Limit = 0x00 default Register 0x3D, PECI TCONTROL Limit = 0x00 default Low Limit Comparison Performed Voltage and temperature channels use a window comparator for error detecting and, therefore, have high and low limits. Fan speed measurements use only a low limit. Analog Monitoring Cycle Time The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1 (0x40). The ADC measures each analog input in turn and, as each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues unless disabled by writing a 0 to Bit 0 of Configuration Register 1. As the ADC is normally left to free-run in this manner, the time taken to monitor all the analog inputs is normally not of interest, because the most recently measured value of any input can be read out at any time. For applications where the monitoring cycle time is important, it can easily be calculated. Rev.1 | Page 26 of 78 | www.onsemi.com ADT7490 ADT7490 (OOL) of Interrupt Status Register 1 (0x41), a Logic 1 indicates an out-of-limit event has been flagged in Interrupt Status Register 2. This means the user also needs to read Interrupt Status Register 2. There is a similar OOL bit in Interrupt Status Register 2 and Interrupt Status Register 3, indicating an out-oflimit event in the next status register. The total number of channels measured consists of · · · · Six dedicated supply voltage inputs Supply voltage (VCC pin) Local temperature Two remote temperatures As mentioned previously, the ADC performs round-robin conversions and takes 11 ms for each voltage measurement, 12 ms for a local temperature reading, and 39 ms for each remote temperature reading. The total monitoring cycle time for averaged voltage and temperature monitoring is, therefore, nominally (7 × 11) + 12 + (2 × 39) = 167 ms Fan TACH measurements and PECI thermal measurements are made in parallel and are not synchronized with the analog measurements in any way. INTERRUPT STATUS REGISTERS The results of limit comparisons are stored in Interrupt Status Register 1 to Interrupt Status Register 4. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding interrupt status register bit is cleared to 0. If the measurement is out of limit, the corresponding interrupt status register bit is set to 1. The state of the various measurement channels can be polled by reading the interrupt status registers over the serial bus. In Bit 7 Alternatively, Pin 10 or Pin 14 can be configured as an SMBALERT output. This hard interrupt automatically notifies the system supervisor of an out-of-limit condition. Reading the interrupt status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. Interrupt status register bits are sticky. Whenever an interrupt status bit is set, indicating an out-of-limit condition, it remains set even if the event that caused it has gone away (until read). The only way to clear the interrupt status bit is to read the interrupt status register after the event has gone away. Interrupt status mask registers allow individual interrupt sources to be masked from causing an SMBALERT on the dedicated alert pin. However, if one of these masked interrupt sources goes out of limit, its associated interrupt status bit is set in the interrupt status registers. Full details of the Interrupt Status and Interrupt Mask registers associated with each measurement channels are detailed in the Table 20 and in the full register map in the Register Tables section. Table 20. Interrupt Status and Interrupt Mask Register Address and Bit Assignments Interrupt Status Register 0x41 Interrupt Mask Register 0x74 Bit 7 OOL Bit 6 R2T Bit 5 LT Bit 4 R1T Bit 3 +5VIN Bit 2 VCC Bit 1 VCCP Bit 0 +2.5VIN/THERM 0x42 0x75 D2 FAULT D1 FAULT FAN4/THERM FAN3 FAN2 FAN1 OOL +12VIN 12VIN 0x43 0x81 0x82 0x83 OOL VTT RES IMON RES PECI3 RES PECI2 OVT PECI1 COMM RES DATA RES PECI0 RES Rev. 1 | Page 27 of 78 | www.onsemi.com ADT7490 ADT7490 registers associated with each measurement channel are detailed in Table 20 and Table 24. SMBALERT Interrupt Behavior The ADT7490 ADT7490 can be polled for status, or an SMBALERT interrupt can be generated for out-of-limit conditions. It is important to note how the SMBALERT output and status bits behave when writing interrupt handler software. HIGH LIMIT TEMPERATURE HIGH LIMIT SMBALERT 06789-030 TEMP BACK IN LIMIT (STATUS BIT STAYS SET) Figure 31. SMBALERT and Status Bit Behavior Note that the SMBALERT output remains low for the entire duration that a reading is out of limit and until the status register has been read. This has implications on how software handles the interrupt. Handling SMBALERT Interrupts To prevent the system from being tied up servicing interrupts, it is recommend to handle the SMBALERT interrupt as follows: 5. 6. 7. INTERRUPT MASK BIT CLEARED (SMBALERT REARMED) Figure 32. How Masking the Interrupt Source Affects SMBALERT Output Figure 31 shows how the SMBALERT output and sticky status bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition subsides and the status register is read. The status bits are referred to as sticky, because they remain set until read by software. This ensures that an out-of-limit event cannot be missed if software is polling the device periodically. 1. 2. 3. 4. INTERRUPT MASK BIT SET 06789-031 TEMP BACK IN LIMIT (STATUS BIT STAYS SET) CLEARED ON READ (TEMP BELOW LIMIT) STICKY STATUS BIT SMBALERT CLEARED ON READ (TEMP BELOW LIMIT) STICKY STATUS BIT TEMPERATURE Detect the SMBALERT assertion. Enter the interrupt handler. Read the status registers to identify the interrupt source. Mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (0x74, 0x75, 0x82, and 0x83). Take the appropriate action for a given interrupt source. Exit the interrupt handler. Periodically poll the status registers. If the interrupt status bit has cleared, reset the corresponding interrupt mask bit to 0. This causes the SMBALERT output and status bits to behave as shown in Figure 32. Enabling the SMBALERT Interrupt Output The SMBALERT interrupt function is disabled by default. Pin 10 or Pin 14 can be reconfigured as an SMBALERT output to signal out-of-limit conditions. Table 21. Configuring Pin 10 as SMBALERT Output Register Configuration Register 3 (Register 0x78), Bit 0 Bit Setting [1] Pin 10 = SMBALERT [0] Pin 10 = PWM2 (default) Assigning THERM Functionality to a Pin Pin 14 on the ADT7490 ADT7490 has three possible functions: SMBALERT, THERM, and TACH4. The user chooses the required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D. If THERM is enabled (Bit 1, Configuration Register 3 at Address 0x78), · · Pin 22 becomes THERM. If Pin 14 is configured as THERM (Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D), THERM is enabled on this pin. If THERM is not enabled, · · Pin 22 becomes a 2.5 VIN measurement input. If Pin 14 is configured as THERM, THERM is disabled on this pin. Table 22. Configuring Pin 14 in Register 0x7D Masking Interrupt Sources The interrupt mask registers allow individual interrupt sources to be masked out to prevent SMBALERT interrupts. Note that masking an interrupt source prevents only the SMBALERT output from being asserted; the appropriate status bit is set normally (see Figure 32). Full details of the status and mask Bit 1 0 0 Bit 0 0 1 Function TACH4 THERM 1 0 SMBALERT 1 1 Reserved Rev.1 | Page 28 of 78 | www.onsemi.com ADT7490 ADT7490 THERM as an Input When THERM is configured as an input, the user can time assertions on the THERM pin. This can be useful for connecting to the PROCHOT output of a CPU to gauge system performance. The 8-bit THERM timer status register (0x79) is designed so that Bit 0 is set to 1 on the first THERM assertion. Once the cumulative THERM assertion time has exceeded 45.52 ms, Bit 1 of the THERM timer is set and Bit 0 now becomes the LSB of the timer with a resolution of 22.76 ms (see Figure 34). THERM The user can also set up the ADT7490 ADT7490 so that the fans run at 100% when the THERM pin is driven low externally. The fans run at 100% for the duration of the time that the THERM pin is pulled low. This is done by setting the BOOST bit (Bit 2) in Configuration Register 3 (Address 0x78) to 1. This works only if the fan is already running, for example, in manual mode when the current duty cycle is above 0x00, or in automatic mode when the temperature is above TMIN. THERM TIMER (REG. 0x79) 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 THERM ASSERTED 22.76ms THERM ACCUMULATE THERM LOW ASSERTION TIMES If the temperature is below TMIN or if the duty cycle in manual mode is set to 0x00, pulling the THERM low externally has no effect. See Figure 33 for more information. THERM TIMER (REG. 0x79) 0 0 0 0 0 0 1 0 7 6 5 4 3 2 1 0 THERM ASSERTED 45.52ms THERM TMIN THERM TIMER (REG. 0x79) THERM 0 0 0 0 0 1 0 1 7 6 5 4 3 2 1 0 THERM ASSERTED 113.8ms (91.04ms + 22.76ms) 06789-033 ACCUMULATE THERM LOW ASSERTION TIMES Figure 34. Understanding the THERM Timer When using the THERM timer, be aware of the following: After a THERM timer read (Register 0x79): THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100%, BECAUSE TEMPERATURE IS ABOVE TMIN AND FANS ARE ALREADY RUNNING. 06789-032 THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100%, BECAUSE TEMPERATURE IS BELOW TMIN. Figure 33. Asserting THERM Low as an Input in Automatic Fan Speed Control Mode · · The contents of the timer are cleared on read. Bit 5 of Interrupt Status 2 register (0x42) needs to be cleared (assuming that the THERM timer limit has been exceeded). If the THERM timer is read during a THERM assertion, the following happens: THERM TIMER The ADT7490 ADT7490 has an internal timer to measure THERM assertion time. For example, the THERM input can be connected to the PROCHOT output of a CPU to measure system performance. The THERM input can also be connected to the output of a trip point temperature sensor. The timer is started on the assertion of the ADT7490 ADT7490 THERM input and stopped when THERM is deasserted. The timer counts THERM times cumulatively, that is, the timer resumes counting on the next THERM assertion. The THERM timer continues to accumulate THERM assertion times until the timer is read (it is cleared on read), or until it reaches full scale. If the counter reaches full scale, it stops at that reading until cleared. · · · · The contents of the timer are cleared. Bit 0 of the THERM timer is set to 1, because a THERM assertion is occurring. The THERM timer increments from zero. If the THERM timer limit (Register 0x7A) = 0x00, the F4P bit is set. Generating SMBALERT Interrupts from THERM Timer Events The ADT7490 ADT7490 can generate SMBALERTs when a programmable THERM timer limit has been exceeded. This allows the system designer to ignore brief, infrequent THERM assertions while capturing longer THERM timer events. Register 0x7A is the THERM timer limit register. This 8-bit register allows a limit from 0 sec (first THERM assertion) to 5.825 sec to be set Rev. 1 | Page 29 of 78 | www.onsemi.com ADT7490 ADT7490 before an SMBALERT is generated. The THERM timer value is compared with the contents of the THERM timer limit register. If the THERM timer value exceeds the THERM timer limit value, the FAN4 bit (Bit 5) of Status Register 2 is set and an SMBALERT is generated. 3. Note that depending on which pins are configured as a THERM timer, setting the FAN4/THERM bit (Bit 5) of the Interrupt Mask Register 2 (0x75), or bit 0 of the Interrupt Mask Register 1 (0x74), masks out SMBALERT; although the FAN4 bit of Interrupt Status Register 2 is still set if the THERM timer limit is exceeded. Figure 35 is a functional block diagram of the THERM timer, THERM limit, and its associated circuitry. Writing a value of 0x00 to the THERM Timer Limit register (0x7A) causes an SMBALERT to be generated on the first THERM assertion. A THERM timer limit value of 0x01 generates an SMBALERT once cumulative THERM assertions exceed 45.52 ms. 4. Configuring the Relevant THERM Behavior 1. 2. Configure the desired pin as the THERM timer input. Setting Bit 1 (THERM timer enable) of Configuration Register 3 (Register 0x78) enables the THERM timer monitoring functionality. This is disabled on Pin 14 and Pin 22 by default. Setting Bit 0 and Bit 1 (Pin 14 Func) of Configuration Register 4 (Register 0x7D) enables THERM timer output functionality on Pin 22 (Bit 1 of Configuration Register 3, THERM, must also be set). Pin 14 can also be used as TACH4. Select the desired fan behavior for THERM timer events. Assuming the fans are running, setting Bit 2 (BOOST bit) of Configuration Register 3 (Register 0x78) causes all fans to run at 100% duty cycle whenever THERM is asserted. 5. This allows fail-safe system cooling. If this bit = 0, the fans run at their current settings and are not affected by THERM events. If the fans are not already running when THERM is asserted, the fans do not run to full speed. Select whether THERM timer events should generate SMBALERT interrupts. Bit 5 of Interrupt Mask Register 2 (0x75) or Bit 0 of Interrupt Mask Register 1 (0x74), depending on which pins are configured as a THERM timer, when set, masks out SMBALERTs when the THERM timer limit value is exceeded. This bit should be cleared if SMBALERTs based on THERM events are required. Select a suitable THERM limit value. This value determines whether an SMBALERT is generated on the first THERM assertion, or only if a cumulative THERM assertion time limit is exceeded. A value of 0x00 causes an SMBALERT to be generated on the first THERM assertion. Select a THERM monitoring time. This value specifies how often OS- or BIOS-level software checks the THERM timer. For example, BIOS can read the THERM timer once an hour to determine the cumulative THERM assertion time. If, for example, the total THERM assertion time is 182.08 ms in Hour 2, and >2.914 sec in Hour 3, this indicates that system performance is degrading significantly because THERM is asserting more frequently on an hourly basis. Rev.1 | Page 30 of 78 | www.onsemi.com ADT7490 ADT7490 2.914s 1.457s 728.32ms THERM TIMER LIMIT 364.16ms (REGISTER 0x7A) 182.08ms 91.04ms 45.52ms 22.76ms 2.914s 1.457s 728.32ms 364.16ms THERM TIMER STATUS 182.08ms (REGISTER 0x79) 91.04ms 45.52ms 22.76ms 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 THERM THERM TIMER CLEARED ON READ COMPARATOR IN OUT LATCH FAN4 BIT (BIT 5) INTERRUPT STATUS 2 REGISTER SMBALERT RESET 1 = MASK FAN4 BIT (BIT 5) INTERRUPT MASK REGISTER 2 (REGISTER 0x75) 06789-034 CLEARED ON READ Figure 35. Functional Block Diagram of THERM Monitoring Circuitry Alternatively, OS- or BIOS-level software can timestamp when the system is powered on. If an SMBALERT is generated due to the THERM timer limit being exceeded, another timestamp can be taken. The difference in time can be calculated for a fixed THERM timer limit time. For example, if it takes one week for a THERM timer limit of 2.914 sec to be exceeded, and the next time it takes only 1 hour, this is an indication of a serious degradation in system performance. shows how the THERM pin asserts low as an output in the event of a critical overtemperature. THERM LIMIT 0.25°C THERM LIMIT TEMP THERM In addition to monitoring THERM as an input, the ADT7490 ADT7490 can optionally drive THERM low as an output. When PROCHOT is bidirectional, THERM can be used to throttle the processor by asserting PROCHOT. The user can preprogram system-critical thermal limits. If the temperature exceeds a thermal limit by 0.25°C, THERM asserts low. If the temperature is still above the thermal limit on the next monitoring cycle, THERM stays low. THERM remains asserted low until the temperature is equal to or below the thermal limit. Because the temperature for that channel is measured only once for every monitoring cycle, after THERM asserts, it is guaranteed to remain low for at least one monitoring cycle. The THERM pin can be configured to assert low if the Remote 1 THERM, local THERM, Remote 2 THERM or PECI temperature limits are exceeded by 0.25°C. The THERM temperature limit registers are at Register 0x6A, Register 0x6B, and Register 0x6C, respectively. Setting Bits [5:7] of Configuration Register 5 (0x7C) enables the THERM output feature for the Remote 1, local, and Remote 2 temperature channels, respectively. Figure 36 MONITORING CYCLE 06789-035 Configuring the THERM Pin as an Output Figure 36. Asserting THERM as an Output, Based on Tripping THERM Limits An alternative method of disabling THERM is to program the THERM temperature limit to ­63°C or less in Offset 64 mode, or -128°C or less in twos complement mode; that is, for THERM temperature limit values less than ­63°C or ­128°C, respectively, THERM is disabled. Enabling and Disabling THERM on Individual Channels. The THERM pin can be enabled/disabled for individual or combinations of temperature channels using Bits [7:5] of Configuration Register 5 (0x7C). THERM Hysteresis Setting Bit 0 of Configuration Register 7 (0x11) disables THERM hysteresis. If THERM hysteresis is enabled and THERM is disabled (Bit 2 of Configuration Register 4, 0x7D), the THERM event is not Rev. 1 | Page 31 of 78 | www.onsemi.com ADT7490 ADT7490 12V 10k 10k TACH ADT7490 ADT7490 Bit 2 in Configuration Register 4 (0x7D) can be set to disable THERM events from affecting the fans. FAN DRIVE USING PWM CONTROL The ADT7490 ADT7490 uses pulse-width modulation (PWM) to control fan speed. This relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The external circuitry required to drive a fan using PWM control is extremely simple. For 4-wire fans, the PWM drive may need only a pull-up resistor. In many cases, the 4-wire fan PWM input has a built-in, pull-up resistor. The ADT7490 ADT7490 PWM frequency can be set to a selection of low frequencies or a single high PWM frequency. The low frequency options are used for 3-wire fans, while the high frequency option is usually used with 4-wire fans. For 3-wire fans, a single N-channel MOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan being driven and the input capacitance of the FET. Because a 10 k (or greater) resistor must be used as a PWM pull-up, an FET with large input capacitance can cause the PWM output to become distorted and adversely affect the fan control range. This is a requirement only when using high frequency PWM mode. Typical notebook fans draw a nominal 170 mA, therefore, SOT devices can be used where board space is a concern. In desktops, fans typically draw 250 mA to 300 mA each. If several fans are driven in parallel from a single PWM output or drive larger server fans, the MOSFET must handle the higher current requirements. The only other stipulation is that the MOSFET should have a gate voltage drive, VGS < 3.3 V, for direct interfacing to the PWM output pin. The MOSFET should also have a low on resistance to ensure that there is not a significant voltage drop across the FET, which would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan. 1N4148 1N4148 3.3V 10k 06789-036 Q1 NDT3055L NDT3055L PWM Additionally, Bit 3 of Configuration Register 4 (0x7D) can be used to select PWM speed on THERM event (100% or maximum PWM). 12V FAN TACH 4.7k THERM Operation in Manual Mode In manual mode, THERM events do not cause fans to go to full speed, unless Bit 5 of Configuration Register 1 (0x40) is set to 1. 12V Figure 37. Driving a 3-Wire Fan Using an N-Channel MOSFET Figure 37 uses a 10 k pull-up resistor for the TACH signal. This assumes that the TACH signal is an open-collector from the fan. In all cases, the TACH signal from the fan must be kept below 3.6 V maximum to prevent damaging the ADT7490 ADT7490. Figure 38 shows a fan drive circuit using an NPN transistor such as a general-purpose MMBT2222 MMBT2222. While these devices are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the fan's current requirements. Ensure that the base resistor is chosen so that the transistor is saturated when the fan is powered on. 12V 12V 10k 10k TACH TACH 4.7k ADT7490 ADT7490 12V FAN 1N4148 1N4148 3.3V 470 Q1 MMBT2222 MMBT2222 PWM 06789-037 If THERM and THERM hysteresis are both enabled, the THERM output asserts as expected. Figure 37 shows how to drive a 3-wire fan using PWM control. Figure 38. Driving a 3-Wire Fan Using an NPN Transistor Because the fan drive circuitry in 4-wire fans is not switched on or off, as with previous PWM driven/powered fans, the internal drive circuit is always on and uses the PWM input as a signal instead of a power supply. This enables the internal fan drive circuit to perform better than 3-wire fans, especially for high frequency applications. Figure 39 shows a typical drive circuit for 4-wire fans. 12V 12V 12V, 4-WIRE FAN 10k TACH