ADT7460 T7460A QSOP-16 ADT7460/D 10-BIT 2N3904 2N3906 1N4148 NDT3055L MMBT2222 - Datasheet Archive

 

dBCOOLR Remote Thermal Monitor and Fan Controller The ADT7460 dBCOOL controller is a thermal monitor and multiple PWM fan

 

ADT7460 ADT7460 dBCOOLR Remote Thermal Monitor and Fan Controller The ADT7460 ADT7460 dBCOOL controller is a thermal monitor and multiple PWM fan controller for noise-sensitive applications requiring active system cooling. It can monitor the temperature of up to two remote sensor diodes plus its own internal temperature. It can measure and control the speed of up to four fans so that they operate at the lowest possible speed for minimum acoustic noise. The automatic fan speed control loop optimizes fan speed for a given temperature. A unique dynamic T MIN control mode enables the system thermals/acoustics to be intelligently managed. The effectiveness of the system's thermal solution can be monitored using the THERM input. The ADT7460 ADT7460 also provides critical thermal protection to the system by using the bidirectional THERM pin as an output to prevent system or component overheating. http://onsemi.com MARKING DIAGRAM T7460A T7460A RQZ #YYWW QSOP-16 QSOP-16 CASE 492 Features · Controls and Monitors Up to 4 Fans · 1 On-Chip and 2 Remote Temperature Sensors · Dynamic TMIN Control Mode Optimizes System Acoustics · · · · · · · · · Intelligently Automatic Fan Speed Control Mode Controls System Cooling Based on Measured Temperature Enhanced Acoustic Mode Dramatically Reduces User Perception of Changing Fan Speeds Thermal Protection Feature via THERM Output Monitors Performance Impact of Intel PentiumR 4 Processor Processor Thermal Control Circuit via THERM Input 2-Wire and 3-Wire Fan Speed Measurement Limit Comparison of All Monitored Values Meets SMBus 2.0 Electrical Specifications (Fully SMBus 1.1-Compliant) This is a Pb-Free Device xxx = Device Code # = Pb-Free Package YYWW = Date Code PIN ASSIGNMENT SCL 1 16 SDA GND 2 15 PWM1/XTO VCC 3 14 VCCP ADT7460 ADT7460 13 D1+ TOP VIEW 12 D1­ 11 D2+ 7 10 D2­ PWM3/ 8 ADDR ENABLE 9 TACH4/ADDR SELECT /THERM TACH3 4 PWM2/ 5 SMBALERT TACH1 6 TACH2 APPLICATIONS · Low Acoustic Noise PCs · Networking and Telecommunications Equipment © Semiconductor Components Industries, LLC, 2010 June, 2010 - Rev. 5 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 45 of this data sheet. 1 Publication Order Number: ADT7460/D ADT7460/D ADT7460 ADT7460 ADDR SELECT SCL ADDR_EN SMBUS ADDRESS SELECTION PWM1 PWM2 PWM3 PWM REGISTERS AND CONTROLLERS SDA SMBALERT SERIAL BUS INTERFACE ADDRESS POINTER REGISTER AUTOMATIC FAN SPEED CONTROL ACOUSTIC ENHANCEMENT CONTROL PWM CONFIGURATION REGISTERS DYNAMIC TMIN CONTROL TACH1 TACH2 FAN SPEED COUNTER TACH3 TACH4 INTERRUPT MASKING PERFORMANCE MONITORING THERMAL PROTECTION THERM VCC VCC TO ADT7460 ADT7460 INTERRUPT STATUS REGISTERS ADT7460 ADT7460 D1+ INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER D1­ D2+ D2­ +2.5VIN LIMIT COMPARATORS 10-BIT 10-BIT ADC VALUE AND LIMIT REGISTERS BAND GAP REFERENCE BAND GAP TEMP SENSOR GND Figure 1. Functional Block Diagram ABSOLUTE MAXIMUM RATINGS Parameter Rating Positive Supply Voltage (VCC) Unit 6.5 V -0.3 to +6.5 V Input Current at Any Pin ±5 mA Package Input Current ±20 mA 150 °C -65 to +150 °C Voltage on Any Input or Output Pin Maximum Junction Temperature (TJMAX) Storage Temperature Range °C Lead Temperature, Soldering IR Reflow Peak Temperature IR Reflow Peak Temperature for Pb-Free Lead Temperature (Soldering, 10 sec) 220 260 300 ESD Rating 1500 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. THERMAL CHARACTERISTICS qJA 16-lead QSOP qJC Unit 150 Package Type 39 °C/W 1. qJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. http://onsemi.com 2 ADT7460 ADT7460 PIN ASSIGNMENT Pin No. Mnemonic 1 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pullup. 2 GND Ground Pin for the ADT7460 ADT7460. 3 VCC Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. VCC is also monitored through this pin. The ADT7460 ADT7460 can also be powered from a 5.0 V supply. Setting Bit 7 of Configuration Register 1 (Reg. 0x40) rescales the VCC input attenuators to correctly measure a 5.0 V supply. 4 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an analog input (AIN3) to measure the speed of 2-wire fans. 5 PWM2 Digital Output (Open Drain). Requires 10 kW typical pullup. Pulse-width modulated output to control Fan 2 speed. SMBALERT Description Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. 6 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an analog input (AIN1) to measure the speed of 2-wire fans. 7 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an analog input (AIN2) to measure the speed of 2-wire fans. 8 PWM3 Digital I/O (Open Drain). Pulse-width modulated output to control Fan 3/4 speed. Requires 10 kW typical pullup. ADDRESS ENABLE 9 TACH4 ADDRESS SELECT THERM If pulled low on powerup, this places the ADT7460 ADT7460 into address select mode, and the state of Pin 9 determines the ADT7460 ADT7460's slave address. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog input (AIN4) to measure the speed of 2-wire fans. If in address select mode, this pin determines the SMBus device address. Alternatively, the pin may be reconfigured as a bidirectional THERM pin. Can be used to time and monitor assertions on the THERM input. For example, can be connected to the PROCHOT output of Intel's Pentium 4 processor or to the output of a trip point temperature sensor. Can be used as an output to signal overtemperature conditions. 10 D2- Cathode Connection to Second Thermal Diode. 11 D2+ Anode Connection to Second Thermal Diode. 12 D1- Cathode Connection to First Thermal Diode. 13 D1+ Anode Connection to First Thermal Diode. 14 +2.5 VIN Analog Input. Monitors 2.5 V supply, typically a chipset voltage. SMBALERT Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. 15 PWM1/XTO Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kW typical pullup. 16 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pullup. http://onsemi.com 3 ADT7460 ADT7460 ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. Parameter (Note 1) Test Conditions/Comments Min Typ (Note 2) Max Unit 3.0 5.0 5.5 V 3.0 20 mA mA ±1.5 ±3.0 °C POWER SUPPLY Supply Voltage Supply Current, ICC Interface inactive, ADC active Standby mode TEMPERATURE-TO-DIGITAL CONVERTER Local Sensor Accuracy 0°C TA 70°C -40°C TA +120°C Resolution Remote Diode Sensor Accuracy ±1.5 ±2.5 ±3.0 °C 0.25 High level Low level °C 180 11 Resolution Remote Sensor Source Current °C 0.25 0°C TA 70°C; 0°C TD 120°C 0°C TA 105°C; 0°C TD 120°C 0°C TA 120°C; 0°C TD 120°C mA ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) ±1.5 Differential Non-linearity, DNL 8 bits % ±1.0 Total Unadjusted Error, TUE LSB ±0.1 Power Supply Sensitivity %/V Conversion Time (Voltage Input) Averaging enabled 11.38 13 ms Conversion Time (Local Temperature) Averaging enabled 12.09 13.50 ms Conversion Time (Remote Temperature) Averaging enabled 25.59 28 ms Total Monitoring Cycle Time Averaging enabled (incl. delay) (Note 3) Averaging disabled 120.17 13.51 134.50 15 ms 140 200 kW ±7 ±11 ±13 % Input Resistance 80 FAN RPM-TO-DIGITAL CONVERTER Accuracy 0°C TA 70°C 0°C TA 105°C -40°C TA +120°C Full-Scale Count Nominal Input RPM 65,535 Fan count = 0xBFFF Fan count = 0x3FFF Fan count = 0x0438 Fan count = 0x021C 109 329 5000 10000 Internal Clock Frequency 82.8 90.0 RPM 97.2 kHz 8.0 mA 0.4 V 1.0 mA OPEN-DRAIN DIGITAL OUTPUTS, PWM1­PWM3, XTO Current Sink, IOL Output Low Voltage, VOL IOUT = -8.0 mA, VCC = 3.3 V High Level Output Current, IOH VOUT = VCC 0.1 OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL IOUT = -4.0 mA, VCC = 3.3 V High Level Output Current, IOH VOUT = VCC 0.4 0.1 V 1.0 mA SMBUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.4 Hysteresis 500 V mV DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, VIH 2.0 V Maximum input voltage 5.5 Input Low Voltage, VIL +0.8 Minimum input voltage Hysteresis 0.5 http://onsemi.com 4 V -0.3 Vp-p ADT7460 ADT7460 ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. Parameter (Note 1) Test Conditions/Comments Min Typ (Note 2) Max Unit DIGITAL INPUT LOGIC LEVELS (THERM) Input High Voltage, VIH 1.7 V Input Low Voltage, VIL 0.8 V DIGITAL INPUT CURRENT Input High Current, IIH VIN = VCC Input Low Current, IIL mA -1.0 VIN = 0 mA +1.0 Input Capacitance, CIN 5.0 pF SERIAL BUS TIMING (Note 4) Clock Frequency, fSCLK Glitch Immunity, tSW See Figure 2 400 kHz Bus Free Time, tBUF See Figure 2 1.3 50 ns ms Start Setup Time, tSU;STA See Figure 2 0.6 ms Start Hold Time, tHD;STA See Figure 2 0.6 ms SCL Low Time, tLOW See Figure 2 1.3 ms SCL High Time, tHIGH See Figure 2 0.6 SCL, SDA Rise Time, tR See Figure 2 300 ns SCL, SDA Fall Time, tF See Figure 2 300 ms Data Setup Time, tSU;DAT See Figure 2 100 Detect Clock Low Timeout, tTIMEOUT Can be optionally disabled 15 35 ms ms ns 1. All voltages are measured with respect to GND, unless otherwise specified. Logic inputs accept input high voltages up to VMAX even when the device is operating below VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and at VIH = 2.0 V for a rising edge. 2. Typicals are at TA = 25°C and represent the most likely parametric norm. 3. The delay is the time between the round robin finishing one set of measurements and starting the next. 4. Guaranteed by design; not production tested tLOW tR tF tHD; STA SCL tHIGH tHD; STA tHD; DAT tSU; STA tSU; STO tSU; DAT SDA tBUF P S S Figure 2. Serial Bus Timing Diagram http://onsemi.com 5 P ADT7460 ADT7460 TYPICAL PERFORMANCE CHARACTERISTICS 3 15 REMOTE TEMPERATURE ERROR (5C) REMOTE TEMPERATURE ERROR (5C) REMOTE TEMPERATURE ERROR (5C) 0 10 DXP TO GND 5 0 ­5 DXP TO VCC (3.3V) ­10 ­15 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 ­20 1 3.3 10.0 30.0 LEAKAGE RESISTANCE (M) 1 100.0 Figure 3. Remote Temperature Error vs. Leakage Resistance LOCAL TEMPERATURE ERROR (5C) REMOTE TEMPERATURE ERROR (5C) HIGH LIMIT +3 SIGMA 0 ­3 SIGMA ­1 LOW LIMIT ­2 10 60 TEMPERATURE (5C) 47.0 2 HIGH LIMIT 1 +3 SIGMA 0 ­3 SIGMA ­1 ­2 ­3 ­40 110 Figure 5. Remote Temperature Error vs. Actual Temperature LOW LIMIT 10 60 TEMPERATURE (5C) 110 Figure 6. Local Temperature Error vs. Actual Temperature 12.5 12 10.0 LOCAL TEMPERATURE ERROR (5C) 14 REMOTE TEMPERATURE ERROR (5C) 22.0 3 1 ­3 ­40 3.3 4.7 10.0 DXP­DXN CAPACITANCE (nF) Figure 4. Remote Temperature Error vs. Capacitance between D+ and D- 3 2 2.2 10 8 6 250mV 4 2 100mV 0 ­2 100k 550k 5M FREQUENCY (Hz) 7.5 250mV 5.0 2.5 100mV 0 ­2.5 ­5.0 100k 50M Figure 7. Remote Temperature Error vs. Power Supply Noise Frequency 550k 5M FREQUENCY (Hz) 50M Figure 8. Local Temperature Error vs. Power Supply Noise Frequency http://onsemi.com 6 ADT7460 ADT7460 TYPICAL PERFORMANCE CHARACTERISTICS 1.90 1.85 SUPPLY CURRENT (mA) 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 2.6 2.5 3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.5 SUPPLY VOLTAGE (V) Figure 9. Supply Current vs. Supply Voltage 40 20mV 14 REMOTE TEMPERATURE ERROR (5C) REMOTE TEMPERATURE ERROR (5C) 16 12 10 8 10mV 6 4 2 0 ­2 60k 110k 35 100mV 30 25 20 15 10 40mV 5 0 20mV ­5 1M FREQUENCY (Hz) 10M ­10 10k 50M Figure 10. Remote Temperature Error vs. Differential Mode Noise Frequency 100k 1M FREQUENCY (Hz) Figure 11. Remote Temperature Error vs. Common-Mode Noise Frequency http://onsemi.com 7 10M ADT7460 ADT7460 Product Description The ADC also accepts input from an on-chip band gap temperature sensor, which monitors system ambient temperature. The ADT7460 ADT7460 is a thermal monitor and multiple fan controller for any system requiring monitoring and cooling. The device communicates with the system via a serial System Management Bus (SMBus). The serial bus controller has an optional address line for device selection (Pin 9), a serial data line for reading and writing addresses and data (Pin 16), and an input line for the serial clock (Pin 1). All control and programming functions of the ADT7460 ADT7460 are performed over the serial bus. In addition, two of the pins can be reconfigured as an SMBALERT output to indicate out-of-limit conditions. Sequential Measurement When the ADT7460 ADT7460 monitoring sequence is started, it cycles sequentially through the measurement of 2.5 V input and the temperature sensors. Measured values from these inputs are stored in value registers. These can be read out over the serial bus or can be compared with programmed limits stored in the limit registers. The results of out-of-limit comparisons are stored in the status registers, which can be read over the serial bus to flag out-of-limit conditions. Measurement Inputs The device has three measurement inputs, one for voltage and two for temperature. It can also measure its own supply voltage and can measure ambient temperature with its on-chip temperature sensor. Pin 14 is an analog input with an on-chip attenuator and is configured to monitor 2.5 V. Power is supplied to the chip via Pin 3, and the system also monitors VCC through this pin. In PCs, this pin is normally connected to a 3.3 V standby supply. This pin can, however, be connected to a 5.0 V supply and monitor it without over-ranging. Remote temperature sensing is provided by the D1± and D2± inputs, to which diode-connected, external temperature-sensing transistors, such as a 2N3904 2N3904 or CPU thermal diode, may be connected. Recommended Implementation Configuring the ADT7460 ADT7460 as in Figure 12 allows the systems designer the following features: Two PWM outputs for fan control of up to three fans (the front and rear chassis fans are connected in parallel). Three TACH fan speed measurement inputs. VCC measured internally through Pin 3. CPU temperature measured using Remote 1 temperature channel. Ambient temperature measured through Remote 2 temperature channel. Bidirectional THERM pin. Allows Intel Pentium 4 PROCHOT monitoring and can function as an overtemperature THERM output. SMBALERT system interrupt output. ADT7460 ADT7460 FRONT CHASSIS FAN CPU FAN PWM1 TACH2 TACH1 REAR CHASSIS FAN PWM3 D2+ TACH3 D2­ THERM CPU PROCHOT AMBIENT TEMPERATURE D1+ SDA D1­ SCL SMBALERT GND Figure 12. Recommended Implementation http://onsemi.com 8 ICH ADT7460 ADT7460 ADT7460 ADT7460 Address Selection Address 0x2E. This function is described in more detail later. Pin 8 is the dual-function PWM3/ADDRESS ENABLE pin. If Pin 8 is pulled low on powerup, the ADT7460 ADT7460 reads the state of Pin 9 (TACH4/ADDRESS SELECT/THERM) to determine the ADT7460 ADT7460's slave address. If Pin 8 is high on powerup, the ADT7460 ADT7460 defaults to SMBus Slave Internal Registers of the ADT7460 ADT7460 Table 1 summarizes the ADT7460 ADT7460's principal internal registers. Table 38 to Table 78 describe the registers in more detail. Table 1. Summary Internal Registers Register Configuration Description These registers provide control and configuration of the ADT7460 ADT7460, including alternate pinout functionality. Address Pointer This register contains the address that selects one of the other internal registers. When writing to the ADT7460 ADT7460, the first byte of data is always a register address, which is written to the address pointer register. Status Registers These registers provide the status of each limit comparison and are used to signal out-of-limit conditions on the temperature, voltage, or fan speed channels. If Pin 14 or Pin 5 is configured as SMBALERT, this pin asserts low whenever an unmasked status bit is set. Interrupt Mask These registers allow each interrupt status event to be masked when Pin 14 or Pin 5 is configured as an SMBALERT output. Value and Limit The results of analog voltage input, temperature, and fan speed measurements are stored in these registers, along with their limit values. Offset These registers allow each temperature channel reading to be offset by a twos complement value written to these registers. TMIN These registers program the starting temperature for each fan under automatic fan speed control. TRANGE Operating Point Enhance Acoustics These registers program the temperature-to-fan speed control slope in automatic fan speed control mode for each PWM output. These registers define the target operating temperatures for each thermal zone when running under dynamic TMIN control. This function allows the cooling solution to adjust dynamically in response to measured temperature and system performance. These registers allow each PWM output controlling fan to be tweaked to enhance the system's acoustics. Theory of Operation Table 2. Address Select Mode Serial Bus Interface Pin 8 State Pin 9 State 0 Low (10 kW to GND) 0101100 (0x2C) 0 High (10 kW pullup) 0101101 (0x2D) 1 Control of the ADT7460 ADT7460 is carried out using the serial System Management Bus (SMBus). The ADT7460 ADT7460 is connected to this bus as a slave device, under the control of a master controller. The ADT7460 ADT7460 has a 7-bit serial bus address. When the device is powered up with Pin 8 (PWM3/ ADDRESS ENABLE) high, the ADT7460 ADT7460 has a default SMBus address of 0101110 or 0x2E. If more than one ADT7460 ADT7460 is to be used in a system, each ADT7460 ADT7460 should be placed in address select mode by strapping Pin 8 low on powerup. The logic state of Pin 9 then determines the device's SMBus address. The logic state of these pins is sampled on powerup. The device address is sampled and latched on the first valid SMBus transaction, more precisely, on the low-to-high transition at the beginning of the eighth SCL pulse, when the serial address byte matches the selected slave address. The selected slave address is chosen using the ADDRESS ENABLE/ADDRESS SELECT pins. Any attempted changes in the address has no effect after this. Don't Care 0101110 (0x2E) (default) Address VCC ADT7460 ADT7460 ADDR_SEL 9 10k 8 PWM3/ADDR_EN ADDRESS = 0x2E Figure 13. Default SMBus Address 0x2E ADT7460 ADT7460 ADDR_SEL PWM3/ADDR_EN 9 10k 8 ADDRESS = 0x2C Figure 14. SMBus Address 0x2C (Pin 9 = 0) http://onsemi.com 9 ADT7460 ADT7460 to the slave device. If the R/W bit is a 1, the master reads from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. VCC ADT7460 ADT7460 ADDR_SEL PWM3/ADDR_EN 10k 9 8 ADDRESS = 0x2D Figure 15. SMBus Address 0x2D (Pin 9 = 1) VCC ADT7460 ADT7460 ADDR_SEL 10k 9 8 PWM3/ADDR_EN NC DO NOT LEAVE ADDR_EN UNCONNECTED. CAN CAUSE UNPREDICTABLE ADDRESSES CARE SHOULD BE TAKEN TO ENSURE THAT PIN 8 (PWM3/ADDR_EN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 8 FLOATING COULD CAUSE THE ADT7460 ADT7460 TO POWERUP WITH AN UNEXPECTED ADDRESS. NOTE THAT IF THE ADT7460 ADT7460 IS PLACED INTO ADDRESS SELECT MODE, PINS 8 AND 9 CAN BE USED AS THE ALTERNATE FUNCTIONS (PWM3, TACH4/THERM) ONLY IF THE CORRECT CIRCUIT IS MUXED IN AT THE CORRECT TIME. Figure 16. Unpredictable SMBus Address if Pin 8 is Unconnected Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the case of the ADT7460 ADT7460, write operations contain either one or two bytes, and read operations contain one byte. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed. Then data can be written in that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. This is illustrated in Figure 17. The device address is sent over the bus followed by R/W being set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. The facility to make hardwired changes to the SMBus slave address allows the user to avoid conflicts with other devices sharing the same serial bus, for example, if more than one ADT7460 ADT7460 is used in a system. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the star condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus a R/W bit, which determine the direction of the data transfer, that is, whether data is written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes http://onsemi.com 10 ADT7460 ADT7460 1 9 9 1 SCL SDA 0 1 0 1 1 A1 A0 D7 R/W START BY MASTER D6 D4 D5 D3 D2 D1 D0 ACK. BY ADT7460 ADT7460 ACK. BY ADT7460 ADT7460 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 1 9 SCL (CONTINUED) D7 SDA (CONTINUED) D6 D5 D4 D3 FRAME 3 DATA BYTE D2 D1 D0 ACK. BY ADT7460 ADT7460 STOP BY MASTER Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register protocol (see System Management Bus specifications Rev. 2.0 for more information). If it is required to perform several read or write operations in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. When reading data from a register, there are two possibilities: If the ADT7460 ADT7460's address pointer register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7460 ADT7460 as before, but only the data byte containing the register address is sent because data is not to be written to the register. This is shown in Figure 18. A read operation is then performed, consisting of the serial bus address, R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 19. If the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so Figure 18 can be omitted. It is possible to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register because the first data byte of a write is always written to the address pointer register. In Figure 17 and Figure 19, the serial bus address is shown as the default value 01011(A1) (A0), where A1 and A0 are set by the address select mode function previously defined. In addition to supporting the Send Byte and Receive Byte protocols, the ADT7460 ADT7460 also supports the Read Byte Write Operations The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7460 ADT7460 are discussed below. The following abbreviations are used in the diagrams: S-start P-stop R-read W-write A-acknowledge A-no acknowledge The ADT7460 ADT7460 uses the following SMBus write protocols: Send Byte In this operation, the master device sends a single command byte to a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends the register address. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. http://onsemi.com 11 ADT7460 ADT7460 1 9 1 9 SCL 0 SDA 10 1 START BY MASTER 1 A1 A0 D7 R/W D6 D4 D5 D2 D3 D1 D0 ACK. BY ADT7460 ADT7460 FRAME 1 SERIAL BUS ADDRESS BYTE ACK. BY ADT7460 ADT7460 STOP BY MASTER FRAME 2 ADDRESS POINTER REGISTER BYTE Figure 18. Writing to the Address Pointer Register Only 1 9 1 9 SCL 0 SDA 10 1 START BY MASTER 1 A1 A0 D7 R/ W D6 D4 D5 D2 D3 D1 D0 ACK. BY ADT7460 ADT7460 FRAME 1 SERIAL BUS ADDRESS BYTE NO ACK. BY STOP BY MASTER MASTER FRAME 2 DATA BYTE FROM ADT7460 ADT7460 Figure 19. Reading Data from a Previously Selected Register Read Operations For the ADT7460 ADT7460, the send byte protocol is used to write to the address pointer register for a subsequent single-byte read from the same address. This is illustrated in Figure 20. 1 2 3 SLAVE W A ADDRESS S 4 Receive Byte 5 6 REGISTER ADDRESS The ADT7460 ADT7460 uses the following SMBus read protocols. A P This is useful when repeatedly reading a single register. The register address needs to have been set up previously. In this operation, the master device receives a single byte from a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts ACK on SDA. 4. The master receives a data byte. 5. The master asserts NO ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. In the ADT7460 ADT7460, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or by write byte operation. Figure 20. Setting a Register Address for Subsequent Read If it is required to read data from the register immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single-byte read without asserting an intermediate stop condition. Write Byte In this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends the register address. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master asserts a stop condition on SDA to end the transaction. This is illustrated in Figure 21. 1 2 3 SLAVE S ADDRESS W A 4 5 REGISTER ADDRESS A 6 1 2 3 SLAVE S ADDRESS R A 4 5 6 DATA A P Figure 22. Single-Byte Read from a Register Alert Response Address Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The SMBALERT output can be used as an interrupt output or can be used as an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device's SMBALERT line goes low, the following occurs: 1. SMBALERT is pulled low. 7 8 DATA A P Figure 21. Single-Byte Write to a Register http://onsemi.com 12 ADT7460 ADT7460 2. Master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address, which must not be used as a specific device address. 3. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known, and it can be interrogated in the usual way. 4. If more than one device's SMBALERT output is low, the one with the lowest device address has priority in accordance with normal SMBus arbitration. 5. Once the ADT7460 ADT7460 has responded to the alert response address, the master must read the status registers and the SMBALERT is cleared only if the error condition has gone away. to 2.25 V, but the input has built-in attenuators to allow measurement of 2.5 V without any external components. To allow the tolerance of the supply voltage, the ADC produces an output of 3/4 full scale (768d or 0x300) for the nominal input voltage and so has adequate headroom to deal with overvoltages. Input Circuitry The internal structure for the 2.5 V analog input is shown in Figure 23. The input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first-order low-pass filter that gives the input immunity to high frequency noise. Table 4. Voltage Measurement Registers Register 0x00 Table 5. 2.5 V Limits Registers Register Table 3. Configuration Register 1 (Reg. 0x40) Description Default 0x44 0: SMBus timeout enabled (default) 1: SMBus timeout disabled 2.5 V low limit 0x00 0x45 Description TODIS 0x00 VCC reading Associated with the voltage measurement channels are a high and low limit register. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. The ADT7460 ADT7460 includes an SMBus timeout feature. If there is no SMBus activity for 25 ms, the ADT7460 ADT7460 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled. TODIS 2.5 V reading 0x22 Bit Default 0x20 SMBus Timeout Description 2.5 V high limit 0xFF 0x48 VCC low limit 0x00 0x49 VCC high limit 0xFF Voltage Measurement Input The ADT7460 ADT7460 has one external voltage measurement channel. It can also measure its own supply voltage, VCC. Pin 14 may be configured to measure a 2.5 V supply. The VCC supply voltage measurement is carried out through the VCC pin (Pin 3). Setting Bit 7 of Configuration Register 1 (Reg. 0x40) allows a 5.0 V supply to power the ADT7460 ADT7460 and be measured without over-ranging the VCC measurement channel. The 2.5 V input can be used to monitor a chipset supply voltage in computer systems. 2.5VIN 45k 94k 30pF Figure 23. Structure of Analog Inputs Table 6 shows the input ranges of the analog inputs and output codes of the 10-bit ADC. When the ADC is running, it samples and converts a voltage input in 711 ms and averages 16 conversions to reduce noise; a measurement takes nominally 11.38 ms. Analog-to-Digital Converter All analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This has a resolution of 10 bits. The basic input range is 0 V http://onsemi.com 13 ADT7460 ADT7460 Table 6. 10-Bit A/D Output Code vs. VIN Input Voltage 5 VIN ADC Output VCC (3.3 VIN) (Note 1) 2.5 VIN Decimal Binary (10 Bits) 5.825 s in Hour 3, this can indicate that system performance is degrading significantly since 1. Configure the THERM input. Setting Bit 1 (THERM ENABLE) of Configuration Register 3 (Reg. 0x78) enables the THERM monitoring function. 2. Select the desired fan behavior for THERM events. Setting Bit 2 (BOOST bit) of Configuration Register 3 (Reg. 0x78) causes all fans to run at 100% duty cycle whenever THERM is asserted. This allows fail-safe system cooling. If this bit = 0, the fans run at their current settings and are not affected by THERM events. 3. Select whether THERM events should generate SMBALERT interrupts. Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when set, masks out SMBALERTs when the THERM limit value is exceeded. This bit should be cleared http://onsemi.com 22 ADT7460 ADT7460 on/off ratio) of a square wave applied to the fan to vary the fan speed. The external circuitry required to drive a fan using PWM control is extremely simple. A single MOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan being driven. Typical notebook fans draw a nominal 170 mA, so SOT devices can be used where board space is a concern. In desktops, fans can typically draw 250 mA to 300 mA each. If the user drives several fans in parallel from a single PWM output or drives larger server fans, the MOSFET needs to handle the higher current requirements. The only other stipulation is that the MOSFET should have a gate voltage drive, VGS < 3.3 V, for direct interfacing to the PWM_OUT pin. VGS can be greater than 3.3 V as long as the pullup on the gate is tied to 5.0 V. The MOSFET should also have a low on resistance to ensure that there is not significant voltage drop across the FET. This would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan. Figure 40 shows how a 3-wire fan can be driven using PWM control. THERM is asserting more frequently on an hourly basis. Alternatively, OS or BIOS level software can time-stamp when the system is powered on. If an SMBALERT is generated due to the THERM limit being exceeded, another time-stamp can be taken. The difference in time can be calculated for a fixed THERM limit time. For example, if it takes one week for a THERM limit of 2.914 s to be exceeded and the next time it takes only one hour, this indicates a serious degradation in system performance. Configuring the ADT7460 ADT7460 THERM Pin as an Output In addition to the ADT7460 ADT7460 being able to monitor THERM as an input, the ADT7460 ADT7460 can optionally drive THERM low as an output. The user can preprogram system critical thermal limits. If the temperature exceeds a thermal limit by 0.25°C, THERM asserts low. If the temperature is still above the thermal limit on the next monitoring cycle, THERM stays low. THERM remains asserted low until the temperature is equal to or below the thermal limit. Since the temperature for that channel is measured only every monitoring cycle, once THERM asserts, it is guaranteed to remain low for at least one monitoring cycle. The THERM pin can be configured to assert low if the Remote 1, local, or Remote 2 temperature THERM limits are exceeded by 0.25°C. The THERM limit registers are at Locations 0x6A, 0x6B, and 0x6C, respectively. Setting Bit 3 of Registers 0x5F, 0x60, and 0x61 enables the THERM output feature for the Remote 1, local, and Remote 2 temperature channels, respectively. Figure 39 shows how the THERM pin asserts low as an output in the event of a critical overtemperature. 12V 12V 10k TACH/AIN 10k 4.7k 3.3V TACH 12V FAN 1N4148 1N4148 ADT7460 ADT7460 10k PWM Q1 NDT3055L NDT3055L Figure 40. Driving a 3-Wire Fan Using an N-Channel MOSFET THERM LIMIT 0.255C Figure 40 uses a 10 kW pullup resistor for the TACH signal. This assumes that the TACH signal is open-collector from the fan. In all cases, the TACH signal from the fan must be kept below 5.0 V maximum to prevent damaging the ADT7460 ADT7460. If in doubt as to whether the fan used has an open-collector or totem pole TACH output, use one of the input signal conditioning circuits shown in the Fan Speed Measurement section. Figure 41 shows a fan drive circuit using an NPN transistor such as a general-purpose MMBT2222 MMBT2222. While these devices are inexpensive, they tend to have much lower current handling capabilities and higher on-resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the fan's current requirements. Ensure that the base resistor is chosen such that the transistor is saturated when the fan is powered on. THERM LIMIT TEMP THERM ADT7460 ADT7460 MONITORING CYCLE Figure 39. Asserting THERM as an Output, Based on Tripping THERM Limits Fan Drive Using PWM Control The ADT7460 ADT7460 uses pulse width modulation (PWM) to control fan speed. This relies on varying the duty cycle (or http://onsemi.com 23 ADT7460 ADT7460 12V 12V 3.3V 10k TYPICAL 10k TACH/AIN 10k 4.7k 3.3V 12V FAN TACH 1N4148 1N4148 TACH4 ADT7460 ADT7460 ADT7460 ADT7460 470 +V 10k TYPICAL TACH3 Q1 MMBT2222 MMBT2222 PWM +V 3.3V 3.3V 5V OR 12V FAN TACH 1N4148 1N4148 5V OR 12V FAN TACH 10k TYPICAL Figure 41. Driving a 3-Wire Fan Using an NPN Transistor Driving Two Fans from PWM3 Figure 43. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET Note that the ADT7460 ADT7460 has four TACH inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is being used in the system, it should be driven from the PWM3 output in parallel with the third fan. Figure 42 shows how to drive two fans in parallel using low cost NPN transistors. Figure 43 is the equivalent circuit using the NDT3055L NDT3055L MOSFET. Note that since the MOSFET can handle up to 3.5 A, it is simply a matter of connecting another fan directly in parallel with the first. Care should be taken in designing drive circuits with transistors and FETs to ensure that the PWM pins are not required to source current and that they sink less than the 8 mA maximum current specified on the data sheet. Table 26. SYNC: Enhance Acoustics Register 1 (Reg. 0x62) Bit PWM3 2.2k 1N4148 1N4148 3.3V TACH3 TACH4 Q1 MMBT3904 MMBT3904 10 1 synchronizes TACH2, TACH3, and TACH4 to PWM3. Figure 44 shows how a 2-wire fan may be connected to the ADT7460 ADT7460. This circuit allows the speed of a 2-wire fan to be measured, even though the fan has no dedicated TACH signal. A series resistor, RSENSE, in the fan circuit converts the fan commutation pulses into a voltage. This is ac-coupled into the ADT7460 ADT7460 through the 0.01 mF capacitor. On-chip signal conditioning allows accurate monitoring of fan speed. The value of RSENSE chosen depends on the programmed input threshold and on the current drawn by the fan. For fans drawing approximately 200 mA, a 2 W RSENSE value is suitable when the threshold is programmed as 40 mV. For fans that draw more current, such as larger desktop or server fans, RSENSE may be reduced for the same programmed threshold. The smaller the threshold programmed the better, since more voltage is developed across the fan and the fan spins faster. Figure 45 shows a typical plot of the sensing waveform at a TACH/AIN pin. The most important thing is that the voltage spikes (either negative going or positive going) are more than 40 mV in amplitude. This allows fan speed to be reliably determined. 12V 1k SYNC Description Driving 2-Wire Fans TACH measurements for fans are synchronized to particular PWM channels, for example, TACH1 is synchronized to PWM1. TACH3 and TACH4 are both synchronized to PWM3, so PWM3 can drive two fans. Alternatively, PWM3 can be programmed to synchronize TACH2, TACH3, and TACH4 to the PWM3 output. This allows PWM3 to drive two or three fans. In this case, the drive circuitry looks the same as shown in Figure 41, Figure 42, and Figure 43. The SYNC bit in Register 0x62 enables this function. 3.3V Mnemonic Driving Up to Three Fans from PWM2 ADT7460 ADT7460 Q1 NDT3055L NDT3055L PWM3 +V Q2 MMBT2222 MMBT2222 ADT7460 ADT7460 10 3.3V 10k TYPICAL PWM Figure 42. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors 1N4148 1N4148 5.0V OR 12V FAN Q1 NDT3055L NDT3055L 0.01F TACH/AIN RSENSE 2 TYPICAL Figure 44. Driving a 2-Wire Fan http://onsemi.com 24 ADT7460 ADT7460 If the fan TACH output has a resistive pullup to VCC, it can be connected directly to the fan input, as shown in Figure 47. n: 250 mV @: ­258mV VCC 12V PULLUP 4.7k TYPICAL ADT7460 ADT7460 TACH OUTPUT FAN SPEED COUNTER TACH Figure 47. Fan with TACH Pullup to VCC CH1 100mV CH3 50.0mV CH2 5.00mV CH4 50.0mV M 4.00ms T A CH1 If the fan output has a resistive pullup to 12 V (or other voltage greater than 5.0 V), the fan output can be clamped with a Zener diode, as shown in Figure 48. The Zener diode voltage should be greater than VIH of the TACH input but less than 5.0 V, allowing for the voltage tolerance of the Zener. A value of between 3 V and 5.0 V is suitable. ­2.00mV 1.00000ms Figure 45. Fan Speed Sensing Waveform at TACH/AIN Pin VCC 12V Laying Out 2-Wire and 3-Wire Fans PULLUP 4.7k TYPICAL Figure 46 shows how to lay out a common circuit arrangement for 2-wire and 3-wire fans. Some components are not populated, depending on whether a 2-wire or 3-wire fan is used. Figure 48. Fan with TACH Pullup to Voltage . 5.0 V, for Example, 12 V, Clamped with Zener Diode If the fan has a strong pullup (less than 1 kW) to 12 V or a totem-pole output, a series resistor can be added to limit the Zener current, as shown in Figure 49. Alternatively, a resistive attenuator may be used, as shown in Figure 50. R1 and R2 should be chosen such that: 2 V < VPULLUP × R2/(RPULLUP + R1 + R2) < 5.0 V The fan inputs have an input resistance of nominally 160 kW to ground. This should be taken into account when calculating resistor values. With a pullup voltage of 12 V and pullup resistor less than 1 kW, suitable values for R1 and R2 would be 100 kW and 47 kW. This gives a high input voltage of 3.83 V. 3.3V OR 5.0V R5 Q1 MMBT2222 MMBT2222 C1 TACH/AIN R3 R4 FAN SPEED COUNTER *CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 y V CC 1N4148 1N4148 R2 ADT7460 ADT7460 TACH ZD1* 12V OR 5.0V R1 TACH OUTPUT PWM FOR 3-WIRE FANS: POPULATE R1, R2, R3 R4 = 0 C1 = UNPOPULATED FOR 2-WIRE FANS: POPULATE R4, C1 R1, R2, R3 UNPOPULATED Figure 46. Planning for 2-Wire or 3-Wire Fans on a PCB TACH Inputs Pins 4, 6, 7, and 9 are open-drain TACH inputs for fan speed measurement. Signal conditioning in the ADT7460 ADT7460 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 5.0 V, even where VCC is less than 5.0 V. In the event that these inputs are supplied from fan outputs that exceed 0 V to 5.0 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 47 to Figure 50 show circuits for most common fan TACH outputs. VCC 5.0V OR 12V FAN PULLUP TYP VCC or Totem-Pole Output, Clamped with Zener and Resistor http://onsemi.com 25 ADT7460 ADT7460 high and low byte registers are read from. This prevents erroneous TACH readings. The fan tachometer reading registers report the number of 11.11 ms period clocks (90 kHz oscillator) gated to the fan speed counter, from the rising edge of the first fan TACH pulse to the rising edge of the third fan TACH pulse (assuming two pulses per revolution are being counted). Since the device is essentially measuring the fan TACH period, the higher the count value the slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates either that the fan has stalled or that it is running very slowly ( Comparison Performed Since the actual fan TACH period is being measured, exceeding a fan TACH limit by 1 sets the appropriate status bit and can be used to generate an SMBALERT. The fan TACH limit registers are 16-bit values consisting of two bytes. VCC 12V VCC or Totem-Pole Output, Attenuated with R1/R2 Fan Speed Measurement The fan counter does not count the fan TACH output pulses directly because the fan speed may be less than 1000 RPM. It would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 90 kHz oscillator into the input of a 16-bit counter for N periods of the fan TACH output (Figure 51). The accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. Table 28. Fan TACH Limit Registers Register 0xFF TACH2 minimum low byte 0xFF TACH2 minimum high byte 0xFF 0x58 TACH3 minimum low byte 0xFF 0x59 TACH3 minimum high byte 0xFF 0x5A TACH4 minimum low byte 0xFF 0x5B 2 TACH1 minimum high byte 0x56 1 0xFF 0x57 TACH TACH1 minimum low byte 0x55 PWM Default 0x54 CLOCK Description TACH4 minimum high byte 0xFF 3 Fan Speed Measurement Rate 4 The fan TACH readings are normally updated once every second. The FAST bit (Bit 3) of Configuration Register 3 (Reg. 0x78), when set, updates the fan TACH readings every 250 ms. If any of the fans are not being driven by a PWM channel but are instead powered directly from 5.0 V or 12 V, its associated dc bit in Configuration Register 3 should be set. This allows TACH readings to be taken on a continuous basis for fans connected directly to a dc source. Figure 51. Fan Speed Measurement N, the number of pulses counted, is determined by the settings of Register 0x7B (fan pulses per revolution register). This register contains two bits for each fan, allowing one, two (default), three, or four TACH pulses to be counted. The fan tachometer readings are 16-bit values consisting of a 2-byte read from the ADT7460 ADT7460. Table 27. Fan Speed Measurement Registers Register Description 0x28 TACH1 low byte 0x00 0x29 TACH1 high byte 0x00 0x2A TACH2 low byte 0x00 0x2B TACH2 high byte 0x00 0x2C TACH3 low byte 0x00 0x2D TACH3 high byte 0x00 0x2E TACH4 Low byte 0x00 0x2F TACH4 high byte Calculating Fan Speed Default 0x00 Assuming a fan with a two pulses/revolution (and two pulses/ revolution being measured), fan speed is calculated by: Fan Speed (RPM) = 90,000 × 60/Fan TACH Reading where: Fan TACH Reading = 16-Bit Fan Tachometer Reading For example: TACH1 High Byte (Reg. 0x29) = 0x17 TACH1 Low Byte (Reg. 0x28) = 0xFF What is Fan 1 speed in RPM? Fan 1 TACH Reading = 0x17FF = 6143d RPM = (f × 60)/Fan 1 TACH Reading RPM = (90000 × 60)/6143 Fan Speed = 879 RPM Reading Fan Speed from the ADT7460 ADT7460 If fan speeds are being measured, this involves a 2-register read for each measurement. The low byte should be read first. This causes the high byte to be frozen until both http://onsemi.com 26 ADT7460 ADT7460 Fan Pulses per Revolution Table 32. Configuration Register 4 (Reg. 0x7D) Different fan models can output either 1, 2, 3, or 4 TACH pulses per revolution. Once the number of fan TACH pulses is determined, it can be programmed into the fan pulses per revolution register (Reg. 0x7B) for each fan. Alternatively, this register can be used to determine the number of pulses/revolution output by a given fan. By plotting fan speed measurements at 100% speed with different pulses/revolution settings, the smoothest graph with the lowest ripple determines the correct pulses/revolution value. Bit Mnemonic FAN1 Default 2 pulses per revolution FAN2 Default 2 pulses per revolution FAN3 Default 2 pulses per revolution FAN4 Default 2 pulses per revolution Table 30. Fan Pulses/Revolution Register Bit Values Value 1 pulse per revolution 01 2 pulses per revolution 10 3 pulses per revolution 11 Fan Startup Timeout Description 00 4 pulses per revolution To prevent false interrupts being generated as a fan spins up (since it is below running speed), the ADT7460 ADT7460 includes a fan startup timeout function. This is the time limit allowed for two TACH pulses to be detected on spin-up. For example, if 2 seconds fan startup timeout is chosen and no TACH pulses occur within 2 seconds of the start of spin-up, a fan fault is detected and flagged in the interrupt status registers. 2-Wire Fan Speed Measurements The ADT7460 ADT7460 is capable of measuring the speed of 2-wire fans, that is, fans without TACH outputs. To do this, the fan must be interfaced as shown in the Fan Drive Circuitry section. In this case, the TACH inputs need to be reprogrammed as analog inputs, AIN. Table 33. PWM1 to PWM3 Configuration (Reg. 0x5C to 0x5E) Bit Mnemonic AIN4 1 indicates that Pin 9 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. 2 AIN3 1 indicates that Pin 4 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. SPIN Description 3 Mnemonic Table 31. Configuration Register 2 (Reg. 0x73) Bit 1 AIN2 AIN1 Description These bits control the startup timeout for PWM1. 000 = no startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 100 = 667 ms 101 = 1 s 110 = 2 s 111 = 4 s Disabling Fan Startup Timeout Although fan startup makes fan spin-ups much quieter than fixed-time spin-ups, the option exists to use fixed spin-up times. Bit 5 (FSPDIS) = 1 in Configuration Register 1 (Reg. 0x40) disables the spin-up for two TACH pulses. Instead, the fan spins up for the fixed time as selected in Registers 0x5C to 0x5E. 1 indicates that Pin 7 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. 0 Description These two bits define the input threshold for 2-wire fan speed measurements. 00 = ±20 mV 01 = ±40 mV 10 = ±80 mV 11 = ±130 mV The ADT7460 ADT7460 has a unique fan spin-up function. It spins the fan at 100% PWM duty cycle until two TACH pulses are detected on the TACH input. Once two pulses are detected, the PWM duty cycle goes to the expected running value, for example, 33%. The advantage of this is that fans have different spin-up characteristics and take different amounts of time to overcome inertia. The ADT7460 ADT7460 runs the fans just fast enough to overcome inertia and is quieter on spin-up than fans programmed to spinup for a given spin-up time. Description AINL Fan Spin-Up Table 29. Fan Pulses/Revolution Register (Reg. 0x7B) Bit Mnemonic 1 indicates that Pin 6 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. PWM Logic State AIN Switching Threshold The PWM outputs can be programmed high for 100% duty cycle (non-inverted) or low for 100% duty cycle (inverted). Having configured the TACH inputs as AIN inputs for 2-wire measurements, the user can select the sensing threshold for the AIN signal. http://onsemi.com 27 ADT7460 ADT7460 Table 34. PWM1 to PWM3 Configuration (Reg. 0x5C to 0x5E) Bits Bit Mnemonic Description INV 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle PWM Drive Frequency The PWM drive frequency can be adjusted for the application. Registers 0x5F to 0x61 configure the PWM frequency for PWM1 to PWM3, respectively. VARY PWM DUTY CYCLE WITH 8-BIT RESOLUTION Table 35. PWM1 to PWM3 Frequency Registers (Reg. 0x5F to 0x61) Bit Mnemonic FREQ Figure 52. Control PWM Duty Cycle Manually with a Resolution of 0.39% Description 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz Programming the PWM Current Duty Cycle Registers The PWM current duty cycle registers are 8-bit registers, which allow the PWM duty cycle for each output to be set anywhere from 0% (0x00) to 100% (0xFF) in steps of 0.39% (256 steps). The value to be programmed into the PWMMIN register is given by: Value (decimal) = PWMMIN/0.39 Example 1: For a PWM duty cycle of 50%, Value (decimal) = 50/0.39 = 128d Value = 128d or 0x80. Example 2: For a PWM duty cycle of 33%, Value (decimal) = 33/0.39 = 85d Value = 85d or 0x54. Fan Speed Control The ADT7460 ADT7460 can control fan speed by two different modes. The first is automatic fan speed control mode. In this mode, fan speed is automatically varied with temperature and without CPU intervention, once initial parameters are set up. The advantage of this is that, in the case of the system hanging, the system is protected from overheating. The automatic fan speed control incorporates a feature called dynamic TMIN calibration. This feature reduces the design effort required to program the automatic fan speed control loop. For more information on how to program the automatic fan speed control loop and dynamic TMIN calibration, see AN613/D AN613/D, the Programming the Automatic Fan Speed Control Loop Application Note. The second fan speed control method is manual fan speed control, which is described next. Table 37. PWM Duty Cycle Registers Register BHVR 111 0xFF (100%) PWM2 duty cycle 0xFF (100%) 0x32 PWM3 duty cycle 0xFF (100%) By reading the PWMx current duty cycle registers, users can keep track of the current duty cycle on each PWM output, even when the fans are running in automatic fan speed control mode or in acoustic enhancement mode. Operating from 3.3 V Standby The ADT7460 ADT7460 has been specifically designed to operate from a 3.3 V STBY supply. In computers that support S3 and S5 states, the core voltage of the processor is lowered in these states. If using the dynamic TMIN mode, lowering the core voltage of the processor would change the CPU temperature and change the dynamics of the system under dynamic TMIN control. Likewise, when monitoring THERM, the THERM timer should be disabled during these states. Table 36. PWM1 to PWM3 Configuration (Reg. 0x5C to 0x5E) Bits PWM1 duty cycle 0x31 The ADT7460 ADT7460 allows the duty cycle of any PWM output to be manually adjusted. This can be useful if you want to change fan speed in software or if you want to adjust PWM duty cycle output for test purposes. Bits of Registers 0x5C, 0x5E (PWM configuration) control the behavior of each PWM output. Mnemonic Default 0x30 Manual Fan Speed Control Bit Description Description Manual mode Once under manual control, each PWM output can be manually updated by writing to Registers 0x30, 0x32 (PWMx current duty cycle registers). http://onsemi.com 28 ADT7460 ADT7460 XNOR Tree Test Mode Power-On Default The ADT7460 ADT7460 includes an XNOR tree test mode. This mode is useful for in-circuit test equipment at board-level testing. By applying stimulus to the pins included in the XNOR tree, it is possible to detect opens or shorts on the system board. Figure 53 shows the signals that are exercised in the XNOR tree test mode. The XNOR tree test is invoked by setting Bit 0 (XEN) of the XNOR tree test enable register (Reg. 0x6F). The ADT7460 ADT7460 does not monitor temperature and fan speed by default on powerup. Monitoring of temperature and fan speed is enabled by setting the start bit in configuration Register 1 (Bit 0, Address 0x40) to 1. The fans run at full speed on powerup. This is because the BHVR bits (Bits ) in the PWMx configuration registers are set to 100 (fans run full speed) by default. TACH1 TACH2 TACH3 TACH4 PWM2 PWM3 PWM1/XTO Figure 53. XNOR Tree Test Table 38. ADT7460 ADT7460 Registers Addr R/W 0x20 R 0x22 0x25 Desc Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 2.5 V Reading 9 8 7 6 5 4 3 2 0x00 R VCC Reading 9 8 7 6 5 4 3 2 0x00 R Remote 1 Temp 9 8 7 6 5 4 3 2 0x80 0x26 R Local Temperature 9 8 7 6 5 4 3 2 0x80 0x27 R Remote 2 Temp 9 8 7 6 5 4 3 2 0x80 0x28 R TACH1 Low Byte 7 6 5 4 3 2 1 0 0x00 0x29 R TACH1 High Byte 15 14 13 12 11 10 9 8 0x00 0x2A R TACH2 Low Byte 7 6 5 4 3 2 1 0 Lockable 0x00 0x2B R TACH2 High Byte 15 14 13 12 11 10 9 8 0x00 0x2C R TACH3 Low Byte 7 6 5 4 3 2 1 0 0x00 0x2D R TACH3 High Byte 15 14 13 12 11 10 9 8 0x00 0x2E R TACH4 Low Byte 7 6 5 4 3 2 1 0 0x00 0x2F R TACH4 High Byte 15 14 13 12 11 10 9 8 0x00 0x30 R/W PWM1 Current Duty Cycle 7 6 5 4 3 2 1 0 0xFF 0x31 R/W PWM2 Current Duty Cycle 7 6 5 4 3 2 1 0 0xFF 0x32 R/W PWM3 Current Duty Cycle 7 6 5 4 3 2 1 0 0xFF 0x33 R/W Remote 1 Operating Point 7 6 5 4 3 2 1 0 0x64 YES 0x34 R/W Local Temp Operating Point 7 6 5 4 3 2 1 0 0x64 YES 0x35 R/W Remote 2 Operating Point 7 6 5 4 3 2 1 0 0x64 YES 0x36 R/W Dynamic TMIN Control Reg. 1 R2T LT R1T PHTR2 PHTL PHTR1 VCCRES CYR2 0x00 YES 0x37 R/W Dynamic TMIN Control Reg. 2 CYR2 CYR2 CYL CYL CYL CYR1 CYR1 CYR1 0x00 YES 0x3D R Device ID Register 7 6 5 4 3 2 1 0 0x27 0x3E R Comp ID Number 7 6 5 4 3 2 1 0 0x41 http://onsemi.com 29 ADT7460 ADT7460 Table 38. ADT7460 ADT7460 Registers Addr R/W Desc Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x3F R Revision Number VER VER VER VER STP STP STP STP 0x40 R/W 0x41 R 0x62 or 0x6A Config Register 1 VCC TODIS FSPDIS RES FSPD RDY LOCK STRT 0x00 Interrupt Stat Reg 1 OOL R2T LT R1T RES VCC RES 2.5 V 0x42 R 0x44 R/W 0x00 Interrupt Stat Reg 2 2.5 V Low Limit D2 D1 5 FAN3 FAN2 FAN1 OVT RES 0x00 7 6 5 4 3 2 1 0 0x45 R/W 0x00 2.5 V High Limit 7 6 5 4 3 2 1 0 0x48 0xFF R/W VCC Low Limit 7 6 5 4 3 2 1 0 Lockable 0x00 YES 0x49 R/W VCC High Limit 7 6 5 4 3 2 1 0 0xFF 0x4E R/W Remote 1 Temp Low Limit 7 6 5 4 3 2 1 0 0x81 0x4F R/W Remote 1 Temp High Limit 7 6 5 4 3 2 1 0 0x7F 0x50 R/W Local Temp Low Limit 7 6 5 4 3 2 1 0 0x81 0x51 R/W Local Temp High Limit 7 6 5 4 3 2 1 0 0x7F 0x52 R/W Remote 2 Temp Low Limit 7 6 5 4 3 2 1 0 0x81 0x53 R/W Remote 2 Temp High Limit 7 6 5 4 3 2 1 0 0x7F 0x54 R/W TACH1 Min Low Byte 7 6 5 4 3 2 1 0 0xFF 0x55 R/W TACH1 Min High Byte 15 14 13 12 11 10 9 8 0xFF 0x56 R/W TACH2 Min Low Byte 7 6 5 4 3 2 1 0 0xFF 0x57 R/W TACH2 Min High Byte 15 14 13 12 11 10 9 8 0xFF 0x58 R/W TACH3 Min Low Byte 7 6 5 4 3 2 1 0 0xFF 0x59 R/W TACH3 Min High Byte 15 14 13 12 11 10 9 8 0xFF 0x5A R/W TACH4 Min Low Byte 7 6 5 4 3 2 1 0 0xFF 0x5B R/W TACH4 Min High Byte 15 14 13 12 11 10 9 8 0xFF 0x5C R/W PWM1 Config Reg BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x62 YES 0x5D R/W PWM2 Config Reg BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x62 YES 0x5E R/W PWM3 Config Reg BHVR BHVR BHVR INV SLOW SPIN SPIN SPIN 0x62 YES 0x5F R/W Remote 1 TRANGE/ PWM1 Freq. RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0xC4 YES 0x60 R/W Local TRANGE/ PWM2 Freq. RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0xC4 YES 0x61 R/W Remote 2 TRANGE/ PWM3 Freq. RANGE RANGE RANGE RANGE THRM FREQ FREQ FREQ 0xC4 YES 0x62 R/W Enhance Acoustics Reg. 1 MIN3 MIN2 MIN1 SYNC EN1 ACOU ACOU ACOU 0x00 YES 0x63 R/W Enhance Acoustics Reg. 2 EN2 ACOU2 ACOU2 ACOU2 EN3 ACOU3 ACOU3 ACOU3 0x00 YES 0x64 R/W PWM1 Min Duty Cycle 7 6 5 4 3 2 1 0 0x80 YES 0x65 R/W PWM2 Min Duty Cycle 7 6 5 4 3 2 1 0 0x80 YES 0x66 R/W PWM3 Min Duty Cycle 7 6 5 4 3 2 1 0 0x80 YES 0x67 R/W Remote1 Temp TMIN 7 6 5 4 3 2 1 0 0x5A YES 0x68 R/W Local Temp TMIN 7 6 5 4 3 2 1 0 0x5A YES 0x69 R/W Remote2 Temp TMIN 7 6 5 4 3 2 1 0 0x5A YES http://onsemi.com 30 ADT7460 ADT7460 Table 38. ADT7460 ADT7460 Registers Addr R/W 0x6A R/W Desc Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable Remote1 THERM Limit 7 6 5 4 3 2 1 0 0x64 YES 0x6B R/W Local THERM Limit 7 6 5 4 3 2 1 0 0x64 YES 0x6C R/W Remote2 THERM Limit 7 6 5 4 3 2 1 0 0x64 YES 0x6D R/W Remote1 Local Hysteresis HYSR1 HYSR1 HYSR1 HYSR1 HYSL HYSL HYSL HYSL 0x44 YES 0x6E R/W Remote2 Temp Hysteresis HYSR2 HYSR2 HYSR2 HYSR2 RES RES RES RES 0x40 YES 0x6F R/W XNOR Tree Test Enable RES RES RES RES RES RES RES XEN 0x00 YES 0x70 R/W Remote1 Temp Offset 7 6 5 4 3 2 1 0 0x00 YES 0x71 R/W Local Temp Offset 7 6 5 4 3 2 1 0 0x00 YES 0x72 R/W Remote2 Temp Offset 7 6 5 4 3 2 1 0 0x00 YES 0x73 R/W Config Reg 2 SHDN CONV ATTN AVG AIN4 AIN3 AIN2 AIN1 0x00 YES 0x74 R/W Interrupt Mask Reg 1 OOL R2T LT R1T RES VCC RES 2.5V 0x00 0x75 R/W Interrupt Mask Reg 2 D2 D1 F4P FAN3 FAN2 FAN1 OVT RES 0x00 0x76 R/W Ext Resolution 1 RES RES VCC VCC RES RES 2.5V 2.5V 0x00 0x77 R/W Ext Resolution 2 TDM2 TDM2 LTMP LTMP TDM1 TDM1 RES RES 0x00 0x78 R/W Config Reg 3 DC4 DC3 DC2 DC1 FAST BOOST THERM ENABLE ALERT 0x00 0x79 R THERM Status Reg TMR TMR TMR TMR TMR TMR TMR ASRT/ TMR 0x00 0x7A R/W THERM Limit Reg LIMT LIMT LIMT LIMT LIMT LIMT LIMT LIMT 0x00 0x7B R/W Fan Pulses per Revolution FAN4 FAN4 FAN3 FAN3 FAN2 FAN2 FAN1 FAN1 0x55 0x7D R/W Config Reg 4 RES RES RES RES AINL AINL RES AL2.5V 0x00 YES 0x7E R Test Register 1 DO NOT WRITE TO THESE REGISTERS 0x00 YES 0x7F R Test Register 2 DO NOT WRITE TO THESE REGISTERS 0x00 YES YES Table 39. Voltage Reading Registers (Power-On Default = 0x00) (Note 1) Register Address R/W Description 0x20 Read-only 2.5 V Reading (8 MSBs of reading) 0x22 Read-only VCC Reading: Measures VCC through the VCC pin (8 MSBs of reading) 1. These voltage readings are in twos complement format. If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended resolution registers are read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. Table 40. Temper