ADSP-21368 ADSP-21367 ADSP-21369 ADSP-21371 ADSP-21375 TXTWI16 RXTWI16 - Datasheet Archive

 

Hardware Reference Includes ADSP-21367, ADSP-21369, ADSP-21371, ADSP-21375 Revision 1.0, September 2006 Part Number 82-000100-01

 

ADSP-21368 ADSP-21368 SHARC® Processor Hardware Reference Includes ADSP-21367 ADSP-21367, ADSP-21369 ADSP-21369, ADSP-21371 ADSP-21371, ADSP-21375 ADSP-21375 Revision 1.0, September 2006 Part Number 82-000100-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2006 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo and icon bar, Blackfin, EZ-KIT Lite, SHARC, the SHARC logo, TigerSHARC, and VisualDSP+ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. CONTENTS PREFACE Purpose of This Manual . xxxi Intended Audience . xxxi Manual Contents . xxxii What's New in This Manual . xxxiv Technical or Customer Support . xxxv Supported Processors . xxxvi Product Information . xxxvi MyAnalog.com . xxxvii Processor Product Information . xxxvii Related Documents . xxxviii Online Technical Documentation . xxxix Printed Manuals . xli Conventions . xliii INTRODUCTION Design Advantages . 1-1 Architectural Overview . 1-6 Processor Core . 1-7 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference iii Contents Processor Peripherals . 1-7 I/O Processor . 1-7 Digital Audio Interface (DAI) . 1-9 Digital Peripheral Interface (DPI) . 1-10 Development Tools . 1-10 Differences From Previous Processors . 1-11 I/O Architecture Enhancements . 1-11 Instruction Set Enhancements . 1-12 I/O PROCESSOR General Procedure for Configuring DMA . 2-2 Core Access to IOP Registers . 2-3 Configuring IOP/Core Interaction . 2-6 Interrupt-Driven I/O . 2-6 Interrupt Latency in Interrupt-Driven Transfers . 2-11 Polling/Status-Driven I/O . 2-12 DMA Controller Operation . 2-13 Chaining DMA Processes . 2-14 Transfer Control Block Chain Loading (TCB) . 2-16 Setting Up DMA Channel Allocation and Priorities . 2-18 Managing DMA Channel Priority . 2-19 DMA Bus Arbitration . 2-20 Setting Up DMA Parameter Registers . 2-24 DMA Transfer Direction . 2-24 Data Buffer Registers . 2-25 iv ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents Port, Buffer, and DMA Control Registers . 2-26 Addressing . 2-29 External Port DMA . 2-35 Setting Up and Starting Chained DMA . 2-36 Delay Line DMA . 2-38 Serial Port DMA . 2-40 Setting Up and Starting Chained DMA . 2-40 Inserting a TCB in an Active Chain . 2-41 Serial Peripheral Interface DMA . 2-42 Setting Up and Starting Chained DMA over the SPI . 2-42 UART DMA . 2-44 Notes On Using DMA With the UART . 2-47 Memory-to-Memory DMA . 2-48 Summary . 2-48 Programming Example . 2-49 EXTERNAL PORT External Memory Interface . 3-2 External Memory Interface on the ADSP-2137x Processors . 3-3 Direct Execution of Instructions From External Memory . 3-3 Throughput and Instruction Execution Rate . 3-3 Location of Interrupt Vector Table (IVT) . 3-4 Instruction Cache . 3-5 Instruction Storage and Packing . 3-9 Register Configurations for External Memory Execution . 3-15 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference v Contents EMI Registers and Signals . 3-16 External Port Arbitration Logic . 3-18 Channel Freezing . 3-18 Managing Data Paths . 3-18 External Memory Interface Pins . 3-19 Asynchronous Memory Interface . 3-20 AMI Timing Control . 3-21 Wait States . 3-21 Bus Idle Cycles . 3-22 Bus Hold Cycles . 3-23 Setting AMI Modes . 3-24 External Memory Reads . 3-25 Data Packing . 3-25 External Memory Writes . 3-26 Data Packing . 3-27 Read/Write Throughput . 3-28 External Access Addressing . 3-28 External Port DMA . 3-30 Booting Through the AMI . 3-30 SDRAM Controller . 3-30 Definition of Terms . 3-31 Timing External Memory Accesses . 3-36 Parallel Connection of SDRAMs . 3-39 SDRAM Control Register (SDCTL) . 3-39 vi ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents SDRAM Control Status Register (SDSTAT) . 3-49 SDRAM Refresh Rate Control Register (SDRRC) . 3-49 SDRAM Initialization . 3-51 SDRAM Address Mapping . 3-51 SDRAM Controller Address Mapping . 3-58 SDC Operation . 3-58 Single Bank Operation . 3-60 Multibank Operation (ADSP-2137x Processors) . 3-60 Data Mask (DQM) . 3-61 SDC Configuration . 3-61 SDC Commands . 3-63 Load Mode Register . 3-64 Single Bank Activation . 3-65 Multibank Activation (ADSP-2137x Processors) . 3-66 Single Precharge (ADSP-2137x Processors) . 3-66 Precharge All . 3-66 Read/Write . 3-67 Read/Write (ADSP-2137x Processors) . 3-69 Burst Stop (ADSP-2137x Processors) . 3-69 Auto-Refresh . 3-70 Self-Refresh Mode . 3-70 No Operation/Command Inhibit . 3-71 Changing System Clock During Runtime . 3-73 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference vii Contents SDRAM Timing . 3-74 SDRAM Read Optimization . 3-75 External Memory Access Restrictions . 3-78 Shared Memory Interface . 3-79 Shared Memory Bus Arbitration . 3-79 Bus Arbitration Protocol . 3-82 Bus Arbitration Priority (RPBA) . 3-86 Bus Mastership Time-out . 3-87 Bus Synchronization After Reset . 3-88 Bus Synchronization Notes . 3-91 Bus Lock and Semaphores . 3-92 Shared Memory Interface Status . 3-93 Shared Memory and the SDRAM Controller . 3-94 Shared Memory Booting . 3-94 DIGITAL AUDIO/DIGITAL PERIPHERAL INTERFACES Structure of the Interfaces . 4-2 DAI/DPI System Design . 4-3 Signal Routing Units . 4-8 Connecting Peripherals . 4-8 Pin Interface . 4-10 Pin Buffers as Signal Output Pins . 4-11 Pin Buffers as Signal Input Pins . 4-12 Bidirectional Pin Buffers . 4-13 viii ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents Making Connections in the SRUs . 4-15 DAI/SRU1 Connection Groups . 4-18 Group A Connections-Clock Signals . 4-19 Group B Connections-Data Signals . 4-25 Group C Connections-Frame Sync Signals . 4-31 Group D Connections-Pin Signal Assignments . 4-36 Group E Connections-Interrupts and Miscellaneous Signals . 4-43 Group F-Pin Enable Signals . 4-47 DPI/SRU2 Connection Groups . 4-51 Group A Connections-Input Routing Signals . 4-52 Group B Connections-Pin Assignment Signals . 4-56 Group C Connections-Pin Enable Signals . 4-60 General-Purpose I/O (GPIO) and Flags . 4-64 DAI GPIO and Flags . 4-64 DPI GPIO and Flags . 4-65 Miscellaneous Signals . 4-65 DAI/DPI Interrupt Controller . 4-65 Relationship to the Core . 4-65 DAI Interrupts . 4-66 DPI Interrupts . 4-67 High and Low Priority Latches . 4-69 Rising and Falling Edge Masks . 4-70 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference ix Contents Configuring Peripherals Using SRU1 . 4-71 Configuring the SPORTs . 4-71 Configuring the PCGs . 4-72 Configuring Peripherals Using SRU2 . 4-72 Configuring the SPI . 4-72 Choosing the Pin Enable for the SPI Clock . 4-72 Configuring the Two Wire Interface . 4-73 Using the SRU() Macro to Configure the DAI . 4-76 SERIAL PORTS Features . 5-2 Operation Modes . 5-3 Serial Port Signals . 5-5 Serial Port Signal Sensitivity . 5-9 SPORT Operation Modes . 5-10 Standard DSP Serial Mode . 5-12 Standard DSP Serial Mode Control Bits . 5-13 Clocking Options . 5-13 Frame Sync Options . 5-13 Data Formatting . 5-14 Data Transfers . 5-15 Status Information . 5-15 Left-Justified Sample Pair Mode . 5-16 Setting the Internal Serial Clock and Frame Sync Rates . 5-17 x ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents Left-Justified Sample Pair Mode Control Bits . 5-17 Setting Word Length (SLEN) . 5-17 Enabling SPORT Master Mode (MSTR) . 5-18 Selecting Transmit and Receive Channel Order (FRFS) . 5-18 Selecting Frame Sync Options (DIFS) . 5-18 Enabling SPORT DMA (SDEN) . 5-19 I2S Mode . 5-20 Setting the Internal Serial Clock and Frame Sync Rates . 5-21 I2S Mode Control Bits . 5-21 Setting Word Length (SLEN) . 5-22 Enabling SPORT Master Mode (MSTR) . 5-23 Selecting Transmit and Receive Channel Order (FRFS) . 5-23 Selecting Frame Sync Options (DIFS) . 5-23 Enabling SPORT DMA (SDEN) . 5-24 Multichannel Operation . 5-25 Frame Syncs in Multichannel Mode . 5-28 Multichannel Mode Control Bits . 5-29 Packed I2S Mode . 5-33 Programming Packed I2S Mode . 5-34 SPORT Loopback . 5-35 Clock Signal Options . 5-36 Frame Sync Options . 5-37 Framed Versus Unframed Frame Syncs . 5-37 Internal Versus External Frame Syncs . 5-38 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xi Contents Active Low Versus Active High Frame Syncs . 5-39 Sampling Edge for Data and Frame Syncs . 5-39 Early Versus Late Frame Syncs . 5-40 Data-Independent Frame Syncs . 5-41 Frame Sync Error Detection . 5-42 Data Word Formats . 5-43 Word Length . 5-43 Endian Format . 5-45 Data Packing and Unpacking . 5-45 Data Type . 5-46 Companding . 5-47 SPORT Control Registers and Data Buffers . 5-49 Register Writes and Effect Latency . 5-58 Serial Port Control Registers (SPCTLx) . 5-59 Transmit and Receive Data Buffers (TXSPxA/B, RXSPxA/B) . 5-67 Clock and Frame Sync Frequency Registers (DIVx) . 5-69 SPORT Reset . 5-71 SPORT Interrupts . 5-72 Moving Data Between SPORTs and Internal Memory . 5-73 DMA Block Transfers . 5-73 Setting Up DMA on SPORT Channels . 5-75 SPORT DMA Parameter Registers . 5-76 SPORT DMA Chaining . 5-81 Single Word Transfers . 5-81 xii ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents SPORT Programming Examples . 5-82 SERIAL PERIPHERAL INTERFACE PORTS Functional Description . 6-2 SPI Interface Signals . 6-4 SPI Clock Signal (SPICLK) . 6-4 SPICLK Timing . 6-5 SPI Slave Select Input (SPIDS) . 6-6 SPI Flag Signals (SPIFLG3-0) . 6-6 Master Out Slave In (MOSI) . 6-7 Master In Slave Out (MISO) . 6-7 SPI General Operations . 6-8 SPI Enable . 6-9 Open Drain Mode (OPD) . 6-9 Master Mode Operation . 6-10 Slave Mode Operation . 6-11 Multimaster Operation . 6-12 SPI Data Transfer Operations . 6-13 SPI Operation Using the Core . 6-13 SPI Operation Using DMA . 6-14 Master Mode DMA Operation . 6-15 Slave Mode DMA Operation . 6-19 Changing SPI Configuration . 6-21 Switching From Transmit To Receive DMA . 6-23 Switching From Receive to Transmit DMA . 6-24 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xiii Contents DMA Error Interrupts . 6-25 DMA Chaining . 6-27 SPI Transfer Formats . 6-27 Beginning and Ending an SPI Transfer . 6-29 SPI Word Lengths . 6-31 8-Bit Word Lengths . 6-31 16-Bit Word Lengths . 6-32 32-Bit Word Lengths . 6-32 Packing . 6-32 SPI Interrupts . 6-33 Error Signals and Flags . 6-35 Mode Fault Error (MME) . 6-35 Transmission Error Bit (TUNF) . 6-37 Reception Error Bit (ROVF) . 6-37 Transmit Collision Error Bit (TXCOL) . 6-37 Programming Notes . 6-38 Routing SPI Signals Using The DPI . 6-38 Programming Examples . 6-38 INPUT DATA PORT Serial Inputs . 7-3 Parallel Data Acquisition Port (PDAP) . 7-8 Masking . 7-9 Packing Unit . 7-9 Packing Mode 11 . 7-9 xiv ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents Packing Mode 10 . 7-10 Packing Mode 01 . 7-11 Packing Mode 00 . 7-11 Clocking Edge Selection . 7-12 Hold Input . 7-12 PDAP Strobe . 7-14 FIFO Control and Status . 7-15 FIFO to Memory Data Transfer . 7-16 IDP Transfers Using the Core . 7-17 Starting an Interrupt-Driven Transfer . 7-18 Core Transfer Notes . 7-19 IDP Transfers Using DMA . 7-20 Simple DMA . 7-20 Ping-Pong DMA . 7-22 DMA Transfer Notes . 7-25 DMA Channel Parameter Registers . 7-27 IDP (DAI) Interrupt Service Routines for DMAs . 7-28 FIFO Overflow . 7-30 Input Data Port Programming Example . 7-31 PULSE WIDTH MODULATION PWM Implementation . 8-1 PWM Waveforms . 8-1 Edge-Aligned Mode . 8-2 Center-Aligned Mode . 8-3 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xv Contents Switching Frequencies . 8-5 Dead Time . 8-6 Duty Cycles . 8-7 Duty Cycles and Dead Time . 8-8 Over Modulation . 8-12 Update Modes . 8-15 Single Update . 8-15 Double Update . 8-15 Configurable Polarity . 8-15 PWM Pins and Signals . 8-16 Crossover . 8-16 PWM Accuracy . 8-17 PWM Registers . 8-18 Duty Cycles . 8-19 Output Enable . 8-20 Programming Example . 8-21 S/PDIF TRANSMITTER/RECEIVER AES3/SPDIF Stream Format . 9-2 Subframe Format . 9-3 Channel Coding . 9-5 Preambles . 9-6 S/PDIF Transmitter . 9-7 Channel Status . 9-9 SRU1 Signals for the S/PDIF Transmitter . 9-10 xvi ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents S/PDIF Transmitter Registers . 9-12 Modes of Operation . 9-12 Standalone Mode . 9-13 Structure of the Serial Input Data . 9-14 S/PDIF Receiver . 9-16 S/PDIF Receiver Registers . 9-17 SRU1 Receiver Signals . 9-18 Phase-Locked Loop . 9-19 Channel Status Decoding . 9-19 Compressed or Non-Linear Audio Data . 9-20 Emphasized Audio Data . 9-21 Single-Channel, Double-Sampling Frequency Mode . 9-21 Error Handling . 9-22 Interrupts . 9-24 DAI Programming Examples . 9-24 S/PDIF Transmitter Programming Guidelines . 9-24 Control Register . 9-24 SRU1 Programming for Input and Output Streams . 9-25 Control Register Programming and Enable . 9-25 S/PDIF Receiver Programming Guidelines . 9-25 Control Register . 9-25 SRU1 Programming . 9-26 Control Register Programming . 9-26 Receiver Locking . 9-26 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xvii Contents Status Bits . 9-26 Interrupted Data Streams on the Receiver . 9-27 ASYNCHRONOUS SAMPLE RATE CONVERTER Theory of Operation . 10-2 Conceptual Model . 10-4 Hardware Model . 10-7 Sample Rate Converter Architecture . 10-8 Group Delay . 10-12 SRC Operation . 10-12 Enabling the SRC . 10-13 Serial Data Ports . 10-13 Data Format . 10-13 Time-Division Multiplex (TDM) Output Mode . 10-15 TDM Input Mode . 10-16 Matched-Phase Mode . 10-16 Bypass Mode . 10-18 De-Emphasis Filter . 10-18 Mute Control . 10-19 Soft Mute . 10-20 Hard Mute . 10-20 Auto Mute . 10-20 SRC Registers . 10-21 Programming the SRC Module . 10-22 SRC Control Register Programming . 10-22 xviii ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents SRU Programming . 10-22 SRC Mute-Out Interrupt . 10-23 Sample Rate Ratio . 10-23 Programming Summary . 10-23 UART PORT CONTROLLER Serial Communications . 11-2 UART Control and Status Registers . 11-3 UARTxLCR Registers . 11-3 UARTxLSR Register . 11-4 UARTxTHR Register . 11-4 UARTxRBR Register . 11-5 UARTxIER Register . 11-7 UARTxIIR Register . 11-9 UARTxDLL and UARTxDLH Registers . 11-11 UARTxSCR Register . 11-12 UARTxMODE Register . 11-13 I/O Mode . 11-13 Packing Mode . 11-15 TWO WIRE INTERFACE CONTROLLER Overview . 12-1 Architecture . 12-2 Register Descriptions . 12-4 TWI Master Internal Time Register . 12-4 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xix Contents TWIDIV Register . 12-5 Slave Mode Control Register . 12-5 Slave Mode Address Register . 12-6 Slave Mode Status Register . 12-6 Master Mode Control Register . 12-6 Master Mode Address Register . 12-6 Master Mode Status Register . 12-7 FIFO Control Register . 12-7 FIFO Status Register . 12-7 Interrupt Source Register . 12-7 Interrupt Enable Register . 12-8 8-Bit Transmit FIFO Register . 12-8 16-Bit Transmit FIFO Register . 12-8 8-Bit Receive FIFO Register . 12-9 16-Bit Receive FIFO Register . 12-10 Data Transfer Mechanics . 12-10 Clock Generation and Synchronization . 12-11 Bus Arbitration . 12-12 Start and Stop Conditions . 12-12 General Call Support . 12-14 Fast Mode . 12-14 Programming Examples . 12-15 General Setup . 12-15 Slave Mode . 12-15 xx ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents Master Mode Clock Setup . 12-17 Master Mode Transmit . 12-17 Master Mode Receive . 12-18 Repeated Start Condition . 12-19 Transmit/Receive Repeated Start Sequence . 12-19 Receive/Transmit Repeated Start Sequence . 12-21 Electrical Specifications . 12-22 PRECISION CLOCK GENERATORS Clock Outputs . 13-3 Frame Sync Outputs . 13-4 Normal Mode . 13-5 Bypass Mode . 13-6 Frame Sync Output Synchronization With an External Clock . 13-7 Frame Sync . 13-8 Phase Shift . 13-9 Phase Shift Settings . 13-10 Pulse Width . 13-10 Bypass Mode . 13-12 Bypass as a Pass Through . 13-12 Bypass as a One-Shot . 13-13 Programming Examples . 13-14 PCG Setup for I2S or Left-Justified DAI . 13-15 Clock and Frame Sync Divisors PCG Channel B . 13-20 PCG Channel A and B Output Example . 13-23 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xxi Contents SYSTEM DESIGN Processor Pin Descriptions . 14-2 Pin Multiplexing . 14-2 Choosing EP Data Mode . 14-6 Interrupt and Timer Pins . 14-8 Core-Based Flag Pins . 14-8 Programming Flags . 14-9 RESETOUT/CLKOUT/RUNRSTIN . 14-12 JTAG Interface Pins . 14-12 Clock Derivation . 14-13 Power Management Control Register . 14-14 PLL Programming Examples . 14-16 Phase-Locked Loop Startup . 14-19 RESET and CLKIN . 14-20 Running Reset (ADSP-2137x) . 14-22 System Design Considerations . 14-23 Running Reset Control Register (RUNRSTCTL) . 14-25 Programming The RUNRSTCTL Register . 14-26 Reset Generators . 14-27 Timing Specifications . 14-28 Input Synchronization Delay . 14-32 Conditioning Input Signals . 14-32 RESET Input Hysteresis . 14-33 xxii ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents Designing for High Frequency Operation . 14-33 Clock Specifications and Jitter . 14-33 Other Recommendations and Suggestions . 14-34 Decoupling Capacitors and Ground Planes . 14-35 Oscilloscope Probes . 14-35 Recommended Reading . 14-36 Booting . 14-37 External Port Booting . 14-39 Booting Through the AMI . 14-39 Shared Memory Booting . 14-40 SPI Port Booting . 14-42 32-Bit SPI Host Boot . 14-43 16-Bit SPI Host Boot . 14-44 8-Bit SPI Host Boot . 14-46 Slave Boot Mode . 14-47 Master Boot . 14-48 Booting From an SPI Flash . 14-51 Booting From an SPI PROM (16-Bit address) . 14-52 Booting From an SPI Host Processor . 14-52 Data Delays, Latencies, and Throughput . 14-52 Execution Stalls . 14-53 DAG Stalls . 14-54 Memory Stalls . 14-54 IOP Register Stalls . 14-55 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xxiii Contents DMA Stalls . 14-56 IOP Buffer Stalls . 14-56 REGISTER REFERENCE I/O Processor Registers . A-2 Notes on Reading Register Drawings . A-3 System Control Register (SYSCTL) . A-5 System Status Register (SYSTAT) . A-9 External Port Registers . A-10 External Port Control Register (EPCTL) . A-10 External Port DMA Control Registers (DMACx) . A-14 AMI Control Registers (AMICTLx) . A-17 AMI Status Register (AMISTAT) . A-20 SDRAM Control Register (SDCTL) . A-21 SDRAM Control Status Register (SDSTAT) . A-26 SDRAM Refresh Rate Control Register (SDRRC) . A-26 Memory-to-Memory DMA Register . A-28 Serial Port Registers . A-29 SPORT Serial Control Registers (SPCTLx) . A-29 SPORT Multichannel Control Registers (SPMCTLx) . A-40 SPORT Transmit Buffer Registers (TXSPx) . A-43 SPORT Receive Buffer Registers (RXSPx) . A-44 SPORT Divisor Registers (DIVx) . A-44 SPORT Count Registers (SPCNTx) . A-45 SPORT Active Channel Select Registers (SPxCSy) . A-46 xxiv ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents SPORT Compand Registers (SPxCCSy) . A-47 SPORT Error Control Register (SPERRCTLx) . A-48 SPORT Error Status Register (SPERRSTAT) . A-49 SPORT DMA Index Registers (IISPx) . A-50 SPORT DMA Modifier Registers (IMSPx) . A-50 SPORT DMA Count Registers (CSPx) . A-51 SPORT Chain Pointer Registers (CPSPx) . A-51 Serial Peripheral Interface Registers . A-52 SPI Control Registers (SPICTL, SPICTLB) . A-52 SPI Port Status (SPISTAT, SPISTATB) Registers . A-56 SPI Port Flags Registers (SPIFLG, SPIFLGB) . A-58 SPI Receive Buffer Registers (RXSPI, RXSPIB) . A-59 RXSPI Shadow Registers (RXSPI_SHADOW, RXSPIB_SHADOW) . A-59 SPI Transmit Buffer Registers (TXSPI, TXSPIB) . A-59 SPI Baud Rate Registers (SPIBAUD, SPIBAUDB) . A-60 SPI DMA Registers . A-61 SPI DMA Configuration Registers (SPIDMAC, SPIDMACB) . A-62 SPI DMA Start Address Registers (IISPI, IISPIB) . A-64 SPI DMA Address Modify Registers (IMSPI, IMSPIB) . A-64 SPI DMA Word Count Registers (CSPI, CSPIB) . A-64 SPI DMA Chain Pointer Registers (CPSPI, CPSPIB) . A-65 Input Data Port Registers . A-65 Input Data Port Control Register 0 (IDP_CTL0) . A-66 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xxv Contents Input Data Port Control Register 1 (IDP_CTL1) . A-68 Input Data Port FIFO Register (IDP_FIFO) . A-69 Input Data Port DMA Control Registers . A-70 IDP_DMA_Ix . A-70 IDP_DMA_Mx . A-71 IDP_DMA_Cx . A-71 Input Data Port Ping-Pong DMA Registers . A-72 IDP Ping-Pong Index Registers (IDP_DMA_IxA) . A-72 IDP Ping-Pong Count Registers (IDP_DMA_PCx) . A-73 Parallel Data Acquisition Port Control Register (IDP_PP_CTL) . A-74 Pulse Width Modulation Registers . A-78 PWM Global Control Register (PWMGCTL) . A-78 PWM Global Status Register (PWMGSTAT) . A-79 PWM Control Register (PWMCTLx) . A-80 PWM Status Registers (PWMSTATx) . A-81 PWM Period Registers (PWMPERIODx) . A-81 PWM Output Disable Registers (PWMSEGx) . A-82 PWM Polarity Select Registers (PWMPOLx) . A-83 PWM Channel Duty Control Registers (PWMAx, PWMBx) . A-84 PWM Channel Low Duty Control Registers (PWMALx, PWMBLx) . A-84 PWM Dead Time Registers (PWMDTx) . A-85 xxvi ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents Sony/Philips Digital Interface Registers . A-86 Transmitter Control Register (DITCTL) . A-86 Left Channel Status for Subframe A Registers (DITCHANAx) . A-89 Right Channel Status for Subframe B Registers (DITCHANBx) . A-90 User Bits Buffer Registers for Subframe A Registers (DITUSRBITAx) . A-90 User Bits Buffer Registers for Subframe B Registers (DITUSRBITBx) . A-91 Receiver Control Register (DIRCTL) . A-92 Receiver Status Register (DIRSTAT) . A-94 Left Channel Status for Subframe A Register (DIRCHANL) . A-96 Right Channel Status for Subframe B Register (DIRCHANR) . A-96 Sample Rate Converter Registers . A-97 SRC Control Registers (SRCCTLx) . A-97 SRC Mute Register (SRCMUTE) . A-107 SRC Ratio Registers (SRCRATx) . A-108 DAI/DPI Registers . A-109 Digital Audio Interface Status Register (DAI_STAT) . A-109 DAI Resistor Pull-up Enable Register (DAI_PIN_PULLUP) . A-111 DAI Pin Buffer Status Register (DAI_PIN_STAT) . A-112 DAI Interrupt Controller Registers . A-112 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xxvii Contents DPI Resistor Pull-up Enable Register (DPI_PIN_PULLUP) . A-115 DPI Pin Buffer Status Register (DPI_PIN_STAT) . A-116 DPI Interrupt Controller Registers . A-116 UART Control and Status Registers . A-118 Line Control Registers (UARTxLCR) . A-118 Line Status Registers (UARTxLSR) . A-120 Transmit Hold Registers (UARTxTHR) . A-121 Receive Buffer Registers (UARTxRBR) . A-122 Interrupt Enable Registers (UARTxIER) . A-123 Interrupt Identification Registers (UARTxIIR) . A-124 Divisor Latch Registers (UARTxDLL, UARTxDLH) . A-125 Scratch Registers (UARTxSCR) . A-126 Mode Registers (UARTxMODE) . A-126 UART DMA Registers . A-127 DMA Control Registers (UARTxTXCTL, UARTxRXCTL) . A-128 DMA Status Registers (UARTxTXSTAT, UARTxRXSTAT) . A-129 Two Wire Interface Registers . A-130 Master Internal Time Register (TWIMITR) . A-131 Clock Divider Register (TWIDIV) . A-132 Slave Mode Control Register (TWISCTL) . A-133 Slave Address Register (TWISADDR) . A-135 Slave Status Register (TWISSTAT) . A-135 xxviii ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Contents Master Control Register (TWIMCTL) . A-136 Master Address Register (TWIMADDR) . A-139 Master Status Register (TWIMSTAT) . A-140 FIFO Control Register (TWIFIFOCTL) . A-143 FIFO Status Register (TWIFIFOSTAT) . A-145 Interrupt Source Register (TWIIRPTL) . A-147 Interrupt Enable Register (TWIIMASK) . A-150 8-Bit Transmit FIFO Register (TXTWI8) . A-152 16-Bit Transmit FIFO Register (TXTWI16 TXTWI16) . A-153 8-Bit Receive FIFO Register (RXTWI8) . A-154 16-Bit Receive FIFO Register (RXTWI16 RXTWI16) . A-154 Precision Clock Generator Registers . A-155 Control Registers (PCG_CTLxx) . A-155 PCG Pulse Width Registers . A-158 PCG Frame Synchronization Registers (PCG_SYNCx) . A-160 Peripheral Interrupt Priority Control Registers . A-164 Peripheral Interrupt Priority Control Registers (PICRx) . A-164 Peripheral Interrupt Priority0 Control Register (PICR0) . A-167 Peripheral Interrupt Priority1 Control Register (PICR1) . A-168 Peripheral Interrupt Priority2 Control Register (PICR2) . A-169 Peripheral Interrupt Priority3 Control Register (PICR3) . A-170 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xxix Contents Power Management Control Register (PMCTL) . A-170 Hardware Breakpoint Control Register . A-175 Enhanced Emulation Status Register . A-179 INTERRUPTS Interrupt Vector Tables . B-1 Interrupt Priorities . B-4 Interrupt Registers . B-6 Interrupt Register (LIRPTL) . B-6 Interrupt Latch Register (IRPTL) . B-13 Interrupt Mask Register (IMASK) . B-18 Interrupt Mask Pointer Register (IMASKP) . B-22 INDEX xxx ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference PREFACE Thank you for purchasing and developing systems using the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x SHARC® processors from Analog Devices. Purpose of This Manual The ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference contains information about the architecture and assembly language for ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x. These are 32-bit, fixed- and floating-point digital signal processors from Analog Devices for use in computing, communications, and consumer applications. The manual provides information on the processor's I/O architecture and the operation of the peripherals associated with each model. Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts (such as the appropriate hardware reference manuals and data sheets) that describe your target architecture. ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xxxi Manual Contents Manual Contents The manual consists of: · Chapter 1, "Introduction" Provides an architectural overview of the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x SHARC processors. · Chapter 2, "I/O Processor" Describes ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors input/output processor architecture and direct memory accesses (DMA) for the peripherals that have this feature. · Chapter 3, "External Port" Describes the operation of the asynchronous memory interface (AMI). · Chapter 4, "Digital Audio/Digital Peripheral Interfaces" Provides information about the digital applications interface (DAI) which allows you to attach an arbitrary number and a variety of peripherals to the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors while retaining high levels of compatibility. · Chapter 5, "Serial Ports" Describes the up to eight dual data line serial ports. Each SPORT contains a clock, a frame sync, and two data lines that can be configured as either a receiver or transmitter pair. · Chapter 6, "Serial Peripheral Interface Ports" Describes the operation of the SPI port. SPI devices communicate using a master-slave relationship and can achieve high data transfer rates because they can operate in full-duplex mode. · Chapter 7, "Input Data Port" Discusses the function of the input data port (IDP) which provides a low overhead method of routing signal routing unit (SRU) signals back to the core's memory. xxxii ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Preface · Chapter 8, "Pulse Width Modulation" Describes the implementation and use of the pulse width modulation module which provides a technique for controlling analog circuits with the microprocessor's digital outputs. · Chapter 9, "S/PDIF Transmitter/Receiver" Provides information on the use of the Sony/Philips Digital Interface which is a standard audio file transfer format that allows the transfer of digital audio signals from one device to another without having to be converted to an analog signal. · Chapter 10, "Asynchronous Sample Rate Converter" Provides information on the sample rate converter module. This module performs synchronous or asynchronous sample rate conversions across independent stereo channels, without using any internal processor resources. · Chapter 11, "UART Port Controller" Describes the operation of the Universal Asynchronous Receiver/Transmitter (UART) which is a full-duplex peripheral compatible with PC-style industry-standard UART. · Chapter 12, "Two Wire Interface Controller" The two wire interface is fully compatible with the widely used I2C bus standard. It is designed with a high level of functionality and is compatible with multi-master, multi-slave bus configurations. · Chapter 13, "Precision Clock Generators" Details the precision clock generators (PCG) each of which generates a pair of signals derived from a clock input signal. · Chapter 14, "System Design" Describes system design features of the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors. These include power, reset, clock, JTAG, and booting, as well as pin descriptions and other system level information. ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xxxiii What's New in This Manual · Appendix A, "Register Reference" Provides a graphical presentation of all registers and describes the bit usage in each register. · Appendix B, "Interrupts" Provides a complete listing of the registers that are used to configure and control interrupts. This hardware reference is a companion document to the ADSP-2136x/ADSP-2137x SHARC Processor Programming Reference. The programming reference provides information relating to the processor core, such as processing elements, internal memory, and program sequencing. It also provides programming specific information, such as complete descriptions of the ADSP-21xxx instruction set and the compute operations, including their assembly language syntax and opcode fields. What's New in This Manual Revision 1.0 of the ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference is the first general release of this manual. The following changes should be noted. · In the preliminary version this manual was titled ADSP-2136x SHARC Processor Hardware reference for the ADSP-21367/8/9 ADSP-21367/8/9 Processors. The title change to ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference was done to reflect the fact that the ADSP-21368 ADSP-21368 processor contains the super set of features of the ADSP-21367 ADSP-21367 and ADSP-21369 ADSP-21369 models as well as the new ADSP-21371 ADSP-21371 and ADSP-21375 ADSP-21375 models. · This version of the manual contains information about the ADSP-21371 ADSP-21371 and ADSP-21375 ADSP-21375 SHARC processors. These new models contain the same core as the ADSP-21367/8/9 ADSP-21367/8/9 processors xxxiv ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Preface and as such are completely code compatible. The primary differences in these new models is the ability to execute programs from external memory and a running reset feature. For more information on these topics, see "Direct Execution of Instructions From External Memory" on page 3-3 and "Running Reset (ADSP-2137x)" on page 14-22. Technical or Customer Support You can reach Analog Devices, Inc. Customer Support in the following ways: · Visit the Embedded Processing and DSP products Web site at http://www.analog.com/processors/manuals · E-mail tools questions to processor.tools.support@analog.com · E-mail processor questions to processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.com (China support) · Phone questions to 1-800-ANALOGD 1-800-ANALOGD · Contact your Analog Devices, Inc. local sales office or authorized distributor · Send questions by mail to: Analog Devices, Inc. One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 USA ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xxxv Supported Processors Supported Processors The following is the list of Analog Devices, Inc. processors supported in VisualDSP+®. Blackfin® (ADSP-BFxxx) Processors The name Blackfin refers to a family of 16-bit, embedded processors. VisualDSP+ currently supports the following Blackfin families: ADSP-BF53x, ADSP-BF54x, and ADSP-BF56x. SHARC (ADSP-21xxx) Processors The name SHARC refers to a family of high-performance, 32-bit, floating-point processors that can be used in speech, sound, graphics, and imaging applications. VisualDSP+ currently supports the following SHARC families: ADSP-2106x, ADSP-2116x, ADSP-2126x, ADSP-2136x, and ADSP-2137x. TigerSHARC® (ADSP-TSxxx) Processors The name TigerSHARC refers to a family of floating-point and fixed-point (8-bit, 16-bit, and 32-bit) processors. VisualDSP+ currently supports the following TigerSHARC families: ADSP-TS101 ADSP-TS101 and ADSP-TS20x. Product Information You can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from the printed publications (manuals). Analog Devices is online at www.analog.com. Our Web site provides information about a broad range of products-analog integrated circuits, amplifiers, converters, and digital signal processors. xxxvi ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Preface MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more. MyAnalog.com Registration Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com. Registration takes about five minutes and serves as a means to select the information you want to receive. If you are already a registered user, just log on. Your user name is your e-mail address. Processor Product Information For information on embedded processors and DSPs, visit our Web site at www.analog.com/processors, which provides access to technical publications, data sheets, application notes, product overviews, and product announcements. You may also obtain additional information about Analog Devices and its products in any of the following ways. · E-mail processor questions to processor.support@analog.com (World wide support) processor.europe@analog.com (Europe support) processor.china@analog.com (China support) ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xxxvii Product Information · Fax questions or requests for information to 1-781-461-3010 (North America) +49-89-76903-157 (Europe) · Access the FTP Web site at ftp ftp.analog.com or ftp://137.71.25.69 ftp://ftp.analog.com Related Documents The following publications that describe the ADSP-2136x SHARC processors (and related processors) can be ordered from any Analog Devices sales office: · ADSP-21362 ADSP-21362 SHARC Processor Data Sheet · ADSP-21363 ADSP-21363 SHARC Processor Data Sheet · ADSP-21364 ADSP-21364 SHARC Processor Data Sheet · ADSP-21365 ADSP-21365 SHARC Processor Data Sheet · ADSP-21366 ADSP-21366 SHARC Processor Data Sheet · ADSP-21367/ADSP-21368/ADSP-21369 ADSP-21367/ADSP-21368/ADSP-21369 SHARC Processor Data Sheet · ADSP-21371 ADSP-21371 SHARC Processor Preliminary Data Sheet · ADSP-21375 ADSP-21375 SHARC Processor Preliminary Data Sheet · ADSP-2136x/ADSP-2137x SHARC Processor Programming Reference xxxviii ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Preface For information on product related development software and Analog Devices processors, see these publications: · VisualDSP+ User's Guide · VisualDSP+ C/C+ Compiler and Library Manual for SHARC Processors · VisualDSP+ Assembler and Preprocessor Manual · VisualDSP+ Linker and Utilities Manual · VisualDSP+ Kernel (VDK) User's Guide Visit the Technical Library Web site to access all processor and tools manuals and data sheets: http://www.analog.com/processors/manuals Online Technical Documentation Online documentation comprises the VisualDSP+ Help system, software tools manuals, hardware tools manuals, processor manuals, the Dinkum Abridged C+ library, and Flexible License Manager (FlexLM) network license manager software documentation. You can easily search across the entire VisualDSP+ documentation set for any topic of interest. For easy printing, supplementary .PDF files of most manuals are also provided. Each documentation file type is described as follows. If documentation is not installed on your system as part of the software installation, you can add it from the VisualDSP+ CD-ROM at any time by running the Tools installation. Access the online documentation from the VisualDSP+ environment, Windows® Explorer, or the Analog Devices Web site. ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xxxix Product Information File Description .CHM Help system files and manuals in Help format .HTM or .HTML Dinkum Abridged C+ library and FlexLM network license manager software documentation. Viewing and printing the .HTML files requires a browser, such as Internet Explorer 4.0 (or higher). .PDF VisualDSP+ and processor manuals in Portable Documentation Format (PDF). Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher). Accessing Documentation From VisualDSP+ From the VisualDSP+ environment: · Access VisualDSP+ online Help from the Help menu's Contents, Search, and Index commands. · Open online Help from context-sensitive user interface items (toolbar buttons, menu commands, and windows). Accessing Documentation From Windows In addition to any shortcuts you may have constructed, there are many ways to open VisualDSP+ online Help or the supplementary documentation from Windows. Help system files (.CHM) are located in the Help folder, and .PDF files are located in the Docs folder of your VisualDSP+ installation CD-ROM. The Docs folder also contains the Dinkum Abridged C+ library and the FlexLM network license manager software documentation. Using Windows Explorer · Double-click the vdsp-help.chm file, which is the master Help system, to access all the other .CHM files. · Double-click any file that is part of the VisualDSP+ documentation set. xl ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Preface Using the Windows Start Button · Access VisualDSP+ online Help by clicking the Start button and choosing Programs, Analog Devices, VisualDSP+, and VisualDSP+ Documentation. · Access the .PDF files by clicking the Start button and choosing Programs, Analog Devices, VisualDSP+, Documentation for Printing, and the name of the book. Accessing Documentation From the Web Download manuals at the following Web site: Select a processor family and book title. Download archive (.ZIP) files, one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files. Printed Manuals For general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD 1-800-ANALOGD (1-800-262-5643) and follow the prompts. VisualDSP+ Documentation Set To purchase VisualDSP+ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit. If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. For information on our distributors, log onto http://www.analog.com/salesdir/continent.asp. ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xli Product Information Hardware Tools Manuals To purchase EZ-KIT Lite® and In-Circuit Emulator (ICE) manuals, call 1-603-883-2430. The manuals may be ordered by title or by product number located on the back cover of each manual. Processor Manuals Hardware reference and instruction set reference manuals may be ordered through the Literature Center at 1-800-ANALOGD 1-800-ANALOGD (1-800-262-5643), or downloaded from the Analog Devices Web site. Manuals may be ordered by title or by product number located on the back cover of each manual. Data Sheets All data sheets (preliminary and production) may be downloaded from the Analog Devices Web site. Only production (final) data sheets (Rev. 0, A, B, C, and so on) can be obtained from the Literature Center at 1-800-ANALOGD 1-800-ANALOGD (1-800-262-5643); they also can be downloaded from the Web site. To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. If the data sheet you want is not listed, check for it on the Web site. xlii ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Preface Conventions Text conventions used in this manual are identified and described as follows. Example Description Close command (File menu) Titles in reference sections indicate the location of an item within the VisualDSP+ environment's menu system. For example, the Close command appears on the File menu. {this | that} Alternative items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required. [this | that] Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that. [this,.] Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this. .SECTION Commands, directives, keywords, and feature names are in text with letter gothic font. filename Non-keyword placeholders appear in text with italic style format. Note: For correct operation, . A Note: provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol. Caution: Incorrect device operation may result if . Caution: Device damage may result if . A Caution: identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol. Warning: Injury to device users may result if . A Warning: identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for devices users. In the online version of this book, the word Warning appears instead of this symbol. ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference xliii Conventions Additional conventions, which apply only to specific chapters, may appear throughout this document. xliv ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference 1 INTRODUCTION The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x SHARC processors are high performance, 32-bit processors used for high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications. By adding on-chip SRAM, integrated I/O peripherals, and an additional processing element for single-instruction, multiple-data (SIMD) support, this processor builds on the ADSP-21000 ADSP-21000 family DSP core to form a complete system-on-a-chip. Design Advantages A digital signal processor's data format determines its ability to handle signals of differing precision, dynamic range, and signal-to-noise ratios. Because floating-point DSP math reduces the need for scaling and the probability of overflow, using a floating-point processor can simplify algorithm and software development. The extent to which this is true depends on the floating-point processor's architecture. Consistency with IEEE workstation simulations and the elimination of scaling are clearly two ease-of-use advantages. High level language programmability, large address spaces, and wide dynamic range allow system development time to be spent on algorithms and signal processing concerns, rather than assembly language coding, code paging, and/or error handling. The processors are highly integrated, 32-bit floating-point processors which provide all of these design advantages. The SHARC processor architecture balances a high performance processor core with high performance program memory (PM), data memory (DM), ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference 1-1 Design Advantages and input/output (I/O) buses. In the core, every instruction can execute in a single cycle. The buses and instruction cache provide rapid, unimpeded data flow to the core to maintain the execution rate. Figure 1-1 shows a detailed block diagram of the processor core and the I/O processor (IOP). This figures illustrates the following architectural features: · Two processing elements (PEx and PEy), each containing 32-bit, IEEE, floating-point computation units-multiplier, arithmetic logic unit (ALU), shifter, and data register file · Program sequencer with related instruction cache, interval timer, and data address generators (DAG1 and DAG2) · An SDRAM controller that provides an interface up to four separate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSCLK · Up to 2M bits of SRAM and 6M bits of on-chip, mask-programmable ROM · IOP with integrated direct memory access (DMA) controller, serial peripheral interface (SPI) compatible port, and serial ports (SPORTs) for point-to-point multiprocessor communications · A variety of audio centric peripheral modules including a Sony/Philips Digital Interface (S/PDIF), sample rate converter (SRC) and pulse width modulation (PWM). Table 1-1 on page 1-5 provides details on these and other features for the current members of the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors families. · JTAG test access port for emulation Figure 1-1 also shows the three on-chip buses: the PM bus, DM bus, and I/O bus. The PM bus provides access to either instructions or data. During a single cycle, these buses let the processor access two data operands 1-2 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Introduction from memory, access an instruction (from the cache), and perform a DMA transfer. Figure 1-1 also shows the asychronous memory interface available on the ADSP-21368 ADSP-21368 processor. INSTRUCTION CACHE 3 2 X 4 8-BI T FLAGS 4-15 ON -C HIP M EM OR Y PW M ADDR 2 PROCES SING E LE ME NTS (PEX , P EY) PM AD D R ES S B U S 32 S D M D A TA B U S TIM E R 64 64 3 8 SHARED M EMORY INTERFACE IOA(24 ) I OP REG ISTER (M EM ORY MAPP ED) CONTROL, S TATUS, & DATA BUFFERS DMA CONTRO LLE R SP DIF (RX /TX) SE RIAL PORTS (8) SP I PO RT (2 ) INPUT DATA PORT/ P DAP TW O W IRE INTERFACE DAI P INS DP I PI NS DPI ROUTING UNIT SRC (8 CHANNELS ) DAI ROUTING UNI T PRE CI SION CLOCK GE NERATO RS (4) 24 IOD(32 ) PX REGIS TER 3 4 CH A N N EL S G PIO FLAGS / IRQ/ TI ME XP 18 CONTRO L ADDRESS CO RE PR OC ESS OR 4 DATA 8 AS YNCHRONO US M EM ORY INTERFACE 32 P M D A TA BU S 32 EX TE RN A L PO RT SDRAM CO NTROLLER D M A D D R ES S BU S PROGRAM SEQ UENCER DATA CO NTROL PINS 2 DAG S 8X4 X3 2 ME MORY -TOME MORY DMA (2) UART (2 ) TIM ERS (3 ) D IGIT A L PE RIPH ER A L INTERF AC E D IGITA L A U DIO INT ER FAC E 20 14 I/O PROCES SOR *THE ADSP -2 13 68 PROCESS OR INCLUDES A CUSTOM ER-DE FI NABLE RO M BLOCK. PLEAS E CONTACT Y OUR ANALOG DE VICES SALES REPRES ENTATI VE FO R ADDITIO NAL DETAILS Figure 1-1. ADSP-21368 ADSP-21368 Block Diagram The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors address the five central requirements for signal processing: Fast, Flexible Arithmetic. The ADSP-21000 ADSP-21000 family processors execute all instructions in a single cycle. They provide fast cycle times and a complete set of arithmetic operations. The processor is IEEE floating-point compatible and allows either interrupt on arithmetic exception or latched status exception handling. ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference 1-3 Design Advantages Unconstrained Data Flow. The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors have a Super Harvard Architecture combined with a ten-port data register file. In every cycle, the processor can write or read two operands to or from the register file, supply two operands to the ALU, supply two operands to the multiplier, and receive three results from the ALU and multiplier. The processor's 48-bit orthogonal instruction word supports parallel data transfers and arithmetic operations in the same instruction. 40-Bit Extended Precision. The processor handles 32-bit IEEE floating-point format, 32-bit integer and fractional formats (twos-complement and unsigned), and extended-precision, 40-bit floating-point format. The processors carry extended precision throughout their computation units, limiting intermediate data truncation errors (up to 80 bits of precision are maintained during multiply-accumulate operations). Dual Address Generators. The processor has two data address generators (DAGs) that provide immediate or indirect (pre- and post-modify) addressing. Modulus, bit-reverse, and broadcast operations are supported with no constraints on data buffer placement. Efficient Program Sequencing. In addition to zero-overhead loops, the processor supports single-cycle setup and exit for loops. Loops are both nestable (six levels in hardware) and interruptable. The processors support both delayed and non-delayed branches. The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors also provide the following features which increase the variety processor applications. High Bandwidth I/O. The processors contain a dedicated, 6M bits on-chip ROM, an external port, an SPI port, serial ports, digital audio interface (DAI), and JTAG. The DAI incorporates a precision clock generator, input data port, and a signal routing unit. Serial Ports. Provides an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at up to half the processor core clock (CCLK) rate. 1-4 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Introduction Input Data Port (IDP). The IDP provides an additional input path to the processor core, configurable as eight channels of serial data or seven channels of serial data and a single channel of up to 20-bit wide parallel data. Two Serial Peripheral Interfaces (SPI). The primary SPI has dedicated pins and the secondary is controlled through the DAI. The SPI provides master or slave serial boot through the SPI, full-duplex operation, master-slave mode, multimaster support, open drain outputs, programmable baud rates, clock polarities, and phases. Digital Audio Interface and Digital Peripheral Interface. The digital audio interface (DAI) and the digital peripheral interface (DPI) are comprised of groups of peripherals and their signal routing units (SRU1 and SRU2 respectively). This allows peripherals to be interconnected to suit a wide variety of systems. It also allows the processors to include an arbitrary number and variety of peripherals while retaining high levels of compatibility without increasing pin count. Signal Routing Units (SRU1/SRU2). The SRUs provide configuration flexibility by allowing software-programmable connections to be made between the DAI/DPI components and the 20 DAI pins and 14 DPI pins. I/O Processor (IOP). The IOP manages the SHARC processor's off-chip data I/O to alleviate the core of this burden. This unit manages the other processor peripherals such as the SPI, DAI, and IDP as well as direct memory accesses (DMA). Table 1-1. SHARC Processor Features Feature ADSP-21367 ADSP-21367 ADSP-21368 ADSP-21368 ADSP-21369 ADSP-21369 ADSP-21371 ADSP-21371 ADSP-21375 ADSP-21375 RAM 2M bit 2M bit 2M bit 1M bit 0.5M bit ROM 6M bit 6M bit1 6M bit1 4M bit1 2M bit1 Audio Decoders in ROM2 Yes No No No No ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference 1-5 Architectural Overview Table 1-1. SHARC Processor Features (Cont'd) Feature ADSP-21367 ADSP-21367 ADSP-21368 ADSP-21368 ADSP-21369 ADSP-21369 ADSP-21371 ADSP-21371 ADSP-21375 ADSP-21375 Pulse Width Modulation Yes Yes Yes Yes No S/PDIF Yes Yes Yes Yes No Shared Memory No Yes No No No SRC Performance 128dB 140dB 128dB 128dB N/A Package Option3 256-ball SBGA 208 Lead MQFP 256-ball SBGA 256-ball SBGA 208 Lead MQFP 208-lead MQFP 208-lead MQFP Processor Speed 333 MHz 333 MHz 333 MHz 266 MHz 266 MHz 1 The ADSP-21367 ADSP-21367 processor include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details. 2 Audio decoding algorithms include PCM, Dolby Digital EX, PCM, Dolby Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES, MPEG2 AAC, MPEG2 2channel, MP3, and functions like bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support will vary depending upon the chip version and the system configurations. Please visit www.analog.com/SHARC for complete information. 3 Analog Devices offers these packages in lead-free (Pb) versions. Architectural Overview The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors form a complete system-on-a-chip, integrating a large, high speed SRAM and I/O peripherals supported by a dedicated I/O bus. The following sections summarize the features of each functional block in the processor architecture, which appears in Figure 1-1. 1-6 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Introduction Processor Core The processor core of the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors contain two processing elements (each with three computation units and data register file), a program sequencer, two data address generators, a timer, and an instruction cache. All digital signal processing occurs in the processor core. For complete information, see the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x SHARC processors. Processor Peripherals The term processor peripherals refers to the multiple on-chip functional blocks used to communicate with off-chip devices. The peripherals include the JTAG, UART, serial ports, SPI ports, DAI/DPI components (PCG, timers, and IDP are a few), and any external devices that connect to the processor. I/O Processor The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors input/output processor (IOP) manages the off-chip data I/O to alleviate the core of this burden. Up to thirty-four channels of DMA are available on the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors-sixteen via the serial ports, 8 via the input data port, 4 for the UARTs, 2 for the SPI interface, 2 for the external port, and 2 for memory-to-memory transfers. The I/O processor can perform DMA transfers between the peripherals and internal memory at the full core clock speed. The architecture of the internal memory allows the IOP and the core to access internal memory simultaneously with no reduction in throughput. Serial Ports. The processors feature up to eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at up to half of the processor core clock rate with maximum of 50M bits per second. Each serial port features two data pins that function as a pair based on the ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference 1-7 Architectural Overview same serial clock and frame sync. Accordingly, each serial port has two DMA channels and serial data buffers associated with it to service the dual serial data pins. Programmable data direction provides greater flexibility for serial communications. Serial port data can automatically transfer to and from on-chip memory using DMA. Each of the serial ports offers a TDM multichannel mode (up to 128 channels) and supports -law or A-law companding. I2S support is also provided with the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors. The serial ports can operate with least significant bit first (LSBF) or most significant bit first (MSBF) transmission order, with word lengths from 3 to 32 bits. The serial ports offer selectable synchronization and transmit modes. Serial port clocks and frame syncs can be internally or externally generated. Serial Peripheral (Compatible) Interface (SPI). The SPI is an industry standard synchronous serial link that enables the SPI-compatible port to communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. It can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The SPI-compatible peripheral implementation also supports programmable baud rate and clock phase/polarities, as well as the use of open drain drivers to support the multimaster scenario to avoid data contention. SDRAM Controller. The SDRAM controller provides an interface of up to four separate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSCLK. Fully compliant with the SDRAM standard, each bank has it's own memory select line (MS0­MS3), and can be configured to contain between 16M bytes and 256M bytes of memory. 1-8 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Introduction ROM-Based Security. For those processors with application code in the on-chip ROM, an optional ROM security feature is included. This feature provides hardware support for securing user software code by preventing unauthorized reading from the enabled code. The processor does not boot-load any external code, executing exclusively from internal ROM. Also, the processor is not freely accessible via the JTAG port. Instead, a 64-bit key is assigned to the user. This key must be scanned in through the JTAG or Test Access Port. The device ignores a wrong key. Emulation features and external boot modes are only available after the correct key is scanned. Digital Audio Interface (DAI) The digital audio interface (DAI) unit is a new addition to the SHARC processor peripherals. This set of audio peripherals consists of an interrupt controller, an interface data port, and a signal routing unit, four precision clock generators (PCGs) and three timers. Some family members have an S/PDIF receiver/transmitter and eight channels asynchronous sample rate converters (SRC). Interrupt Controller. The DAI contains its own interrupt controller that indicates to the core when DAI audio events have occurred. This interrupt controller offer 32 independently configurable channels. Input Data Port (IDP). The input data port provides the DAI with a way to transmit data from within the DAI to the core. The IDP provides a means for up to eight additional DMA paths from the DAI into on-chip memory. All eight channels support 24-bit wide data and share a 16-deep FIFO. Signal Routing Unit One (SRU1). Conceptually similar to a "patch-bay" or multiplexer, the SRU provides a group of registers that define the interconnection of the serial ports, the input data port, the DAI pins, and the precision clock generators. ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference 1-9 Development Tools Digital Peripheral Interface (DPI) The digital peripheral interface (DPI) unit is a new addition to the SHARC processor peripherals. This set of audio peripherals consists of an interrupt controller, a two wire interface port (TWI), and a signal routing unit, three timers and a Universal Asynchronous Receiver/Transmitter (UART). Interrupt Controller. The DPI contains its own interrupt controller that indicates to the core when DPI audio events have occurred. This interrupt controller offer 32 independently configurable channels. Two Wire Interface (TWI). The two wire interface (TWI) controller allows a device to interface to an Inter IC bus as specified by the Philips I2C Bus Specification version 2.1 dated January 2000. Universal Asynchronous Receiver/Transmitter (UART). A full-duplex peripheral compatible with PC-style, industry-standard UARTs. The UART converts data between serial and parallel formats. The UART includes interrupt handling hardware. Interrupts can be generated from 12 different events. Signal Routing Unit Two (SRU2). Conceptually similar to a "patch-bay" or multiplexer, SRU2 provides a group of registers that define the interconnection of the DPI's peripherals, the DPI pins, and the timers. Development Tools The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors are supported by VisualDSP+, an easy-to-use integrated development and debugging environment (IDDE). VisualDSP+ allows you to manage projects from start to finish from within a single, integrated interface. Because the project development and debug environments are integrated, you can move easily between editing, building, and debugging activities. 1-10 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference Introduction Differences From Previous Processors This section identifies differences between the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors and previous SHARC processors: ADSP-21161 ADSP-21161, ADSP-21160 ADSP-21160, ADSP-21060 ADSP-21060, ADSP-21061 ADSP-21061, ADSP-21062 ADSP-21062, and ADSP-21065L ADSP-21065L. Like the ADSP-2116x family, the ADSP-2136x SHARC processor family is based on the original ADSP-2106x SHARC family. The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors preserve much of the ADSP-2106x architecture and is code compatible to the ADSP-21160 ADSP-21160, while extending performance and functionality. For background information on SHARC processors and the ADSP-2106x family DSPs, see the ADSP-2106x SHARC User's Manual or the ADSP-21065L ADSP-21065L SHARC DSP Technical Reference. I/O Architecture Enhancements The I/O processor provides much greater throughput than that on the ADSP-2106x processors. The DMA controller supports up to 34 channels compared to 14 channels on the ADSP-21161 ADSP-21161 processor. DMA transfers occur at clock speed in parallel with full speed processor execution. The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors also provide delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. In addition to the above, the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors have up to eight serial ports (SPORTs), a 32-bit external memory interface, a universal asynchronous transmitter/receiver (UART) and an I2C compatible interface called the TWI (two wire interface). ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference 1-11 Differences From Previous Processors Instruction Set Enhancements The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors provide source code compatibility with the previous SHARC processor family members to the application assembly source code level. All instructions, control registers, and system resources available in the ADSP-2106x core programming model are also available in the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors. Instructions, control registers, or other facilities required to support the new feature set of the ADSP-2116x core include: · Code compatibility to the ADSP-21160 ADSP-21160 SIMD core · Supersets of the ADSP-2106x programming model · Reserved facilities in the ADSP-2106x programming model · Symbol name changes from the ADSP-2106x programming models These name changes can be managed through reassembly by using the development tools to apply the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processor symbol definitions header file and linker description file. While these changes have no direct impact on existing core applications, system and I/O processor initialization code and control code do require modifications. Although the porting of source code written for the ADSP-2106x family to the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors has been simplified, code changes are required to take full advantage of the new features. For more information, see the ADSP-2136x SHARC Processor Programming Reference. 1-12 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference 2 I/O PROCESSOR In applications that use extensive off-chip data I/O, programs may find it beneficial to use a processor resource other than the processor core to perform data transfers. The ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors contain an I/O processor (IOP) that supports a variety of DMA (direct memory access) operations. Each DMA operation transfers an entire block of data. These operations include the transfer types listed below and shown in Figure 2-2 on page 2-25. · Internal memory external memory devices (through the external port) · Internal memory digital audio/digital peripheral interfaces (DAI/DPI) · Internal memory serial port I/O · Internal memory serial peripheral interface I/O · Internal memory UART I/O · Internal memory internal memory By managing DMA, the I/O processor frees the processor core, allowing it to perform other operations while off-chip data I/O occurs as a background task. The multibank architecture of the internal memory allows the core and IOP to simultaneously access the internal memory if the accesses are to different memory banks. This means that DMA transfers to internal memory do not impact core performance. The processor core continues to perform computations without penalty. ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference 2-1 General Procedure for Configuring DMA To further increase off-chip I/O, multiple DMAs can occur at the same time. The IOP accomplishes this by managing DMAs of processor memory through the TWI, UART, SPI, input data port (IDP), and serial ports. Accesses to IOP spaces (from the processor core) should not use Type 1 (dual access) or LW instructions. General Procedure for Configuring DMA To configure the ADSP-21367/8/9 ADSP-21367/8/9 and ADSP-2137x processors to use DMA, use the following general procedure. 1. Determine which DMA options you want to use: · IOP/core interaction method ­ interrupt-driven or status-driven (polling) · DMA transfer method ­ chained, non-chained, or delay line · Channel priority scheme ­ fixed or rotating 2. Determine how you want the DMA to operate: · Set up the data's source and/or destination addresses (INDEX) · Set up the word COUNT (data buffer size) · Configure the MODIFY values (step size) 3. Configure the peripheral(s): · External port (includes AMI, SDRAM) · Serial ports (SPORTs) · Universal asynchronous receive/transmit (UART) 2-2 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference I/O Processor · Serial peripheral interface ports (SPI) · Input data port (IDP) 4. Enable DMA · Set the applicable bits in the appropriate control registers For peripheral specific DMA information, see the following sections. · "External Port DMA" on page 2-35 · "Serial Port DMA" on page 2-40 · "Serial Peripheral Interface DMA" on page 2-42 · "UART DMA" on page 2-44 · "Memory-to-Memory DMA" on page 2-48 Core Access to IOP Registers In certain cases, extra core cycles are needed to process register accesses. The access cycles are shown in Table 2-1 and the registers are shown in Table 2-2. Table 2-1. I/O Processor Stall Conditions Type Of Access Number of Core Cycles Core write1 1 Core read1 2 Unconditional, isolated I/O processor register write2 1 Unconditional I/O processor register write after a write2 2 (back-to-back) Unconditional I/O processor register read2 7/8 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference 2-3 Core Access to IOP Registers Table 2-1. I/O Processor Stall Conditions (Cont'd) Type Of Access Number of Core Cycles Aborted conditional I/O processor register read/write 2 3 Conditional I/O processor register read/write 2 9/10 1 2 Applies to memory-mapped registers from Table 2-2. Applies to all other memory-mapped registers not in Table 2-2. Table 2-2. Memory-Mapped Emulation/Breakpoint Registers Register Address EEMUIN Emulator input FIFO 0x30020 EEMUSTAT Enhanced emulation status 0x30021 EEMUOUT Emulator output FIFO 0x30022 OSPID Operating system process ID 0x30023 SYSCTL System control 0x30024 BRKCTL Breakpoint control 0x30025 REVPID Emulation/revision ID 0x30026 PSA1S/E Instruction breakpoint address number 1 start/end 0x300A0/ 0x300A1 PSA2S/E Instruction breakpoint address number 2 start/end 0x300A2/ 0x300A3 PSA3S/E Instruction breakpoint address number 3 start/end 0x300A4/ 0x300A5 PSA4S/E Instruction breakpoint address number 4 start/end 0x300A6/ 0x300A7 EMUN Number of breakpoints before EMU interrupt 0x300AE IOAS/E 2-4 Description I/O address breakpoint start/end 0x300B0/ 0x300B1 ADSP-21368 ADSP-21368 SHARC Processor Hardware Reference I/O Processor Table 2-2. Memory-Mapped Emulation/Breakpoint Registers (Cont'd) Register Description Address DMA1S/E Data memory breakpoint addre