ADS8481 SLAS385 18BIT ADS8383 ADS8381 ADS8401 ADS8411 ADS8380 ADS8382 ADS8482 - Datasheet Archive

 

SLAS385 - JULY 2005 18BIT, 1MSPS, PSEUDODIFFERENTIAL UNIPOLAR INPUT, MICROPOWER SAMPLING ANALOGTODIGITAL CONVERTER WITH PARALLEL

 

ADS8481 ADS8481 SLAS385 SLAS385 - JULY 2005 18BIT 18BIT, 1MSPS, PSEUDODIFFERENTIAL UNIPOLAR INPUT, MICROPOWER SAMPLING ANALOGTODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE FEATURES APPLICATIONS D Medical Instruments D Optical Networking D Transducer Interface D High Accuracy Data Acquisition Systems D Magnetometers D 1-MHz Sample Rate D 18-Bit NMC Ensured Over Temperature D Zero Latency D Low Power: 250 mW at 1 MSPS D Unipolar Single-Ended Input Range: 0 V to Vref The ADS8481 ADS8481 is an 18-bit, 1-MSPS A/D converter with an internal 4.096-V reference and a pseudo-differential unipolar single-ended input. The device includes a 18-bit capacitor-based SAR A/D converter with inherent sample and hold. The ADS8481 ADS8481 offers a full 18-bit interface, a 16-bit option where data is read using two read cycles, or an 8-bit bus option using three read cycles. D Onboard Reference D Onboard Reference Buffer D High-Speed Parallel Interface D Wide Digital Supply 2.7 V ~ 5.25 V D 8-/16-/18-Bit Bus Transfer The ADS8481 ADS8481 is available in a 48-lead TQFP or 7x7 QFN package and is characterized over the industrial -40°C to 85°C temperature range. D 48-Pin TQFP or 7x7 QFN Package HIGH SPEED SAR CONVERTER FAMILY TYPE/SPEED 500 kHz 580 kHz ADS8383 ADS8383 ADS8381 ADS8381 18-Bit Pseudo-Diff 750 kHz 1 MHz 1.25 MHz 2 MHz ADS8401 ADS8401 3 MHz 4 MHz ADS8411 ADS8411 ADS8481 ADS8481 ADS8380 ADS8380 (S) 18-Bit Pseudo-Bipolar, Fully Diff ADS8382 ADS8382(S) ADS8482 ADS8482 ADS8371 ADS8371 ADS8471 ADS8471 16-Bit Pseudo-Diff ADS8405 ADS8405 ADS8472 ADS8472 16-Bit Pseudo-Bipolar, Fully Diff ADS8402 ADS8402 ADS8412 ADS8412 ADS8406 ADS8406 14-Bit Pseudo-Diff ADS7890 ADS7890 (s) 12-Bit Pseudo-Diff ADS7886 ADS7886 SAR +IN -IN + _ CDAC ADS7891 ADS7891 ADS7883 ADS7883 Output Latches and 3-State Drivers ADS7881 ADS7881 BYTE 16-/8-Bit Parallel DATA Output Bus BUS 18/16 Comparator REFIN REFOUT 4.096-V Internal Reference Clock Conversion and Control Logic CONVST BUSY CS RD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright 2005, Texas Instruments Incorporated PRODUCT PREVIEW DESCRIPTION ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGE TYPE 17 48 Pin TQFP PRODUCT PREVIEW ADS8481IB ADS8481IB ±6 ±3 -1 to +1.5 -2 to +3 -1 to +1.5 18 17 18 48 Pin TQFP 7x7 48 Pin QFN 7x7 48 Pin QFN PFB -40 C -40°C to 85°C PFB RGZ RGZ -40 C -40°C to 85°C -40 C -40°C to 85°C -40 C -40°C to 85°C Tape and reel 250 ADS8481IPFBR ADS8481IPFBR Tape and reel 1000 Tape and reel 250 ADS8481IBPFBR ADS8481IBPFBR Tape and reel 1000 Tape and reel 250 ADS8481IRGZR ADS8481IRGZR Tape and reel 1000 ADS8481IBRGZT ADS8481IBRGZT ADS8481I ADS8481I ±3 -2 to +3 TEMPERATURE RANGE TRANSPORT MEDIA QTY. ADS8482IRGZT ADS8482IRGZT ADS8481IB ADS8481IB ±6 PACKAGE DESIGNATOR ORDERING INFORMATION ADS8481IBPFBT ADS8481IBPFBT ADS8481I ADS8481I MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES RESOLUTION (BIT) ADS8481IPFBT ADS8481IPFBT MODEL MAXIMUM INTEGRAL LINEARITY (LSB) Tape and reel 250 ADS8481IBRGZR ADS8481IBRGZR Tape and reel 1000 NOTE: For the most current specifications and package information, refer to our website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) RATING +IN to AGND -IN to AGND Voltage -0.4 V to +VA + 0.1 V -0.4 V to 0.5 V +VA to AGND -0.3 V to 7 V +VBD to BDGND +VA to +VBD -0.3 V to 7 V -0.3 V to 2.55 V Digital input voltage to BDGND -0.3 V to +VBD + 0.3 V Digital output voltage to BDGND -0.3 V to +VBD + 0.3 V Operating free-air temperature range, TA -40°C to 85°C Storage temperature range, Tstg -65°C to 150°C Junction temperature (TJ max) Power dissipation 150°C (TJMax - TA)/JA JA thermal impedance 86°C/W Vapor phase (60 sec) 215°C Lead temperature, soldering Infrared (15 sec) 220°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. TQFP package 2 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 SPECIFICATIONS TA = -40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input Full-scale input voltage (1) +IN - (-IN) 0 +IN -IN Absolute input voltage Vref Vref + 0.2 0.2 -0.2 -0.2 Input capacitance V V 65 pF 1 nA 18 Input leakage current Bits System Performance ADS8481I ADS8481I Integral linearity(2) (3) Differential linearity Offset error(4) Gain error(4) (5) 17 ADS8481IB ADS8481IB 18 ADS8481I ADS8481I -6 6 ADS8481IB ADS8481IB -3 3 ADS8481I ADS8481I No missing codes -2 3 ADS8481IB ADS8481IB -1 1.5 -1 ADS8481IB ADS8481IB ADS8481IB ADS8481IB Vref = 4.096 V Vref = 4.096 V ±0.5 0.75 LSB (18 bit) LSB (18 bit) 1 ±0.25 mV -0.1 0.1 %FS -0.06 0.06 %FS 30 At 3FFFFh output code µV RMS 75 Noise Power supply rejection ratio Bits -0.75 ADS8481I ADS8481I ADS8481I ADS8481I 18 PRODUCT PREVIEW Resolution dB Sampling Dynamics Conversion time Acquisition time(6) 630 Throughput rate ns 1000000 250 ns 1 MHz Aperture delay 4 ns Aperture jitter 15 ps Step response 150 ns 150 ns Over voltage recovery (1) Ideal input span, does not include gain or offset error. (2) LSB means least significant bit (3) This is endpoint INL, not best fit. (4) Measured relative to an ideal full-scale input [+IN - (-IN)] of 4.096 V (5) This specification does not include the internal reference voltage error and drift. (6) If the time between conversion is > 1 ms, the first output if invalid. 3 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 SPECIFICATIONS (CONTINUED) TA = -40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dynamic Characteristics ADS8481I ADS8481I ADS8481IB ADS8481IB -110 VIN = 4 Vpp at 1 kHz -112 ADS8481I ADS8481I Total harmonic distortion (THD) (1) ADS8481IB ADS8481IB -98 VIN = 4 Vpp at 10 kHz -108 ADS8481I ADS8481I ADS8481IB ADS8481IB VIN = 4 Vpp at 100 kHz -99 ADS8481I ADS8481I ADS8481IB ADS8481IB -90 VIN = 4 Vpp at 250 kHz -91 ADS8481I ADS8481I ADS8481IB ADS8481IB 92 VIN = 4 Vpp at 1 kHz 94 ADS8481I ADS8481I PRODUCT PREVIEW Signal to noise ratio (SNR) (1) ADS8481IB ADS8481IB 91 VIN = 4 Vpp at 10 kHz 93 ADS8481I ADS8481I ADS8481IB ADS8481IB VIN = 4 Vpp at 100 kHz 92 88 VIN = 4 Vpp at 250 kHz 90 ADS8481I ADS8481I ADS8481IB ADS8481IB 91 VIN = 4 Vpp at 1 kHz 93 ADS8481I ADS8481I Signal to noise + distortion (SINAD) (1) ADS8481IB ADS8481IB 90 VIN = 4 Vpp at 10 kHz 92 ADS8481I ADS8481I ADS8481IB ADS8481IB VIN = 4 Vpp at 100 kHz 91 87 VIN = 4 Vpp at 250 kHz 89 ADS8481I ADS8481I ADS8481IB ADS8481IB 110 VIN = 4 Vpp at 1 kHz 112 VIN = 4 Vpp at 10 kHz 107 ADS8481I ADS8481I Spurious free dynamic range (SFDR)(1) ADS8481IB ADS8481IB 98 ADS8481I ADS8481I ADS8481IB ADS8481IB dB 98 VIN = 4 Vpp at 100 kHz 98 ADS8481I ADS8481I ADS8481IB ADS8481IB dB 89 ADS8481I ADS8481I ADS8481IB ADS8481IB dB 90 ADS8481I ADS8481I ADS8481IB ADS8481IB dB -98 90 VIN = 4 Vpp at 250 kHz 94 -3dB Small signal bandwidth 3 MHz Voltage Reference Input Reference voltage at REFIN, Vref Reference resistance(2) Reference current drain 2.5 4.096 4.2 500 fs = 1 MHz V k 1 mA 120 ms Internal Reference Output Internal reference start-up time From 95% (+VA), with 1-µF storage capacitor Reference voltage range, Vref Source current IO = 0 Static load Line regulation +VA = 4.75 V ~ 5.25 V Drift IO = 0 (1) Calculated on the first nine harmonics of the input frequency (2) Can vary ±20% 4 4.065 4.096 5 V 10 0.6 4.13 µA mV PPM/C ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 SPECIFICATIONS (CONTINUED) TA = -40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Input/Output Logic family - CMOS Logic level VIH VIL IIH = 5 µA IIL = 5 µA VOH VOL IOH = 2 TTL loads IOL = 2 TTL loads +VBD-1 +VBD + 0.3 0.8 -0.3 V +VBD - 0.6 0.4 Data format - Straight Binary Power Supply Requirements +VBD Power supply voltage Supply current(1) Power dissipation(1) 2.7 3.3 5.25 4.75 +VA 5 5.25 fs = 1 MHz fs = 1 MHz V V 50 mA 250 mW Temperature Range 85 °C PRODUCT PREVIEW Operating free-air -40 (1) This includes only +VA current. +VBD current is typical 1 mA with 5 pF load capacitance on all output pins. 5 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 TIMING CHARACTERISTICS All specifications typical at -40°C to 85°C, +VA =+VBD = 5 V (1), (2), (3) PARAMETER MIN TYP MAX UNIT t(CONV) t(ACQ) Conversion time Acquisition time(4) 630 ns 1000000 t(HOLD) tpd1 ns Sample capacitor hold time 25 ns tpd2 tpd3 CONVST low to BUSY high 40 ns Propagation delay time, end of conversion to BUSY low 15 ns Propagation delay time, start of convert state to rising edge of BUSY 15 ns tw1 tsu1 Pulse duration, CONVST low 40 ns Setup time, CS low to CONVST low 20 ns tw2 Pulse duration, CONVST high 20 250 CONVST falling edge jitter tw3 tw4 PRODUCT PREVIEW th1 Pulse duration, BUSY signal low t(ACQ)min Pulse duration, BUSY signal high Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS18/16 BUS18/16 input changes) after CONVST low ns 10 ps ns 630 ns 40 ns 0 ns 0 ns td1 tsu2 Delay time, CS low to RD low tw5 ten Pulse duration, RD low td2 td3 Delay time, data hold from RD high Delay time, BUS18/16 BUS18/16 or BYTE rising edge or falling edge to data valid 10 tw6 tw7 Pulse duration, RD high 20 ns Pulse duration, CS high 20 ns th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge 0 ns Setup time, RD high to CS high 50 Enable time, RD low (or CS low for read cycle) to data valid ns 20 5 ns ns 20 ns td4 tsu3 Delay time, BYTE edge to BUS18/16 BUS18/16 edge skew 0 ns Setup time, BYTE or BUS18/16 BUS18/16 transition to RD falling edge 10 ns th3 Hold time, BYTE or BUS18/16 BUS18/16 transition to RD falling edge 10 ns tdis Disable time, RD high (CS high for read cycle) to 3-stated data bus td5 Delay time, BUSY low to MSB data valid delay td6 Delay time, CS rising edge to BUSY falling edge 50 ns td7 Delay time, BUSY falling edge to CS rising edge 50 ns tsu5 BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16 BUS18/16 transition setup time, from BUS18/16 BUS18/16 to next BUS18/16 BUS18/16. 50 ns tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the next falling edge of CS (when CS is used to abort). 60 20 0 (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins. (4) If the time between conversion is > 1 ms, then first output if invalid. 6 ns ns 610 ns ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 TIMING CHARACTERISTICS All specifications typical at -40°C to 85°C, +VA =+VBD = 3 V (1), (2), (3) PARAMETER MIN TYP MAX UNIT t(CONV) t(ACQ) Conversion time Acquisition time(4) 630 ns 1000000 t(HOLD) tpd1 ns Sample capacitor hold time 25 ns tpd2 tpd3 CONVST low to BUSY high 40 ns Propagation delay time, end of conversion to BUSY low 25 ns Propagation delay time, start of convert state to rising edge of BUSY 25 ns tw1 tsu1 Pulse duration, CONVST low 40 ns Setup time, CS low to CONVST low 20 ns tw2 Pulse duration, CONVST high 20 250 CONVST falling edge jitter th1 Pulse duration, BUSY signal low t(ACQ)min Pulse duration, BUSY signal high Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS 18/16 input changes) after CONVST low ps ns 630 ns 40 ns 0 ns 0 ns td1 tsu2 Delay time, CS low to RD low tw5 ten Pulse duration, RD low td2 td3 Delay time, data hold from RD high Delay time, BUS18/16 BUS18/16 or BYTE rising edge or falling edge to data valid 10 tw6 tw7 Pulse duration, RD high 20 ns Pulse duration, CS high 20 ns th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge 0 PRODUCT PREVIEW tw3 tw4 ns 10 ns Setup time, RD high to CS high 50 Enable time, RD low (or CS low for read cycle) to data valid ns 30 5 ns ns 30 ns td4 tsu3 Delay time, BYTE edge to BUS18/16 BUS18/16 edge skew 0 ns Setup time, BYTE or BUS18/16 BUS18/16 transition to RD falling edge 10 ns th3 Hold time, BYTE or BUS18/16 BUS18/16 transition to RD falling edge 10 ns tdis Disable time, RD high (CS high for read cycle) to 3-stated data bus td5 Delay time, BUSY low to MSB data valid delay td6 Delay time, CS rising edge to BUSY falling edge 50 ns td7 Delay time, BUSY falling edge to CS rising edge 50 ns tsu5 BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/16 BUS18/16 transition setup time, from BUS18/16 BUS18/16 to next BUS18/16 BUS18/16. 50 ns tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the next falling edge of CS (when CS is used to abort). 70 30 ns 0 ns 620 ns (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins. (4) If the time between conversion is > 1 ms, the first output if invalid. 7 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 PIN ASSIGNMENTS REFM REFM +VA AGND AGND +VA CS RD CONVST BYTE BUS18/16 BUS18/16 +VBD PFB PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 BUSY DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 BDGND DB10 +VBD 1 +VA AGND AGND DB17 DB16 DB15 DB14 DB13 DB12 DB11 PRODUCT PREVIEW REFIN REFOUT NC +VA AGND +IN -IN AGND +VA +VA AGND AGND NC - No connection BUSY DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 BDGND RGZ PACKAGE (TOP VIEW) +VBD DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 AGND AGND +VA AGND AGND AGND +VA +VA -IN +IN AGND NC +VA REFIN 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 REFOUT +VBD BUS18/16 BUS18/16 BYTE CONVST RD CS +VA AGND AGND +VA REFM REFM NC - No internal connection NOTE: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 8 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 TERMINAL FUNCTIONS NO. PFB NO. RGZ I/O 5, 8, 11, 12, 14, 15, 44, 45 8, 9, 17, 20, 23, 24, 26, 27 - Analog ground BDGND 25 37 - Digital ground for bus interface digital supply BUSY 36 48 O Status output. High when a conversion is in progress. BUS18/1 BUS18/1 6 38 2 I Bus size select input. Used for selecting 18-bit or 16-bit wide bus transfer. 0: Data bits output on the 18-bit data bus pins DB[17:0]. 1: Last two data bits D[1:0] from 18-bit wide bus output on: a) the low byte pins DB[9:2] if BYTE = 0 b) the high byte pins DB[17:10] if BYTE = 1 BYTE 39 3 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[9:2] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[17:10]. CONVST 40 4 I Convert start. The falling edge of this input ends the acquisition period and starts the hold period. CS 42 6 I Chip select. The falling edge of this input starts the acquisition period. AGND DESCRIPTION 8-Bit Bus BYTE = 0 Data Bus BYTE = 1 16-Bit Bus BYTE = 1 BYTE = 0 BYTE = 0 18-Bit Bus BYTE = 0 BUS18/16 BUS18/16 = 0 BUS18/16 BUS18/16 = 0 BUS18/16 BUS18/16 = 1 BUS18/16 BUS18/16 = 0 BUS18/16 BUS18/16 = 1 BUS18/16 BUS18/16 = 0 DB17 16 28 O D17 (MSB) D9 All ones D17 (MSB) All ones D17 (MSB) DB16 17 29 O D16 D8 All ones D16 All ones D16 DB15 18 30 O D15 D7 All ones D15 All ones D15 DB14 19 31 O D14 D6 All ones D14 All ones D14 DB13 20 32 O D13 D5 All ones D13 All ones D13 DB12 21 33 O D12 D4 All ones D12 All ones D12 DB11 22 34 O D11 D3 D1 D11 All ones D11 DB10 23 35 O D10 D2 D0(LSB) D10 All ones D10 DB9 26 38 O D9 All ones All ones D9 All ones D9 DB8 27 39 O D8 All ones All ones D8 All ones D8 DB7 28 40 O D7 All ones All ones D7 All ones D7 DB6 29 41 O D6 All ones All ones D6 All ones D6 DB5 30 42 O D5 All ones All ones D5 All ones D5 DB4 31 43 O D4 All ones All ones D4 All ones D4 DB3 32 44 O D3 All ones All ones D3 D1 D3 DB2 33 45 O D2 All ones All ones D2 D0 (LSB) D2 DB1 34 46 O D1 All ones All ones D1 All ones D1 DB0 35 47 O D0 (LSB) All ones All ones D0 (LSB) All ones D0 (LSB) -IN 7 19 I Inverting input channel +IN 6 18 I Noninverting input channel NC 3 15 - No connection REFIN 1 13 I Reference input. REFOUT 2 14 O Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when internal reference is used. 47, 48 11, 12 I Reference ground. RD 41 5 I Synchronization pulse for the parallel output. When CS is low, this serves as output enable and puts the previous conversion results on the bus. +VA 4, 9, 10, 13, 43, 46 7, 10, 16, 21, 22, 25 - Analog power supplies, 5-V DC 24, 37 36 - Digital power supply for bus REFM +VBD 9 PRODUCT PREVIEW NAME ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 TYPICAL CHARACTERISTICS DNL 1 +VA = +VBD = 5 V, Vref = 4.096 V, TA = 255C 0.8 DNL - LSBs 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 32768 65536 98304 131072 163840 196608 229376 262144 163840 196608 229376 262144 CODE INL PRODUCT PREVIEW 3 +VA = +VBD = 5 V, Vref = 4.096 V, TA = 255C INL - LSBs 2 1 0 -1 -2 -3 0 32768 65536 98304 131072 CODE Amplitude - dB FFT 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 +VA = +VBD = 5 V, Vref = 4.096 V, TA = 255C 0 100 200 300 f - Frequency - kHz 10 400 500 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 TIMING DIAGRAMS tw2 tw1 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 CS tpd3 CONVERT t(HOLD) tw7 td7 td6 t(CONV) t(CONV) SAMPLING (When CS Toggle) PRODUCT PREVIEW t(ACQ) tsu(ABORT) tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tsu5 tsu2 tpd4 th2 td1 RD tdis ten DB[17:12] Hi-Z D[17:12] Hi-Z D[9:4] MSB DB[11:10] DB[9:0] Hi-Z Hi-Z D[11:10] D[3:2] D[1:0] D[9:0] Hi-Z Hi-Z Signal internal to device Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling 11 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 tw7 td7 CS tpd3 CONVERT td6 t(CONV) t(CONV) t(HOLD) SAMPLING (When CS Toggle) t(ACQ) tsu(ABORT) PRODUCT PREVIEW tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tpd4 th2 RD = 0 ten DB[17:12] DB[11:10] DB[9:0] ten tdis Previous Hi-Z D[17:12] Hi-Z Hi-Z Previous D[11:10] Previous D [9:0] Hi-Z Hi-Z Hi-Z tdis ten MSB D[17:12] D[11:10] D[9:0] D[9:4] D[3:2] D[1:0] Hi-Z Hi-Z Hi-Z Repeated D[17:12] Repeated D[11:10] Repeated D [9:0] Signal internal to device Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND 12 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 CS = 0 tpd3 tw7 td7 td6 CONVERT t(CONV) t(CONV) t(HOLD) PRODUCT PREVIEW t(ACQ) SAMPLING (When CS = 0) tsu(ABORT) tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tsu5 tpd4 th2 RD tdis ten MSB DB[17:12] DB[11:10] DB[9:0] Hi-Z Hi-Z Hi-Z D[17:12] D[11:10] D[3:2] Hi-Z D[9:4] D[9:0] D[1:0] Hi-Z Hi-Z Signal internal to device Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling 13 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 tw2 tw1 CONVST tpd1 tw4 tpd2 tw3 BUSY CS = 0 CONVERT t(CONV) t(CONV) tpd3 tpd3 t(HOLD) t(HOLD) t(ACQ) PRODUCT PREVIEW SAMPLING (When CS = 0) tsu(ABORT) tsu(ABORT) BYTE tsu5 tsu5 BUS 18/16 tsu5 RD = 0 tsu5 th1 th1 td5 DB[17:12] DB[11:10] DB[9:0] D[17:12] Previous LSB D[11:10] D[9:0] D[9:4] D[3:2] Next D[17:12] D[1:0] Next D[11:10] Next D[9:0] Signal internal to device Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND - Auto Read 14 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 CS RD BYTE tsu5 BUS 18/16 DB[17:0] Hi-Z tdis Valid Hi-Z td3 tdis td3 Valid Valid Hi-Z PRODUCT PREVIEW ten ten Figure 5. Detailed Timing for Read Cycles 15 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 APPLICATION INFORMATION MICROCONTROLLER INTERFACING ADS8481 ADS8481 to 8-Bit Microcontroller Interface Figure 6 shows a parallel interface between the ADS8481 ADS8481 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V 0.1 µF AGND 10 µF Ext Ref Input 0.1 µF PRODUCT PREVIEW Micro Controller GPIO GPIO GPIO GPIO RD AD[7:0] -IN +IN +VA REFIN REFM AGND Analog Input Digital 3 V CS AD8481 AD8481 BYTE BUS18/16 BUS18/16 CONVST RD DB[17:10] Data Bus D[17:0] 0.1 µF BDGND BDGND +VBD Figure 6. ADS8481 ADS8481 Application Circuitry Analog 5 V 0.1 µF AGND 10 µF 0.1 µF AGND AGND REFM REFIN REFOUT +VA 1 µF ADS8481 ADS8481 Figure 7. ADS8481 ADS8481 Using Internal Reference 16 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 PRINCIPLES OF OPERATION The ADS8481 ADS8481 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 6 for the application circuit for the ADS8481 ADS8481. The conversion clock is generated internally. The conversion time of 630 ns is capable of sustaining a 1 MHz throughput. The analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The ADS8481 ADS8481 can operate with an external reference with a range from 2.5 V to 4.2 V. A 4.096-V internal reference is included. When internal reference is used, pin 2 (REFOUT) is connected to pin 1 (REFIN) with an 0.1-µF decoupling capacitor and 1-µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM) (see Figure 7). The internal reference of the converter is double buffered. If an external reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if external reference is used. ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array. The voltage on the -IN input is limited between ­0.2 V and 0.2 V, allowing the input to reject small signals which are common to both the +IN and -IN inputs. The +IN input has a range of ­0.2 V to Vref + 0.2 V. The input span [+IN - (-IN)] is limited to 0 V to Vref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8481 ADS8481 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (65 pF) to an 18-bit settling level within the acquisition time (250 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1 G. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN and -IN inputs and the span [+IN - (-IN)] must be within the limits specified. Outside of these ranges, the converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters are used. Care must be taken to ensure that the output impedance of the sources driving the +IN and -IN inputs are matched. If this is not observed, the two inputs could have different setting times. This may result in offset error, gain error, and linearity error which varies with temperature and input voltage. DIGITAL INTERFACE Timing And Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The ADS8481 ADS8481 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required. Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8481 ADS8481 switches from the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY output is brought high immediately following CONVST going low. BUSY stays high throughout the conversion process and returns low when the conversion has ended. Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when BUSY is low. 17 PRODUCT PREVIEW REFERENCE ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion. Reading Data The ADS8481 ADS8481 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 125 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE and BUS18/16 BUS18/16 are used for multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus. BUS18/16 BUS18/16 is used whenever the last two bits on the 18-bit bus is output on either bytes of the higher 16-bit bus. Refer to Table 1 for ideal output codes. Table 1. Ideal Input Voltages and Output Codes DESCRIPTION ANALOG VALUE Full scale range Least significant bit (LSB) +Full scale PRODUCT PREVIEW DIGITAL OUTPUT STRAIGHT BINARY +Vref (+Vref)/262144 BINARY CODE HEX CODE (+Vref) ­ 1 LSB (+Vref)/2 11 1111 1111 1111 1111 3FFFF 10 0000 0000 0000 0000 20000 (+Vref)/2 ­ 1 LSB 0V 01 1111 1111 1111 1111 1FFFF 00 0000 0000 0000 0000 00000 Midscale Midscale ­ 1 LSB Zero The output data is a full 18-bit word (D17-D0 D17-D0) on DB17­DB0 pins (MSB-LSB) if both BUS18/16 BUS18/16 and BYTE are low. The result may also be read on an 16-bit bus by using only pins DB17-DB2 DB17-DB2. In this case two reads are necessary: the first as before, leaving both BUS18/16 BUS18/16 and BYTE low and reading the 16 most significant bits (D17-D2 D17-D2) on pins DB17-DB2 DB17-DB2, then bringing BUS18/16 BUS18/16 high while holding BYTE low. When BUS18/16 BUS18/16 is high, the lower two bits (D1­D0) appear on pins DB3-DB2. The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB17-DB10 DB17-DB10. In this case three reads are necessary: the first as before, leaving both BUS18/16 BUS18/16 and BYTE low and reading the 8 most significant bits on pins DB17-DB10 DB17-DB10, then bringing BYTE high while holding BUS18/16 BUS18/16 low. When BYTE is high, the medium bits (D9-D2) appear on pins DB17-DB10 DB17-DB10. The last read is done by bringing BUS18/16 BUS18/16 high while holding BYTE high. When BUS18/16 BUS18/16 is high, the lower two bits (D1­D0) appear on pins DB11-DB10 DB11-DB10. The last read cycle is not necessary if only the first 16 most significant bits are of interest. All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low for simplicity. This is referred to as the AUTO READ operation. Table 2. Conversion Data Read Out DATA READ OUT BYTE BUS18/16 BUS18/16 PINS DB17-DB12 DB17-DB12 PINS DB11-DB10 DB11-DB10 PINS DB9-DB4 PINS DB3-DB2 PINS DB1-DB0 High All One's D1-D0 All One's All One's All One's High All One's All One's All One's D1-D0 All One's High Low D9-D4 D3-D2 All One's All One's All One's Low 18 High Low Low D17-D12 D17-D12 D11-D10 D11-D10 D9-D4 D3-D2 D1-D0 ADS8481 ADS8481 www.ti.com SLAS385 SLAS385 - JULY 2005 RESET On power-up, internal POWER-ON RESET circuitry generates the reset required for the device. The first three conversions after power-up are used to load factory trimming data for a specific device to assure high accuracy of the converter. The results of the first three conversions are invalid and should be discarded. The device can also be reset through the use of the combination fo CS and CONVST. Since the BUSY signal is held at high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter. D Issue a CONVST when CS is low and the internal convert state is high. The falling edge of CONVST starts a reset. D Issue a CS (select the device) while the internal convert state is high. The falling edge of CS causes a reset. Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A new sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal reset. LAYOUT As the ADS8481 ADS8481 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to achieve good performance from the converter. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. On average, the ADS8481 ADS8481 draws very little current from an external reference as the reference voltage is internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor is recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND must be shorted on the same ground plane under the device. The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry. As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8481 ADS8481 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 3 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors-all designed to essentially low-pass filter the 5-V supply, removing the high frequency noise. Table 3. Power Supply Decoupling Capacitor Placement POWER SUPPLY PLANE SUPPLY PINS CONVERTER ANALOG SIDE CONVERTER DIGITAL SIDE Pin pairs that require shortest path to decoupling capacitors (4,5), (8,9), (10,11), (13,15), (43,44), (45,46) (24,25) Pins that require no decoupling 12, 14 37 19 PRODUCT PREVIEW For optimum performance, care must be taken with the physical layout of the ADS8481 ADS8481 circuitry. MECHANICAL DATA MTQF019A MTQF019A ­ JANUARY 1995 ­ REVISED JANUARY 1998 PFB (S-PQFP-G48 S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°­ 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. 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