ADM1027 12VIN 10-BIT 123C/W 27C/W RQ-24 2N3906 VRM10 2N3904/06 2N3904 MMBT2222 - Datasheet Archive

 

Controller and Voltage Monitor ADM1027* FEATURES Monitors up to 5 Supply Voltages Controls and Monitors up to 4 Fan Speeds 1

 

dB COOLTM Remote Thermal Controller and Voltage Monitor ADM1027 ADM1027* FEATURES Monitors up to 5 Supply Voltages Controls and Monitors up to 4 Fan Speeds 1 On-Chip and 2 Remote Temperature Sensors Monitors up to 5 Processor VID Bits Automatic Fan Speed Control Mode Controls System Cooling Based on Measured Temperature Enhanced Acoustic Mode Dramatically Reduces User Perception of Changing Fan Speeds 2-Wire and 3-Wire Fan Speed Measurement Limit Comparison of All Monitored Values Meets SMBus 2.0 Electrical Specifications (Fully SMBus 1.1 Compliant) GENERAL DESCRIPTION The ADM1027 ADM1027 dBCOOL controller is a complete systems monitor and multiple PWM fan controller for noise sensitive applications requiring active system cooling. It can monitor 12 V, 5 V, 2.5 V CPU supply voltage, plus its own supply voltage. It can monitor the temperature of up to two remote sensor diodes, plus its own internal temperature. It can measure and control the speed of up to four fans so that they operate at the lowest possible speed for minimum acoustic noise. The automatic fan speed control loop optimizes fan speed for a given temperature. Once the control loop parameters are programmed, the ADM1027 ADM1027 can vary fan speed without CPU intervention. APPLICATIONS Low Acoustic Noise PCs Networking and Telecommunications Equipment FUNCTIONAL BLOCK DIAGRAM ADDR SELECT ADDR EN SCL SDA SMBALERT VID4 VID3 VID REGISTER VID2 SMBUS ADDRESS SELECTION SERIAL BUS INTERFACE VID1 ADDRESS POINTER REGISTER VID0 PWM1 PWM2 PWM3 PWM REGISTERS AND CONTROLLERS AUTOMATIC FAN SPEED CONTROL ACOUSTIC ENHANCEMENT CONTROL PWM CONFIGURATION REGISTERS TACH1 TACH2 FAN SPEED COUNTER TACH3 INTERRUPT MASKING TACH4 VCC VCC TO ADM1027 ADM1027 D1+ D1­ D2+ D2­ +5VIN ADM1027 ADM1027 INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER +12VIN 12VIN +2.5VIN 10-BIT 10-BIT ADC BAND GAP REFERENCE VCCP BAND GAP TEMP. SENSOR INTERRUPT STATUS REGISTERS LIMIT COMPARATORS VALUE AND LIMIT REGISTERS GND *Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. to T ADM1027 ADM1027­SPECIFICATIONS1, 2, 3, 4 (T = T otherwise(0C to 105C), V unless noted.) A MIN MAX CC = VMIN to VMAX (3 V to 5.5 V), Parameter Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage Supply Current, ICC 3.0 3.3 1.4 5.5 3 V mA Interface Inactive, ADC Active ±3 ±2 o TEMP-TO-DIGITAL CONVERTER Local Sensor Accuracy ±1 0.25 Resolution Remote Diode Sensor Accuracy ±1 Resolution Remote Sensor Source Current 0.25 200 12 ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total Unadjusted Error, TUE Differential Nonlinearity, DNL Power Supply Sensitivity Conversion Time (Voltage Input) Conversion Time (Local Temperature) Conversion Time (Remote Temperature) Total Monitoring Cycle Time Total Monitoring Cycle Time Input Resistance ± 0.5 80 ± 0.1 11.38 12.09 25.59 120.17 13.51 140 FAN RPM-TO-DIGITAL CONVERTER Accuracy OPEN-DRAIN DIGITAL OUTPUTS, PWM1­PWM3, XTO Current Sink, IOL Output Low Voltage, VOL High Level Output Current, IOH ±1 ± 1.5 ±1 12.29 13.05 27.64 129.78 14.59 250 ±6 ±8 65,535 Full-Scale Count Nominal Input RPM Internal Clock Frequency ±3 ± 1.5 82.8 C C o C o C o C o C o C o C o C mA mA 0oC TA 105oC 0oC TA 70oC TA = 40oC % % LSB %/V ms ms ms ms ms k All ADC Inputs except 12 V 12 V Input 8 Bits o High Level Low Level Averaging Enabled Averaging Enabled Averaging Enabled Averaging Enabled Averaging Disabled % % 0oC TA 70oC 3.0 V VCC 3.6 V Fan Count = 0xBFFF Fan Count = 0x3FFF Fan Count = 0x0438 Fan Count = 0x021C 109 329 5,000 10,000 90 97.2 RPM RPM RPM RPM kHz 0.1 8.0 0.4 1 mA V mA ­2­ 0oC TD 120oC 0oC TD 120oC; 0oC TA 70oC TA = 40oC 0oC TD 120oC; TA = 40oC IOUT = ­8.0 mA, VCC = 3.3 V VOUT = VCC REV. A ADM1027 ADM1027 Parameter Min SMBUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis DIGITAL INPUT LOGIC LEVELS (VID0­4) Input High Voltage, VIH Input Low Voltage, VIL DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, VIH Max Unit Test Conditions/Comment 0.1 0.4 1 V mA IOUT = ­4.0 mA, VCC = 3.3 V VOUT = VCC 0.4 OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Current, IOH Typ V V mV 2.0 500 1.7 0.8 2.0 5.5 0.8 Input Low Voltage, VIL ­0.3 Hysteresis DIGITAL INPUT CURRENT Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN SERIAL BUS TIMING Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU;STA Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU;DAT Data Hold Time, tHD;DAT Detect Clock Low Timeout, tTIMEOUT 0.5 ­1 1 5 10 100 50 4.7 4.7 4.0 4.7 4.0 50 1000 300 250 300 15 35 V V V V V V V p-p REV. A ­3­ Minimum Input Voltage mA mA pF VIN = VCC VIN = 0 kHz ns ms ms ms ms ms ns ms ns ns ms See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 Can Be Optionally Disabled NOTES 1 All voltages are measured with respect to GND, unless otherwise specified. 2 Typicals are at TA = 40C and represent the most likely parametric norm. 3 Logic inputs will accept input high voltages up to V MAX even when the device is operating down to V MIN. 4 Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and V IH = 2.0 V for a rising edge. Specifications subject to change without notice. Maximum Input Voltage ADM1027 ADM1027 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . 6.5 V Voltage on 12 VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Voltage on Any Other Input or Output Pin . . . . ­0.3 V to +6.5 V Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA Package Input Current . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Maximum Junction Temperature (TJ MAX) . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . . . ­65C to +150C Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V SDA 1 24 PWM1/XTO SCL 2 23 VCCP GND 3 22 2.5VIN VCC 4 21 12VIN 12VIN VID0 5 ADM1027 ADM1027 20 5V IN 19 VID4 VID1 6 VID2 7 (Not to Scale) 18 D1+ VID3 8 17 D1­ TACH3 9 16 D2+ PWM2/SMBALERT 10 15 D2­ *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TOP VIEW TACH1 11 14 TACH4/ADDRESS SELECT TACH2 12 13 PWM3/ADDRESS ENABLE THERMAL CHARACTERISTICS 24-Lead QSOP Package: qJA = 123C/W 123C/W, qJC = 27C/W 27C/W ORDERING GUIDE Model Temperature Range Package Description Package Option ADM1027 ADM1027 0ºC to 105ºC 24-Lead QSOP RQ-24 RQ-24 tLOW tR tHD; STA tF SCL tHD; STA tHD; DAT tHIGH tSU; STA tSU; DAT tSU; STO SDA tBUF P S P S Figure 1. Diagram for Serial Bus Timing CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM1027 ADM1027 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ­4­ WARNING! ESD SENSITIVE DEVICE REV. A ADM1027 ADM1027 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description 1 SDA Digital I/O (Open-Drain). SMBus bidirectional serial data. Requires SMBus pull-up. 2 SCL Digital Input (Open-Drain). SMBus serial clock input. Requires SMBus pull-up. 3 GND Ground Pin for the ADM1027 ADM1027. 4 VCC Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. VCC is also monitored through this pin. The ADM1027 ADM1027 can also be powered from a 5 V supply. Setting Bit 7 of Configuration Register 1 (Reg. 0x40) rescales the VCC input attenuators to correctly measure a 5 V supply. 5 VID0 Digital Input (Open-Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). 6 VID1 Digital Input (Open-Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). 7 VID2 Digital Input (Open-Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). 8 VID3 Digital Input (Open-Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). 9 TACH3 Digital Input (Open-Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an analog input (AIN3) to measure the speed of 2-wire fans. 10 PWM2/SMBALERT Digital Output (Open-Drain). Requires 10 kW typical pull-up. Pulsewidth modulated output to control Fan 2 speed. This pin may be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. 11 TACH1 Digital Input (Open-Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an analog input (AIN1) to measure the speed of 2-wire fans. 12 TACH2 Digital Input (Open-Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an analog input (AIN2) to measure the speed of 2-wire fans. 13 PWM3/ADDRESS ENABLE Digital I/O (Open-Drain). Pulsewidth modulated output to control Fan 3 speed. Requires 10 kW typical pull-up. If pulled low on power-up, this places the ADM1027 ADM1027 into address select mode, and the state of Pin 14 will determine the ADM1027 ADM1027's slave address. 14 TACH4/ADDRESS SELECT Digital Input (Open-Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog input (AIN4) to measure the speed of 2-wire fans. If in address select mode, this pin determines the SMBus device address. 15 D2­ Cathode Connection to Second Thermal Diode. 16 D2+ Anode Connection to Second Thermal Diode. 17 D1­ Cathode Connection to First Thermal Diode. 18 D1+ Anode Connection to First Thermal Diode. 19 VID4 Digital Input (Open-Drain). Voltage supply readouts from CPU. This value is read into the VID register (Reg. 0x43). 20 5VIN Analog Input. Monitors 5 V power supply. 21 12VIN 12VIN Analog Input. Monitors 12 V power supply. 22 2.5VIN Analog Input. Monitors 2.5 V supply, typically a chipset voltage. 23 VCCP Analog Input. Monitors processor core voltage (0 V to 3 V). 24 PWM1/XTO Digital Output (Open-Drain). Pulsewidth modulated output to control Fan 1 speed. Requires 10 kW typical pull-up. Also functions as the output from the XOR tree in XOR test mode. REV. A ­5­ ADM1027 ADM1027 FUNCTIONAL DESCRIPTION General Description Internal Registers of the ADM1027 ADM1027 A brief description of the ADM1027 ADM1027's principal internal registers follows. More detailed information on the function of each register is given in Tables IV to XXXVI. The ADM1027 ADM1027 is a complete systems monitor and multiple fan controller for any system requiring monitoring and cooling. The device communicates with the system via a serial system management bus. The serial bus controller has an optional address line for device selection (Pin 14), a serial data line for reading and writing addresses and data (Pin 1), and an input line for the serial clock (Pin 2). All control and programming functions of the ADM1027 ADM1027 are performed over the serial bus. In addition, one of the pins can be reconfigured as an SMBALERT output to indicate out-of-limit conditions. Configuration Registers Provide control and configuration of the ADM1027 ADM1027, including alternate pinout functionality. Address Pointer Register Contains the address that selects one of the other internal registers. When writing to the ADM1027 ADM1027, the first byte of data is always a register address, which is written to the Address Pointer Register. Status Registers Measurement Inputs The device has six measurement inputs, four for voltage and two for temperature. It can also measure its own supply voltage and can measure ambient temperature with its on-chip temperature sensor. Provide the status of each limit comparison and are used to signal out-of-limit conditions on the temperature, voltage, or fan speed channels. If Pin 10 is configured as SMBALERT, then this pin will assert low whenever a status bit gets set. Pins 20 to 23 are analog inputs with on-chip attenuators, configured to monitor 5 V, 12 V, 2.5 V, and the processor core voltage (2.25 V input), respectively. Interrupt Mask Registers Allow each interrupt status event to be masked when Pin 10 is configured as an SMBALERT output. This affects only the SMBALERT output and not the bits in the status register. Power is supplied to the chip via Pin 4, which the system also uses to monitor VCC. In PCs, this pin is normally connected to a 3.3 V standby supply. This pin can, however, be connected to a 5 V supply and monitor it without overranging. VID Register The status of the VID0 to VID4 pins of the processor can be read from this register. Remote temperature sensing is provided by the D1+/­ and D2+/­ inputs, to which diode-connected, external temperaturesensing transistors such as a 2N3906 2N3906 or CPU thermal diode may be connected. Value and Limit Registers The ADC also accepts input from an on-chip band gap temperature sensor that monitors system ambient temperature. Offset Registers The results of analog voltage inputs, temperature, and fan speed measurements are stored in these registers, along with their limit values. Allow each temperature channel reading to be offset by a twos complement value written to these registers. Sequential Measurement TMIN Registers When the ADM1027 ADM1027 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensors. Measured values from these inputs are stored in value registers. These can be read out over the serial bus, or can be compared with programmed limits stored in the limit registers. The results of out-of-limit comparisons are stored in the status registers, which can be read over the serial bus to flag out-of-limit conditions. Program the starting temperature for each fan under automatic fan speed control. TRANGE Registers Program the temperature-to-fan speed control slope in automatic Fan Speed Control Mode for each PWM output. Enhance Acoustics Registers Allow each PWM output controlling fan to be tweaked to enhance the system's acoustics. Processor Voltage ID Five digital inputs (VID0 to VID4 - Pins 5 to 8 and 19) read the processor Voltage ID code and store it in the VID register, from which it can be read out by the management system over the serial bus. The VID code monitoring function is compatible with both VRM9.x and future VRM10 VRM10 solutions. The VID code monitoring function is compatible with VRM9.x. ADM1027 ADM1027 Address Selection Pin 13 is the dual function PWM3/ADDRESS ENABLE pin. If Pin 13 is pulled low on power-up, the ADM1027 ADM1027 will read the state of Pin 14 (TACH4/ADDRESS SELECT pin) to determine the ADM1027 ADM1027 slave address. If Pin 13 is high on power-up, then the ADM1027 ADM1027 will default to SMBus slave address 0x5C. This function is described later in more detail. ­6­ REV. A Typical Performance Characteristics­ADM1027 ADM1027 10 DXP TO GND 0 ­5 DXP TO VCC (3.3V) ­10 ­15 ­20 1.0 10.0 30.0 3.3 LEAKAGE RESISTANCE (M) LOCAL TEMPERATURE ERROR (C) REMOTE TEMPERATURE ERROR (C) 8.0 250mV 4.0 2.0 100mV 5M 550k FREQUENCY (Hz) REMOTE TEMPERATURE ERROR (C) REMOTE TEMPERATURE ERROR (C) 20mV 10.0 8.0 10mV 4.0 2.0 0 1M 10M FREQUENCY (Hz) 50M TPC 7. Remote Temperature Error vs. Differential Mode Noise Frequency REV. A ­27 ­30 ­33 2.2 3.3 4.7 10.0 22.0 DXP ­ DXN CAPACITANCE (nF) 2 1 +3 SIGMA 0 ­1 ­3 SIGMA ­2 ­3 ­40 47.0 0 40 80 TEMPERATURE (C) 120 TPC 3. Remote Temperature Error vs. Actual Temperature 1.90 1.85 10.0 7.5 250mV 5.0 2.5 0 100mV 1.80 1.75 1.70 1.65 1.60 1.55 1.50 ­2.5 1.45 5M 550k FREQUENCY (Hz) 50M 40.0 12.0 ­2.0 60k 110k ­24 TPC 5. Local Temperature Error vs. Power Supply Noise Frequency 16.0 6.0 ­21 ­5.0 100k 50M TPC 4. Remote Temperature Error vs. Power Supply Noise Frequency 14.0 ­18 12.5 10.0 ­2.0 100k ­15 TPC 2. Remote Temperature Error vs. Capacitance between D+ and D­ 12.0 0 ­9 ­12 1 14.0 6.0 REMOTE TEMPERATURE ERROR (C) ­6 ­36 100.0 TPC 1. Remote Temperature Error vs. Leakage Resistance ­3 SUPPLY CURRENT (mA) 5 3 3 0 REMOTE TEMPERATURE ERROR (C) REMOTE TEMPERATURE ERROR (C) REMOTE TEMPERATURE ERROR (C) 15 35.0 100mV 30.0 25.0 20.0 15.0 10.0 40mV 5.0 20mV 0 ­5.0 ­10.0 10k 100k 1M 10M FREQUENCY (Hz) TPC 8. Remote Temperature Error vs. Common Mode Noise Frequency ­7­ 1.40 2.60 3.00 3.40 3.80 4.20 4.60 5.00 5.40 2.50 5.50 TPC 6. Supply Current vs. Supply Voltage ADM1027 ADM1027 SERIAL BUS INTERFACE VCC Control of the ADM1027 ADM1027 is carried out using the serial System Management Bus (SMBus). The ADM1027 ADM1027 is connected to this bus as a slave device, under the control of a master controller. ADM1027 ADM1027 ADDR_SEL The ADM1027 ADM1027 has a 7-bit serial bus address. When the device is powered up with Pin 13 (PWM3/ADDRESS ENABLE) high, the ADM1027 ADM1027 will have a default SMBus address of 0101110 or 0x5C. If more than one ADM1027 ADM1027 is to be used in a system, then each ADM1027 ADM1027 should be placed in address select mode by strapping Pin 13 low on power-up. The logic state of Pin 14 then determines the device's SMBus address. 13 PWM3/ADDR_EN Pin 14 State 0 0 1 Low (10 kW to GND) High (10 kW pull-up) Don't Care Figure 5. Unpredictable SMBus Address if Pin 13 is Unconnected Care should be taken to ensure that Pin 13 (PWM3/ ADDR_EN) is either tied high or low. Leaving Pin 13 floating could cause the ADM1027 ADM1027 to power up with an unexpected address. Address 0101100 (0x58) 0101101 (0x5A) 0101110 (0x5C) (default) Note that if the ADM1027 ADM1027 is placed into address select mode, Pins 13 and 14 can be used as their alternate functions once address assignment has taken place (PWM3, TACH4). Care should be taken using muxes to connect in the appropriate circuit at the appropriate time. VCC ADM1027 ADM1027 ADDR_SEL The serial bus protocol operates as follows: 14 10k 1. The master initiates data transfer by establishing a start condition, defined as a high to low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus the R/W bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. 13 PWM3/ADDR_EN ADDRESS = 0x5C Figure 2. Default SMBus Address = 0x5C ADM1027 ADM1027 ADDR_SEL 10k 14 The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. 13 PWM3/ADDR_EN ADDRESS = 0x58 Figure 3. SMBus Address = 0x58 (Pin 14 = 0) The device address is sampled and latched on the first valid SMBus transaction, so any attempted addressing changes made thereafter will have no immediate effect. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. The facility to make hardwired changes to the SMBus slave address allows the user to avoid conflicts with other devices sharing the same serial bus (for example, if more than one ADM1027 ADM1027 is used in a system). Once the SMBus address has been assigned, these pins return to their original function. However, since the circuits required to set up the SMBus address are unworkable with the PWM and TACH circuits, it would require the use of muxes to switch in and out the correct circuit at the correct time. 3. When all data bytes have been read or written, stop conditions are established. In write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. VCC ADM1027 ADM1027 ADDR_SEL PWM3/ADDR_EN NC DO NOT LEAVE ADDR_EN UNCONNECTED! CAN CAUSE UNPREDICTABLE ADDRESSES Table I. ADM1027 ADM1027 Address Select Mode Pin 13 State 10k 14 10k 14 13 ADDRESS = 0x5A Figure 4. SMBus Address = 0x5A (Pin 14 = 1) ­8­ REV. A ADM1027 ADM1027 register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. Any number of bytes of data can be transferred over the serial bus in one operation. However, it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and subsequently cannot be changed without starting a new operation. When reading data from a register, there are two possibilities: 1. If the ADM1027 ADM1027 address pointer register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. This is done by performing a write to the ADM1027 ADM1027 as before, but only sending the data byte containing the register address, as data is not to be written to the register. This is shown in Figure 7. In the case of the ADM1027 ADM1027, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions: To write data to one of the device data registers or read data from it, the address pointer register must be set so the correct data register is addressed, then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, then the write operation contains a second data byte that is written to the register selected by the address pointer register. A read operation is then performed consisting of the serial bus address, R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 8. 2. If the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so Figure 7 can be omitted. This is illustrated in Figure 6. The device address is sent over the bus followed by R/W being set to 0. This is followed by two data bytes. The first data byte is the address of the internal data 1 9 9 1 SCL 0 SDA 1 0 1 1 A0 A1 D6 D7 R/W START BY MASTER D4 D5 D2 D3 D1 D0 ACK. BY ADM1027 ADM1027 ACK. BY ADM1027 ADM1027 FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 1 9 SCL (CONTINUED) D7 SDA (CONTINUED) D4 D5 D6 D2 D3 D1 D0 ACK. BY ADM1027 ADM1027 FRAME 3 DATA BYTE STOP BY MASTER Figure 6. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register 1 9 9 1 SCL SDA 0 1 START BY MASTER 0 1 1 A1 A0 D7 R/W D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM1027 ADM1027 FRAME 1 SERIAL BUS ADDRESS BYTE ACK. BY ADM1027 ADM1027 STOP BY MASTER FRAME 2 ADDRESS POINTER REGISTER BYTE Figure 7. Writing to the Address Pointer Register Only 1 9 9 1 SCL SDA START BY MASTER 0 1 0 1 1 A1 FRAME 1 SERIAL BUS ADDRESS BYTE A0 D7 R/W D6 D5 D4 D3 D2 FRAME 2 DATA BYTE FROM ADM1027 ADM1027 ­9­ D0 NO ACK. BY STOP BY MASTER MASTER Figure 8. Reading Data from a Previously Selected Register REV. A D1 ACK. BY ADM1027 ADM1027 ADM1027 ADM1027 3. 4. 5. 6. 7. 8. Notes 1. It is possible to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register. 2. In Figures 6 to 8, the serial bus address is shown as the default value 01011(A1)(A0), where A1 and A0 are set by the address select mode function previously defined. The addressed slave device asserts ACK on SDA. The master sends a command code. The slave asserts ACK on SDA. The master sends a data byte. The slave asserts ACK on SDA. The master asserts a stop condition on SDA to end the transaction. This is illustrated in Figure 10. 1 3. In addition to supporting the send byte and receive byte protocols, the ADM1027 ADM1027 also supports the read byte protocol (see System Management Bus specifications Rev. 2.0 for more information). S 2 3 SLAVE W A ADDRESS 4 5 REGISTER ADDRESS 6 7 8 A DATA A P Figure 10. Single Byte Write to a Register 4. If it is required to perform several read or write operations in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. ADM1027 ADM1027 READ OPERATIONS ADM1027 ADM1027 WRITE OPERATIONS This is useful when repeatedly reading a single register. The register address needs to have been set up previously. In this operation, the master device receives a single byte from a slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the read bit (high). 3. The addressed slave device asserts ACK on SDA. 4. The master receives a data byte. 5. The master asserts NO ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. The ADM1027 ADM1027 uses the following SMBus read protocols: Receive Byte The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADM1027 ADM1027 are discussed below. The following abbreviations are used in the diagrams: S ­ START P ­ STOP R ­ READ W ­ WRITE A ­ ACKNOWLEDGE A ­ NO ACKNOWLEDGE The ADM1027 ADM1027 uses the following SMBus write protocols: In the ADM1027 ADM1027, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. Send Byte In this operation, the master device sends a single command byte to a slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a stop condition on SDA and the transaction ends. 1 S 2 3 SLAVE S W A ADDRESS 4 REGISTER ADDRESS 5 6 A P The SMBALERT output can be used as an interrupt output or can be used as an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device's SMBALERT line goes low, the following procedure occurs: Figure 9. Setting a Register Address for Subsequent Read In this operation, the master device sends a command byte and one data byte to the slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). SLAVE R A DATA ADDRESS 5 Alert Response Address (ARA) is a feature of SMBus devices, which allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. A P Write Byte 4 Alert Response Address 6 If it is required to read data from the register immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read without asserting an intermediate stop condition. 3 Figure 11. Single Byte Read from a Register For the ADM1027 ADM1027, the send byte protocol is used to write a register address to RAM for a subsequent single byte read from the same address. This is illustrated in Figure 9. 1 2 1. SMBALERT is pulled low. 2. Master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. 3. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known and it can be interrogated in the usual way. 4. If more than one device's SMBALERT output is low, the one with the lowest device address will have priority, in accordance with normal SMBus arbitration. ­10­ REV. A ADM1027 ADM1027 5. Once the ADM1027 ADM1027 has responded to the alert response address, the master must read the status registers and the SMBALERT will only be cleared if the error condition has gone away. VOLTAGE MEASUREMENT LIMIT REGISTERS Associated with each voltage measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. SMBus Timeout The ADM1027 ADM1027 includes an SMBus timeout feature. If there is no SMBus activity for a minimum of 15 ms and a maximum of 35 ms, the ADM1027 ADM1027 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled. CONFIGURATION REGISTER 1 ­ Register 0x40 Reg. 0x44 2.5 V Low Limit = 0x00 default Reg. 0x45 2.5 V High Limit = 0xFF default Reg. 0x46 VCCP Low Limit = 0x00 default Reg. 0x47 VCCP High Limit = 0xFF default Reg. 0x48 VCC Low Limit = 0x00 default Reg. 0x49 VCC High Limit = 0xFF default TODIS = 0; SMBus timeout enabled (default) TODIS = 1; SMBus timeout disabled Reg. 0x4A 5 V Low Limit = 0x00 default Reg. 0x4B 5 V High Limit = 0xFF default VOLTAGE MEASUREMENT INPUTS Reg. 0x4C 12 V Low Limit = 0x00 default The ADM1027 ADM1027 has four external voltage measurement channels. It can also measure its own supply voltage, VCC. Reg. 0x4D 12 V High Limit = 0xFF default Pins 20 to 23 are dedicated to measuring 5 V, 12 V, 2.5 V supplies and the processor core voltage VCCP (0 V to 3 V input). The VCC supply voltage measurement is carried out through the VCC pin (Pin 4). Setting Bit 7 of Configuration Register 1 (Reg. 0x40) allows a 5 V supply to power the ADM1027 ADM1027 and be measured without overranging the VCC measurement channel. The 2.5 V input can be used to monitor a chipset supply voltage in computer systems. 12VIN 12VIN 120k 20k 5VIN 30pF 93k 47k 30pF 68k ANALOG-TO-DIGITAL CONVERTER 3.3VIN All analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the inputs have built-in attenuators to allow measurement of 2.5 V, 3.3 V, 5 V, 12 V and the processor core voltage VCCP, without any external components. To allow for the tolerance of these supply voltages, the ADC produces an output of 3/4 full scale (768 decimal or 300 hex) for the nominal input voltage, and so has adequate headroom to cope with overvoltages. 71k 2.5VIN 30pF MUX 45k 94k 30pF 35k VCCPIN 105k 35pF INPUT CIRCUITRY The internal structure for the analog inputs is shown in Figure 12. Each input circuit consists of an input protection diode, an attenuator, and a capacitor to form a first order low-pass filter that gives the input immunity to high frequency noise. VOLTAGE MEASUREMENT REGISTERS Reg. 0x20 2.5 V Reading = 0x00 default Reg. 0x21 VCCP Reading = 0x00 default Figure 12. Structure of Analog Inputs Table II shows the input ranges of the analog inputs and output codes of the 10-bit A/D converter. When the ADC is running, it samples and converts a voltage input in 711 ms, and averages 16 conversions to reduce noise. Therefore a measurement on any input takes nominally 11.38 ms. Reg. 0x22 VCC Reading = 0x00 default Reg. 0x23 5 V Reading = 0x00 default Reg. 0x24 12 V Reading = 0x00 default REV. A ­11­ ADM1027 ADM1027 Table II. 10-Bit A/D Output Code vs. V IN Input Voltage A/D Output 12 VIN 5 VIN VCC (3.3 VIN)* 2.5 VIN VCCPIN Decimal Binary (10 Bits) 2.9970 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 11111101 01 11111101 10 11111101 11 11111110 00 11111110 01 11111110 10 11111110 11 11111111 00 11111111 01 11111111 10 11111111 11 *The VCC output codes listed assume that V CC is 3.3 V. If V CC input is reconfigured for 5 V operation (by setting Bit 7 of Configuration Register 1), then the V CC output codes are the same as for the 5 V IN column. ­12­ REV. A ADM1027 ADM1027 VID CODE MONITORING Single-Channel ADC Conversions The ADM1027 ADM1027 has five dedicated voltage ID (VID code) inputs. These are digital inputs that can be read back through the VID register (Reg. 0x43) to determine the processor voltage required/being used in the system. Five VID code inputs support VRM9.x solutions. Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADM1027 ADM1027 into single-channel ADC conversion mode. In this mode, the ADM1027 ADM1027 can be made to read a single voltage channel only. If the internal ADM1027 ADM1027 clock is used, the selected input will be read every 711 ms. The appropriate ADC channel is selected by writing to Bits of TACH1 minimum high byte register (0x55). VID CODE REGISTER ­ Register 0x43 = VID0 (reflects logic state of Pin 5) Bits Reg. 0x55 000 001 010 011 100 = VID1 (reflects logic state of Pin 6) = VID2 (reflects logic state of Pin 7) = VID3 (reflects logic state of Pin 8) = VID4 (reflects logic state of Pin 19) Channel Selected 2.5 V VCCP VCC 5V 12 V Configuration Register 2 (Reg. 0x73) ADDITIONAL ADC FUNCTIONS = 1 Averaging off = 1 Bypass input attenuators = 1 Single-channel convert mode A number of other functions are available on the ADM1027 ADM1027 to offer the systems designer increased flexibility: Turn Off Averaging For each voltage measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. There may be an instance where the user would like to speed up conversions. Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns averaging off. This effectively gives a reading 16¥ faster than 711 ms, but the reading may be noisier. TACH1 Minimum High Byte (Reg. 0x55) Selects ADC channel for single-channel convert mode Bypass Voltage Input Attenuators Setting Bit 5 of Configuration Register 2 (Reg. 0x73) removes the attenuation circuitry from the 2.5 V, VCCP, VCC, 5 V, and 12 V inputs. This allows the user to directly connect external sensors or rescale the analog voltage measurement inputs for other applications. The input range of the ADC without the attenuators is 0 V to 2.25 V. REV. A ­13­ ADM1027 ADM1027 TEMPERATURE MEASUREMENT SYSTEM Local Temperature Measurement The ADM1027 ADM1027 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip 10-bit ADC. The 8-bit MSB temperature data is stored in the local temp register (Address 0x26). As both positive and negative temperatures can be measured, the temperature data is stored in twos complement format, as shown in Table III. Theoretically, the temperature sensor and ADC can measure temperatures from ­128oC to +127oC with a resolution of 0.25oC. However, this exceeds the operating temperature range of the device (0oC to 105oC), so local temperature measurements outside this range are not possible. Temperature measurement from ­127oC to +127oC is possible using a remote sensor. The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about ­2 mV/oC. Unfortunately, the absolute value of Vbe varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass production. The technique used in the ADM1027 ADM1027 is to measure the change in Vbe when the device is operated at two different currents. This is given by where: DVbe = KT q ¥ ln ( N ) K is Boltzmann's constant. q is charge on the carrier. T is absolute temperature in kelvins. Remote Temperature Measurement N is the ratio of the two currents. The ADM1027 ADM1027 can measure the temperature of two remote diode sensors or diode-connected transistors connected to Pins 15 and 16, or 17 and 18. Figure 13 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors. It could equally well be a discrete transistor such as a 2N3904/06 2N3904/06. VDD I NI IBIAS CPU THERMDA REMOTE SENSING TRANSISTOR D+ VOUT+ THERMDC D­ VOUT­ TO ADC BIAS DIODE LOW-PASS FILTER fC = 65kHz Figure 13. Signal Conditioning for Remote Diode Temperature Sensors ­14­ REV. A ADM1027 ADM1027 If a discrete transistor is used, the collector will not be grounded, and should be linked to the base. If a PNP transistor is used, the base is connected to the D­ input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D­ input and the base to the D+ input. Figure 14 shows how to connect the ADM1027 ADM1027 to an NPN or PNP transistor for temperature measurement. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D­ input. To measure DVbe, the sensor is switched between operating currents of I and N I. The resulting waveform is passed through a 65 kHz low-pass filter to remove noise, and to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to DVbe. This voltage is measured by the ADC to give a temperature output in 10-bit, twos complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. A remote temperature measurement takes nominally 25.5 ms. The results of remote temperature measurements are stored in 10-bit, twos complement format, as illustrated in Table III. The extra resolution for the temperature measurements is held in the Extended Resolution Register 2 (Reg. 0x77). This gives temperature readings with a resolution of 0.25oC. Table III. Temperature Data Format* Temperature Digital Output (10-Bit) ­128C ­125C ­100C ­75C ­50C ­25C ­10oC 0C +10.25C +25.5C +50.75C +75C +100C +125C +127C 1000 0000 00 1000 0011 00 1001 1100 00 1011 0101 00 1100 1110 00 1110 0111 00 1111 0110 00 0000 0000 00 0000 1010 01 0001 1001 10 0011 0010 11 0100 1011 00 0110 0100 00 0111 1101 00 0111 1111 00 ADM1027 ADM1027 2N3904 2N3904 NPN D­ Figure 14a. Measuring Temperature Using an NPN Transistor ADM1027 ADM1027 D+ 2N3906 2N3906 PNP D­ Figure 14b. Measuring Temperature Using a PNP Transistor NULLING OUT TEMPERATURE ERRORS As CPUs run faster, it is getting more difficult to avoid high frequency clocks when routing the D­/D+ traces around a system board. Even when recommended layout guidelines are followed, there may still be temperature errors attributed to noise being coupled onto the D+/D­ lines. High frequency noise generally has the effect of giving temperature measurements that are too high by a constant amount. The ADM1027 ADM1027 has temperature offset registers at addresses 0x70, 0x71, and 0x72 for the Remote 1, Local, and Remote 2 temperature channels. By doing a one-time calibration of the system, you can determine the offset caused by system board noise and null it out using the offset registers. The offset registers automatically add a twos complement 8-bit reading to every temperature measurement. The LSB adds a 1C offset to the temperature reading so the 8-bit register effectively allows temperature offsets of up to 127C with a resolution of 1C. This ensures that the readings in the temperature measurement registers are as accurate as possible. TEMPERATURE OFFSET REGISTERS Reg. 0x70 Remote 1 Temperature Offset = 0x00 (0C default) Reg. 0x71 Local Temperature Offset = 0x00 (0C default) Reg. 0x72 Remote 2 Temperature Offset = 0x00 (0C default) *Bold denotes 2 LSBs of measurement in Extended Resolution Register 2 (Reg. 0x77) with 0.25 oC resolution. REV. A D+ ­15­ ADM1027 ADM1027 TEMPERATURE MEASUREMENT REGISTERS Single-Channel ADC Conversions Reg. 0x25 Remote 1 Temperature = 0x80 default Reg. 0x26 Local Temperature = 0x80 default Reg. 0x27 Remote 2 Temperature = 0x80 default Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADM1027 ADM1027 into single-channel ADC conversion mode. In this mode, the ADM1027 ADM1027 can be made to read a single temperature channel only. If the internal ADM1027 ADM1027 clock is used, the selected input will be read every 1.4 ms. The appropriate ADC channel is selected by writing to Bits of TACH1 minimum high byte register (Reg. 0x55). Reg. 0x77 Extended Resolution 2 = 0x00 default TDM2 = Remote 2 Temperature LSBs LTMP = Local Temperature LSBs TDM1 = Remote 1 Temperature LSBs Bits Reg 0x55 101 110 111 TEMPERATURE MEASUREMENT LIMIT REGISTERS Associated with each temperature measurement channel are high and low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Channel Selected Remote 1 Temp Local Temp Remote 2 Temp Configuration Register 2 (Reg. 0x73) = 1 Averaging off = 1 Single-channel convert mode Reg. 0x4E Remote 1 Temperature Low Limit = 0x81 default Reg. 0x4F Remote 1 Temperature High Limit = 0x7F default Reg. 0x50 Local Temperature Low Limit = 0x81 default Reg. 0x51 Local Temperature High Limit = 0x7F default Reg. 0x52 Remote 2 Temperature Low Limit = 0x81 default Reg. 0x53 Remote 2 Temperature High Limit = 0x7F default READING TEMPERATURE FROM THE ADM1027 ADM1027 It is important to note that temperature can be read from the ADM1027 ADM1027 as an 8-bit value (with 1C resolution), or as a 10bit value (with 0.25C resolution). If only 1C resolution is required, the temperature readings can be read back at any time and in no particular order. TACH1 Minimum High Byte (Reg. 0x55) Selects ADC channel for single-channel convert mode OVERTEMPERATURE EVENTS Overtemperature events on any of the temperature channels can be detected and dealt with automatically. Registers 0x6A to 0x6C are the THERM limits. When a temperature exceeds its THERM limit, all fans will run at 100% duty cycle. The fans will stay running at 100% until the temperature drops below THERM ­ 4C. THERM LIMIT If the 10-bit measurement is required, this involves a 2-register read for each measurement. The extended resolution register (Reg. 0x77) should be read first. This causes all temperature reading registers to be frozen until all temperature reading registers have been read from. This prevents an MSB reading from being updated while its two LSBs are being read, and vice versa. HYSTERESIS = 4C TEMP FANS 100% Figure 15. THERM Limit Operation ADDITIONAL ADC FUNCTIONS A number of other functions are available on the ADM1027 ADM1027 to offer the systems designer increased flexibility: Turn Off Averaging For each temperature measurement read from a value register, 16 readings have actually been made internally and the results averaged before being placed into the value register. There may be an instance where the user would like to take a very fast measurement, e.g., of CPU temperature. Setting Bit 4 of Configuration Register 2 (Reg. 0x73) turns averaging off. This takes a reading every 13 ms. The measurement itself takes 4 ms. ­16­ REV. A ADM1027 ADM1027 SMBALERT, STATUS, AND MASK REGISTERS SMBALERT CONFIGURATION Pin 10 of the ADM1027 ADM1027 can be configured as either PWM2 or as an SMBALERT output. The SMBALERT output may be used to signal out-of-limit conditions as explained below. The default state of Pin 10 is PWM2. To configure Pin 10 as SMBALERT: Configuration Reg. 3 (Addr = 0x78), Bit 0 = 1 = SMBALERT Configuration Reg. 3 (Addr = 0x78), Bit 0 = 0 = PWM2 = default LIMIT VALUES Associated with each measurement channel on the ADM1027 ADM1027 are high and low limits. These can form the basis of system status monitoring; a status bit can be set for any out-of-limit condition and detected by polling the device. Alternatively, SMBALERT interrupts can be generated to flag a processor or microcontroller of out-of-limit conditions. 8-BIT LIMITS The following is a list of 8-bit limits on the ADM1027 ADM1027: Voltage Limit Registers 16-Bit Limits The fan TACH measurements are 16-bit results. The fan TACH limits are also 16 bits, consisting of a high byte and low byte. Since fans running underspeed or stalled are normally the only conditions of interest, only high limits exist for fan TACHs. Since fan TACH period is actually being measured, exceeding the limit indicates a slow or stalled fan. Fan Limit Registers Reg. 0x54 TACH1 Minimum Low Byte = 0xFF default Reg. 0x55 TACH1 Minimum High Byte = 0xFF default Reg. 0x56 TACH2 Minimum Low Byte = 0xFF default Reg. 0x57 TACH2 Minimum High Byte = 0xFF default Reg. 0x58 TACH3 Minimum Low Byte = 0xFF default Reg. 0x59 TACH3 Minimum High Byte = 0xFF default Reg. 0x5A TACH4 Minimum Low Byte = 0xFF default Reg. 0x5B TACH4 Minimum High Byte = 0xFF default OUT-OF-LIMIT COMPARISONS The ADM1027 ADM1027 will measure all parameters in round-robin format and set the appropriate status bit for out-of-limit conditions. Comparisons are done differently depending on whether the measured value is being compared to a high or low limit. Reg. 0x44 2.5 V Low Limit = 0x00 default Reg. 0x45 2.5 V High Limit = 0xFF default Reg. 0x46 VCCP Low Limit = 0x00 default Reg. 0x47 VCCP High Limit = 0xFF default Reg. 0x48 VCC Low Limit = 0x00 default Reg. 0x49 VCC High Limit = 0xFF default Reg. 0x4A 5 V Low Limit = 0x00 default Reg. 0x4B 5 V High Limit = 0xFF default Reg. 0x4C 12 V Low Limit = 0x00 default Reg. 0x4D 12 V High Limit = 0xFF default HIGH LIMIT: > COMPARISON PERFORMED LOW LIMIT: < OR = COMPARISON PERFORMED Temperature Limit Registers Reg. 0x4E Remote 1 Temp Low Limit = 0x81 default Reg. 0x4F Remote 1 Temp High Limit = 0x7F default Reg. 0x6A Remote 1 THERM Limit = 0x64 default Reg. 0x50 Local Temp Low Limit = 0x81 default Reg. 0x51 Local Temp High Limit = 0x7F default Reg. 0x6B Local THERM Limit = 0x64 default Reg. 0x52 Remote 2 Temp Low Limit = 0x81 default Reg. 0x53 Remote 2 Temp High Limit = 0x7F default Reg. 0x6C Remote 2 THERM Limit = 0x64 default REV. A ­17­ ADM1027 ADM1027 ANALOG MONITORING CYCLE TIME STATUS REGISTER 1 (REG. 0x41) The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1(Reg. 0x40). The ADC measures each analog input in turn and as each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues unless disabled by writing a 0 to Bit 0 of Configuration Register 1. Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and Status Register 2 should be read. Bit 6 (R2T) = 1, Remote 2 temp high or low limit has been exceeded. Bit 5 (LT) = 1, Local temp high or low limit has been exceeded. Since the ADC will normally be left to free-run in this manner, the time taken to monitor all the analog inputs will normally not be of interest as the most recently measured value of any input can be read out at any time. Bit 4 (R1T) = 1, Remote 1 temp high or low limit has been exceeded. Bit 3 (5 V) = 1, 5 V high or low limit has been exceeded. Bit 2 (VCC) = 1, VCC high or low limit has been exceeded. Bit 1 (VCCP) = 1, VCCP high or low limit has been exceeded. For applications where the monitoring cycle time is important, it can easily be calculated. Bit 0 (2.5 V) = 1, 2.5 V high or low limit has been exceeded. The total number of channels measured is Four dedicated supply voltage inputs 3.3 VSTBY or 5 V supply (VCC pin) Local temperature Two remote temperatures STATUS REGISTER 2 (REG. 0x42) Bit 7 (D2) = 1, indicates an open or short on D2+/D2­ inputs. Bit 6 (D1) = 1, indicates an open or short on D2+/D2­ inputs. Bit 5 (FAN4) = 1, indicates Fan 4 has dropped below minimum speed. As mentioned previously, the ADC performs round-robin conversions and takes 11.38 ms for each voltage measurement, 12 ms for a local temperature reading, and 25.5 ms for a remote temperature reading. The total monitoring cycle time for averaged voltage and temperature monitoring is therefore nominally Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below minimum speed. Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum speed. Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum speed. (5 11.38) + 12 + (2 25.5) = 120 ms Bit 1 (OVT) = 1, indicates that a THERM overtemperature limit has been exceeded. Fan TACH measurements are made in parallel and are not synchronized with the analog measurements in any way. Bit 0 (12 V) = 1, 12 V high or low limit has been exceeded. STATUS REGISTERS The results of limit comparisons are stored in Status Registers 1 and 2. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding status register bit will be cleared to 0. If the measurement is out-of-limits, the corresponding status register bit will be set to 1. The state of the various measurement channels may be polled by reading the status registers over the serial bus. When 1, Bit 7 (OOL) of Status Register 1 (Reg. 0x41) means that an out-oflimit event has been flagged in Status Register 2. This means that the user need read only Status Register 2 when this bit is set. Alternatively, Pin 10 can be configured as an SMBALERT output. This will automatically notify the system supervisor of an out-of-limit condition. Reading the status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. Status register bits are "sticky." Whenever a status bit gets set, indicating an out-of-limit condition, it will remain set even if the event that caused it has gone away (until read). The only way to clear the status bit is to read the status register after the event has gone away. Interrupt status mask registers (Reg. 0x74, 0x75) allow individual interrupt sources to be masked from causing an SMBALERT. However, if one of these masked interrupt sources goes outof-limit, its associated status bit will get set in the interrupt status registers. ­18­ REV. A ADM1027 ADM1027 SMBALERT INTERRUPT BEHAVIOR HIGH LIMIT The ADM1027 ADM1027 can be polled for status, or an SMBALERT interrupt can be generated for out-of-limit conditions. It is important to note how the SMBALERT output and status bits behave when writing interrupt handler software. TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT) HIGH LIMIT STICKY STATUS BIT SMBALERT TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT) STICKY STATUS BIT SMBALERT TEMP BACK IN LIMIT (STATUS BIT STAYS SET) INTERRUPT MASK BIT SET INTERRUPT MASK BIT CLEARED (SMBALERT REARMED) TEMP BACK IN LIMIT (STATUS BIT STAYS SET) Figure 17. How Masking the Interrupt Source Affects SMBALERT Output Figure 16. SMBALERT and Status Bit Behavior MASKING INTERRUPT SOURCES Interrupt Mask Registers 1 and 2 are located at Addresses 0x74 and 0x75. These allow individual interrupt sources to be masked out to prevent SMBALERT interrupts. Note that masking an interrupt source prevents only the SMBALERT output from being asserted; the appropriate status bit will be set as normal. Figure 16 shows how the SMBALERT output and sticky status bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition subsides and the status register is read. The status bits are referred to as sticky since they remain set until read by software. This ensures that an out-of-limit event cannot be missed if software is polling the device periodically. Note that the SMBALERT output remains low for the entire duration that a reading is out-of-limit and until the status register has been read. This has implications on how software handles the interrupt. INTERRUPT MASK REGISTER 1 (REG. 0x74) Bit 7 (OOL) = 1, set this bit to 1 to allow masking of interrupts by Status Register 2. If this bit = 0, then setting a bit in Mask Register 2 to 1 will have no effect. Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature. HANDLING SMBALERT INTERRUPTS Bit 5 (LT) = 1, masks SMBALERT for local temperature. To prevent the system from being tied up servicing interrupts, it is recommend to handle the SMBALERT interrupt as follows: Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature. 1. Detect the SMBALERT assertion. Bit 3 (5 V) = 1, masks SMBALERT for 5 V channel. 2. Enter the interrupt handler. Bit 2 (VCC) = 1, masks SMBALERT for VCC channel. 3. Read the status registers to identify the interrupt source. Bit 1 (VCCP) = 1, masks SMBALERT for VCCP channel. 4. Mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (Reg. 0x74, 0x75). Bit 0 (2.5 V) = 1, masks SMBALERT for 2.5 V channel. INTERRUPT MASK REGISTER 2 (REG. 0x75) 5. Take the appropriate action for a given interrupt source. Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors. 6. Exit the interrupt handler. Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors. 7. Periodically poll the status registers. If the interrupt status bit has cleared, reset the corresponding interrupt mask bit to 0. This will cause the SMBALERT output and status bits to behave as shown in Figure 17. Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4. Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3. Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2. Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1. Bit 1 (OVT) = 1, masks SMBALERT for overtemperature (exceeding THERM limits). Bit 0 (12 V) = 1, masks SMBALERT for 12 V channel. REV. A ­19­ ADM1027 ADM1027 FAN DRIVE CIRCUITRY Fan Drive Using PWM Control The ADM1027 ADM1027 uses Pulsewidth Modulation (PWM) to control fan speed. This relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The external circuitry required to drive a fan using PWM control is extremely simple. A single NMOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan being driven. Typical notebook fans draw a nominal 170 mA, so SOT devices can be used where board space is a concern. In desktops, fans can typically draw 250 mA to 300 mA each. If you drive several fans in parallel from a single PWM output or drive larger server fans, the MOSFET will need to handle the higher current requirements. The only other stipulation is that the MOSFET should have a gate voltage drive, VGS < 3.3 V for direct interfacing to the PWM_OUT pin. VGS can be greater than 3.3 V as long as the pull-up on the gate is tied to 5 V. The MOSFET should also have a low on resistance to ensure that there is not significant voltage drop across the FET. This would reduce the voltage applied across the fan and thus the maximum operating speed of the fan. Figure 18 uses a 10 kW pull-up resistor for the TACH signal. This assumes that the TACH signal is open-collector from the fan. In all cases, the TACH signal from the fan must be kept below 5 V maximum to prevent damaging the ADM1027 ADM1027. If in doubt as to whether the fan used has an open-collector or totem pole TACH output, use one of the input signal conditioning circuits shown in the Fan Speed Measurement section. Figure 19 shows a fan drive circuit using an NPN transistor such as a general-purpose MMBT2222 MMBT2222. While these devices are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the fan's current requirements. Ensure that the base resistor is chosen such that the transistor is saturated when the fan is powered on. 12V 10k 10k TACH/AIN 12V FAN 4.7k ADM1027 ADM1027 Figure 18 shows how a 3-wire fan may be driven using PWM control. 12V 12V 3.3V 10k PWM 12V Q1 MMBT2222 MMBT2222 10k 10k TACH/AIN 12V FAN Figure 19. Driving a 3-Wire Fan Using an NPN Transistor 4.7k ADM1027 ADM1027 3.3V 10k PWM Q1 NDT3055L NDT3055L Figure 18. Driving a 3-Wire Fan Using an N-Channel MOSFET ­20­ REV. A ADM1027 ADM1027 NDT3055L NDT3055L MOSFET. Note that since the MOSFET can handle up to 3.5 A, it is simply a matter of connecting another fan directly in parallel with the first. Driving 2 Fans From PWM3 Note that the ADM1027 ADM1027 has four TACH inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is being used in the system, it should be driven from the PWM3 output in parallel with the third fan. Figure 20 shows how to drive two fans in parallel using low cost NPN transistors. Figure 21 is the equivalent circuit using the Care should be taken in designing drive circuits with transistors and FETs to ensure that the PWM pins are not required to source current, and that they sink less than the 8 mA max current specified on the data sheet. 12V 3.3V 3.3V ADM1027 ADM1027 TACH3 TACH4 10k PWM3 2.2k Q1 MMBT3904 MMBT3904 Q2 MMBT2222 MMBT2222 10 10 Q3 MMBT2222 MMBT2222 Figure 20. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors 3.3V 10k TYPICAL TACH4 +V 3.3V ADM1027 ADM1027 10k TYPICAL TACH3 +V TACH 5V OR 12V FAN TACH 5V OR 12V FAN 3.3V 10k TYPICAL PWM3 Q1 NDT3055L NDT3055L Figure 21. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET REV. A ­21­ ADM1027 ADM1027 Driving 2-Wire Fans Tek PreVu [ ] T T Figure 22 shows how a 2-wire fan may be connected to the ADM1027 ADM1027. This circuit allows the speed of a 2-wire fan to be measured even though the fan has no dedicated TACH signal. A series resistor, RSENSE, in the fan circuit converts the fan commutation pulses into a voltage. This is ac-coupled into the ADM1027 ADM1027 through the 0.01 F capacitor. On-chip signal conditioning allows accurate monitoring of fan speed. For fans drawing approximately 200 mA, a 2 W RSENSE value is suitable. For fans that draw more current, such as larger desktop or server fans, RSENSE may be reduced. The smaller RSENSE is the better, since more voltage will be developed across the fan, and the fan will spin faster. Figure 23 shows a typical plot of the sensing waveform at a TACH/AIN pin. The most important thing is that the negative going spikes are more than 250 mV in amplitude. This allows fan speed to be reliably determined. : +250mV @: ­258mV 1 4 Ch1 100mV Ch3 50.0mV Ch2 5.00mV Ch4 50.0mV M 4.00ms A Ch1 T ­2.00mV ­1.00000ms Figure 23. Fan Speed Sensing Waveform at TACH/AIN Pin +V Laying Out for 2-Wire and 3-Wire Fans ADM1027 ADM1027 5V OR 12V FAN 3.3V 10k TYPICAL Figure 24 shows how to lay out a common circuit arrangement for 2-wire and 3-wire fans. Some components will not be populated depending on whether a 2-wire or 3-wire fan is being used. Q1 NDT3055L NDT3055L PWM 12V OR 5V 0.01F TACH/AIN R1 RSENSE 2 TYPICAL 3.3V OR 5V R2 R5 Figure 22. Driving a 2-Wire Fan PWM Q1 MMBT2222 MMBT2222 C1 TACH/AIN R3 R4 FOR 3-WIRE FANS: POPULATE R1, R2, R3 R4 = 0 C1 = UNPOPULATED FOR 2-WIRE FANS: POPULATE R4, C1 R1, R2, R3 UNPOPULATED Figure 24. Planning for 2-Wire or 3-Wire Fans on a PCB ­22­ REV. A ADM1027 ADM1027 With a pull-up voltage of 12 V and pull-up resistor less than 1 kW, suitable values for R1 and R2 would be 100 kW and 47 kW. This will give a high input voltage of 3.83 V. FAN SPEED MEASUREMENTS TACH Inputs Pins 11, 12, 9, and 14 are open-drain TACH inputs intended for fan speed measurement. 5V OR 12V Signal conditioning in the ADM1027 ADM1027 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 5 V, even where VCC is less than 5 V. In the event that these inputs are supplied from fan outputs that exceed 0 V to 5 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. VCC FAN PULL-UP TYP VCC or Totem-Pole Output, Clamped with Zener and Resistor VCC 5V OR 12V 5V OR 12V FAN VCC FAN PULL-UP 4.7k TYP ADM1027 ADM1027 TACHO OUTPUT TACH X FAN SPEED COUNTER ADM1027 ADM1027 PULL-UP TYP VCC or Totem-Pole Output, Attenuated with R1/R2 Fan Speed Measurement The fan counter does not count the fan TACH output pulses directly because the fan speed may be less than 1000 RPM and it would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 90 kHz oscillator into the input of a 16-bit counter for N periods of the fan TACHO output (Figure 26), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. ZD1* CLOCK *CHOOSE ZD1 VOLTAGE APPROX 0.8 VCC PWM Figure 25b. Fan with TACH Pull-Up to Voltage > 5 V (e.g., 12 V) Clamped with Zener Diode TACH If the fan has a strong pull-up (less than 1 k) to 12 V, or a totem-pole output, then a series resistor can be added to limit the Zener current, as shown in Figure 25c. Alternatively, a resistive attenuator may be used, as shown in Figure 25d. 1 2 3 4 R1 and R2 should be chosen such that 2 V < VPULLUP ¥ R2 ( RPULLUP + R1 + R2) > 5 V The fan inputs have an input resistance of nominally 160 kW to ground; this should be taken into account when calculating resistor values. REV. A Figure 26. Fan Speed Measurement N, the number of pulses counted, is determined by the settings of Register 0x7B (fan pulses per revolution register). This register contains two bits for each fan, allowing 1, 2 (default), 3, or 4 TACH pulses to be counted. ­23­ ADM1027 ADM1027 Fan Speed Measurement Registers Fan Speed Measurement Rate The fan tachometer readings are 16-bit values consisting of a 2-byte read from the ADM1027 ADM1027. The fan TACH readings are normally updated once every second. Reg. 0x28 TACH1 Low Byte = 0x00 default Reg. 0x29 TACH1 High Byte = 0x00 default The fast bit (Bit 3) of Configuration Register 3 (Reg. 0x78), when set, updates the fan TACH readings every 250 ms. Reg. 0x2C TACH3 Low Byte = 0x00 default If any of the fans are not being driven by a PWM channel but are powered directly from 5 V or 12 V, their associated dc bit in Configuration Register 3 should be set. This allows TACH readings to be taken on a continuous basis for fans connected directly to a dc source. Reg. 0x2D TACH3 High Byte = 0x00 default Calculating Fan Speed Reg. 0x2A TACH2 Low Byte = 0x00 default Reg. 0x2B TACH2 High Byte = 0x00 default Reg. 0x2E TACH4 Low Byte = 0x00 default Reg. 0x2F TACH4 High Byte = 0x00 default Reading Fan Speed From the ADM1027 ADM1027 If fan speeds are being measured, this involves a 2-register read for each measurement. The low byte should be read first. This causes the high byte to be frozen until both high and low byte registers have been read from. This prevents erroneous TACH readings. The fan tachometer reading registers report back the number of 11.11 s period clocks (90 kHz oscillator) gated to the fan speed counter, from the rising edge of the first fan TACH pulse to the rising edge of the third fan TACH pulse (assuming two pulses per revolution are being counted). Since the device is essentially measuring the fan TACH period, the higher the count value, the slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates that the fan either has stalled or is running very slowly (< 100 RPM). HIGH LIMIT: > COMPARISON PERFORMED Since actual fan TACH period is being measured, exceeding a fan TACH limit by 1 will set the appropriate status bit and can be used to generate an SMBALERT. Fan Tach Limit Registers The fan TACH limit registers are 16-bit values consisting of two bytes. Reg. 0x54 TACH1 Minimum Low Byte = 0xFF default Reg. 0x55 TACH1 Minimum High Byte = 0xFF default Reg. 0x56 TACH2 Minimum Low Byte = 0xFF default Assuming a fan with 2 pulses/revolution (and 2 pulses/rev being measured), fan speed is calculated by: Fan Speed ( RPM ) = (90, 000 ¥ 60) Fan Tach Reading where Fan Tach Reading = 16-bit fan tachometer reading. Example: TACH1 high byte (Reg. 0x29) = 0x17 TACH1 low byte (Reg. 0x28) = 0xFF What is Fan 1 speed in RPM? Fan 1 TACH reading = 0x17FF = 6143 decimal RPM = (f ¥ 60)/fan 1 TACH reading RPM = (90000 ¥ 60)/6143 Fan Speed = 879 RPM FAN PULSES PER REVOLUTION Different fan models can output either 1, 2, 3, or 4 TACH pulses per revolution. Once the number of fan TACH pulses has been determined, it can be programmed into the fan pulses per revolution register (Reg. 0x7B) for each fan. Alternatively, this register can be used to determine the number or pulses/ revolution output by a given fan. By plotting fan speed measurements at 100% speed with different pulses/rev setting, the smoothest graph with the lowest ripple determines the correct pulses/rev value. Fan Pulses Per Revolution Register FAN1 default = 2 pulses/rev FAN2 default = 2 pulses/rev FAN3 default = 2 pulses/rev FAN4 default = 2 pulses/rev Reg. 0x57 TACH2 Minimum High Byte = 0xFF default 00 = 1 pulse/rev Reg. 0x58 TACH3 Minimum Low Byte = 0xFF default 01 = 2 pulses/rev Reg. 0x59 TACH3 Minimum High Byte = 0xFF default 10 = 3 pulses/rev Reg. 0x5A TACH4 Minimum Low Byte = 0xFF default 11 = 4 pulses/rev Reg. 0x5B TACH4 Minimum High Byte = 0xFF default ­24­ REV. A ADM1027 ADM1027 2-Wire Fan Speed Measurements PWM1 CONFIGURATION (REG. 0x5C) The ADM1027 ADM1027 is capable of measuring the speed of 2-wire fans, i.e., fans without TACH outputs. To do this, the fan must be interfaced as shown in the Fan Drive Circuitry section of the data sheet. In this case, the TACH inputs need to be reprogrammed as analog inputs, AIN. SPIN CONFIGURATION REGISTER 2 (REG. 0x73) Bit 3 (AIN4) = 1, Pin 14 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. Bit 2 (AIN3) = 1, Pin 9 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. These bits control the start-up timeout for PWM1. 000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec PWM2 CONFIGURATION (REG. 0x5D) SPIN Bit 1 (AIN2) = 1, Pin 12 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. Bit 0 (AIN1) = 1, Pin 11 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. These bits control the start-up timeout for PWM2. 000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec FAN SPIN-UP PWM3 CONFIGURATION (REG. 0x5E) The ADM1027 ADM1027 has a unique fan spin-up function. It will spin the fan at 100% PWM duty cycle until two TACH pulses are detected on the TACH input. Once two pulses have been detected, the PWM duty cycle will go to the expected running value, e.g., 33%. The advantage of this is that fans have different spin-up characteristics and will take different times to overcome inertia. The ADM1027 ADM1027 just runs the fans fast enough to overcome inertia and will be quieter on spin-up than fans programmed to spin up for a given spin-up time. SPIN These bits control the start-up timeout for PWM3. 000 = No startup timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec Disabling Fan Start-Up Timeout FAN START-UP TIMEOUT To prevent false interrupts being generated as a fan spins up (since it is below running speed), the ADM1027 ADM1027 includes a fan start-up timeout function. This is the time limit allowed for two TACH pulses to be detected on spin-up. For example, if 2 seconds fan start-up timeout is chosen, and no TACH pulses occur within 2 seconds of the start of spin-up, a fan fault is detected and flagged in the interrupt status registers. REV. A Although fan start-up makes fan spin-ups much quieter than fixed-time spin-ups, the option is there to use fixed spin-up times. Bit 5 (FSPDIS) = 1 in Configuration Register 1 (Reg. 0x40) disables the spin-up for two TACH pulses. Instead, the fan will spin up for the fixed time as selected in registers 0x5C to 0x5E. ­25­ ADM1027 ADM1027 MANUAL FAN SPEED CONTROL MODE PWM CONFIGURATION (REG. 0x5C to 0x5E) PWM Logic State BHVR 111 = Manual Mode The PWM outputs can be programmed to be high for 100% duty cycle (noninverted) or low for 100% duty cycle (inverted). PWM1 Configuration (Reg. 0x5C) Once under manual control, each PWM output may be manually updated by writing to Registers 0x30 to 0x32 (PWMx current duty cycle registers). INV Programming the PWM Current Duty Cycle Registers 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle PWM2 Configuration (Reg. 0x5D) INV 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle PWM3 Configuration (Reg. 0x5E) INV 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle PWM Drive Frequency The PWM drive frequency can be adjusted for the application. Registers 0x5F to 0x61 configure the PWM frequency for PWM1 to PWM3, respectively. PWM1 FREQUENCY REGISTERS (REG. 0x5F to 0x61) FREQ 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz Manual Fan Speed Control The ADM1027 ADM1027 allows the duty cycle of any PWM output to be manually adjusted. This can be useful if you want to change fan speed in software or want to adjust PWM duty cycle output for test purposes. Bits of Registers 0x5C to 0x5E (PWM configuration) control the behavior of each PWM output. The PWM current duty cycle registers are 8-bit registers that allow the PWM duty cycle for each output to be set anywhere from 0% to 100%. This allows the PWM duty cycle to be set in steps of 0.39%. The value to be programmed into the PWMMIN register is given by Value (decimal ) = PWM MIN 0.39 Example 1: for a PWM duty cycle of 50%, Value (decimal) = 50/0.39 = 128 decimal Value = 128 decimal or 80 hex. Example 2: for a PWM duty cycle of 33%, Value (decimal) = 33/0.39 = 85 decimal Value = 85 decimal or 54 hex. PWM Duty Cycle Registers Reg. 0x30 PWM1 Duty Cycle = 0xFF (100% default) Reg. 0x31 PWM2 Duty Cycle = 0xFF (100% default) Reg. 0x32 PWM3 Duty Cycle = 0xFF (100% default) By reading the PWMx current duty cycle registers, you can keep track of the current duty cycle on each PWM output, even when the fans are running in automatic fan speed control mode or acoustic enhancement mode. ­26­ REV. A ADM1027 ADM1027 AUTOMATIC FAN SPEED CONTROL MODE The ADM1027 ADM1027 has a local temperature sensor and two remote temperature channels that may be connected to an on-chip diode-connected transistor on a CPU. These three temperature channels may be used as the basis for automatic fan speed control to drive fans using pulsewidth modulation (PWM). In general, the greater the number of fans in a system, the better the cooling, but to the detriment of system acoustics. Automatic fan speed control reduces acoustic noise by optimizing fan speed according to measured temperature. Reducing fan speed can also decrease system current consumption. The automatic fan speed control mode is very flexible, owing to the number of programmable parameters, including TMIN and TRANGE, as discussed in detail later. The TMIN and TRANGE values chosen for a given fan are critical, since these define the thermal characteristics of the system. The thermal validation of the system is one of the most important steps of the design process, so these values should be carefully selected. The aim of this section is not only to provide the system designer with an understanding of the automatic fan control loop, but also to provide step-by-step guidance as to how to most effectively evaluate and select the critical system parameters. To optimize the system characteristics, the designer needs to give some forethought to how the system will be configured, e.g., the number of fans, where they are located, and what temperatures are being measured in the particular system. The mechanical or thermal engineer who is tasked with the actual system evaluation should also be involved at the beginning of the process. Automatic Fan Control Overview Figure 27 gives a top-level overview of the automatic fan control circuitry on the ADM1027 ADM1027. From a systems-level perspective, up to three system temperatures can be monitored and used to control three PWM outputs. The three PWM outputs can be used to control up to four fans. The ADM1027 ADM1027 allows the speed of four fans to be monitored. The right side of the block diagram shows controls that are fan-specific. The designer has control over individual parameters such as minimum PWM duty cycle, fan speed failure thresholds, and even ramp control of the PWM outputs. This ultimately allows graceful fan speed changes that are less perceptible to the system user. THERMAL CALIBRATION REMOTE 1 TEMP TMIN TRANGE 0% MUX TRANGE 0% TRANGE RAMP CONTROL (ACOUSTIC ENHANCEMENT RAMP CONTROL (ACOUSTIC ENHANCEMENT TACHOMETER 3 AND 4 MEASUREMENT 0% Figure 27. Automatic Fan Control Block Diagram REV. A PWM GENERATOR PWM2 PWM CONFIG PWM MIN 100% TMIN PWM1 TACHOMETER 2 MEASUREMENT THERMAL CALIBRATION REMOTE 2 TEMP PWM GENERATOR PWM CONFIG PWM MIN 100% TMIN RAMP CONTROL (ACOUSTIC ENHANCEMENT TACHOMETER 1 MEASUREMENT THERMAL CALIBRATION LOCAL TEMP PWM CONFIG PWM MIN 100% ­27­ PWM GENERATOR PWM3 ADM1027 ADM1027 3. Use wide tracks to minimize inductance and reduce noise pickup. A 10 mil track minimum width and spacing is recommended. Step 1 Determine the Hardware Configuration Essentially this means choosing whether to use Pin 10 as a PWM2 output or as an SMBALERT output and deciding which SMBus address is to be used. To set Pin 10 as SMBALERT, set Bit 0 of Configuration Register 3 (Addr = 0x78) equal to 1. The default state is PWM2, where this bit equals 0. 4. Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D­ path and at the same temperature. Avoid routing D+/D­ on multiple layers or through vias if possible. These increase series resistance that will cause temperature error. It also refers to the layout recommendations of the ADM1027 ADM1027 on a motherboard, for example. 5. Place a 0.1 mF supply bypass capacitor close to the ADM1027 ADM1027. ADM1027 ADM1027 Placement Considerations Motherboards are electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly the D+/D­ lines of a remote diode sensor. The following precautions should be taken: 1. Place the ADM1027 ADM1027 as close as possible to the remote sensing diode. Provided that the worst noise sources such as clocks and data/address buses are avoided, this distance can be 4 inches to 8 inches. 2. Route the D+ and D­ tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. Do NOT run the D+/D­ lines in different directions. 6. If the distance to the remote sensor is more than 8 inches, the use of shielded twisted pair cable is recommended. This will work up to 100 feet. Connect the twisted pair to D+/D­ and the shield to GND close to the ADM1027 ADM1027. Leave the remote end of the shield unconnected to avoid ground loops. Because the measurement technique uses switched current sources, excessive cable (adds resistance) and/or filter capacitance can affect the measurement. A 1 W series resistance introduces about 0.8oC error. ­28­ REV. A ADM1027 ADM1027 Step 2 Automatic Fan Control Mux Options Configuring the Mux: Which Temperature Controls Which Fan? (BHVR) REGISTERS 0x5C, 0x5D, 0x5E Having decided on the system hardware configuration, the fans can be assigned to particular temperature channels. Not only can fans be assigned to individual channels, but how a fan behaves is configurable. For example, fans can run under automatic fan control, manually (software control), or can run at the fastest speed calculated by multiple temperature channels. The MUX is the bridge between temperature measurement channels and the three PWM outputs. Bits (BHVR bits) of Registers 0x5C, 0x5D, and 0x5E (PWM configuration registers) control the behavior of the fans connected to the PWM1, PWM2, and PWM3 outputs. The values selected for these bits determine how the MUX connects a temperature measurement channel to a PWM output. 000 = Remote 1 temp controls PWMx 001 = Local temp controls PWMx 010 = Remote 2 temp controls PWMx 101 = Fastest speed calculated by local and remote 2 temp controls PWMx 110 = Fastest speed calculated by all three temperature channels controls PWMx The fastest speed calculated options refer to the ability to control one PWM output based on multiple temperature channels. While the thermal characteristics of the three temperature zones can be set up differently, they can drive a single fan. An example would be if the fan turns on when Remote 1 temp exceeds 60C or local temp exceeds 45C. Other Mux Options (BHVR) REGISTERS 0x5C, 0x5D, 0x5E 011 = PWMx runs full-speed (default). 100 = PWMx disabled. 111 = Manual Mode. PWMx is run under software control. In this mode, PWM duty cycle registers (Reg. 0x30 to 0x32) are writable and control the PWM outputs. MUX PWM MIN THERMAL CALIBRATION 100% REMOTE 1 = AMBIENT TEMP TMIN TRANGE 0% PWM MIN 100% MUX TMIN TRANGE 0% THERMAL CALIBRATION 100% TMIN TRANGE PWM GENERATOR TACH1 PWM CONFIG RAMP CONTROL (ACOUSTIC ENHANCEMENT PWM MIN PWM GENERATOR ­29­ FRONT CHASSIS PWM CONFIG RAMP CONTROL (ACOUSTIC ENHANCEMENT PWM GENERATOR Figure 28. Assigning Temperature Channels to Fan Channels REV. A PWM2 TACH2 TACHOMETERS 3 AND 4 MEASUREMENT 0% PWM1 CPU FANSINK TACHOMETER 2 MEASUREMENT REMOTE 2 = CPU TEMP RAMP CONTROL (ACOUSTIC ENHANCEMENT TACHOMETER 1 MEASUREMENT THERMAL CALIBRATION LOCAL = VRM TEMP PWM CONFIG PWM3 TACH3 REAR CHASSIS ADM1027 ADM1027 Step 3 TMIN Registers Determine TMIN Setting for Each Thermal Channel Reg. 0x67 Remote 1 Temperature TMIN = 0x5A (90C default) TMIN is the temperature at which the fans will start to turn on under automatic fan control. The speed at which the fan runs at TMIN is programmed later. The TMIN values chosen will be temperature channel specific, e.g., 25C for ambient channel, 30C for VRM temperature, and 40C for processor temperature. Reg. 0x68 Local Temperature TMIN = 0x5A (90C default) TMIN is an 8-bit twos complement value that can be programmed in 1C increments. There is a TMIN register associated with each temperature measurement channel, Remote 1, Local and Remote 2 Temp. Once the TMIN value is exceeded, the fan turns on and runs at minimum PWM duty cycle. The fan will turn off once temperature has dropped below TMIN ­ THYST (detailed later). To overcome fan inertia, the fan is spun up until two valid TACH rising edges are counted. See the Fan Start-Up Timeout section for more details. In some cases, primarily for psycho-acoustic reasons, it is desirable that the fan never switches off below TMIN. Bits of Enhance Acoustics Register 1 (Reg. 0x62), when set, keep the fans running at PWM minimum duty cycle should the temperature be below TMIN. Reg. 0x69 Remote 2 Temperature TMIN = 0x5A (90C default) Enhance Acoustics Reg 1 (Reg. 0x62) Bit 7 (MIN3) = 0, PWM3 is OFF (0% PWM duty cycle) when temperature is below TMIN ­ THYST. Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle below TMIN ­ THYST. Bit 6 (MIN2) = 0, PWM2 is OFF (0% PWM duty cycle) when temperature is below TMIN ­ THYST. Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle below TMIN ­ THYST. Bit 5 (MIN1) = 0, PWM1 is OFF (0% PWM duty cycle) when temperature is below TMIN ­ THYST. Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle below TMIN ­ THYST. PWM DUTY CYCLE 100% 0% TMIN PWM MIN THERMAL CALIBRATION 100% REMOTE 2 = CPU TEMP TMIN TRANGE 0% MUX TRANGE 0% THERMAL CALIBRATION 100% TMIN TRANGE TACH1 PWM CONFIG RAMP CONTROL (ACOUSTIC ENHANCEMENT PWM GENERATOR PWM2 FRONT CHASSIS TACH2 PWM MIN PWM CONFIG RAMP CONTROL (ACOUSTIC ENHANCEMENT PWM GENERATOR TACHOMETERS 3 AND 4 MEASUREMENT 0% PWM1 CPU FANSINK TACHOMETER 2 MEASUREMENT REMOTE 1 = AMBIENT TEMP PWM GENERATOR PWM MIN 100% TMIN RAMP CONTROL (ACOUSTIC ENHANCEMENT TACHOMETER 1 MEASUREMENT THERMAL CALIBRATION LOCAL = VRM TEMP PWM CONFIG PWM3 TACH3 REAR CHASSIS Figure 29. Understanding TMIN Parameter ­30­ REV. A ADM1027 ADM1027 Step 4 Programming the PWMMIN Registers Determine PWMMIN for Each PWM (Fan) Output The PWMMIN registers are 8-bit registers that allow the minimum PWM duty cycle for each output to be configured anywhere from 0% to 100%. This allows minimum PWM duty cycle to be set in steps of 0.39%. PWMMIN is the minimum PWM duty cycle that each fan in the system will run at. It is also the start speed for each fan under automatic fan control once the temperature rises above TMIN. For maximum system acoustic benefit, PWMMIN should be as low as possible. Starting the fans at higher speeds than necessary will merely make the system louder than needed. Depending on the fan used, the PWMMIN setting should be in the range 20% to 33% duty cycle. This value can be found through fan validation. The value to be programmed into the PWMMIN register is given by Value (decimal ) = PWM MIN 0.39 Example 1: For a minimum PWM Duty Cycle of 50%, Value (decimal) = 50/0.39 = 128 decimal Value = 128 decimal or 80 hex 100% PWM DUTY CYCLE Example 2: For a minimum PWM duty cycle of 33%, Value (decimal) = 33/0.39 = 85 decimal Value = 85 decimal or 54 hex PWMMIN Registers PWMMIN Reg. 0x64 PWM1 Minimum Duty Cycle = 0x80 (50% default) 0% Reg. 0x65 PWM2 Minimum Duty Cycle = 0x80 (50% default) TMIN Reg. 0x66 PWM3 Minimum Duty Cycle = 0x80 (50% default) TEMPERATURE Figure 30. PWMMIN Determines Minimum PWM Duty Cycle It is important to note that more than one PWM output can be controlled from a single temperature measurement channel. For example, Remote 1 temperature can control PWM1 and PWM2 outputs. If two different fans are used on PWM1 and PWM2, then the fan characteristics can be set up differently. So Fan 1 driven by PWM1 can have a different PWMMIN value than that of Fan 2 connected to PWM2. Figure 31 illustrates this as PWM1MIN (front fan) is turned on at a minimum duty cycle of 20%, whereas PWM2MIN (rear fan) turns on at a minimum of 40% duty cycle. Note however, that both fans turn on at the exact same temperature, defined by TMIN. Fan Speed and PWM Duty Cycle Note that PWM duty cycle does not directly correlate to fan speed in rpm. Running a fan at 33% PWM duty cycle does not equate to running the fan at 33% speed. Driving a fan at 33% PWM duty cycle actually runs the fan at closer to 50% of its full speed. This is because fan speed in %rpm relates to the square root of PWM duty cycle. Given a PWM square wave as the drive signal, fan speed in RPM equates to PWM DUTY CYCLE 100% M2 PW M1 PW PWM2MIN PWM1MIN 0% TMIN TEMPERATURE Figure 31. Operating Two Different Fans from a Single-Temperature Channel REV. A ­31­ % fan speed = PWM duty cycle ¥ 10 ADM1027 ADM1027 Determine TRANGE for Each Temperature Channel TRANGE is the range of temperature over which automatic fan control occurs once the programmed TMIN temperature has been exceeded. TRANGE is actually a temperature slope and not an arbitrary value, i.e., a TRANGE of 40C only holds true for PWMMIN = 33%. If PWMMIN is increased or decreased, the effective TRANGE is changed, as described later. TRANGE is implemented as a slope, which means as PWMMIN is changed, TRANGE changes, but the actual slope remains the same. The higher the PWMMIN value, the smaller the effective TRANGE will be, i.e., the fan will reach full speed (100%) at a lower temperature. 100% PWM DUTY CYCLE Step 5 TRANGE PWM DUTY CYCLE 100% 50% 33% 25% 10% 0% 30C 40C 45C 54C PWMMIN 0% TMIN TMIN TEMPERATURE Figure 34. Increasing PWMMIN Changes Effective TRANGE Figure 32. TRANGE Parameter Affects Cooling Slope The TRANGE or fan control slope is determined by the following procedure: For a given TRANGE value, the temperature at which the fan will run full-speed for different PWMMIN values can easily be calculated: 1. Determine the maximum operating temperature for that channel, e.g., 70C. where: 2. Determine experimentally the fan speed (PWM duty cycle value) will not exceed that temperature at the worst-case operating points, e.g., 70C is reached when the fans are running at 50% PWM duty cycle. TMAX = TMIN + ( MaxD.C. - MinD.C.) ¥ TRANGE 170 TMAX = Temperature at which the fan runs full-speed TMIN = Temperature at which the fan will turn on MaxD.C. = Maximum duty cycle (100%) = 255 decimal 3. Determine the slope of the required control loop to meet these requirements. MinD.C. = PWMMIN 4. Use best fit approximation to determine the most suitable TRANGE value. There is ADM1027 ADM1027 evaluation software available to calculate the best fit value; ask your local Analog Devices representative for more details. Example: Calculate TMAX, given TMIN = 30C, TRANGE = 40C, and PWMMIN = 10% duty cycle = 26 decimal TMAX = TMIN + ( MaxD.C . - MinD.C .) ¥ TRANGE 170 TMAX = 30C + (100% - 10%) ¥ 40C 170 TMAX = 30C + (255 - 26) ¥ 40C 170 100% PWM DUTY CYCLE TRANGE = PWM duty cycle versus temperature slope TMAX = 84C (effective TRANGE = 54C) Example: Calculate TMAX, given TMIN = 30C, TRANGE = 40C and PWMMIN = 25% duty cycle = 64 decimal 50% TMAX = TMIN + ( MaxD.C . - MinD.C .) ¥ TRANGE 170 33% TMAX = 30C + (100% - 25%) ¥ 40C 170 0% 30C 40C TMAX = 30C + (255 - 64) ¥ 40C 170 TMAX = 75C (effective TRANGE = 45C) TMIN Figure 33. Adjusting PWMMIN Affects TRANGE ­32­ REV. A ADM1027 ADM1027 Example: Calculate TMAX, given TMIN = 30C, TRANGE = 40C, and PWMMIN = 33% duty cycle = 85 decimal Bits * TMAX = TMIN + ( MaxD.C . - MinD.C .) ¥ TRANGE 170 TMAX = 30C + (100% - 33%) ¥ 40C 170 TMAX = 30C + (255 - 85) ¥ 40C 170 TMAX = 70C (effective TRANGE = 40C) Example: Calculate TMAX, given TMIN = 30C, TRANGE = 40C, and PWMMIN = 50% duty cycle = 128 decimal TMAX = TMIN + ( MaxD.C . - MinD.C .) ¥ TRANGE 170 TMAX = 30C + (100% - 50%) ¥ 40C 170 TMAX = 30C + (255 - 128) ¥ 40C 170 TMAX = 60C (effective TRANGE = 30C) Selecting a TRANGE Slope The TRANGE value can be selected for each temperature channel: Remote 1, Local and Remote 2 Temp. Bits (TRANGE) of Registers 0x5F to 0x61 define the TRANGE value for each temperature channel. REV. A TRANGE (C) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 2 2.5 3.33 4 5 6.67 8 10 13.33 16 20 26.67 32 (default) 40 53.33 80 * Register 0x5F configures remote 1 T RANGE. Register 0x60 configures local T RANGE. Register 0x61 configures remote 2 T RANGE. ­33­ ADM1027 ADM1027 Step 6 Determine TTHERM for Each Temperature Channel TTHERM is the absolute maximum temperature allowed on a temperature channel. Above this temperature, a component such as the CPU or VRM may be operating beyond its safe operating limit. When the measured temperature exceeds TTHERM, all fans are driven at 100% PWM duty cycle (full speed) to provide critical system cooling. The fans remain running at 100% until the temperature drops below TTHERM ­ hysteresis. The hysteresis value is 4C. The TTHERM limit should be considered the maximum worstcase operating temperature of the system. Since exceeding any TTHERM limit runs all fans at 100%, it has very negative acoustic effects. Ultimately, this limit should be set up as a fail-safe, and the user should ensure that it is not exceeded under normal system operating conditions. Note that the TTHERM limits are nonmaskable and affect the fan speed no matter what automatic fan control settings are configured. This allows some flexibility since a TRANGE value can be selected based on its slope, while a hard limit, e.g., 70C, can be programmed as TMAX (the temperature at which the fan reaches full speed) by setting TTHERM to 70C. THERM hysteresis is 4C. THERM Registers Reg. 0x6A Remote 1 THERM Limit = 0x64 (100C default) Reg. 0x6B Local Temperature THERM Limit = 0x64 (100C default) Reg. 0x6C Remote 2 THERM Limit = 0x64 (100C default) TRANGE PWM DUTY CYCLE 100% 0% TTHERM TMIN PWM MIN THERMAL CALIBRATION 100% REMOTE 2 = CPU TEMP TMIN TRANGE 0% PWM MIN 100% MUX TMIN TRANGE 0% THERMAL CALIBRATION 100% TMIN TRANGE PWM GENERATOR TACH1 PWM CONFIG RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM MIN PWM GENERATOR PWM2 FRONT CHASSIS TACH2 PWM CONFIG RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETERS 3 AND 4 MEASUREMENT 0% PWM1 CPU FANSINK TACHOMETER 2 MEASUREMENT REMOTE 1 = AMBIENT TEMP RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 1 MEASUREMENT THERMAL CALIBRATION LOCAL = VRM TEMP PWM CONFIG PWM GENERATOR PWM3 TACH3 REAR CHASSIS Figure 35. Understanding How TTHERM Relates to Automatic Fan Control ­34­ REV. A ADM1027 ADM1027 Step 7 Determine THYST for Each Temperature Channel THYST is the amount of extra cooling a fan provides after the measured temperature has dropped back below TMIN before the fan turns off. The premise for temperature hysteresis (THYST) is that without it, the fan would merely chatter, or cycle on and off regularly, whenever the temperature is hovering about the TMIN setting. The THYST value chosen will determine the amount of time needed for the system to cool down or heat up, as the fan is turning on and off. Values of hysteresis are programmable in the range 1C to 15C. Larger values of THYST prevent the fans chattering on and off as previously described. The THYST default value is 4C. Hysteresis Registers Note that in some applications it is required that the fans not turn off below TMIN, but remain running at PWMMIN. Bits of Enhance Acoustics Register 1 (Reg. 0x62) allow the fans to be turned off or kept spinning below TMIN. If the fans are always on, the THYST value has no effect on the fan whe