ADC1298X 10-BIT 30MSPS AVBB33D AVSS33D AVDD33D AVBB33A AVSS33A AVDD33A - Datasheet Archive

 

0.18µm 10-BIT 30MSPS ADC µ GENERAL DESCRIPTION The ADC1298X is a CMOS 10-bit low-voltage and high-speed A/D converter

 

ADC1298X ADC1298X 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ GENERAL DESCRIPTION The ADC1298X ADC1298X is a CMOS 10-bit low-voltage and high-speed A/D converter (ADC) for video and other applications. It has a four-step pipelined architecture, which consists of sample & hold amplifier, multiplying D/A converters (DACs), and subranging flash ADCs. The maximum conversion rate of ADC1298X ADC1298X is 30MSPS 30MSPS and supply voltage is 3.3V single. FEATURES - Process : CMOS - Resolution : 10-bit - Maximum Conversion Rate : 30MSPS 30MSPS - Power Supply : 3.3V Single - Power Consumption : 60mW - Differential Linearity Error : ± 1.0 LSB (Typ) - Integral Linearity Error : ± 2.0 LSB (Typ) - Internal Sample-and-Hold - Operating Temperature Range : 0 °C ­ 70 °C TYPICAL APPLICATIONS - CCD imaging processors Camcorders, scanners, and security cameras. - Read channel LSI HDD, DVD, and CD-ROM drives - IF and baseband signal digitizers - Portable equipments for low-power applications 1 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X AVBB33D AVBB33D AVSS33D AVSS33D AVDD33D AVDD33D AVBB33A AVBB33A AVSS33A AVSS33A AVDD33A AVDD33A FUNCTIONAL BLOCK DIAGRAM DO[0] (LSB) AIP 3-Bit MDAC SAH AIN 3-Bit MDAC 3-Bit MDAC DO[1] DO[2] DO[3] 4-Bit Flash 3-Bit Flash 3-Bit Flash 3-Bit Flash DO[4] DO[5] DO[6] DO[7] CLK DO[8] Digital Corection Logic STBY SU IT DO[9] (MSB) EOC Bias Current Generator RT RB Clock Generator CML Generator CK CML Ver 1.1 (Apr. 2002) This datasheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. 2 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X CORE PIN DESCRIPTION Name I/O Type I/O Pad Pin Description AIP AI phiar50_abb Analog Input (RB ~ RT) AIN AI phiar50_abb Analog Input (RT ~ RB) STBY DI phicc_abb STandBy (Active High) SU DI phicc_abb SpeedUp (Active High) STC DI phicc_abb STart of Conversion (Active High) CK DI phicc_abb Input Clock (30MHz) DO[9:0] DO phob8_abb Digital Output EOC DO phob8_abb End-Of-Conversion RT AB phoa_abb Reference Top Bias (+2.15V) RB AB phoa_abb Reference Bottom Bias (+1.15V) CML AB phoa_abb Common-Mode Level (+1.65V) IT AB phiar50_abb AVDD33A AVDD33A AP vdd3t_abb Analog Power AVSS33A AVSS33A AG vss3t_abb Analog Ground AVBB33A AVBB33A AG vbb3_abb Analog Substrate Bias AVDD33D AVDD33D DP vdd3t_abb Digital Power AVSS33D AVSS33D DG vss3t_abb Digital Ground AVBB33D AVBB33D DG vbb3_abb Digital Substrate Bias Bias Current Generator Test 100uA in Normal, 10uA in STBY mode I/O Type Abbr. - AI: Analog Input - DI: Digital Input - AO: Analog Output - DO: Digital Output - AB: Analog Bi-direction - DB: Digital Bi-direction - AP: Analog Power - AG: Analog Ground - DP: Digital Power - DG: Digital Ground 3 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X CORE CONFIGURATION AVDD33A AVDD33A AVSS33A AVSS33A AVBB33A AVBB33A DO[0] (LSB) RT RB CML IT AIP DO[1] DO[2] DO[3] DO[4] adc1298x DO[5] DO[6] AIN CK STBY SU STC DO[7] DO[8] DO[9] (MSB) EOC AVDD33D AVDD33D 4 AVSS33D AVSS33D AVBB33D AVBB33D 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit Supply Voltage AVDD33A AVDD33A AVDD33D AVDD33D -0.3 to 4.5 V Analog Input Voltage AIP / AIN -0.3 to AVDD33A AVDD33A+0.3 V Digital Input Voltage CK -0.3 to AVDD33D AVDD33D+0.3 V VOH, VOL -0.3 to AVDD33D AVDD33D+0.3 V Tstg -45 to 125 °C Digital Output Voltage Storage Temperature Range NOTES: 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to AVSS33A/AVSS33D AVSS33A/AVSS33D unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5k resistor (Human body model). RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit Supply Voltage AVDD33A AVDD33A - AVSS33A AVSS33A AVDD33D AVDD33D - AVSS33D AVSS33D 3.15 3.3 3.45 V Supply Voltage Difference AVDD33A AVDD33A - AVDD33D AVDD33D -0.1 0.0 0.1 V RT RB ­ AVSS33A AVSS33A 2.15 1.15 AVDD33A AVDD33A ­ V AIP/AIN RB ­ RT V Tpwh ­ ­ 16.6 16.6 ­ ­ ns ­ 3.0 ­ ­ 0.3 ­ V 0 ­ 70 °C Reference Input Voltage Analog Input Voltage Clock High Time Clock Low Time Digital Input 'L' Voltage Digital Input 'H' Voltage Operating Temperature NOTE: Tp w l VIL VIH Topr It is strongly recommended that all the supply pins (AVDD33A AVDD33A, AVDD33D AVDD33D) be powered from the same source to avoid power latch-up. 5 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit ­ ­ 10 ­ Bits Differential Linearity Error DLE ­ ­ ±1.0 LSB AIP/AIN : RB ­ RT (Ramp Input) Integral Linearity Error ILE ­ ­ ±2.0 LSB FS : 1MHz Resolution Test Conditions 2MHz Reference Current IREF ­ 1.25 2 mA 1.0V/800 = 1.25mA Bottom Offset Voltage Error EOB ­ ­ ±10 LSB EOB = AI(0, 1) - (RB-RT) Top Offset Voltage Error EOT ­ ­ ±10 LSB EOT = (RT-RB) - AI(1022, 1023) NOTES: 1. Converter Specifications (unless otherwise specified) AVDD33A AVDD33A=3.3V AVDD33D AVDD33D=3.3V AVSS33A AVSS33A=GND AVSS33D AVSS33D=GND RT=2.15V RB=1.15V STBY=LOW STC=HIGH SU=LOW Ta = 25°C 2. AI(D1, D2) denotes the net voltage difference between AIP and AIN at the instant when of which the counterpart Digital Output code transits from D1 to D2. AC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Test Conditions Clock High Time Tpwh ­ 16.6 ­ ns ­ Clock Low Time Tp w l ­ 16.6 ­ ns Conversion Rate FS 30 ­ ­ MSPS Dynamic Supply Current IS ­ 18 25 mA IS = (IREF) + I(AVDD33A AVDD33A) + I(AVDD33D AVDD33D) FS : 30MHz Analog Input Range VIN AVSS 2.0 AVDD VPP Analog Input Capacitance CIN ­ 10 ­ pF ­ Analog Input Bandwidth FIN ­ 1 6 MHz ­ Digital Output Data Delay tD ­ 10 ­ ns See "DELAY TIMING DIAGRAM" SNDR1 SNDR2 SNDR3 ­ 48 ­ dB AIN : 1, 2, 4MHz respectively (Sine Input) FS : 30MHz Signal to Noise Distortion Ratio (SNDR) 6 SNDR varies according to VIN 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X OUTPUT MAPPING TABLE Index AIP (V) AIN (V) Digital Output 0 1.15 ~ 1.15+1× LSBD 2.15-1×LSBD ~ 2.15 0000000000 1 1.15+1×LSBD ~1.15+2×LSBD 2.15-2×LSBD ~ 2.15-1×LSBD 0000000001 2 1.15+2×LSBD ~1.15+3×LSBD 2.15-3×LSBD ~ 2.15-2×LSBD 0000000010 ··· ··· ··· ··· 511 1.15+511×LSBD ~1.15+512×LSBD 2.15-512×LSBD ~ 2.15-511×LSBD 0111111111 512 1.15+512×LSBD ~1.15+513×LSBD 2.15-513×LSBD ~ 2.15-512×LSBD 1000000000 513 1.15+513×LSBD ~1.15+514×LSBD 2.15-514×LSBD ~ 2.15-513×LSBD 1000000001 ··· ··· ··· ··· 1021 1.15+1021×LSBD ~1.15+1022×LSBD 2.15-1022×LSBD ~2.15-1021×LSBD 1111111101 1022 1.15+1022×LSBD ~1.15+1023×LSBD 2.15-1023×LSBD ~2.15-1022×LSBD 1111111110 1023 1.15+1023×LSBD ~ 2.15 1.25 ~ 2.15-1023×LSBD 1111111111 NOTES: 1. For Differential Input .AIP = RB ~ RT .AIN = RT ~ RB .1×LSBD = (RT - RB)/1024 = 0.9765mV and for Single Input .AIP = (RT + RB)/2 - (RT - RB) ~ (RT + RB)/2 + (RT - RB) .AIN = (RT + RB)/2 .1×LSBS = 2×(RT - RB)/1024 = 1.9530mV 7 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X DELAY TIMING DIAGRAM AI(3) AI(4) AI(5) AI(6) AI(7) AI(8) AI STC CK td DO DO[0] DO[1] DO[2] DO[3] DO[4] 3 Clock Pipeline Delay 8ns 4ns 8ns 4ns CK STC Tsafe Tsafe NOTES: 1. Digital Output Code, DO[9:0], is renewed only when STC (STart-Of-Conversion) is 'HIGH' and the last code during the STC is 'HIGH' will be kept otherwise. 2. During STC is 'HIGH', ADC1298X ADC1298X generates EOC (End-Of-Conversion) and DO[9:0] with the pipeline delay of 3 clock periods from the instant that the counterpart analog input was sampled. 3. The state transition of STC to 'LOW' will be immediately reflected to DO[9:0] and EOC, while the transition to 'HIGH' requires the same delay as the pipeline delay to ensure the validity of DO[9:0] and EOC. 4. The signal transition of STC is valid only in the Tsafe region, so the setup-hold timing constraints must be carefully taken into consideration on STC generation. 5. Because EOC is generated by STC regardless of the state of STBY, EOC will be toggled normally in spite of STBY 'HIGH' if only STC is 'HIGH'. Do not refer to the EOC while STBY is 'HIGH', because it is invalid in actual although it is toggled normaly with STC 'HIGH'. 8 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X DELAY TIMING DIAGRAM AI(3) AI(a) AI(b) AI(c) AI(d) AI STC CK td DO DO[0] DO[0] Invalid Invalid Invalid DO[a] Invalid DO[a] 3 Clock Pipeline Delay STBY CK td DO DO[0] Invalid Invalid 1us Stablilization Delay EOC NOTES: 1. When STBY goes 'HIGH', the internal circuitry remains active but not operates properly because the current supplied to each internal block is reduced. So although the digital output DO[9:0] seems to be generated normally, it is totally invalid while STBY remains 'HIGH'. 2. When STBY returns to 'LOW', it takes about 1us stabilization time for internal circuitry to stabilize itself and begin to generate vaild outputs. If the current were forced to be zero with STBY 'HIGH', it would take quite longer time than the case we had it small but not zero. That is why we leave some amount of current in low-current mode rather than cutting the current off, and why we call this control signal as 'STBY (STand-BY)' rather than 'PD (Power-Down)'. 9 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X FUNCTIONAL DESCRIPTION 1. ADC1298X ADC1298X is a four-stage pipelined A/D Converter comprising a sample-and-hold, two multiflying DAC (MDAC) and four flash ADC each of which yields 4, 3, 3 and 3 bits. The N-bit flash ADC is composed of 2n latching comparators, and multiplying DAC is composed of N+2 capacitors and a fully-differential amplifier. 2. ADC1298X ADC1298X operates as follows. During the first "Low" cycle of the external clock the analog input data is tracked by the sample-and-holder and sampled at the rising edge of the clock to be converted. The sampled data is fed to the first MDAC and first 4-bit flash ADC which produce 4-bit digital output code corresponding to the sampled analog data. The first MDAC reconstructs the analog voltage corresponding to the first 4-bit flash ADC's digital output, and amplifies, by the gain of 23, the residue voltage which is the voltage difference between the recunstructed voltage and the input voltage of the first MDAC. The 3-bit flash ADC, and MDAC of second to fourth stage operate as the same manner with the first stage but that finally these blocks produce 3-bit digital output codes and amplify a residue voltage by a gain of 22. The respective digital output codes from each of the flash ADCs are fed to the Digital Correction Logic (DCL) to correct the inter-stage conversion error. 3. ADC1298X ADC1298X has the error correction scheme, which handles the offset error which stems from the mismatch between the first, second, third and fourth flash ADC's comparator. BLOCK DESCRIPTION 1. SAH SAH (sample-and-hold) is the circuit which samples the analog input signal and holds the sampled value until the next sampling instant. It is required that the difference between the real analog input signal and the sampled output signal of SAH be as small as it can be to guarantee fidelity of the following 10-bit data conversion process. This SAH consists of fully differential op-amp, switching transistors, and sampling capacitors. The sampling clocks are non-overlapping (Q1, Q2) and sampling capacitance is 1.0pF. SAH uses its own bias circuit to avoid interference from any other blocks and SAH amp is designed to have open-loop dc gain higher than 80dB and phase margin higher than 60 degree. Its input block is designed to be the rail-to-rail architecture using complementary differential pair. 2. FLASH The flash converter compares analog input signal with reference voltages, and the result are transferred to MDAC and digital correction logic block. The comparators inside have a fully differential structure. 3. MDAC MDAC is the most important block next to SAH and it governs the overall performances of ADC as SAH does. MDAC consists of amp, selection logic and capacitor array. Capacitor array is made up of the sampling capacitors and switches to implement D/A conversion process and predefined gain. 10 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X TIMING DIAGRAM A5 A4 AI A6 A7 A8 CK SAH FLASH1 MDAC1 FLASH2 MDAC2 FLASH3 Track Sample Track Sample REF sample Amplify Preset Latch Track Track Sample Track Latch Encode Track AI Residue sample amplify REF sample Amplify Preset Latch Track Latch Encode AI Residue sample amplify REF sample Amplify Preset Latch Track Latch Encode AI Residue sample amplify MDAC3 REF sample FLASH4 Amplify Preset Latch Track Latch Encode Digital Correction DO Sample Track A1 A2 A3 Latch A4 3 Clock Pipeline Delay 11 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X CORE EVALUATION GUIDE - ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. +3.3V Analog Power GND GND AVDD33A AVDD33A RT RB CML IT AIP AVSS33A AVSS33A AVBB33A AVBB33A DO[0] (LSB) DO[1] DO[2] DO[3] DO[4] DO[5] adc1298x AIN CK STBY SU STC MUX DO[6] DO[7] DO[8] Host DSP Core DO[9] (MSB) AVDD33D AVDD33D AVSS33D AVSS33D AVBB33D AVBB33D EOC Bidirectional PAD GND +3.3V Analog Power External Pins Internal Pins 12 : 10µF Electronic Capacitor Unless otherwise specified : 0.1µF Ceramic Capacitor Unless otherwise specified ADC Function Measureing & Digital Input Forcing 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X USER GUIDE 1. Input Signal Range following Signal Mode The differential mode input signal is recommend to allow wider dynamic input range and to enhance noise immunity of internal sample-and-holder, although ADC1298X ADC1298X is designed to be able to adopt both the single and the differential mode input. < Differential Mode Input Range > Pin Input Range Conditions AIP RB ~ RT ­ AIN RT ~ RB 180º phase shifted with respect to AIP < Single Mode Input Range > Pin Input Range Conditions AIP (RT+RB)/2-(RT-RB) ~ (RT+RB)/2+(RT-RB) ­ AIN (RT + RB)/2 Tied to Clean DC Source (Recommended) Or Internal CML can be used by connecting AIN to CML 2. Input Signal Speed Normal Input Bandwidth of ADC1298X ADC1298X is in range of 1 ~ 6MHz, which is targeted to the frequency content of the signals in normal video systems. If it is necessary to have the bandwidth of the input signal to ADC1298X ADC1298X near or over nyquist frequency (15MHz, half the clock frequency) to use ADC1298X ADC1298X for the application signals of which to feed to ADC1298X ADC1298X can have signal frequencies higher than 6MHz, contact SEC for the guide on additional performance issues. 13 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X AVBB33A AVBB33A AVDD33A AVDD33A AVBB33A AVBB33A AVDD33A AVDD33A AVSS33A AVSS33A AVBB33A AVBB33A AVDD33A AVDD33A AVSS33A AVSS33A PHANTOM CELL INFORMATION AVBB33A AVBB33A AVBB33A AVBB33A SUB/Guard Ring AVDD33A AVDD33A Power/Guard Ring AVSS33A AVSS33A GND Ring AVDD33A AVDD33A AVSS33A AVSS33A AVSS33A AVSS33A AIN AIP RB CML RT adc1298x 10-Bit 30MHz ADC SU IT STBY AVSS33D AVSS33D AVSS33D AVSS33D 14 AVBB33D AVBB33D AVDD33D AVDD33D AVDD33D AVDD33D AVBB33D AVBB33D AVSS33D AVSS33D CK EOC DO[0] DO[1] DO[2] DO[3] DO[4] DO[5] DO[6] DO[7] DO[8] DO[9] AVSS33D AVSS33D AVDD33D AVDD33D AVBB33D AVBB33D AVBB33D AVBB33D STC AVSS33D AVSS33D GND Ring AVDD33D AVDD33D Power/Guard Ring AVSS33D AVSS33D SUB/Guard Ring AVDD33D AVDD33D 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X LAYOUT GUIDE Port Name I/O Type I/O Pad Layout Guide [Priority] AIP AI phiar50_abb . Keep the Paths to PADs as Short as Possible. [1] . Overlaps by other Signal Lines, especially by Digital Signal Lines, are not allowed (strong requirement). [1] . Put as many Contacts/Vias as Possible on Contact Area, if Metal Layers are Switched. [-] AIN AI phiar50_abb . Put as many Contacts/Vias as Possible on Contact Area, if Metal Layers are Switched. [-] . Shield, if Possible. [7] STBY DI phicc_abb . Keep it from Crossing Analog Signal Line, if possible. [5] SU DI phicc_abb . Keep it from Crossing Analog Signal Line, if possible. [X] STC DI phicc_abb . Keep it from Crossing Analog Signal Line, if possible. [X] CK DI phicc_abb . Keep it from Crossing any Analog Signal Line. (strong requirement) [2] DO[9:0] DO phob8_abb . Keep it from Crossing Analog Signal Lines, if possible. [4] . Make it not to Run over 1,000um. [6] EOC DO phob8_abb . Keep it from Crossing any Analog Signal Line. (strong requirement) [2] . Make it not to Run over 1,000um. [6] RT AB phoa_abb . Keep the Paths to PADs as Short as Possible. [1] . Overlaps by other Signal Lines, especially by Digital Signal Lines, are not allowed. (strong requirement) [1] RB AB phoa_abb . Put as many Contacts/Vias as Possible on Contact Area, if Metal Layers are Switched. [-] CML AB phoa_abb . Shield, if Possible. [7] IT AB phiar50_abb AVDD33A AVDD33A AP vdd3t_abb . Overlaps by Digital Signal Lines are not allowed. (strong requirement) [4] . Keep the Paths to PADs as Short as Possible. [3] AVSS33A AVSS33A AG vss3t_abb . Put as many Contacts/Vias as Possible on Contact Area, if Metal Layers are Switched. [-] AVBB33A AVBB33A AG vbb3_abb . Ports exist on 3 sides of Core and internally connected to each other by the power ring. Connect PAD to the Port which is most convenient to Route interconnecting Line. [-] AVDD33D AVDD33D DP vdd3t_abb . Overlaps by Analog Signal Lines are not allowed. (strong requirement) [2] . Keep the Paths to PADs as Short as Possible. [4] AVSS33D AVSS33D DG vss3t_abb . Put as many Contacts/Vias as Possible on Contact Area, if Metal Layers are Switched. [-] AVBB33D AVBB33D DG vbb3_abb . Ports exist on 3 sides of Core and internally connected to each other by the power ring. Connect PAD to the Port which is most convenient to Route interconnecting Line. [-] . Leave it Float. . Keep the Phantom Port Width to PAD or Other Core. 15 0.18µm 10-BIT 10-BIT 30MSPS 30MSPS ADC µ ADC1298X ADC1298X PACKAGE CONFIGURATION (1.65V) AVDD33D AVDD33D 48 AVDD33D AVDD33D 47 3 RB AVBB33D AVBB33D 46 4 RB 1.15V 1 RT 2 RT 2.15V AVSS33D AVSS33D 45 5 CML AVSS33D AVSS33D 44 6 AVDD33A AVDD33A EOC 42 NC 41 9 AVSS33A AVSS33A NC 40 10 AVSS33A AVSS33A NC 39 11 AIP 0.0V 7 AVDD33A AVDD33A 8 AVBB33A AVBB33A 3.3V STC 43 NC 38 12 NC 13 AIN adc1298x NC 37 DO[9] 36 14 NC DO[8] 35 15 SU DO[7] 34 16 IT DO[6] 33 17 STBY DO[5] 32 3.3V 18 AVDD33R AVDD33R DO[4] 31 0.0V 19 AVSS33R AVSS33R DO[3] 30 20 CK DO[2] 29 21 NC DO[1] 28 22 NC DO[0] 27 23 NC NC 26 24 NC NC 25 300MHz : Actual Input/Output Pin : Control Input Pin : Eliminable Input/Output Pin : Default Setting for Control Input Pin 16 3.3V 0.0V