ADC10D040 DS200297 ADC10D040CIVS ADC10D040EVAL AN450 200297A1 200297A0 200297A4 - Datasheet Archive

 

Dual 10-Bit, 40 MSPS, 267 mW A/D Converter General Description Features The ADC10D040 is a dual low power, high performance CMOS

 

ADC10D040 ADC10D040 Dual 10-Bit, 40 MSPS, 267 mW A/D Converter General Description Features The ADC10D040 ADC10D040 is a dual low power, high performance CMOS analog-to-digital converter that digitizes signals to 10 bits resolution at sampling rates up to 45 MSPS while consuming a typical 267 mW from a single 3.3V supply. No missing codes is guaranteed over the full operating temperature range. The unique two stage architecture achieves 9.4 Effective Bits over the entire Nyquist band at 40 MHz sample rate. An output formatting choice of straight binary or 2's complement coding and a choice of two gain settings eases the interface to many systems. Also allowing great flexibility of use is a selectable 10-bit multiplexed or 20-bit parallel output mode. An offset correction feature minimizes the offset error. To ease interfacing to most low voltage systems, the digital output power pins of the ADC10D040 ADC10D040 can be tied to a separate supply voltage of 1.5V to 3.6V, making the outputs compatible with other low voltage systems. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 1 mW and from which recovery is less than 1 ms. Bringing the STBY (Standby) pin high places the converter into a standby mode where power consumption is about 30 mW and from which recovery is 800 ns. The ADC10D040 ADC10D040's speed, resolution and single supply operation make it well suited for a variety of applications, including high speed portable applications. Operating over the industrial (-40° TA +85°C) temperature range, the ADC10D040 ADC10D040 is available in a 48-pin TQFP. An evaluation board is available to ease the design effort. n n n n n n n n n © 2003 National Semiconductor Corporation DS200297 DS200297 Internal sample-and-hold Internal Reference Capability Dual gain settings Offset correction Selectable straight binary or 2's complement output Multiplexed or parallel output bus Single +3.0V to 3.6V operation Power down and standby modes 3V TTL Logic input/output compatible Key Specifications Resolution 10 Bits Conversion Rate 40 MSPS ENOB 9.4 Bits (typ) DNL 0.35 LSB (typ) Conversion Latency Parallel Outputs 2.5 Clock Cycles - Multiplexed Outputs, I Data Bus 2.5 Clock Cycles - Multiplexed Outputs, Q Data Bus 3 Clock Cycles n PSRR 90 dB n Power Consumption - Normal Operation 267 mW (typ) < 1 mW (typ) - Power Down Mode - Fast Recovery Standby Mode 30 mW (typ) n n n n n Applications n n n n n n Digital Video CCD Imaging Portable Instrumentation Communications Medical Imaging Ultrasound www.national.com ADC10D040 ADC10D040 Dual 10-Bit, 40 MSPS, 267 mW A/D Converter September 2002 ADC10D040 ADC10D040 Connection Diagram 20029701 TOP VIEW Ordering Information Industrial Temperature Range (-40°C TA +85°C) ADC10D040CIVS ADC10D040CIVS TQFP ADC10D040EVAL ADC10D040EVAL www.national.com NS Package Evaluation Board 2 ADC10D040 ADC10D040 Block Diagram 20029702 Pin Descriptions and Equivalent Circuits Pin No. Symbol 48 47 I+ I- Analog inputs to "I" ADC. With VREF = 1.4V, conversion range is 1.15V to 1.85V with GAIN pin low, or 0.8V to 2.2V with GAIN pin high. 37 38 Q+ Q- Analog inputs to "Q" ADC. With VREF = 1.4V, conversion range is 1.15V to 1.85V with GAIN pin low, or 0.8V to 2.2V with GAIN pin high. 1 Equivalent Circuit Description Analog Reference Voltage input. The voltage at this pin should be in the range of 0.6V to 1.6V. With 1.4V at this pin and the GAIN pin low, the full scale differential inputs are 1.4 VP-P. With 1.4V at this pin and the GAIN pin high, the full scale differential inputs are 2.8 VP-P. This pin should be bypassed with a minimum 1 µF capacitor. VREF 3 www.national.com ADC10D040 ADC10D040 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit (Continued) Description This is an analog output which can be used as a reference source and/or to set the common mode voltage of the input. It should be bypassed with a minimum of 1 µF low ESR capacitor in parallel with a 0.1 µF capacitor. This pin has a nominal output voltage of 1.5V and has a 1 mA output source capability. 45 VCMO 43 VRP Top of the reference ladder. Do not drive this pin. Bypass this pin with a 10 µF low ESR capacitor and a 0.1 µF capacitor. 44 VRN Bottom of the reference ladder. Do not drive this pin. Bypass this pin with a 10 µF low ESR capacitor and a 0.1 µF capacitor. www.national.com 4 Pin No. 33 2 31 32 34 35 36 8 thru 27 28 40, 41 Symbol Equivalent Circuit (Continued) Description CLK Digital clock input for both converters. The analog inputs are sampled on the falling edge of this clock input. OS Output Bus Select. With this pin at a logic high, both the "I" and the "Q" data are present on their respective 10-bit output buses (Parallel mode of operation). When this pin is at a logic low, the "I" and "Q" data are multiplexed onto the "I" output bus and the "Q" output lines all remain at a logic low (multiplexed mode). OC Offset Correct pin. A low-to-high transition on this pin initiates an independent offset correction sequence for each converter, which takes 34 clock cycles to complete. During this time 32 conversions are taken and averaged. The result is subtracted from subsequent conversions. Each input pair should have 0V differential value during this entire 34 clock period. OF Output Format pin. When this pin is LOW the output format is Straight Binary. When this pin is HIGH the output format is 2's complement. This pin may be changed asynchronously, but this will result in errors for one or two conversions. STBY Standby pin. The device operates normally with a logic low on this and the PD (Power Down) pin. With this pin at a logic high and the PD pin at a logic low, the device is in the standby mode where it consumes just 30 mW of power. It takes just 800 ns to come out of this mode after the STBY pin is brought low. PD Power Down pin that, when high, puts the converter into the Power Down mode where it consumes just 1 mW of power. It takes less than 1 ms to recover from this mode after the PD pin is brought low. If both the STBY and PD pins are high simultaneously, the PD pin dominates. GAIN This pin sets the internal signal gain at the inputs to the ADCs. With this pin low the full scale differential input peak-to-peak signal is equal to VREF. With this pin high the full scale differential input peak-to-peak signal is equal to 2 x VREF. I0­I9 and Q0­Q9 3V TTL/CMOS-compatible Digital Output pins that provide the conversion results of the I and Q inputs. I0 and Q0 are the LSBs, I9 and Q9 are the MSBs. Valid data is present just after the rising edge of the CLK input in the Parallel mode. In the multiplex mode, I-channel data is valid on I0 through I9 when the I/Q output is high and the Q-channel data is valid on I0 through I9 when the I/Q output is low. I/Q Output data valid signal. In the multiplexed mode, this pin transitions from low to high when the data bus transitions from Q-data to I-data, and from high to low when the data bus transitions from I-data to Q-data. In the Parallel mode, this pin transitions from low to high as the output data changes. VA Positive analog supply pin. This pin should be connected to a quiet voltage source of +3.0V to +3.6V. VA and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. 5 www.national.com ADC10D040 ADC10D040 Pin Descriptions and Equivalent Circuits ADC10D040 ADC10D040 Pin Descriptions and Equivalent Circuits Pin No. Symbol Equivalent Circuit (Continued) Description VD Digital supply pin. This pin should be connected to a quiet voltage source of +3.0V to +3.6V. VA and VD should have a common supply and be separately bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. 6, 30 VDR Digital output driver supply pins. These pins should be connected to a voltage source of +1.5V to VD and be bypassed with 10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors. 3, 39, 42, 46 AGND The ground return for the analog supply. AGND and DGND should be connected together close to the ADC10D040 ADC10D040 package. 5 DGND The ground return for the digital supply. AGND and DGND should be connected together close to the ADC10D040 ADC10D040 package. 7, 29 DR GND 4 www.national.com The ground return of the digital output drivers. 6 Operating Ratings (Notes 1, 2) (Notes 1, 2) Operating Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VA, VD Supply Voltage Positive Supply Voltages Voltage on Any Pin VCM Input Common Mode Range GAIN = Low ESD Susceptibility (Note 5) Storage Temperature 0.6V to 1.8V Digital Input Pins Voltage Range 250V Soldering Temperature, Infrared, 10 sec. (Note 6) VREF/2 to (VA­VREF/2) VREF Voltage Range 2500V Machine Model VREF/4 to (VA­VREF/4) GAIN = High See (Note 4) Human Body Model ± VREF/2 ± VREF GAIN = Low GAIN = High ± 25 mA ± 50 mA Package Dissipation at TA = 25°C +1.5V to VD VIN Differential Voltage Range -0.3V to (VA or VD +0.3V) Package Input Current (Note 3) +3.0V to +3.6V VDR Supply Voltage 3.8V Input Current at Any Pin (Note 3) -40°C TA +85°C -0.3V to (VA +0.3V) 235°C -65°C to +150°C Converter Electrical Characteristics The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5 VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, VIN (a.c. coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (Note 7). Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) STATIC CONVERTER CHARACTERISTICS INL Integral Non-Linearity ± 0.65 ± 1.9 LSB (max) DNL Differential Non-Linearity ± 0.35 +1.2 -1.0 LSB (max) LSB (min) 10 Bits Without Offset Correction -3.3 +7 -12 LSB (max) LSB (min) With Offset Correction +0.4 +1.5 -0.5 LSB (max) LSB (min) -4 +5 -12 %FS (max) %FS (min) Resolution with No Missing Codes VOFF GE Offset Error Gain Error DYNAMIC CONVERTER CHARACTERISTICS fIN = 4.43 MHz, VIN = FSR -0.1 dB 9.5 SNR Signal-to-Noise Plus Distortion Ratio Signal-to-Noise Ratio 9.5 9.4 fIN = 4.43 MHz, VIN = FSR -0.1 dB 59 fIN = 10.4 MHz, VIN = FSR -0.1 dB, TA = 25°C 59 fIN = 19.7 MHz, VIN = FSR -0.1 dB 58 fIN = 4.43 MHz, VIN = FSR -0.1 dB SINAD Effective Number of Bits fIN = 10.4 MHz, VIN = FSR -0.1 dB, TA = 25°C fIN = 19.7 MHz, VIN = FSR -0.1 dB ENOB 60 fIN = 10.4 MHz, VIN = FSR -0.1 dB, TA = 25°C 60 Bits 9.1 Bits (min) Bits dB 56.3 dB (min) dB dB 57.3 dB (min) fIN = 19.7 MHz, VIN = FSR -0.1 dB Second Harmonic fIN = 10.4 MHz, VIN = FSR -0.1 dB, TA = 25°C -69 -67 dB -86 dB fIN = 10.4 MHz, VIN = FSR -0.1 dB -83 dB fIN = 19.7 MHz, VIN = FSR -0.1 dB HS2 dB fIN = 4.43 MHz, VIN = FSR -0.1 dB Total Harmonic Distortion dB -70 fIN = 19.7 MHz, VIN = FSR -0.1 dB THD 59 fIN = 4.43 MHz, VIN = FSR -0.1 dB -81 dB -61 dB (min) fIN = 4.43 MHz, VIN = FSR -0.1 dB HS3 Third Harmonic -73 dB fIN = 10.4 MHz, VIN = FSR -0.1 dB -73 dB fIN = 19.7 MHz, VIN = FSR -0.1 dB -72 dB 7 www.national.com ADC10D040 ADC10D040 Absolute Maximum Ratings ADC10D040 ADC10D040 Converter Electrical Characteristics (Continued) The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5 VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, VIN (a.c. coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (Note 7). Symbol Parameter Conditions Typical (Note 8) Limits (Note 9) Units (Limits) fIN = 4.43 MHz, VIN = FSR -0.1 dB IMD Spurious Free Dynamic Range Intermodulation Distortion 72 dB fIN = 10.4 MHz, VIN = FSR -0.1 dB 72 dB fIN = 19.7 MHz, VIN = FSR -0.1 dB SFDR 70 dB 71 dB fIN1 < 8.5 MHz, VIN = FSR -6.1 dB fIN2 < 9.5 MHz, VIN = FSR -6.1 dB Overrange Output Code Underrange Output Code FPBW (VIN+-VIN-) > 1.5V (VIN+-VIN-) < -1.5V 1023 0 Full Power Bandwidth 140 MHz INTER-CHANNEL CHARACTERISTICS Crosstalk 1 MHz input to tested channel, 10.3 MHz input to other channel -72 dB Channel - Channel Aperture Delay Match fIN = 8 MHz 8.5 ps 0.1 %FS Gain Pin = AGND 1.4 VP-P Gain Pin = VA 2.8 VP-P Clock High 6 pF Clock Low Channel - Channel Gain Matching REFERENCE AND ANALOG CHARACTERISTICS VIN Analog Differential Input Range CIN Analog Input Capacitance (each input) 3 pF RIN Analog Differential Input Resistance 13.5 k VREF Reference Voltage 1.4 IREF Reference Input Current