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Part Manufacturer Description Datasheet BUY
HI3-674AJN-5 Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 visit Intersil
HI5812JIB Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 visit Intersil
HI3-674AKN-5 Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 visit Intersil
HI5812JIP Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP24 visit Intersil
HI5812KIB Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 visit Intersil
HI3-574AJN-5 Intersil Corporation 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP28 visit Intersil

ADC 10 Ghz

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: -4.0 GHz 1.10:1 â'"DC-1.0 GHz 1.25:1 â'"1.0-2.0 GHz 1.20:1 â'"DC-40 GHz 1.10:1 â'"DC-1.0 GHz 1.25:1 â'"1.0-2.0 GHz 1.25:1 â'"DC-4.0 GHz 1.25:1 â'"DC-2.0 GHz 1.20:1 â'"DC-500 MHz 1.35:1 â'"500-1000 MHz 1.25:1 , Range DC-4.0 GHz DC-2.0 GHz Input Power (Watts Avg.) 10 20 PPT 515-30-4 PPR & PPT 51 5-30 , -4.0 GHz DC-2.0 GHz DC-1.0 GHz 40 100 1 50 PPR & PPT 975-250-3 DC-1.0 GHz 250 PPR & PPT , -4 GHz GENERAL INFORMATION These high power devices are designed to dissipate power in RFcircuits when Aeroflex / Inmet
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Abstract: 1.10:1 â'"DC-1.0 GHz 1.25:1 â'"1.0-2.0 GHz 1.20:1 â'"DC-4 GHz 1.10:1 â'"DC-1.0 GHz 1.25:1 â , 1-20 DC-4 GHz 10 1-10 1 1-20 ±0.5 ±1.0 ±0.5 ±2.0 ±1.0 ±3.0 PPA 20 1-20 DC-4 GHz 20 1-5 6-9 10-1 5 16-20 ±0.5 ±0.5 ±0.75 ±1.0 ±0.5 ±0.5 ±1.0 ±2.0 ±0.5 ±1.0 ±1.5 ±3.0 PPA 50 1-20 DC-1 GHz 1-20 DC-500 MHz dB VSWR (Typical)2 2.5-4 GHz 1.3:1 1.1 5:1 â'" DC-1.0 GHz 1.35:1 â'" 1.0-2.5 GHz 1.50:1 â MCE / KDI Integrated Products
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A3RS91 350REF PCX-100-M-500 PCX050-F-50 PCX050-F-100 PCX050-M-100
Abstract: Reference Board IN+ OUT- T/H IN- ADC OUT+ USB DC BLOCKS 10 MHz Reference BAND PASS , signal frequency of 5 GHz which is well beyond the approximately 2.8 GHz bandwidth of the particular ADC , reflect sampling by the HMC661LC4B. The noise spectrum still occurs over 18 GHz of bandwidth but the ADC , the ADC, reducing the total noise detected. In summary, the input noise bandwidth is 18 GHz for ADC , to observe an 8 to 10 dB difference between the noise levels of the hold-mode and track mode ADC Hittite Microwave
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EV8AQ160

Abstract: P22-R22 Four Cross Point Switch 2.5 GHz Differential Symmetrical Input Clock Required ADC Master Reset (LVDS , EV8AQ160 ­ In four-channel mode, the same 1.25 GHz clock is directed to all four ADC cores and T/H. ­ In two-channel mode, the in-phase 1.25 GHz clock is sent to ADC A or C and the inverted 1.25 GHz clock is sent to , equivalent sampling frequency of 2.5 Gsps. ­ In one-channel mode, the in-phase 1.25 GHz clock is sent to ADC A while the inverted 1.25 GHz clock is sent to ADC B, the in-phase 1.25 GHz clock is delayed by 90
e2v semiconductors
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P22-R22 EV8AQ160CTPY marking AC9 EBGA380 F-91572 0846BS

HMC5640BLC4B

Abstract: bandwidth well beyond the intrinsic 2.8 GHz ADC bandwidth. The small ripples in the frequency response , Combination within the 2.8 GHz ADC bandwidth by up to 11 dB. This enhancement occurs because the , PAGE 1 â'¢ APRIL 2011 www.mpdigest.com Hittiteâ'™s 18 GHz Ultra Wideband Track-and-Hold Amplifier Enhances High Speed ADC Performance by Hittite Microwave W ideband data acquisition , antenna) directly to a wideband, high dynamic range Analogto-Digital Converter (ADC) for digitization
Hittite Microwave
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HMC5640BLC4B
Abstract: GHz ADC bandwidth. This bandwidth is obtained because the HMC661LC4B takes on the burden of sampling , -10 -15 -20 0 2 4 6 8 10 12 14 16 18 FREQUENCY (GHz) Figure 2 , the SFDR beyond the bandwidth of the ADC but also enhances it for frequencies within the 2.8 GHz ADC , ADC-Only S/N THA and ADC SFDR THA and ADC S/N THA and ADC 10 Avgs 70 S/N, SFDR (dBc) v00.0812 60 50 40 30 0 2 4 6 8 10 12 FREQUENCY (GHz) Figure 3. Time Domain Hittite Microwave
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HMC661LC4

EV8AQ160

Abstract: EBGA380 Four Cross Point Switch 2.5 GHz Differential Symmetrical Input Clock Required ADC Master Reset (LVDS , internal sampling clocks: ­ In four-channel mode, the same 1.25 GHz clock is directed to all four ADC cores and T/H. ­ In two-channel mode, the in-phase 1.25 GHz clock is sent to ADC A or C and the inverted 1.25 GHz clock is sent to ADC B or D, while the analog input is sent to both ADCs, resulting in an , GHz clock is sent to ADC A while the inverted 1.25 GHz clock is sent to ADC B, the in-phase 1.25 GHz
e2v semiconductors
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BLD-3 BHD4N ald2 transistor BH-D6 ALD3 bld3 0846CS

EV10AQ190

Abstract: Marking D9N Selection + SDA 10-bit 1.25 Gsps ADC core Gain T/ H Gain 10-bit 1.25 -Gsps ADC core Gain T/H 10-bit 1.25 -Gsps ADC core Gain T/ H 10-bit 1.25 Gsps ADC core 2.5 GHz clock T/H Phase Offset , EV10AQ190 Low power QUAD 10-bit 1.25 Gsps ADC Datasheet Summary Main Features · Quad ADC with , is made up of four 10-bit ADC cores which can be considered independently (four-channel mode) or , same 1.25 GHz clock is directed to all four ADC cores and T/H ­ in two-channel mode, the in-phase 1.25
e2v semiconductors
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Marking D9N EVX10AQ190TPY marking aa5 EV10AQ190TPY-EB transistor marking c3n DIODE B4N 0952CS

AN851

Abstract: 0.9 2R -2L 4R-4 L 3R3L 1.0 2.3 GHz 2.4 GHz WiBro 374 MHz IF ) . Rev. 0 | Page 2 , 06147-001 ADF4153 AN-851 25 cations Inc. 15 3 10 2 1 Digital Communi- 2.3 GHz 2.5 GHz WiMax 25 MHz 60 dB 150 MHz ~50 dB Digital Communications Inc. 10 0 2100 , ) ADC 11 200 MHz IF ~250 mW AD9246 AD8370 10 AD9246 ADC 650 MHz IF 80 MSPS 0 70 MHz IF IF â'"5 ADC â'"10 MEASURED RESPONSE (dB) ADC ADC â'"15 â
Analog Devices
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AN851 16-QAM- 64-QAM- 64-QAM ADF4360-8 ATF541M4 ADL5350

EV10AQ190

Abstract: transistor b9n Selection + SDA 10-bit 1.25 Gsps ADC core Gain T/ H Gain 10-bit 1.25 -Gsps ADC core Gain T/H 10-bit 1.25 -Gsps ADC core Gain T/ H 10-bit 1.25 Gsps ADC core 2.5 GHz clock T/H Phase Offset , EV10AQ190 Low power QUAD 10-bit 1.25 Gsps ADC Datasheet Summary Main Features · Quad ADC with , is made up of four 10-bit ADC cores which can be considered independently (four-channel mode) or , same 1.25 GHz clock is directed to all four ADC cores and T/H ­ in two-channel mode, the in-phase 1.25
e2v semiconductors
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transistor b9n dioda C5N H1 dioda DIODE A7N A7N transistor a2n dioda 0952BS

VARI-L VCO PLL

Abstract: 8 bit ttl ADC ! LMH6550 ADC 400 W! LMH6551 ADC 370 NE NE NE W! 1.2 GHz 2 , - SC70-5, SOT23-5 ID 1 AV = +10 2 AV = +2 , (VIN) ADC (VINFSR , (Oscilloscope) 8 1-3 GSPS ADC () (Step Response) · Nyquist 7.3~7.5 (ENOB) · 1.75 GHz · 10-18 , -N PLL 0.2 ~ 3.0 GHz 1.0 ~ 5.0 GHz -219 dBc/Hz -219 dBc/Hz ­ ­ UTCSP-20, TSSOP , VCO ~ 1.0 GHz ­ -139 dBc/Hz at 900 kHz LLP-28 LMX2531 VCO 0.765 ~ 2.76
National Semiconductor
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ADC10065 TSSOP-28 ADC10080 ADC10DL065 TQFP-64 ADC12DL040 VARI-L VCO PLL 8 bit ttl ADC PLL 2400 MHZ varil vco VARI-L VCO PLL 5 ghz SIGNAL PATH designer

FRS transceiver

Abstract: LYR170-641 ADACMasterIII · 125MSPS, 14-bit ADC (×2) · 500MSPS, 16-bit interpolating DAC (×2) · SX35 Virtex-4 FPGA-AC , 1 GHz SFF SDR evaluation module · SX35 Virtex-4 FPGA (×1) · DM6446 DM SoC · 128MB SDRAM and NAND flash memory Applications ADACMasterIII · 125MSPS, 14-bit ADC (×2) · 500MSPS, 16 , Selectable bandwidths: 5 MHz or 20 MHz · RF range: 0.2GHz to 1 GHz Small form factor SDR development , 125-MSPS, 14-bit ADC (×2) · 500-MSPS, 16-bit, interpolating DAC (×2) ADACMasterIII FPGA target
Lyrtech
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FRS transceiver LYR170-641 LYR173-611 DM6446 SFF SDR Development LSP151-611 WiMAX RF Transceiver mimo LSP000-652 200MH LSP000-659 LSP154-631 TMS320DM6446 MSP430
Abstract: 14-bit, 1.0 GSPS, ADC cores that shatter existing performance limitations in GHz bandwidth signal , of 79 dBc @ 1 GHz AIN, and 75 dBc @ 1.8 GHz AIN AD9680 Dual, 14-bit, 1.0 GSPS JESD204B ADC with , - and 14-bit, 2.5 GSPS/1.0 GSPS (respectively) ADC cores that provide up to 80 dB of wideband dynamic , FMC module comprised of: AD9680â'"dual, 14-bit, 1.0 GSPS ADC; AD9144â'"quad, 16-bit, 2.8 GSPS , '¢ SNR = 65.3 dBFS at 340 MHz (AIN = â'1.0 dBFS), 61.4 dBFS at 1 GHz â'¢ ENOB = 10.8 bits at 10 MHz â Analog Devices
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BR12627-

RQW 130

Abstract: MRF911 r - 30 m Adc, V fiF « 10 Vdc, f - 1.0 GHz» Collector-Base Capacitance (V c b * 10 Vdc, lg - 0. f - , GHz) (lc - 5.0 m Adc, V c e " 10 Vdc, f - 2.0 GHz) Power Gain at Optim um Noise Figure (1C * 5.0 m Adc , Gain (1) (1C 30 m Adc, V C£ - 10 Vdc. f - 1.0 GHz) (1C " 30 m Adc, V CE " 10 Vdc, f - 2.0 GHz) n f m , Product - f t = 5.0 GHz (Typ) @ f = 1.0 GHz · High Power Gain Grnax = 12.S dB (Typ) @ f - 1.0 GHz HIGH , noted). Characteristic O FF CHARACTERISTICS C ollector-Em itter Breakdown Voltage ( lc * 1.0 m Adc, I s
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OCR Scan
MRF911 RQW 130 case 317-01
Abstract: -5 -10 3-Bit ADC IN XOR Dout dBFS (dB) -15 1:2 DEMUX CLK -20 -25 -30 -35 -40 Inhibit -45 XOR IN OCLK -50 0 2 4 6 8 10 FREQUENCY (GHz , â'" DC - 18 GHz Input Band Track-and-Hold â'" 8-Bit 1000 MSPS ADC â'" PLL + VCO â'" Clock Delay , EVAL01-HMC9000 35 0 1 2 3 4 5 6 7 8 9 10 Fin (GHz) Data Converter , IF 2(N) LVDS ADC IF 2(P) RX2 HMC1030LP4E Power Detector â'¢ DC - 3.9 GHz RF Front Hittite Microwave
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ADC-0713 13-BIT 12-BIT 14-BIT 16-BIT 10-BIT

EV8AQ160

Abstract: EBGA380 directed to all four ADC cores and T/H · In two-channel mode, the in-phase 1.25 GHz clock is sent to ADC A or C and the inverted 1.25 GHz clock is sent to ADC B or D, while the analog input is sent to both , ­BDC­12/10 e2v semiconductors SAS 2010 EV8AQ160 · In one-channel mode, the in-phase 1.25 GHz clock is sent to ADC A while the inverted 1.25 GHz clock is sent to ADC B, the in-phase 1.25 GHz clock is delayed by 90° to generate the clock for ADC C and the inverted 1.25 GHz clock is delayed by 90° to
e2v semiconductors
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A23 851 diode phase control trigger 0846I

EV8AQ160

Abstract: 0846G internal sampling clocks: · In four-channel mode, the same 1.25 GHz clock is directed to all four ADC cores and T/H · In two-channel mode, the in-phase 1.25 GHz clock is sent to ADC A or C and the inverted 1.25 GHz clock is sent to ADC B or D, while the analog input is sent to both ADCs, resulting in an , SAS 2009 EV8AQ160 · In one-channel mode, the in-phase 1.25 GHz clock is sent to ADC A while the inverted 1.25 GHz clock is sent to ADC B, the in-phase 1.25 GHz clock is delayed by 90° to generate the
e2v semiconductors
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0846G

LQFP-32

Abstract: ADC0808 New New * 8 A/D GHz A/D 8 ADC ADC 3GSPS ADC ADC GHz ADC · GHz ADC Xilinx Virtex 4 FPGA · · ­ Xilinx Vertex 4 Verilog ­ ADC Wavevision PC · , LQFP-128 Exp. Pad LQFP-128 Exp. Pad 8 GHz ADC GHz ADC08D1500 @ 1.5GSPS ENOB vs · , () : 500MSPS 3GSPS 7.0 6.0 GHz · 1 ADC 6GSPS I-Channel Q-Channel 5.0 0 400 800 , 1500 1750 (MHz) · LIDAR www.national.com/JPN/adc 3 GHz A/D
National Semiconductor
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ADC08500 ADC081000 ADC081500 ADC082500 ADC083000 ADC08B3000 LQFP-32 ADC0808 ADC78H90 verilog/ADC128S102 LQFP128

EV8AQ160

Abstract: internal sampling clocks: · In four-channel mode, the same 1.25 GHz clock is directed to all four ADC cores and T/H · In two-channel mode, the in-phase 1.25 GHz clock is sent to ADC A or C and the inverted 1.25 GHz clock is sent to ADC B or D, while the analog input is sent to both ADCs, resulting in an , SAS 2010 EV8AQ160 · In one-channel mode, the in-phase 1.25 GHz clock is sent to ADC A while the inverted 1.25 GHz clock is sent to ADC B, the in-phase 1.25 GHz clock is delayed by 90° to generate the
e2v semiconductors
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LIDAR radar

Abstract: ADC digital calibration time interleaved Jitter (ps) 169 MHz Input to ADC 0.010 t -Bi 16 t -Bi 14 0.100 t -Bi 12 t -Bi 10 , higher system sample rate. Ex. 1.25 GHz input clock: 2.5 GSPS per ADC (Auto DES), and now 5 GSPS through , GHz Sampling Design Challenge 1 National Semiconductor Ghz Ultra High Speed ADCs Target , GSPS Family Today http://www.national.com/appinfo/adc/ghz_adc.html Dual Channel Single Channel ADC083000 3 GHz BW DDR, SBI ADC08B3000 ADC08D1520 ADC08D1500 2 GHz BW DES, DDS, SPI SPEED
National Semiconductor
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ADC08D1020 ADC08D1000 ADC08D500 LMH6702 LIDAR radar ADC digital calibration time interleaved 8Bit CPU National Semiconductor LMH6570 LMH6515
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