ADAU1442/ADAU1445/ADAU1446 ADAU1442/ ADAU1445/ ADAU1446 24-CHANNEL ADAU1442 - Datasheet Archive

 

with Flexible Audio Routing Matrix ADAU1442/ADAU1445/ADAU1446 FEATURES I2C and SPI control interfaces Standalone operation

 

SigmaDSP Digital Audio Processor with Flexible Audio Routing Matrix ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 FEATURES I2C and SPI control interfaces Standalone operation Self-boot from serial EEPROM 4-channel, 10-bit auxiliary control ADC Multipurpose pins for digital controls and outputs Easy implementation of available third-party algorithms On-chip regulator for generating 1.8 V from 3.3 V supply 100-lead TQFP and LQFP packages Temperature range: -40°C to +105°C Fully programmable audio digital signal processor (DSP) for enhanced sound processing Features SigmaStudio, a proprietary graphical programming tool for the development of custom signal flows 172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz 4k parameter RAM, 8k data RAM Flexible audio routing matrix (FARM) 24-channel digital input and output Up to 8 stereo asynchronous sample rate converters (from 1:8 up to 7.75:1 ratio and 139 dB DNR) Stereo S/PDIF input and output Supports serial and TDM I/O, up to fS = 192 kHz Multichannel byte-addressable TDM serial port Pool of 170 ms digital audio delay (at 48 kHz) Clock oscillator for generating master clock from crystal PLL for generating core clock from common audio clocks APPLICATIONS Automotive audio processing Head units Navigation systems Rear-seat entertainment systems DSP amplifiers (sound system amplifiers) Commercial audio processing FUNCTIONAL BLOCK DIAGRAM SPI/I2C* SELFBOOT ADAU1442/ ADAU1442/ ADAU1445/ ADAU1445/ ADAU1446 ADAU1446 1.8V REGULATOR SPDIFI MP[3:0]/ MP[11:4] ADC[3:0] I2C/SPI CONTROL INTERFACE AND SELF-BOOT MP/ AUX ADC S/PDIF RECEIVER PROGRAMMABLE AUDIO PROCESSOR CORE XTALI XTALO PLL CLOCK OSCILLATOR S/PDIF TRANSMITTER CLKOUT SPDIFO FLEXIBLE AUDIO ROUTING MATRIX (FARM) BIT CLOCK (BCLK) FRAME CLOCK (LRCLK) SERIAL DATA INPUT PORT (×9) UP TO 16 CHANNELS OF ASYNCHRONOUS SAMPLE RATE CONVERTERS SERIAL DATA OUTPUT PORT (×9) SDATA_OUT[8:0] (24-CHANNEL 24-CHANNEL DIGITAL AUDIO OUTPUT) BIT CLOCK (BCLK) SERIAL CLOCK DOMAINS FRAME CLOCK (LRCLK) (×12) *SPI/I2C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS. THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS, SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS. 07696-001 SDATA_IN[8:0] (24-CHANNEL 24-CHANNEL DIGITAL AUDIO INPUT) Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 TABLE OF CONTENTS Features . 1 ASRC Modes and Settings . 58 Applications. 1 DSP Core . 60 Functional Block Diagram . 1 DSP Core Modes and Settings. 61 Revision History . 3 Reliability Features . 62 General Description . 4 RAMs . 64 Specifications. 5 S/PDIF Receiver and Transmitter . 65 Digital Timing Specifications . 8 S/PDIF Modes and Settings . 66 Absolute Maximum Ratings. 11 Multipurpose Pins. 69 Thermal Resistance . 11 Multipurpose Pins Modes and Settings. 69 ESD Caution. 11 Auxiliary ADC. 70 Pin Configuration and Function Descriptions. 12 Auxiliary ADC Modes and Settings . 70 Theory of Operation . 17 Interfacing with Other Devices . 71 System Block Diagram. 17 Drive Strength Modes and Settings . 71 Overview. 18 Flexible TDM Modes . 76 Initialization . 20 Serial Input Flexible TDM Interface Modes and Settings. 76 Master Clock and PLL . 21 Serial Output Flexible TDM Interface Modes and Settings . 78 Voltage Regulator . 25 Software Features. 81 SRC Group Delay . 25 Software Safeload . 81 Control Port . 26 Software Slew . 81 Serial Data Input/Output. 31 Global RAM and Register Map . 82 Serial Input Ports . 37 Overview of Register Address Map . 82 Serial Input Port Modes and Settings . 39 Details of Register Address Map . 82 Serial Output Ports. 41 Applications Information . 87 Serial Output Port Modes and Settings . 42 Layout Recommendations . 87 Flexible Audio Routing Matrix (FARM) . 46 Typical Application Schematics. 89 Flexible Audio Routing Matrix Modes and Settings. 52 Outline Dimensions . 92 Asynchronous Sample Rate Converters . 58 Ordering Guide . 92 Rev. C | Page 2 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 REVISION HISTORY 9/10-Rev. B to Rev. C 4/09-Rev. 0 to Rev. A Added Table 1, Renumbered Sequentially .4 Changes to System Initialization Sequence Section .20 Changes to Table 12 .24 Changes to Figure 20 .29 Changes to EEPROM Format Section.30 Changes to Table 26 .39 Changes to Table 30 .44 Changes to Stereo ASRC[3:0] Lock Status and Mute Register (Address 0xE101), Stereo ASRC[3:0] Mute Ramp Disable Register (Address 0xE103), and Stereo ASRC[7:4] Lock Status and Mute Register (Address 0xE141) Sections .58 Changes to Architecture Section and Figure 51.60 Changes to Core Run Register (Address 0xE228) Section .61 Changes to Table 55 .66 Changes to Table 59 .67 Changes to Multipurpose Pins Section and Table 68 .69 Added ADAU1446 ADAU1446 . Universal Added LQFP . Universal Added Minimum Digital Current (DVDD) of ADAU1446 ADAU1446, Maximum Digital Current (DVDD) of ADAU1446 ADAU1446, and AVDD, DVDD, PVDD During Operation of ADAU1446 ADAU1446 Parameters, Table 1 .5 Changes to Table 4 .9 Changes to Overview Section.16 Change to Table 9.21 Changes to Voltage Regulator Section .23 Changes to EEPROM Format Section.28 Changes to Serial Clock Domains Section .32 Changes to Flexible Audio Routing Matrix-Input Side Section; Added Figure 40; Renumbered Sequentially.46 Changes to Stereo ASRC Routing Overview Section.47 Changes to ASRC Input Select Pairs[7:0] Registers (Address 0xE080 to Address 0xE087) Section.51 Changes to ASRC Output Rate Bits (Bits[5:0]) Section.53 Changes to Serial Output Data Selector Bits (Bits[5:0]) Section .55 Changes to ASRC Modes and Settings Section.56 Added Table 43; Renumbered Sequentially.61 Updated Outline Dimensions.90 Changes to Ordering Guide.90 4/10-Rev. A to Rev. B Added ADAU1442 ADAU1442 . Universal Changes to General Description Section .4 Changes to Table 1 .5 Added Table 2; Renumbered Sequentially .6 Changes to Table 4 .11 Changes to Overview Section.16 Changes to Power-Up Sequence Section, System Initialization Sequence Section, and Table 6.19 Changes to Data Bytes Section .28 Changes to Serial Clock Domains Section .33 Changes to Flexible Audio Routing Matrix-Input Side Section.47 Changes to ASRC Input Select Pairs[7:0] Registers (Address 0xE080 to Address 0xE087) Section .52 Changes to ASRC Output Rate Bits (Bits[5:0]) Section .54 Changes to Stereo ASRC[3:0] Lock Status and Mute Register (Address 0xE101) Section.57 Changes to Stereo ASRC[7:4] Lock Status and Mute Register (Address 0xE141) Section.58 Changes to S/PDIF Transmitter Section .64 Changes to Multipurpose Pins Section .68 Added Multipurpose Pin Value Registers (Address 0x129A to Address 0x12A5) Section and Table 66; Renumbered Sequentially.68 Change to Table 84.82 Changes to Ordering Guide.91 1/09-Revision 0: Initial Version Rev. C | Page 3 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 GENERAL DESCRIPTION The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 are enhanced audio processors that allow full flexibility in routing all input and output signals. The SigmaDSP® core features full 28-bit processing (56-bit in double-precision mode), synchronous parameter loading for ensuring filter stability, and 100% code efficiency with the SigmaStudioTM tools. This DSP allows system designers to compensate for the real-world limitations of speakers, amplifiers, and listening environments, resulting in a dramatic improvement of the perceived audio quality through speaker equalization, multiband compression, limiting, and third-party branded algorithms. The flexible audio routing matrix (FARM) allows the user to multiplex inputs from multiple sources running at various sample rates to or from the SigmaDSP core. This drastically reduces the complexity of signal routing and clocking issues in the audio system. FARM includes up to eight stereo asynchronous sample rate converters (depending on the device model), Sony/ Philips Digital Interconnect Format (S/PDIF) input and output, and serial (I2S) and time division multiplexing (TDM) I/Os. Any of these inputs can be routed to the SigmaDSP core or to any of the asynchronous sample rate converters (ASRCs). Similarly, any one of the output signals can be taken from the SigmaDSP core or from any of the ASRC outputs. This routing scheme, which can be modified at any time via control registers, allows for maximum system flexibility. The ADAU1442 ADAU1442, ADAU1445 ADAU1445, and ADAU1446 ADAU1446 differ only in ASRC functionality and packaging. The ADAU1442/ADAU1445 ADAU1442/ADAU1445 contain 16 channels of ASRCs and are packaged in TQFP packages, whereas the ADAU1446 ADAU1446 contains no ASRCs and is packaged in an LQFP. The ADAU1442 ADAU1442 can handle nine clock domains, the ADAU1445 ADAU1445 can handle three clock domains, and the ADAU1446 ADAU1446 can handle one clock domain. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 can be controlled in one of two operational modes: the settings of the chip can be loaded and dynamically updated through the SPI/I2C® port, or the DSP can self-boot from an external EEPROM in a system with no microcontroller. There is also a bank of multipurpose (MP) pins that can be used as general-purpose digital I/Os or as inputs to the 4-channel auxiliary control ADC. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 are supported by the SigmaStudio graphical development environment. This software includes audio processing blocks such as FIR and IIR filters, dynamics processors, mixers, low level DSP functions, and third-party algorithms for fast development of custom signal flows. Table 1. Device ADAU1442 ADAU1442 ADAU1445 ADAU1445 ADAU1446 ADAU1446 ASRC Channels 16 16 0 ASRC Clock Domains 8 2 N/A Rev. C | Page 4 of 92 Package TQFP TQFP LQFP ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, TA = 25°C, master clock input = 12.288 MHz, core clock fCORE = 172.032 MHz, I/O pins set to 2 mA drive setting, unless otherwise noted. Table 2. Parameter ANALOG PERFORMANCE Auxiliary Analog Inputs Resolution Full-Scale Analog Input Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Gain Error Input Impedance Sample Rate POWER Supply Voltage Analog Voltage (AVDD) Digital Voltage (DVDD) PLL Voltage (PVDD) IOVDD Voltage (IOVDD) Supply Current Analog Current (AVDD) PLL Current (PVDD) I/O Current (IOVDD) Min Typ Max Unit +2.3 +2.0 +2.0 Bits V LSB LSB LSB k kHz 10 AVDD -2.3 -2.0 -2.0 200 fCORE/896 2.97 1.62 2.97 2.97 3.3 1.8 3.3 3.3 3.63 1.98 3.63 3.63 Test Conditions/Comments AVDD = 3.3 V ± 10%. 4:1 multiplexed input, each channel at fCORE/3584. For fCORE = 172.032 MHz, each channel is sampled at 48 kHz. V V V V 2 10 10 mA mA mA Digital Current (DVDD) ADAU1442 ADAU1442 Typical Program 335 mA Minimal Program 115 mA 270 mA 115 mA 135 mA Test program includes 16 channels I/O, 10-band EQ per channel, all ASRCs active. Test program includes 2 channels I/O, 10-band EQ per channel. dB kHz A-weighted, 20 Hz to 20 kHz. ADAU1445 ADAU1445 Typical Program Minimal Program ADAU1446 ADAU1446 Typical Program Minimal Program ASYNCHRONOUS SAMPLE RATE CONVERTERS 1 Dynamic Range I/O Sample Rate 110 139 6 192 Rev. C | Page 5 of 92 Depends greatly on the number of active serial ports, clock pins, and characteristics of external loads. Test program includes 16 channels I/O, 10-band EQ per channel, all ASRCs active. Test program includes 2 channels I/O, 10-band EQ per channel. Test program includes 16 channels I/O, 10-band EQ per channel, all ASRCs active. Test program includes 2 channels I/O, 10-band EQ per channel. ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Parameter I/O Sample Rate Ratio THD + N CRYSTAL OSCILLATOR Transconductance REGULATOR 2 DVDD Voltage 1 2 Min 1:8 Typ -133 Max 7.75:1 -120 40 1.65 1.75 Unit Test Conditions/Comments dB mS 1.85 V Maximum 500 mA load. To calculate the group delay, refer to the SRC Group Delay section. Regulator specifications are calculated using an NJT4030P NJT4030P transistor from On Semiconductor in the circuit. AVDD = 3.3 V ± 10%, DVDD = 1.8 V ± 10%, PVDD = 3.3 V, IOVDD = 3.3 V ± 10%, TA = -40°C to +105°C, master clock input = 12.288 MHz, core clock fCORE = 172.032 MHz, I/O pins set to 2 mA drive setting, unless otherwise noted. Table 3. Parameter ANALOG PERFORMANCE Auxiliary Analog Inputs Resolution Full-Scale Analog Input Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Gain Error Input Impedance Sample Rate DIGITAL I/O Input Voltage, High (VIH) Min Typ Input Leakage, Low (IIL) at 0 V High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Input Capacitance (CI) Multipurpose Pins Output Drive POWER Supply Voltage Analog Voltage (AVDD) Digital Voltage (DVDD) PLL Voltage (PVDD) IOVDD Voltage (IOVDD) Supply Current Analog Current (AVDD) Unit +2.3 +2.0 +2.0 Bits V LSB LSB LSB k kHz 10 AVDD -2.3 -2.0 -2.0 200 fCORE/896 0.7 × IOVDD V Input Voltage, Low (VIL) Input Leakage, High (IIH) at 3.3 V Max 0.3 × IOVDD V -2 +2 A -2 60 -85 -2 +8 140 -10 +2 A A A A -8 -140 0.85 × IOVDD +2 -60 A A V V pF mA 0.1 × IOVDD 5 2 2.97 1.62 2.97 2.97 3.3 1.8 3.3 3.3 2 Rev. C | Page 6 of 92 3.63 1.98 3.63 3.63 V V V V mA Test Conditions/Comments AVDD = 3.3 V ± 10%. 4:1 multiplexed input, each channel at fCORE/3584. For fCORE = 172.032 MHz, each channel is sampled at 48 kHz. Digital input pins except SPDIFI. 1 Digital input pins except SPDIFI.1 Digital input pins except MCLK and SPDIFI. MCLK. SPDIFI. All other pins. CLKMODEx, RSVD, PLLx, RESET. MCLK. SPDIFI. IOH = 1 mA. IOL = 1 mA. Guaranteed by design. These pins are not designed for static current draw and should not drive LEDs directly. ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Parameter PLL Current (PVDD) I/O Current (IOVDD) Min Typ 10 10 Unit mA mA Test Conditions/Comments 460 mA ADAU1445 ADAU1445 365 mA ADAU1446 ADAU1446 315 mA Test program includes 24 channels I/O, fully utilized program RAM. Test program includes 24 channels I/O, fully utilized program RAM. Test program includes 24 channels I/O, fully utilized program RAM. 960 mW AVDD, DVDD, PVDD During Operation of ADAU1445 ADAU1445 780 mW AVDD, DVDD, PVDD During Operation of ADAU1446 ADAU1446 675 mW Maximum Digital Current (DVDD) ADAU1442 ADAU1442 Power Dissipation AVDD, DVDD, PVDD During Operation of ADAU1442 ADAU1442 Reset, All Supplies ASYNCHRONOUS SAMPLE RATE CONVERTERS 2 Dynamic Range I/O Sample Rate I/O Sample Rate Ratio THD + N CRYSTAL OSCILLATOR Transconductance REGULATOR 3 DVDD Voltage Max 94 -133 192 7.75:1 -120 40 1.65 1.75 1 Rev. C | Page 7 of 92 dB kHz A-weighted, 20 Hz to 20 kHz. dB mS 1.85 SPDIFI input voltage range exceeds the requirements of the S/PDIF specification. To calculate the group delay, refer to the SRC Group Delay section. 3 Regulator specifications are calculated using an NJT4030P NJT4030P transistor from On Semiconductor in the circuit. 2 All supplies at nominal +10%, IOVDD is not included in measurement. All supplies at nominal +10%, IOVDD is not included in measurement. All supplies at nominal +10%, IOVDD is not included in measurement. mW 139 6 1:8 Depends greatly on the number of active serial ports, clock pins, and characteristics of external loads. V Maximum 500 mA load. ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 DIGITAL TIMING SPECIFICATIONS TA = -40°C to +105°C, DVDD = 1.8 V, IOVDD = 3.3 V. Table 4. Parameter 1 MASTER CLOCK fMP tMP tMD CLKOUT Jitter CORE CLOCK fCORE SERIAL PORT fBCLK tBCLK tBIL tBIH tLIS tLIH tSIS tSIH tTS tSODS tSODM SPI PORT fCCLK write fCCLK read tCCPL tCCPH tCLS tCLH tCLPH tCLDLY tCDS tCDH tCOV I2C PORT fSCL tSCLH tSCLL tSCS tSCH tDS tDH tSCLR tSCLF tSDR tSDF tBFT MULTIPURPOSE PINS AND RESET fMP tMPIL tRLPW 1 2 Min Max Unit Description 2.822 40.69 25 24.576 354.36 75 250 MHz ns % ps Master clock (MCLK) frequency. See the Master Clock and PLL section. Master clock (MCLK) period. See the Master Clock and PLL section. Master clock (MCLK) duty cycle. Cycle-to-cycle rms average. 172.032 MHz DSP core clock frequency. 24.576 MHz ns ns ns ns ns ns ns ns ns ns BCLK frequency. BCLK period. BCLKx low pulse width, slave mode. BCLKx high pulse width, slave mode. LRCLKx setup to BCLKx input rising edge, slave mode. LRCLKx hold from BCLKx input rising edge, slave mode. SDATA_INx setup to BCLKx input rising edge. SDATA_INx hold from BCLKx input rising edge. BCLKx output falling edge to LRCLKx output timing skew. SDATA_OUTx delay in slave mode from BCLKx output falling edge. SDATA_OUTx delay in master mode from BCLKx output falling edge. MHz MHz ns ns ns ns ns ns ns ns ns CCLK frequency. 2 CCLK frequency.2 CCLK pulse width low. CCLK pulse width high. CLATCH setup to CCLK rising edge. CLATCH hold from CCLK rising edge. CLATCH pulse width high. Minimum delay between CLATCH low pulses. CDATA setup to CCLK rising edge. CDATA hold from CCLK rising edge. COUT valid output delay from CCLK falling edge. kHz s s s s ns s ns ns ns ns s SCL clock frequency. SCL pulse width high. SCL pulse width low. Start and repeated start condition setup time. Start condition hold time. Data setup time. Data hold time. SCL rise time. SCL fall time. SDA rise time. SDA fall time. Bus-free time between stop and start. Hz s MPx maximum switching rate. MPx pin input latency until high/low value is read by core. Guaranteed by design. RESET low pulse width. 40.69 30 30 20 20 10 10 5 30 30 32 16 20 20 0 35 20 20 0 35 40 400 0.6 1.3 0.6 0.6 100 0.9 300 300 300 300 1.3 fS/2 1.5 × 1/fS,NORMAL 10 ns All timing specifications are given for the default (I2S) states of the serial audio input ports and the serial audio output ports (see Table 26 and Table 30). Maximum SPI CCLK clock frequency is dependent on current drive strength and capacitive loads on the circuit board. Rev. C | Page 8 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Digital Timing Diagrams tLIH tBIH BCLKx INPUT tBIL tLIS LRCLKx INPUT tSIS SDATA_INx LEFT-JUSTIFIED MODE MSB MSB ­ 1 tSIH tSIS SDATA_INx I2S MODE MSB tSIH tSIS tSIS SDATA_INx RIGHT-JUSTIFIED MODE LSB MSB tSIH tSIH 8-BIT CLOCKS (24-BIT 24-BIT DATA) 12-BIT 12-BIT CLOCKS (20-BIT 20-BIT DATA) 07696-002 14-BIT 14-BIT CLOCKS (18-BIT 18-BIT DATA) 16-BIT 16-BIT CLOCKS (16-BIT 16-BIT DATA) Figure 2. Serial Input Port Timing tBIH BCLKx OUTPUT tTS tBIL LRCLKx OUTPUT SDATA_OUTx I2S MODE tSODS tSODM MSB MSB ­ 1 tSODS tSODM MSB tSODS tSODM SDATA_OUTx RIGHT-JUSTIFIED MODE MSB LSB 8-BIT CLOCKS (24-BIT 24-BIT DATA) 12-BIT 12-BIT CLOCKS (20-BIT 20-BIT DATA) 14-BIT 14-BIT CLOCKS (18-BIT 18-BIT DATA) 07696-003 SDATA_OUTx LEFT-JUSTIFIED MODE 16-BIT 16-BIT CLOCKS (16-BIT 16-BIT DATA) Figure 3. Serial Output Port Timing Rev. C | Page 9 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 tCLS tCLH tCLPH tCCPL tCCPH CLATCH CCLK CDATA tCDH tCDS 07696-004 COUT tCOV Figure 4. SPI Port Timing tDS tSCH tSCH SDA tSCLH SCL tSCS tSCLL tSCLF tBFT 07696-005 tSCLR Figure 5. I2C Port Timing tMP RESET tRLPW Figure 6. Master Clock and Reset Timing Rev. C | Page 10 of 92 07696-006 MCLK ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter DVDD to Ground AVDD to Ground IOVDD to Ground Digital Inputs Maximum Ambient Temperature Maximum Junction Temperature Storage Temperature Range Soldering (10 sec) Rating 0 V to 2.2 V 0 V to 4.0 V 0 V to 4.0 V DGND ­ 0.3 V to IOVDD + 0.3 V -40°C to +105°C 150°C -65°C to +150°C 300°C JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type 100-Lead TQFP 100-Lead LQFP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 11 of 92 JA 26.3 41.4 JC 9.4 9.5 Unit °C/W °C/W ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 DGND IOVDD LRCLK8 SDATA_OUT4 SDATA_IN7 BCLK7 LRCLK7 SDATA_OUT3 SDATA_IN6 BCLK6 LRCLK6 DVDD DGND IOVDD SDATA_OUT2 SDATA_IN5 BCLK5 LRCLK5 SDATA_OUT1 SDATA_IN4 BCLK4 LRCLK4 SDATA_OUT0 SDATA_IN3 DVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 DVDD DGND 1 74 BCLK8 PIN 1 IOVDD 2 73 SDATA_IN8 BCLK3 3 72 SDATA_OUT5 LRCLK3 4 71 LRCLK9 SDATA_IN2 5 BCLK2 70 BCLK9 6 69 SDATA_OUT6 LRCLK2 7 68 LRCLK10 LRCLK10 SDATA_IN1 8 67 BCLK10 BCLK10 BCLK1 9 66 SDATA_OUT7 LRCLK1 10 65 LRCLK11 LRCLK11 SDATA_IN0 11 BCLK0 12 64 BCLK11 BCLK11 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 DGND 13 63 IOVDD TOP VIEW (Not to Scale) IOVDD 14 62 DGND 61 SDATA_OUT8 LRCLK0 15 60 PLL0 MP11 16 59 PLL1 MP10 17 58 MP0/ADC0 MP9 18 MP8 19 57 MP1/ADC1 ADDR0 20 56 MP2/ADC2 55 MP3/ADC3 CLATCH 21 SCL/CCLK 22 54 RESET SDA/COUT 23 53 CLKOUT 52 IOVDD ADDR1/CDATA 24 51 DGND DVDD 25 07696-007 DVDD AGND AVDD SPDIFO SPDIFI PGND PVDD PLL_FILT XTALI XTALO VDRIVE IOVDD DGND DVDD MP4 MP5 MP6 MP7 PLL2 RSVD CLKMODE0 CLKMODE1 SELFBOOT DGND IOVDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NOTES 1. THE EXPOSED PAD DOES NOT HAVE AN INTERNAL ELECTRICAL CONNECTION TO THE INTEGRATED CIRCUIT, BUT SHOULD BE CONNECTED TO THE GROUND PLANE OF THE PCB FOR PROPER HEAT DISSIPATION. Figure 7. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Type 1 Description 1, 13, 26, 38, 51, 62, 76, 88 DGND PWR Digital Ground. The AGND, DGND, and PGND pins should be tied directly together in a common ground plane. DGND pins should be decoupled to a DVDD pin with a 100 nF capacitor. 2, 14, 27, 39, 52, 63, 77, 89 IOVDD PWR Input and Output Supply. The voltage on this pin sets the highest input voltage that should be present on the digital input pins. This pin is also the supply for the digital output signals on the clock, data, control port, and MP pins. IOVDD should always be set to 3.3 V. The current draw of this pin is variable because it is dependent on the loads of the digital outputs. 3 BCLK3 D_IO Bit Clock, Input/Output Clock Domain 3. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 3 is set up as a master or slave. When not used, this pin can be left disconnected. 4 LRCLK3 D_IO Frame Clock, Input/Output Clock Domain 3. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 3 is set up as a master or slave. When not used, this pin can be left disconnected. 5 SDATA_IN2 D_IN Serial Data Port 2 Input. When not used, this pin can be left disconnected. Rev. C | Page 12 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Pin No. Mnemonic Type 1 Description 6 BCLK2 D_IO Bit Clock, Input Clock Domain 2. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected. 7 LRCLK2 D_IO Frame Clock, Input Clock Domain 2. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected. 8 SDATA_IN1 D_IN Serial Data Port 1 Input. When not used, this pin can be left disconnected. 9 BCLK1 D_IO Bit Clock, Input Clock Domain 1. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 1 is set up as a master or slave. When not used, this pin can be left disconnected. 10 LRCLK1 D_IO Frame Clock, Input Clock Domain 1. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 1 is set up as a master or slave. When not used, this pin can be left disconnected. 11 SDATA_IN0 D_IN Serial Data Port 0 Input. When not used, this pin can be left disconnected. 12 BCLK0 D_IO Bit Clock, Input Clock Domain 0. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 0 is set up as a master or slave. When not used, this pin can be left disconnected. 15 LRCLK0 D_IO Frame Clock, Input Clock Domain 0. This pin is bidirectional, with the direction depending on whether the Input Clock Domain 0 is set up as a master or slave. When not used, this pin can be left disconnected. 16 MP11 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 17 MP10 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 18 MP9 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 19 MP8 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 20 ADDR0 D_IN Address 0 for I2C and SPI. In I2C mode, this pin, in combination with ADDR1, allows up to four ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 devices to be used on the same I2C bus. In SPI mode, setting ADDR0 either low or high allows up to two ICs to be used with a common SPI latch signal. 21 CLATCH D_IN SPI Latch Signal. Must go low at the beginning of an SPI transaction and high at the end of a transaction. Each SPI transaction may take a different number of CCLK cycles to complete, depending on the address and read/write bits that are sent at the beginning of the SPI transaction. When not used, this pin should be tied to ground, preferably with a 10 k pull-down resistor. 22 SCL/CCLK D_IN Serial Clock/Continuous Clock. In I2C mode, this pin functions as SCL and is always an open collector input, except when in self-boot mode, where it is an open collector output (I2C master). The line connected to this pin should have a 2.0 k pull-up resistor. In SPI mode, this pin functions as CCLK and is an input pin that can be either run continuously or gated off between SPI transactions. 23 SDA/COUT D_IO Serial Data/Continuous Output. In I2C mode, this pin functions as SDA and is a bidirectional open collector. The line connected to the SDA pin should have a 2.0 k pull-up resistor. In SPI mode, this pin functions as COUT and is used for reading back registers and memory locations. The COUT pin is three-stated when an SPI read is not active. 24 ADDR1/CDATA D_IN Address 1/Continuous Data. In I2C mode, this pin functions as ADDR1 and, in combination with ADDR0, sets the I2C address of the IC. This allows up to four ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 devices to be used on the same I2C bus. In SPI mode, this pin functions as CDATA and is the SPI data input. 25, 37, 50, 75, 87, 100 DVDD PWR 1.8 V Digital Supply. This can be supplied externally or generated from a 3.3 V supply with the on-board 1.8 V regulator. Each DVDD pin should be decoupled to DGND with a 100 nF capacitor. 28 SELFBOOT D_IN Self-Boot Select. Allows the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 to be controlled by the control port or to perform a self-boot. Setting this pin high (that is, to 1) initiates a self-boot operation when the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 are brought out of a reset. This pin can be tied directly to a voltage source or ground or pulled up/down with a resistor. 29 CLKMODE1 D_IN Output Clock Mode 1. With CLKMODE0, this pin sets the frequency of the CLKOUT signal. 30 CLKMODE0 D_IN Output Clock Mode 0. With CLKMODE1, this pin sets the frequency of the CLKOUT signal. 31 RSVD D_IN Reserved. Tie this pin to ground, preferably with a 10 k pull-down resistor. 32 PLL2 D_IN PLL Mode Select Pin 2. 33 MP7 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. Rev. C | Page 13 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Pin No. Mnemonic Type 1 Description 34 MP6 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 35 MP5 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 36 MP4 D_IO Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected. 40 VDRIVE A_OUT Regulator Drive. Supplies the drive current for the 1.8 V regulator. The base of the voltage regulator's external PNP transistor is driven from VDRIVE. 41 XTALO A_OUT Crystal Oscillator Output. A 100 damping resistor should be connected between this pin and the crystal. This output should not be used to directly drive a clock to another IC; the CLKOUT pin exists for this purpose. If the crystal oscillator is not used, the XTALO pin can be left unconnected. 42 XTALI A_IN Crystal Oscillator Input. This pin provides the master clock for the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446. If the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 generate the master clock in the system, this pin should be connected to the crystal oscillator circuit. If the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 are slaves to an external master clock, this pin should be connected to the master clock signal generated by another IC. 43 PLL_FILT A_OUT Phase-Locked Loop Filter. Two capacitors and a resistor must be connected to this pin as shown in Figure 11. 44 PVDD PWR Phase-Locked Loop Supply. Provides the 3.3 V power supply for the PLL. This should be decoupled to PGND with a100 nF capacitor. 45 PGND PWR Phase-Locked Loop Ground. Ground for the PLL supply. The AGND, DGND, and PGND pins can be tied directly together in a common ground plane. PGND should be decoupled to PVDD with a 100 nF capacitor. 46 SPDIFI D_IN S/PDIF Input. Accepts digital audio data in the S/PDIF format. When not used, this pin can be left disconnected. 47 SPDIFO D_OUT S/PDIF Output. Outputs digital audio data in the S/PDIF format. When not used, this pin can be left disconnected. 48 AVDD PWR Analog Supply. 3.3 V analog supply for the auxiliary ADC. This pin should be decoupled to AGND with a 100 nF capacitor. 49 AGND PWR Analog Ground. Ground for the analog supply. This pin should be decoupled to AVDD with a 100 nF capacitor. 53 CLKOUT D_OUT Master Clock Output. Used to output a master clock to other ICs in the system. Set using the CLKMODEx pins. When not used, this pin can be left disconnected. 54 RESET D_IN Reset. Active-low reset input. Reset is triggered on a high-to-low edge and exited on a low-to-high edge. For detailed information about initialization, see the Power-Up Sequence section. A reset event sets all RAMs and registers to their default values. 55 MP3/ADC3 D_IO, A_IN Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 3. When not used, this pin can be left disconnected. 56 MP2/ADC2 D_IO, A_IN Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 2. When not used, this pin can be left disconnected. 57 MP1/ADC1 D_IO, A_IN Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 1. When not used, this pin can be left disconnected. 58 MP0/ADC0 D_IO, A_IN Multipurpose, General-Purpose IO/Auxiliary ADC Input 0. When not used, this pin can be left disconnected. 59 PLL1 D_IN Phase-Locked Loop Mode Select Pin 1. 60 PLL0 D_IN Phase-Locked Loop Mode Select Pin 0. 61 SDATA_OUT8 D_OUT Serial Data Port 0 Output. When not used, this pin can be left disconnected. 64 BCLK11 BCLK11 D_IO Bit Clock, Output Clock Domain 2. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected. 65 LRCLK11 LRCLK11 D_IO Frame Clock, Output Clock Domain 2. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected. Rev. C | Page 14 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Pin No. Mnemonic Type 1 Description 66 SDATA_OUT7 D_OUT Serial Data Port 7 Output. When not used, this pin can be left disconnected. 67 BCLK10 BCLK10 D_IO Bit Clock, Output Clock Domain 10. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 10 is set up as a master or slave. When not used, this pin can be left disconnected. 68 LRCLK10 LRCLK10 D_IO Frame Clock, Output Clock Domain 10. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 10 is set up as a master or slave. When not used, this pin can be left disconnected. 69 SDATA_OUT6 D_OUT Serial Data Port 6 Output. When not used, this pin can be left disconnected. 70 BCLK9 D_IO Bit Clock, Output Clock Domain 9. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 9 is set up as a master or slave. When not used, this pin can be left disconnected. 71 LRCLK9 D_IO Frame Clock, Output Clock Domain 9. This pin is bidirectional, with the direction depending on whether the Output Clock Domain 9 is set up as a master or slave. When not used, this pin can be left disconnected. 72 SDATA_OUT5 D_OUT Serial Data Port 5 Output. When not used, this pin can be left disconnected. 73 SDATA_IN8 D_IN Serial Data Port 8 Input. When not used, this pin can be left disconnected. 74 BCLK8 D_IO Bit Clock, Input/Output Clock Domain 8. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 8 is set up as a master or slave. When not used, this pin can be left disconnected. 78 LRCLK8 D_IO Frame Clock, Input/Output Clock Domain 8. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 8 is set up as a master or slave. When not used, this pin can be left disconnected. 79 SDATA_OUT4 D_OUT Serial Data Port 4 Output. When not used, this pin can be left disconnected. 80 SDATA_IN7 D_IN Serial Data Port 7 Input. When not used, this pin can be left disconnected. 81 BCLK7 D_IO Bit Clock, Input/Output Clock Domain 7. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 7 is set up as a master or slave. When not used, this pin can be left disconnected. 82 LRCLK7 D_IO Frame Clock, Input/Output Clock Domain 7. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 7 is set up as a master or slave. When not used, this pin can be left disconnected. 83 SDATA_OUT3 D_OUT Serial Data Port 3 Output. When not used, this pin can be left disconnected. 84 SDATA_IN6 D_IN Serial Data Port 6 Input. When not used, this pin can be left disconnected. 85 BCLK6 D_IO Bit Clock, Input/Output Clock Domain 6. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 6 is set up as a master or slave. When not used, this pin can be left disconnected. 86 LRCLK6 D_IO Frame Clock, Input/Output Clock Domain 6. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 6 is set up as a master or slave. When not used, this pin can be left disconnected. 90 SDATA_OUT2 D_OUT Serial Data Port 2 Output. When not used, this pin can be left disconnected. 91 SDATA_IN5 D_IN Serial Data Port 5 Input. When not used, this pin can be left disconnected. 92 BCLK5 D_IO Bit Clock, Input/Output Clock Domain 5. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 5 is set up as a master or slave. When not used, this pin can be left disconnected. 93 LRCLK5 D_IO Frame Clock, Input/Output Clock Domain 5. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 5 is set up as a master or slave. When not used, this pin can be left disconnected. 94 SDATA_OUT1 D_OUT Serial Data Port 1 Output. When not used, this pin can be left disconnected. 95 SDATA_IN4 D_IN Serial Data Port 4 Input. When not used, this pin can be left disconnected. Rev. C | Page 15 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Pin No. Mnemonic Type 1 Description 96 BCLK4 D_IO Bit Clock, Input/Output Clock Domain 4. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 4 is set up as a master or slave. When not used, this pin can be left disconnected. 97 LRCLK4 D_IO Frame Clock, Input/Output Clock Domain 4. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 4 is set up as a master or slave. When not used, this pin can be left disconnected. 98 SDATA_OUT0 D_OUT Serial Data Port 0 Output. When not used, this pin can be left disconnected. 99 SDATA_IN3 D_IN Serial Data Port 3 Output. When not used, this pin can be left disconnected. 1 PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_OUT = digital output, D_IO = digital input/output. Rev. C | Page 16 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 THEORY OF OPERATION SYSTEM BLOCK DIAGRAM MP[3:0]/ RESET SPI/I2C* SELFBOOT MP[11:4] ADC[3:0] +3.3V VDRIVE 5 8 ADAU1442/ ADAU1442/ ADAU1445/ ADAU1445/ ADAU1446 ADAU1446 4 RESET I2C/SPI CONTROL INTERFACE AND SELF-BOOT MP XTALI, XTALO 3 2 4 4 1.8V REGULATOR PLL[2:0] PLL_FILT AUXILIARY ADC PLL CLOCK OSCILLATOR 2 CLOCK OUTPUT SERIAL DATA INPUT PORT (×9) 9 BIT CLOCK (BCLK) 3 TO 9 FRAME CLOCK (LRCLK) 28-/56-BIT 28-/56-BIT, 172MHz PROGRAMMABLE AUDIO PROCESSOR CORE, 170ms DELAY MEMORY FLEXIBLE AUDIO ROUTING MATRIX (OUTPUT SIDE) SDATA_IN[8:0] 9 (24-CHANNEL 24-CHANNEL DIGITAL AUDIO INPUT) CLKOUT S/PDIF TRANSMITTER S/PDIF RECEIVER FLEXIBLE AUDIO ROUTING MATRIX (INPUT SIDE) SPDIFI UP TO 16 CHANNELS OF ASYNCHRONOUS SAMPLE RATE CONVERTERS SERIAL DATA OUTPUT PORT (×9) 9 3 TO 9 CLKMODE[1:0] SPDIFO 9 3 TO 9 3 TO 9 SDATA_OUT[8:0] (24-CHANNEL 24-CHANNEL DIGITAL AUDIO OUTPUT) BIT CLOCK (BCLK) FRAME CLOCK (LRCLK) SERIAL CLOCK DOMAINS (×12) 8 DGND 8 AVDD AGND IOVDD *SPI/I2C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS. THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS, SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS. Figure 8. System Block Diagram Rev. C | Page 17 of 92 PVDD PGND 07696-008 6 DVDD ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 OVERVIEW The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 are each a 24-channel audio DSP with an integrated S/PDIF receiver and transmitter, flexible serial audio ports, up to 16 channels of asynchronous sample rate converters (ASRCs), flexible audio routing, and user interface capabilities. Signal processing capabilities include equalization, crossover, bass enhancement, multiband dynamics processing, delay compensation, speaker compensation, and stereo image widening. These algorithms can be used to compensate for the real-world limitations of speakers, amplifiers, and listening environments, resulting in an improvement in the perceived audio quality. An on-board oscillator can be connected to an external crystal to generate the master clock. A phase-locked loop (PLL) allows the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 to be clocked from a variety of clock frequencies. The PLL can accept inputs of 64 × fS, 128 × fS, 256 × fS, 384 × fS, or 512 × fS to generate the internal master clock of the core, where fS is the sampling rate of audio in normal-rate processing mode. In dual- or quad-rate mode, these multipliers are halved or quartered, respectively. System sample rates include, but are not limited to, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz. Each ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 operates from a 1.8 V digital power supply and a 3.3 V analog supply. An on-board voltage regulator can be used to operate the chip from a single 3.3 V supply. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 have a sophisticated control port that supports complete read and write capability of all memory locations, excluding read-only addresses. Control registers are provided to offer complete control of the chip's configuration and serial modes. Handshaking is included for ease of memory uploads and downloads. The ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446 can be configured for either SPI or I2C control. Program RAM, parameter RAM, and register contents can be saved in an external EEPROM, from which the ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446 can self-boot on startup. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 serial ports operate with digital audio I/Os in the I2S, left-justified, right-justified, or TDMcompatible mode. The flexible serial data ports allow for direct interconnection to a variety of ADCs, DACs, and general-purpose DSPs. The combination of an on-board S/PDIF transmitter and receiver and 16 channels of ASRCs allows for easy compatibility with an extensive number of external devices, and a system with up to nine sampling rates. The flexible audio routing matrix (FARM) is a system of multiplexers used to distribute the audio signals in the ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446 among the serial inputs and outputs, audio core, and ASRCs. FARM can easily be configured by setting the appropriate registers. The ADAU1442 ADAU1442, ADAU1445 ADAU1445, and ADAU1446 ADAU1446 are distinguished by the number of on-board ASRCs and maximum sample rates. The ADAU1442 ADAU1442 contains eight 2-channel ASRCs, the ADAU1445 ADAU1445 contains two 8-channel ASRCs, and the ADAU1446 ADAU1446 has no ASRCs. Two sets of serial ports at the input and output can operate in a special flexible TDM mode, which allows the user to independently assign byte-specific locations to audio streams at varying bit depths. This mode ensures compatibility with codecs using similar flexible TDM streams. The core of the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 is a 28-bit DSP (or a 56-bit DSP when using double-precision mode) optimized for audio processing, and it can process audio at sample rates of up to 192 kHz. The program and parameter RAMs can be loaded with a custom audio processing signal flow built with the SigmaStudio graphical programming software from Analog Devices, Inc. The values stored in the parameter RAM control individual signal processing blocks, such as IIR and FIR equalization filters, dynamics processors, audio delays, and mixer levels. A software safeload feature allows for transparent parameter updates and prevents clicks on the output signals. Reliability features such as a CRC and program counter watchdog help ensure that the system can detect and recover from any errors related to memory corruption. S/PDIF signals can be routed through an ASRC for processing in the DSP or can be sent directly to output on MP pins for recovery of the embedded audio signal. Other components of the embedded signal, including status and user bits, are not lost and can be output on the MP pins as well. Multipurpose (MP) pins are available for providing a simple user interface without the need for an external microcontroller. Twelve pins are available to input external control signals and output flags or controls to other devices in the system. Four of these can alternatively be assigned to an auxiliary ADC for use with analog controls such as potentiometers or system voltages. As inputs, MP pins can be connected to push buttons, switches, rotary encoders, potentiometers, or other external control circuitry to control the internal signal processing program. When configured as outputs, these pins can be used to drive LEDs (with a buffer), to output flags to a microcontroller, to control other ICs, or to connect to other external circuitry in an application. The SigmaStudio software is used to program and control the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 through the control port. Along with designing and tuning a signal flow, the software can configure all of the DSP registers in real time and download a new program and parameter into the external self-boot EEPROM. SigmaStudio's easy-to-use graphical interface allows anyone with audio processing knowledge to easily design a DSP signal flow and port it to a target application without the need for writing line-level code. At the same time, the software provides enough flexibility and programmability for an experienced DSP programmer to have in-depth control of the design. In SigmaStudio, the user can add signal processing cells from the library by dragging and dropping cells, connect them together in a flow, compile the design, and load the program and parameter files into the ADAU1442/ADAU1445/ ADAU1442/ADAU1445/ ADAU1446 ADAU1446 memory through the control port. The complicated tasks of linking, compiling, and downloading the project are all handled automatically by the software. Rev. C | Page 18 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Signal processing algorithms available in the provided libraries include · · · · · · · · · · · · Single- and double-precision biquad filter Mono and multichannel dynamics processors with peak or rms detection Mixer and splitter Tone and noise generator Fixed and variable gain Loudness Delay Stereo enhancement Dynamic bass boost Noise and tone source Level detector MP pin control and conditioning New processing algorithms are always being developed. Analog Devices also provides proprietary and third-party algorithms for applications such as matrix decoding, bass enhancement, and surround virtualizers. Contact Analog Devices for information about licensing these algorithms. Several power-saving mechanisms have been designed into the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446, including programmable pad strength for digital I/O pins and the ability to block the master clock from reaching unused subsystems. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 are fabricated on a single monolithic integrated circuit for operation over the -40°C to +105°C temperature range. The ADAU1442 ADAU1442 and ADAU1445 ADAU1445 are housed in a 100-lead TQFP package, with an exposed pad to assist in heat dissipation, and the ADAU1446 ADAU1446, due to its lower power consumption, is housed in a 100-lead LQFP package. Rev. C | Page 19 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 INITIALIZATION Power-Up Sequence The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 have a built-in initialization period, which allows sufficient time for the PLL to lock and the registers to initialize their values. On a positive edge of RESET, the PLL settings are immediately set by the PLL0, PLL1, and PLL2 pins, and the master clock signal is blocked from the chip subsystems. The initialization time, which is measured from the rising edge of RESET, is dependent on the frequency of the signal input to the XTALI pin, or fXTALI. The total initialization time is These include the ASRCs, S/PDIF receiver and transmitter, auxiliary ADCs, and DSP core. More information is available in the Master Clock and PLL Modes and Settings section. System Initialization Sequence Before the IC can process audio in the DSP, the following initialization sequence must be completed. (Step 5 through Step 11 can be performed in any order, as needed.) 1. 2. 1/(fXTALI/D) × 215 sec where D is the PLL divider, as set by the PLL0, PLL1, and PLL2 pins. The PLL divider settings are described in Table 9. 3. For example, if the signal input to XTALI has a frequency of 12.288 MHz and the PLL divider is set to 4 (PLL = 0, PLL1 = 1, and PLL2 = 0), the initialization time lasts 4. 1/(12288000/4) × 215 sec = 0.010667 sec (or 10.667 ms) 5. New values should not be written via the control port until the initialization is complete. Table 8 shows some typical times to boot the ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446 into the operational state necessary for an application, assuming that a 400 kHz I2C clock or a 5 MHz SPI clock is used and a full program, parameter set, and all registers (9 kB) are loaded. In reality, most applications use less than this full amount, and unused program and parameter RAM need not be initialized; therefore, the total boot time may be shorter. 6. 7. 8. 9. Recommended Program/Parameter Loading Procedure When writing large amounts of data to the program or parameter RAM in direct write mode, such as when downloading the initial contents of the RAMs from an external memory, the processor core should be disabled to prevent unpleasant noises from appearing at the audio output. When small amounts of data are transmitted during real-time operation of the DSP, such as when updating individual parameters, the software safeload mechanism can be used. More information is available in the Software Safeload section. Power-Reduction Modes 10. 11. 12. 13. 14. Power on the IC and bring it out of reset. The order of the power supplies (DVDD, IOVDD, and AVDD) does not matter. Wait at least 10.667 ms for the initialization to complete if the XTALI input is 12.288 MHz and the PLL divider is set to 4 (see the Power-Up Sequence section for information about calculating the initialization time if another fXTALI is used). Enable the master clocks of all modules to be used (see the Master Clock and PLL Modes and Settings section). Set the DSP core rate select register (0xE220) to 0x001C. This disables the start pulse to the core. Deassert the core run bit (see the DSP Core Modes and Settings section). Set the serial input modes (see the Serial Input Port Modes Registers (Address 0xE000 to Address 0xE008) section). Set the serial output modes (see the Serial Output Port Modes Registers (Address 0xE040 to Address 0xE049) section). Set the routing matrix modes (see details of Address 0xE080 to Address 0xE09B in the Flexible Audio Routing Matrix Modes section). Write the parameter RAM (Address 0x0000 to Address 0x0FFF). Write the program RAM (Address 0x2000 to Address 0x2FFF). Write the nonmodulo data RAM (Addresses vary based on the SigmaStudio project file). Write all other necessary control registers, such as ASRCs and S/PDIF (Address 0xE221 to Address 0xE24C). Set the DSP core rate select register (0xE220) to the desired value. This enables the start pulse to the core. Table 12 contains a list of valid settings. Assert the core run bit (see the DSP Core Modes and Settings section). Sections of the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 chips can be turned on and off as needed to reduce power consumption. Table 8. Power-Up Time PLL Lock Time (ms) (fXTALI = 12.288 MHz, PLL Divider = 4) 10.667 Approximate Boot Time; Loading Maximum Program/Parameter/Registers (ms) I2C (@ 400 kHz SCL) 25 SPI (@ 5 MHz CCLK) 2 Rev. C | Page 20 of 92 SPI (@ 25 MHz CCLK) 0.4 Total (ms) 11.067 to 35.667 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 MASTER CLOCK AND PLL Using the Oscillator The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 can use an on-board oscillator to generate its master clock. However, an external crystal must be attached to complete the oscillator circuit. The on-board oscillator is designed to work with a 256 × fS,NORMAL master clock, which is 12.288 MHz when fS,NORMAL is 48 kHz and 11.2896 MHz when fS,NORMAL is 44.1 kHz. The resonant frequency of this crystal should be in this range even when the core is processing dualor quad-rate signals. When the core is processing dual-rate signals (for example, fS,DUAL = 88.2 kHz or 96 kHz), resonant frequency of the crystal should be 128 × fS,DUAL. When the core is processing quad-rate signals (for example, fS,QUAD = 192 kHz), the resonant frequency of the crystal should be 64 × fS,QUAD. The external crystal in the circuit should be an AT-cut parallel resonance device operating at its fundamental frequency. Ceramic resonators should not be used. Figure 9 shows the crystal oscillator circuit recommended for proper operation. C1 XTALO C2 XTALI 07696-009 100 Figure 9. Crystal Oscillator Circuit The 100 damping resistor on XTALO provides the oscillator with a voltage swing of approximately 2.2 V at the XTALI pin. The crystal shunt capacitance should be 7 pF. Its optimal load capacitance, specified by the manufacturer, should be about 18 pF, although the circuit supports values up to 25 pF. The equivalent series resistance should also be as small as possible. The necessary values of Load Capacitor C1 and Load Capacitor C2 can be calculated from the crystal load capacitance with the following equation: CL = C1 × C 2 + C STRAY C1 + C 2 where CSTRAY is the stray capacitance in the circuit and is usually assumed to be approximately 2 pF to 5 pF. Short trace lengths in the oscillator circuit decrease stray capacitance, thereby increasing the loop gain of the circuit and helping to avoid crystal start-up problems. On the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 evaluation boards, the capacitance value for C1 and C2 is 22 pF. XTALO should not be used to directly drive the crystal signal to another IC. This signal is an analog sine wave and is not appropriate to drive a digital input. A separate pin, CLKOUT, is provided for this purpose. CLKOUT can output 256 × fS,NORMAL, 512 × fS,NORMAL, or a buffered, digital copy of the crystal oscillator signal to other ICs in the system. CLKOUT is set up using the CLKMODEx pins. For a more detailed explanation of CLKOUT, refer to the Using the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 as Clock Master section. Setting Master Clock and PLL Mode The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 master clock input feeds a PLL, which generates the 3584 × fS,NORMAL clock (172.032 MHz when fS,NORMAL is 48 kHz) to run the DSP core. This rate is referred to as fCORE. In normal operation, the input to the master clock must be one of the following: 64 × fS,NORMAL, 128 × fS,NORMAL, 256 × fS,NORMAL, 384 × fS,NORMAL, or 512 × fS,NORMAL, where fS,NORMAL is the audio sampling rate with the core in normal-rate processing mode. The PLL divider mode is set by PLL0, PLL1, and PLL2 as detailed in Table 9. If the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 cores are set to receive dual-rate signals (by reducing the number of program steps per sample by a factor of 2 using the DSP core rate select register), then the master clock frequency must be 32 × fS,DUAL, 64 × fS,DUAL, 128 × fS,DUAL, 192 × fS,DUAL, or 256 × fS,DUAL. If the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 cores are set to receive quad-rate signals (by reducing the number of program steps per sample by a factor of 4 using the DSP core rate select register), then the master clock frequency must be 16 × fS,QUAD, 32 × fS,QUAD, 64 × fS,QUAD, 96 × fS,QUAD, or 128 × fS,QUAD. On powerup, a clock signal must be present on XTALI so that the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 can complete its initialization routine. If at any point during operation the clock signal is removed from XTALI, the DSP should be reset to avoid unpredictable behavior on output pins. The clock mode should not be changed without also resetting the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446. If the mode is changed during operation, a click or pop can result on the outputs. The state of the PLLx pins should be changed while RESET is held low. The phase-locked loop uses the PLL mode select pins (PLL0, PLL1, and PLL2) to derive a 64 × fS,NORMAL clock from whatever signal is present at the XTALI pin. This clock signal is multiplied by 56 to produce the core clock. Therefore, fCORE is 3584 × fS,NORMAL. In a system with a fS,NORMAL of 48 kHz, the PLL derives a 3.072 MHz clock and then multiplies it by 56 to produce a 172.032 MHz core clock. The core clock (fCORE) should never exceed 172.032 MHz, though it may be lower in some applications. Rev. C | Page 21 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Table 9. PLL Modes DSP Core Rate 1 Normal Dual Quad Input to MCLK (XTALI Pin) 64 × fS,NORMAL 128 × fS,NORMAL 256 × fS,NORMAL 384 × fS,NORMAL 512 × fS,NORMAL 32 × fS,DUAL 64 × fS,DUAL 128 × fS,DUAL 192 × fS,DUAL 256 × fS,DUAL 16 × fS,QUAD 32 × fS,QUAD 64 × fS,QUAD 96 × fS,QUAD 128 × fS,QUAD PLL2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 PLL1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 PLL0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 PLL Divider 2 1 2 4 6 8 1 2 4 6 8 1 2 4 6 8 Core Clock Multiplier 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 Core Clock (fCORE) 3584 × fS,NORMAL 3584 × fS,NORMAL 3584 × fS,NORMAL 3584 × fS,NORMAL 3584 × fS,NORMAL 1792 × fS,DUAL 1792 × fS,DUAL 1792 × fS,DUAL 1792 × fS,DUAL 1792 × fS,DUAL 896 × fS,QUAD 896 × fS,QUAD 896 × fS,QUAD 896 × fS,QUAD 896 × fS,QUAD Instructions per Sample 3584 3584 3584 3584 3584 1792 1792 1792 1792 1792 896 896 896 896 896 1 If the normal DSP core rate (fS,NORMAL) is 44.1 kHz, the dual DSP core rate (fS,DUAL) is 88.2 kHz, and the quad DSP core rate (fS,QUAD) is 176.4 kHz. Likewise, if fS,NORMAL is 48 kHz, then fS,DUAL is 96 kHz and fS,QUAD is 192 kHz. 2 The PLL divider is set by the PLLx pins. XTALI fS,NORMAL × 64, 128, 256, 384, 512 fS,DUAL × 32, 64, 128, 192, 256 fS,QUAD × 16, 32, 64, 96, 128 REGISTER 0xE220 SELECTS THE DSP CORE RATE (NORMAL, DUAL, QUAD) fS,NORMAL × 64 fS,DUAL × 32 fS,QUAD × 16 fS,NORMAL × 3584 fS,DUAL × 1792 fS,QUAD × 896 ÷ × PLL DIVIDER CORE CLOCK MULTIPLIER Figure 10. Master Clock Signal Flow Rev. C | Page 22 of 92 DSP CORE 07696-010 PLL MODE PINS SELECT THE PLL DIVIDER (1, 2, 4, 6, 8) ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 PLL Loop Filter The PLL loop filter should be connected to the PLL_FILT pin. This filter, shown in Figure 11, includes three passive components- two capacitors and a resistor. The values of these components do not need to be exact; the tolerance can be up to 10% for the resistor and up to 20% for each capacitor. The 3.3 V signal shown in the schematic can be connected to the PVDD supply of the chip. PVDD 1.5k 33nF ADAU1442/ ADAU1442/ ADAU1445/ ADAU1445/ ADAU1446 ADAU1446 PLL_FILT 07696-011 1.8nF Figure 11. PLL Loop Filter Using the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 as Clock Masters To output a master clock from the ADAU1442/ADAU1445/ ADAU1442/ADAU1445/ ADAU1446 ADAU1446 to other chips in the system, the CLKOUT pin is used. To set the frequency of this clock signal, the CLKMODEx pins must be set (see Table 10). Table 10. CLKOUT Modes CLKOUT Signal Disabled Buffered Oscillator 256 × fS,NORMAL 512 × fS,NORMAL CLKMODE1 0 0 1 1 CLKMODE0 0 1 0 1 Master Clock and PLL Modes and Settings DSP Core Rate Select Register (Address 0xE220) The core's start pulse initiates the operation of the core and determines the sample rate of signals processed inside the core. This pulse can originate from one of three internally generated fS signals (fS,NORMAL, fS,DUAL, or fS,QUAD), one of the 12 serial input fS signals (an LRCLK signal associated with a serial input port), one of the 12 serial output fS signals (an LRCLK signal associated with a serial output port), or LRCLK recovered from the S/PDIF receiver input. Setting the value of the DSP core rate select register sets the speed of the DSP core (see Table 12). By default, the signals processed in the core are at the normal DSP core rate; therefore, the core clock is 3584 × fS,NORMAL. For a system processing signals in the core at the dual rate, the start pulse should be set to the internally generated dual rate, and the core clock is 1792 × fS,DUAL. For a system processing signals in the core at the quad rate, the start pulse should be set to the internally generated quad rate, and the core clock is 896 × fS,QUAD. Master Clock Enable Switch Register (Address 0xE280) For power-saving purposes, various parts of the chip can be switched on and off. Setting the appropriate bit to 0 disables the corresponding subsystem, and setting the bit to 1 enables the subsystem. This is the first register that should be set after the device is powered on and completes its initialization. Failure to set this register may compromise future register writes. Table 11. Bit Descriptions of Register 0xE280 Bit Position [15:9] 8 7 6 5 4 3 2 1 0 1 2 Description 1 Reserved Enable MCLK to auxiliary ADCs Enable MCLK to S/PDIF transmitter Enable MCLK to S/PDIF receiver Enable MCLK to DSP core Enable MCLK to Stereo ASRC[7:4] 2 Enable MCLK to Stereo ASRC[3:0]2 Enable MCLK to serial outputs Enable MCLK to serial inputs Enable MCLK to flexible audio routing matrix (FARM) Default 0 0 0 0 0 0 0 0 0 0 = disable, 1 = enable. See the Flexible Audio Routing Matrix-Input Side section for more information. Rev. C | Page 23 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Table 12. Bit Descriptions of Register 0xE220 Bit Position [15:5] [4:0] 1 Description Reserved Start pulse select 00000 = internally generated normal rate (fS,NORMAL) 00001 = internally generated dual rate (fS,DUAL) 00010 = internally generated quad rate (fS,QUAD) 00011 = fS from serial input Stereo Pair 0 1 00100 = fS from serial input Stereo Pair 11 00101 = fS from serial input Stereo Pair 21 00110 = fS from serial input Stereo Pair 31 00111 = fS from serial input Stereo Pair 41 01000 = fS from serial input Stereo Pair 51 01001 = fS from serial input Stereo Pair 61 01010 = fS from serial input Stereo Pair 71 01011 = fS from serial input Stereo Pair 81 01100 = fS from serial input Stereo Pair 91 01101 = fS from serial input Stereo Pair 101 01110 = fS from serial input Stereo Pair 111 01111 = fS from serial output Stereo Pair 01 10000 = fS from serial output Stereo Pair 11 10001 = fS from serial output Stereo Pair 21 10010 = fS from serial output Stereo Pair 31 10011 = fS from serial output Stereo Pair 41 10100 = fS from serial output Stereo Pair 51 10101 = fS from serial output Stereo Pair 61 10110 = fS from serial output Stereo Pair 71 10111 = fS from serial output Stereo Pair 81 11000 = fS from serial output Stereo Pair 91 11001 = fS from serial output Stereo Pair 101 11010 = fS from serial output Stereo Pair 111 11011 = fS from S/PDIF receiver1 11100 = no start pulse; core is disabled 11101 = no start pulse; core is disabled 11110 = no start pulse; core is disabled 11111 = no start pulse; core is disabled Default 00000 fS is the LRCLK of the associated stereo audio pair in the flexible audio routing matrix whose frequency is dependent on the settings of its associated serial port and the clock pad multiplexer. The intended function of the DSP core rate select register is to allow the DSP core to be synchronized to an external LRCLK signal that is being used by any of the serial ports or S/PDIF receiver. Rev. C | Page 24 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 VOLTAGE REGULATOR The digital supply voltage of the ADAU1442/ADAU1445/ ADAU1442/ADAU1445/ ADAU1446 ADAU1446 must be set to 1.8 V. The chip includes an on-board voltage regulator that allows the device to be used in systems where a 1.8 V supply is not available but a 3.3 V supply is. The only external components needed for this are a PNP transistor and one resistor. Only one pin, VDRIVE, is necessary to support the regulator. The recommended design for the voltage regulator is shown in Figure 12. The 10 F and 100 nF capacitors shown in this schematic are recommended for bypassing but are not necessary for operation. Each DVDD pin should have its own 100 nF bypass capacitor, but only one bulk capacitor (10 F) is needed for all pins. In this design, 3.3 V is the main system voltage; 1.8 V is generated at the collector of the transistor, which is connected to the DVDD pins. VDRIVE is connected to the base of the PNP transistor. If the regulator is not used in the design, VDRIVE can be tied to ground. + 1k DVDD VDRIVE Many transistors fit these specifications. Analog Devices recommends the NJT4030P NJT4030P from On Semiconductor. For projects with stringent size constraints, an FMMT734 FMMT734 from Zetex can be used. The ADAU1446 ADAU1446, which does not contain ASRCs, has a lower maximum digital current draw of approximately 235 mA. The maximum power dissipation of the transistor in this case should be around 355 mW. SRC GROUP DELAY For fS_OUT > fS_IN, 07696-012 ADAU1442/ ADAU1442/ ADAU1445/ ADAU1445/ ADAU1446 ADAU1446 (3.3 V - 1.8 V) × 310 mA = 465 mW The group delay of the sample rate converter is dependent on the input and output sampling frequencies as described in the following equations. 3.3V 10µF 100nF Two specifications must be considered when choosing a regulator transistor: the current amplification factor (hFE or beta) should be at least 200, and the collector must be able to dissipate the heat generated when regulating from 3.3 V to 1.8 V. The maximum digital current draw of the ADAU1442 ADAU1442 and ADAU1445 ADAU1445, which use ASRCs, is 310 mA. The equation to determine the minimum power dissipation specifications of the transistor is as follows: GDS = 16 f S _ IN + 32 f S _ IN For fS_OUT < fS_IN, Figure 12. Voltage Regulator Design GDS = 16 f S _ IN 32 f S _ IN × + f S _ IN f S _ OUT where GDS is the group delay in seconds. Rev. C | Page 25 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 CONTROL PORT I2C Port Overview The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 support a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. Two pins, serial data (SDA) and serial clock (SCL), carry information between the ADAU1442/ADAU1445/ ADAU1442/ADAU1445/ ADAU1446 ADAU1446 and the system I2C master controller. In I2C mode, the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 are always slaves on the bus, which means that the parts cannot initiate a data transfer. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 can operate in one of three control modes: I2C control mode, SPI control mode, or self-boot mode (no external controller). The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 have both a 4-wire SPI control port and a 2-wire I2C bus control port. Each can be used to set the RAMs and registers. When the SELFBOOT pin is low at power-up, the chip defaults to I2C mode but can be put into SPI control mode by pulling Pin CLATCH low three times. When the SELFBOOT pin is set high at power-up, the ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446 load the program, parameters, and register settings from an external EEPROM at startup. The control port is capable of full read and write operations for all memories and registers, except for those that are read only. Most signal processing parameters are controlled by writing new values to the parameter RAM using the control port. Other functions, such as mute and input/output mode control, are programmed by writing to the registers. All addresses can be accessed in either a single-word mode or a burst mode. A control word consists of the chip address, the register/RAM subaddress, and the data to be written. The number of bytes per word depends on the type of data that is being written. The first byte (Byte 0) of a control word contains the 7-bit chip address plus the R/W bit. The next two bytes (Byte 1 and Byte 2) together form the subaddress of the memory or register location within the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446. This subaddress must be two bytes because the memory locations within the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 are directly addressable, and their sizes exceed the range of single-byte addressing. All subsequent bytes (starting with Byte 3) contain the data, such as control port data, program data, or parameter data. The exact formats for specific types of writes are shown in Figure 13 and Figure 19. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 have several mechanisms for updating signal processing parameters in real time without causing pops or clicks in the output. In cases where large blocks of data must be downloaded, the output of the DSP core can be halted, new data can be loaded, and then the output of the DSP core can be restarted. This is typically done during the booting sequence at startup or when loading a new program into RAM. In cases where only a few parameters must be changed, they can be loaded without halting the program. A software-based safeload mechanism is included for this purpose, and it can be used to buffer a full set of parameters (for example, the five coefficients of a biquad) and then transfer these parameters into the active program within one audio frame. The control port pins are multifunctional according to the mode in which the part is operating. Table 16 details these functions. Each slave device is recognized by a unique address. The address bit sequence is shown in Table 13. The ADAU1442/ADAU1445/ ADAU1442/ADAU1445/ ADAU1446 ADAU1446 have eight possible slave addresses: four for writing operations and four for reading. These are unique addresses for the device and are listed in Table 14. Users can communicate with these addresses by using the USBi communication channel list in the hardware configuration tab of SigmaStudio. The LSB of the byte sets either a read or write operation; Logic Level 1 corresponds to a read operation, and Logic Level 0 corresponds to a write operation. Address Bit 5 and Address Bit 6 are set by tying the ADDRx pins of the ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446 to Logic Level 0 or Logic Level 1. Both SDA and SCL should have pull-up resistors on the lines connected to them (a standard value is 2.0 k, but this can be changed depending on the capacitive load on the line). The voltage on these signal lines should not be greater than the voltage of IOVDD (3.3 V). Table 13. ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Address Bit Sequence Bit 0 0 Bit 1 1 Bit 2 1 Bit 3 1 Bit 4 0 Bit 5 ADDR1 Bit 6 ADDR0 Bit 7 R/W Table 14. ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 I2C Slave Addresses ADDR1 0 0 0 0 1 1 1 1 1 ADDR0 0 0 1 1 0 0 1 1 Read/Write1 0 1 0 1 0 1 0 1 Slave Address 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0 = write, 1 = read. Addressing Initially, all devices on the I2C bus are in an idle state, in which the devices monitor the SDA and SCL lines for a start condition and the proper address. The I2C master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address or an address and data stream follow. All devices on the bus respond to the start condition and shift the next eight bits (7-bit address + R/W bit) MSB first. The device that recognizes the transmitted Rev. C | Page 26 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 address responds by pulling the data line low during the ninth clock pulse. This ninth bit is known as an acknowledge bit. All other devices withdraw from the bus at this point and return to the idle condition. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. A Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. A data transfer takes place until a stop condition is encountered. A stop condition occurs when SDA transitions from low to high while SCL is held high. Figure 13 shows the timing of an I2C write. Burst mode addressing, where the subaddresses are automatically incremented at word boundaries, can be used for writing large amounts of data to contiguous memory locations. This increment happens automatically, unless a stop condition is encountered after a single-word write. The registers and RAMs in the ADAU1445/ ADAU1445/ ADAU1446 ADAU1446 range in width from one to five bytes; therefore, the auto-increment feature knows the mapping between subaddresses and the word length of the destination register (or memory location). A data transfer is always terminated by a stop condition. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446 do not issue an acknowledge and return to the idle condition. If the user exceeds the highest subaddress while in auto-increment mode, one of two actions is taken. In read mode, the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 output the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of a read. A no-acknowledge condition is where the SDA line is not pulled low on the ninth clock pulse on SCL. If the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446, and the part returns to the idle condition. I2C Read and Write Operations Figure 15 shows the sequence of a single-word write operation. Every ninth clock, the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 issue an acknowledge by pulling SDA low. Figure 16 shows the sequence of a burst mode write operation. This figure shows an example in which the target destination registers are two bytes. The ADAU1442/ADAU1445/ ADAU1442/ADAU1445/ ADAU1446 ADAU1446 know to increment the subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with a 2-byte word length. The sequence of a single-word read operation is shown in Figure 17. Note that, even though this is a read operation, the first R/W bit is a 0, indicating a write operation. This is because the subaddress must be written to set up the internal address. After the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 acknowledge the receipt of the subaddress, the master must issue a repeated start command followed by the chip address byte with the R/W set to 1, indicating a read operation. This causes the SDA pin of the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 to switch directions and begin driving data back to the master. The master then responds every ninth pulse with an acknowledge pulse to the ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446. Figure 18 shows the sequence of a burst mode read operation. This figure shows an example in which the target read registers are two bytes. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 increment the subaddress every two bytes because the requested subaddress corresponds to a register or memory area with word lengths of two bytes. Other address ranges can have a variety of word lengths, ranging from one to five bytes; the ADAU1442/ADAU1445/ ADAU1442/ADAU1445/ ADAU1446 ADAU1446 always decode the subaddress and set the autoincrement circuit so that the address increments after the appropriate number of bytes. SCL SDA START BY MASTER 0 1 1 1 0 0 ADR SEL R/W ACK BY ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 FRAME 1 CHIP ADDRESS BYTE ACK BY ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 FRAME 2 SUBADDRESS BYTE 1 ACK BY ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 FRAME 2 SUBADDRESS BYTE 2 ACK BY ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 FRAME 3 DATA BYTE 1 SCL (CONTINUED) Figure 13. I2C Write Clocking Rev. C | Page 27 of 92 STOP BY MASTER 07696-013 SDA (CONTINUED) ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 SCL 0 SDA 1 1 1 0 0 ADR SEL R/W ACK BY ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 FRAME 2 SUBADDRESS BYTE 1 ACK BY ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 FRAME 1 CHIP ADDRESS BYTE START BY MASTER SCL (CONTINUED) SDA (CONTINUED) 0 1 ACK BY REPEATED ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 START BY MASTER FRAME 3 SUBADDRESS BYTE 2 1 1 0 ADR SEL 0 R/W ACK BY ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 FRAME 4 CHIP ADDRESS BYTE SCL (CONTINUED) SDA (CONTINUED) ACK BY MASTER STOP BY MASTER 07696-014 ACK BY MASTER FRAME 5 READ DATA BYTE 1 FRAME 6 READ DATA BYTE 2 Figure 14. I2C Read Clocking CHIP ADDRESS, R/W = 0 AS SUBADDRESS, HIGH AS SUBADDRESS, LOW DATA BYTE 1 AS DATA BYTE 2 AS AS . DATA BYTE N AS P 07696-015 S S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE. SHOWS A ONE-WORD WRITE, WHERE EACH WORD HAS N BYTES. Figure 15. Single-Word I2C Write Sequence CHIP ADDRESS, R/W = 0 AS SUBADDRESS, HIGH AS SUBADDRESS, LOW AS AS AS AS AS . DATA-WORD 1, DATA-WORD 1, DATA-WORD 2, DATA-WORD 2, BYTE 1 BYTE 2 BYTE 1 BYTE 2 AS AS P DATA-WORD N, DATA-WORD N, BYTE 1 BYTE 2 S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE. SHOWS AN N-WORD WRITE, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.) 07696-016 S Figure 16. Burst Mode I2C Write Sequence CHIP ADDRESS, R/W = 0 AS SUBADDRESS, HIGH AS SUBADDRESS, LOW AS S CHIP ADDRESS, R/W = 1 AS DATA BYTE 1 AM DATA BYTE 2 AM DATA BYTE N . AM P AM P 07696-017 S S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE. SHOWS A ONE-WORD WRITE, WHERE EACH WORD HAS N BYTES. Figure 17. Single-Word I2C Read Sequence CHIP ADDRESS, R/W = 0 AS SUBADDRESS, HIGH AS SUBADDRESS, LOW AS S CHIP ADDRESS, R/W = 1 AS AM DATA-WORD 1, BYTE 1 AM DATA-WORD 1, BYTE 2 . AM DATA-WORD N, DATA-WORD N, BYTE 1 BYTE 2 S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE. SHOWS AN N-WORD WRITE, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.) Figure 18. Burst Mode I2C Read Sequence Rev. C | Page 28 of 92 07696-018 S ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 SPI Port allows two ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 devices to share a CLATCH signal, yet still operate independently. When ADDR0 is low, the chip address is 0000000; when ADDR0 is high, the address is 0000001. The LSB of the first byte determines whether the SPI transaction is a read (Logic Level 1) or a write (Logic Level 0). Users can communicate with both ICs with up to five latch signals by using the USBi communication channel list in the hardware configuration tab in SigmaStudio. 2 By default, the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 are in I C mode, but these parts can be put into SPI control mode by pulling CLATCH low three times. Each low pulse should have a minimum duration of 20 ns, and the delay between pulses should be at least 20 ns. The SPI port uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA, and COUT signals. The CLATCH signal goes low at the beginning of a transaction and high at the end of a transaction. The CCLK signal latches CDATA on a low-to-high transition. COUT data is shifted out of the ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446 on the falling edge of CCLK and should be clocked into a receiving device, such as a microcontroller, on the next CCLK falling edge (rising edge is possible if tCOV timing is met). The CDATA signal carries the serial input data, and the COUT signal is the serial output data. The COUT signal remains three-stated until a read operation is requested. This allows other SPI-compatible peripherals to share the same readback line. All SPI transactions have the same word sequence shown in Table 15 (see Figure 4 for an SPI port timing diagram). All data written should be MSB first. Subaddress The 16-bit subaddress word is decoded into a location in one of the memories or registers. This subaddress is the location of the appropriate RAM location or register. Data Bytes The number of data bytes varies according to the register or memory being accessed. In burst write mode, an initial subaddress is given followed by a continuous sequence of data for consecutive memory or register locations. A sample timing diagram for a single SPI write operation to the parameter RAM is shown in Figure 19. A sample timing diagram of a single SPI read operation is shown in Figure 20. The COUT pin goes from three-state to driven at the beginning of Byte 3. In this example, Byte 0 to Byte 2 contain the addresses and R/W bit, and subsequent bytes carry the data. Chip Address R/W The first byte of an SPI transaction includes the 7-bit chip address and a R/W bit. The chip address is set by the ADDR0 pin. This Table 15. Generic Control Word Sequence Byte 0 Chip Address[6:0], R/W Byte 2 Subaddress[7:0] Byte 4 1 Data Byte 3 Data Continues to end of data. CLATCH CDATA BYTE 0 BYTE 1 BYTE 2 07696-019 CCLK BYTE 3 Figure 19. SPI Write Clocking (Single-Write Mode) CLATCH CCLK CDATA COUT BYTE 1 BYTE 0 BYTE 2 HIGH-Z DATA Figure 20. SPI Read Clocking (Single-Read Mode) Rev. C | Page 29 of 92 DATA HIGH-Z 07696-020 1 Byte 1 Subaddress[15:8] ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Self-Boot On power-up, the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 can load a program and a set of parameters that are saved in an external EEPROM. Combined with the auxiliary ADC and the multipurpose pins, this can potentially eliminate the need for a microcontroller in a simple audio system. The self-boot sequence is accomplished by the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 acting as masters on the I2C bus on startup, which occurs when the SELFBOOT pin is set high. The ADAU1442/ADAU1445/ ADAU1442/ADAU1445/ ADAU1446 ADAU1446 cannot self-boot in SPI mode. The maximum necessary EEPROM size is 40,960 bytes, or 40 kB. This much memory is only needed if the program RAM (4096 × 6 bytes) and parameter RAM (4096 × 4 bytes) are each completely full. A self-boot operation is triggered on the rising edge of RESET when the SELFBOOT pin is set high, and it occurs after 10 ms when the PLL has locked. The ADAU1442/ADAU1445/ ADAU1442/ADAU1445/ ADAU1446 ADAU1446 read the program, parameter, and register data from the EEPROM. After the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 have finished self-booting, additional messages can be sent to the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 on the I2C bus, although this typically is not necessary in a self-booting application. The I2C device address for the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 is 0x68 for a write and 0x69 for a read in this mode. The ADDRx pins have different functions when the chip is in this mode; therefore, the settings on them are ignored. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 are masters on the I2C bus during a self-boot operation. Care should be taken that no other device on the I2C bus tries to perform a write operation during self-booting. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 generate SCL at 8 × fs; therefore, when fs,NORMAL is 48 kHz, SCL runs at 384 kHz. SCL has a duty cycle of in accordance with the I2C specification. The ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 read from EEPROM Chip Address 0xA1. The LSBs of the addresses of some EEPROMs are pin configurable; in most cases, these pins should be tied low to set this address. SigmaStudio writes to the EEPROM at Address 0xA0. EEPROM Format The EEPROM data contains a sequence of messages. Each discrete message is one of the four types defined in Table 17. Each message consists of a sequence of one or more bytes. The first byte identifies the message type. Bytes are written MSB first. Most messages are block write (0x01) types, which are used for writing to the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 program RAM, parameter RAM, and control registers. The body of the message following the message type should start with two bytes indicating message length and then include a byte indicating the chip address. Following this is always a 2-byte register or memory address field, as with all other control port transactions. SigmaStudio is capable of generating the EEPROM data necessary to self-boot the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446, using the function called write latest compilation to E2PROM. This function can be accessed by right-clicking the ADAU1442/ADAU1445/ ADAU1442/ADAU1445/ ADAU1446 ADAU1446 IC in the hardware configuration window. Table 16. Functions of the Control Port Pins Pin SCL/CCLK SDA/COUT ADDR1/CDATA CLATCH ADDR0 I2C Mode SCL-input SDA-open collector output ADDR1-input Unused input-tie to ground or power ADDR0-input SPI Mode CCLK-input COUT-output CDATA-input CLATCH-input ADDR0-input Self-Boot SCL-output SDA-open collector output Unused input-tie to ground or power Unused input-tie to ground or power Unused input-tie to ground or power Table 17. EEPROM Message Types Message ID 0x00 0x01 Message Type End Write 0x02 0x03 Delay No op Following Bytes None One byte indicating message length (including chip address and subaddress), one byte indicating chip address, two bytes indicating subaddress, and an appropriate number of data bytes Two bytes for delay None Rev. C | Page 30 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 SERIAL DATA INPUT/OUTPUT The flexible serial data input and output ports of the ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446 can be set to accept or transmit data in a 2-channel (usually I2S format), packed TDM4, or standard 4-, 8-, or 16-channel TDM stream. Data is processed in twos complement, MSB-first format. The left-channel data field always precedes the right-channel data field in 2-channel streams. In the TDMn modes (where n represents the total number of channels in the stream), Slot 0 to Slot (n/2) - 1 fall in the first half of the audio frame, and Slot n/2 to Slot n - 1 are in the second half of the frame. TDM mode allows fewer serial data pins to be used, freeing more pins for other data streams. The serial modes are set in the serial output port modes and serial input port modes control registers. When referring to audio data streams, the terms TDM2 and I2S should be treated with care. In this document, TDM2 refers to any 2-channel stream, whereas I2S refers specifically to a 2-channel, negative BCLK polarity, negative LRCLK polarity, MSB delayby-1 stream. The serial data clocks are fully bidirectional and do not need to be synchronous with the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 master clock input. However, asynchronous data streams must be routed through an on-board asynchronous sample rate converter to be processed in the core. The input control registers allow control of clock polarity and data input modes. All common data formats are available with flexible MSB start, bit depth (24-, 20-, or 16-bit), and TDM settings. In all modes except the right-justified modes, the serial port accepts an arbitrary number of bits up to a limit of 24. Extra bits do not cause an error, but they are truncated internally. Proper operation of the right-justified modes requires that there be exactly 64 BCLKs per audio frame (for 2-channel data). The LRCLK in TDM mode can be input to the ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 either as a 50/50 duty cycle clock or as a bit-wide pulse. In TDM mode, the bit clock supplied by the ADAU1442/ ADAU1442/ ADAU1445/ADAU1446 ADAU1445/ADAU1446 in master mode is limited to 25 MHz. This, in turn, limits the sampling rate at which it can supply master clocks in various TDM modes. Table 18 displays the modes in which the serial output port functions for some common audio sample rates. The output control registers give the user control of clock polarities, clock frequencies, clock types, and data format. In all modes except the right-justified modes (MSB delayed by 8, 12, or 16), the serial port accepts an arbitrary number of bits up to a limit of 24. Extra bits do not cause an error, but are truncated internally. Proper operation of the right-justified modes requires the LSB to align with the edge of the LRCLK. The default settings of all serial port control registers correspond to 2-channel, I2S mode, and 24-bit slave mode, and these registers are set as slaves to the clock domain corresponding to their channel number. Table 18. Serial Input and Output Port TDM Capabilities Mode TDM2 TDM4 TDM8 TDM16 TDM16 1 BCLK Cycles per Frame 64 64 64 64 64 128 128 128 128 128 256 256 256 256 256 512 512 512 512 512 fS (kHz) 44.1 48 88.2 96 192 44.1 48 88.2 96 192 44.1 48 88.2 96 192 44.1 48 88.2 96 192 BCLK Frequency (MHz) 2.8224 3.072 5.6448 6.144 12.288 5.6448 6.144 11.2896 12.288 24.576 11.2896 12.288 22.5792 24.576 49.152 22.5792 24.576 45.1584 49.152 98.304 Valid Mode Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No1 Yes Yes No1 No1 No1 The device will not work in this mode. Connections to an external DAC are handled exclusively with the output port pins. The output LRCLKx and BCLKx pins can be set to be either master or slave, and the SDATA_OUT pins are used to output data from the SigmaDSP to the external DAC. Table 19 shows the proper configurations for standard audio data formats, and Figure 21 presents an overview of the serial data input/output ports. Rev. C | Page 31 of 92 ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Table 19. Configurations for Standard Audio Data Formats LRCLK Polarity Frame begins on falling edge Frame begins on rising edge Frame begins on rising edge Frame begins on falling edge Frame begins on rising edge LRCLK Type Clock BCLK Polarity Data changes on falling edge MSB Position Delayed from LRCLKx edge by 1 BCLK Clock Data changes on falling edge Aligned with LRCLKx edge Clock Data changes on falling edge Delayed from LRCLKx edge by 8, 12, or 16 BCLKs Clock Data changes on falling edge Delayed from start of frame clock by 1 BCLK Pulse Data changes on falling edge Delayed from start of frame clock by 1 BCLK SERIAL OUTPUT MODES SERIAL INPUT MODES DSP CORE FARM 3 4 5 6 7 8 3 4:2 4:2 4:2 4:2 4:2 4:2 DEDICATED INPUT CLOCK DOMAINS (×3) 2 6 7 8 9 10 11 ASSIGNABLE INPUT/OUTPUT DOMAINS (×6) Figure 21. Overview of Serial Data Input/Output Ports Rev. C | Page 32 of 92 2 2 2 BCLK8/LRCLK8 2 5 9 TO 11 BCLK7/LRCLK7 2 BCLK4/LRCLK4 BCLK3/LRCLK3 2 BCLK5/LRCLK5 2 4 CLOCK PAD MULTIPLEXERS 3 TO 8 BCLK2/LRCLK2 BCLK0/LRCLK0 2 BCLK1/LRCLK1 0 TO 2 2 18:2 (×9) 2 2 DEDICATED OUTPUT CLOCK DOMAINS (×3) 07696-030 2 BCLK6/LRCLK6 1 OUTPUT CLOCK DOMAIN SELECTOR INPUT CLOCK DOMAIN SELECTOR 18:2 (×9) 0 SERIAL OUTPUT PORTS (×9) AND BCLK11/LRCLK11 BCLK11/LRCLK11 SERIAL INPUT PORTS (×9) SDATA_OUT0 SDATA_OUT1 SDATA_OUT2 SDATA_OUT3 SDATA_OUT4 SDATA_OUT5 SDATA_OUT6 SDATA_OUT7 SDATA_OUT8 BCLK9/LRCLK9 SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3 SDATA_IN4 SDATA_IN5 SDATA_IN6 SDATA_IN7 SDATA_IN8 BCLK10/LRCLK10 BCLK10/LRCLK10 Format I2S (Figure 22) Left-Justified (Figure 23) Right-Justified (Figure 24) TDM with Clock (Figure 25) TDM with Pulse (Figure 26) ADAU1442/ADAU1445/ADAU1446 ADAU1442/ADAU1445/ADAU1446 Serial Audio Data Timing Diagrams Figure 22 to Figure 26 show timing diagrams for standard audio data formats. LEFT CHANNEL LRCLKx RIGHT CHANNEL LSB MSB LSB MSB 07696-021 BCLKx SDATA_INx, SDATA_OUTx 1/FS 2 Figure 22. I S Mode-16 Bits to 24 Bits per Channel BCLKx SDATA_INx, SDATA_OUTx RIGHT CHANNEL LEFT CHANNEL MSB LSB MSB LSB 07696-022 LRCLKx 1/FS Figure 23. Left-Justified Mode-16 Bits to 24 Bits per Channel RIGHT CHANNEL LEFT CHANNEL BCLKx SDATA_INx, SDATA_OUTx MSB LSB MSB LSB 07696-023 LRCLKx 1/FS Figure 24. Right-Justified Mode-16 Bits to 24 Bits per Channel LRCLKx 256 BCLKs BCLKx 32 BCLKs SDATA_INx, SDATA_OUTx SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LRCLK MSB ­ 1 MSB ­ 2 07696-024 BCLK MSB DATA Figure 25. TDM Mode LRCLKx BCLKx MSB TDM MSB TDM CH 0 SLOT 0 CH 8 SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 07696-025 SDATA_I