AD9874 APCO25 VDDC16 AD9874BST AD9874EB ST-48 16-BIT 24-BIT ADSP-2153X LOR/16 - Datasheet Archive

 

IF Digitizing Subsystem AD9874* FEATURES 10 MHz­300 MHz Input Frequency 6.8 kHz­270 kHz Output Signal Bandwidth 8.1 dB

 

a IF Digitizing Subsystem AD9874 AD9874* FEATURES 10 MHz­300 MHz Input Frequency 6.8 kHz­270 kHz Output Signal Bandwidth 8.1 dB SSB NF 0 dBm IIP3 AGC Free Range up to ­34 dBm 12 dB Continuous AGC Range 16 dB Front End Attenuator Baseband I/Q 16-bit (or 24-bit) Serial Digital Output LO and Sampling Clock Synthesizers Programmable Decimation Factor, Output Format, AGC, and Synthesizer Settings 370 Input Impedance 2.7 V­3.6 V Supply Voltage Low Current Consumption: 20 mA 48­Lead LQFP Package (1.4 mm Thick) GENERAL DESCRIPTION APPLICATIONS Multimode Narrowband Radio Products Analog/Digital UHF/VHF FDMA Receivers TETRA, APCO25 APCO25, GSM/EDGE Portable and Mobile Radio Products Base Station Applications The SPI port programs numerous parameters of the AD9874 AD9874, thus allowing the device to be optimized for any given application. Programmable parameters include the following: synthesizer divide ratios; AGC attenuation and attack/decay time; the received signal strength level; decimation factor; the output data format; 16 dB attenuator; and the selected bias currents. The bias currents of the LNA and mixer can be further reduced at the expense of the degraded performance for batterypowered applications. The AD9874 AD9874 is a general-purpose IF subsystem that digitizes a low level 10 MHz­300 MHz IF input with a signal bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9874 AD9874 consists of a low noise amplifier, a mixer, a band-pass sigma-delta analog-to-digital converter, and a decimation filter with programmable decimation factor. An automatic gain control (AGC) circuit gives the AD9874 AD9874 12 dB of continuous gain adjustment. Auxiliary blocks include both clock and LO synthesizers. The AD9874 AD9874's high dynamic range and inherent antialiasing provided by the band-pass sigma-delta converter allow the AD9874 AD9874 to cope with blocking signals up to 95 dB stronger than the desired signal. This attribute can often reduce the cost of a radio by reducing its IF filtering requirements. Also, it enables multimode radios of varying channel bandwidths, allowing the IF filter to be specified for the largest channel bandwidth. FUNCTIONAL BLOCK DIAGRAM MXOP MXON IF2P IF2N GCP GCN DAC AD9874 AD9874 AGC ­16dB IFIN - ADC LNA DECIMATION FILTER FORMATTING/SSI DOUTA DOUTB FS CLKOUT FREF CONTROL LOGIC LO SYNC IOUTL SAMPLE CLOCK SYNTHESIZER LOP LON LO VCO AND LOOP FILTER IOUTC CLKP CLKN VOLTAGE REFERENCE VREFP VCM VREFN SPI PC PD PE SYNCB LO VCO AND LOOP FILTER *Protected by U.S. Patent No. 5,969,657; other patents pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 = VDDD = VDDH 2.7 to AD9874 AD9874­SPECIFICATIONS (VDDI f= VDDF = VDDA =f VDDC16 VDDC16.8VDDL =unless otherwise= noted.)3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, f = 18 MSPS, f = 109.65 MHz, = 107.4 MHz, = MHz, CLK IF Parameter LO 1 REF Temp Test Level Min Typ Max Unit SYSTEM DYNAMIC PERFORMANCE SSB Noise Figure @ Min VGA Attenuation3, 4 @ Max VGA Attenuation3, 4 Dynamic Range with AGC Enabled3, 4 IF Input Clip Point @ Max VGA Attenuation3 @ Min VGA Attenuation3 Input Third Order Intercept (IIP3) Gain Variation over Temperature Full Full Full Full Full Full Full IV IV IV IV IV IV IV 8.1 13 95 ­19 ­31 0 0.7 9.5 dB dB dB dBm dBm dBm dB LNA + MIXER Maximum RF and LO Frequency Range LNA Input Impedance Mixer LO Input Resistance Full 25oC 25oC IV V V 300 LO SYNTHESIZER LO Input Frequency LO Input Amplitude FREF (Reference) Frequency FREF Input Amplitude Minimum Charge Pump Current @ 5 V5 Maximum Charge Pump Current @ 5 V5 Charge Pump Output Compliance6 Synthesizer Resolution Full Full Full Full Full Full Full Full IV IV IV IV VI VI VI IV 7.75 0.3 0.1 0.3 0.48 3.87 0.4 6.25 CLOCK SYNTHESIZER CLK Input Frequency CLK Input Amplitude Minimum Charge Pump Output Current5 Maximum Charge Pump Output Current5 Charge Pump Output Compliance6 Synthesizer Resolution Full Full Full Full Full Full IV IV VI VI VI IV 13 0.3 0.48 3.87 0.4 2.2 SIGMA-DELTA ADC Resolution Clock Frequency (fCLK) Center Frequency Pass-Band Gain Variation Alias Attenuation Full Full Full Full Full IV IV V IV IV 16 13 GAIN CONTROL Programmable Gain Step AGC Gain Range (Continuous) Full Full V V Full VI 2.7 3.0 3.6 V Full VI 2.7 3.0 3.6 V Full VI 1.8 3.6 V Full VI 2.7 5.0 5.5 V Full Full Full VI VI VI 20 17 0.01 26.5 22 0.1 mA mA mA +85 °C 2 OVERALL Analog Supply Voltage (VDDA, VDDF, VDDI) Digital Supply Voltage (VDDD, VDDC, VDDL) Interface Supply Voltage7 (VDDH) Charge Pump Supply Voltage (VDDP, VDDQ) Total Current High Performance Setting8 Low Power Mode8 Standby OPERATING TEMPERATURE RANGE 91 ­20 ­32 ­5 2 500 370//1.4 1 MHz //pF k 0.67 5.3 MHz V p-p MHz V p-p mA mA V kHz 26 VDDC 0.78 6.2 VDDQ ­ 0.4 MHz V p-p mA mA V kHz 24 26 0.67 5.3 300 2.0 25 3 0.78 6.2 VDDP ­ 0.4 Bits MHz MHz dB dB fCLK/8 1.0 80 16 12 ­40 dB dB NOTES 1 Standard operating mode: LNA/Mixer @ high bias setting, VGA @ Min ATTEN setting, synthesizers in normal (not fast acquire) mode, f CLK = 18 MHz, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins. 2 This includes 0.9 dB loss of matching network. 3 AGC with DVGA enabled. 4 Measured in 10 kHz bandwidth. 5 Programmable in 0.67 mA steps. 6 Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2). 7 VDDH must be less than VDDD + 0.5 V. 8 Clock VCO off, add additional 0.7 mA with VGA @ Max ATTEN setting. Specifications subject to change without notice. ­2­ REV. 0 AD9874 AD9874 DIGITAL SPECIFICATIONS (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS, fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted.)1 Parameter Temp Test Level Min DECIMATOR Decimation Factor2 Pass-Band Width Pass-Band Gain Variation Alias Attenuation Full Full Full Full IV V IV IV 48 SPI-READ OPERATION (See Figure 1a) PC Clock Frequency PC Clock Period (tCLK) PC Clock HI (tHI) PC Clock LOW (tLOW) PC to PD Setup Time (tDS) PC to PD Hold Time (tDH) PE to PC Setup Time (tS) PC to PE Hold Time (tH) Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV SPI-WRITE OPERATION3 (See Figure 1b) PC Clock Frequency PC Clock Period (tCLK) PC Clock HI (tHI) PC Clock LOW (tLOW) PC to PD Setup Time (tDS) PC to PD Hold Time (tDH) PC to PD (or DOUBT) Data Valid Time (tDV) PE to PD Output Valid to Hi-Z (tEZ) Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV 100 45 45 2 2 3 SSI (see Figure 2b) CLKOUT Frequency CLKOUT Period (tCLK) CLKOUT Duty Cycle (tHI, tLOW) CLKOUT to FS Valid Time (tV) CLKOUT to DOUT Data Valid Time (tDV) Full Full Full Full Full IV IV IV IV IV 0.867 38.4 33 ­1 ­1 CMOS LOGIC INPUTS4 Logic "1" Voltage (VIH) Logic "0" Voltage (VIL) Logic "1" Current (VIH) Logic "0" Current (VIL) Input Capacitance Full Full Full Full Full IV IV IV IV IV VDDH­0.2 CMOS LOGIC OUTPUTS3,4,5 Logic "1" Voltage (VIH) Logic "0" Voltage (VIL) Full Full IV IV Typ Max Unit 960 50% 1.2 88 fCLKOUT dB dB 10 MHz ns ns ns ns ns ns ns 10 MHz ns ns ns ns ns ns ns 26 1153 67 1 1 MHz ns ns ns ns 100 45 45 2 2 5 5 8 3 50 0.5 10 10 3 VDDH­0.2 0.2 V V mA mA pF V V NOTES 1 Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f CLK = 18 MHz, decimation factor = 300, 10 pF load on SSI output pins: VDDx = 3.0 V. 2 Programmable in steps of 48 or 60. 3 CMOS output mode with C LOAD = 10 pF and Drive Strength = 7. 4 Absolute Max and Min input/output levels are VDDH +0.3 V and ­0.3 V. 5 IOL = 1 mA; specification is also dependent on Drive Strength setting. Specifications subject to change without notice. REV. 0 ­3­ AD9874 AD9874 ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to Min Max Unit VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDF, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI VDDP, VDDQ GNDF, GNDA, GNDC, GNDD, GNDH, GNDL, GNDI, GNDQ, GNDP, GNDS MXOP, MXON, LOP, LON, IFIN, CXIF, CXVL, CXVM PC, PD, PE, CLKOUT, DOUTA, DOUTB, FS, SYNCB IF2N, IF2P, GCP, GCN VREFP, VREFN, RREF IOUTC IOUTL CLKP, CLKN FREF Junction Temperature Storage Temperature Lead Temperature (10 sec) GNDF, GNDA, GNDC, GNDD, GNDH, GNDL, GNDI, GNDS VDDR, VDDA, VDDC, VDDD, VDDH, VDDL, VDDI GNDP, GNDQ GNDF, GNDA, GNDC, GNDD, GNDH, GNDL, GNDI, GNDQ, GNDP, GNDS GNDI ­0.3 +4.0 V ­4.0 +4.0 V ­0.3 ­0.3 +6.0 +0.3 V V ­0.3 VDDI + 0.3 V GNDH ­0.3 VDDH + 0.3 V GNDF GNDA GNDQ GNDP GNDC GNDL ­0.3 ­0.3 ­0.3 ­0.3 ­0.3 ­0.3 VDDF + 0.3 VDDA + 0.3 VDDQ + 0.3 VDDP + 0.3 VDDC + 0.3 VDDL + 0.3 150 +150 300 V V V V V V °C °C °C ­65 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance EXPLANATION OF TEST LEVELS TEST LEVEL 48-Lead LQFP JA = 76.2°C/W JC = 17°C/W I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures. AC testing done on sample basis. III. Sample tested only. IV. Parameter is guaranteed by design and/or characterization testing. V. Parameter is a typical value only. VI. All devices are 100% production tested at 25°C; min. and max. guaranteed by design and characterization for industrial temperature range. ORDERING GUIDE Model Temperature Range AD9874BST AD9874BST ­40°C to +85°C AD9874EB AD9874EB Package Description Package Option 48-Lead Thin Plastic Quad Flatpack (LQFP) Evaluation Board ST-48 ST-48 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9874 AD9874 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ­4­ WARNING! ESD SENSITIVE DEVICE REV. 0 AD9874 AD9874 GNDP IOUTL VDDP VDDL CXVM LON LOP CXVL GNDI CXIF IFIN VDDI PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 MXOP 1 MXON 2 36 GNDL PIN 1 IDENTIFIER 35 FREF GNDF 3 34 GNDS IF2N 4 33 SYNCB IF2P 5 VDDF 6 GCP 7 32 GNDH AD9874 AD9874 TOP VIEW (Not to Scale) 31 FS 30 DOUTB GCN 8 29 DOUTA VDDA 9 28 CLKOUT GNDA 10 27 VDDH VREFP 11 26 VDDD VREFN 12 25 PE PC PD GNDC CLKP CLKN GNDS GNDD RREF VDDQ IOUTC GNDQ VDDC 13 14 15 16 17 18 19 20 21 22 23 24 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description Pin Mnemonic Description 1 2 3 4 5 6 7 8 9 10 11 12 13 MXOP MXON GNDF IF2N IF2P VDDF GCP GCN VDDA GNDA VREFP VREFN RREF 27 28 29 30 VDDH CLKOUT DOUTA DOUTB 31 32 33 FS GNDH SYNCB 34 35 GNDS FREF 14 15 VDDQ IOUTC 36 37 38 GNDL GNDP IOUTL 39 VDDP 16 GNDQ 17 18 19 VDDC GNDC CLKP 40 41 42 VDDL CXVM LON 43 LOP 20 CLKN 44 CXVL 21 22 23 24 25 26 GNDS GNDD PC PD PE VDDD Mixer Output, Positive Mixer Output, Negative Ground for Front End of ADC Second IF Input (to ADC), Negative Second IF Input (to ADC), Positive Positive Power Supply for Front End of ADC Filter Capacitor for ADC Full-Scale Control Full-Scale Control Ground Positive Power Supply for ADC Back End Ground for ADC Back End Voltage Reference, Positive Voltage Reference, Negative Reference Resistor: Requires 100 k to GNDA Positive Power Supply for Clock Synthesizer Clock Synthesizer Charge Pump Output Current Ground for Clock Synthesizer Charge Pump Positive Power Supply for Clock Synthesizer Ground for Clock Synthesizer Sampling Clock Input/Clock VCO Tank, Positive Sampling Clock Input/Clock VCO Tank, Negative Substrate Ground Ground for Digital Functions Clock Input for SPI Port Data I/O for SPI Port Enable Input for SPI Port Positive Power Supply for Internal Digital Functions 45 46 GNDI CXIF 47 48 IFIN VDDI Positive Power Supply for Digital Interface Clock Output for SSI Port Data Output for SSI Port Data Output for SSI Port (Inverted) or SPI Port Frame Sync for SSI Port Ground for Digital Interface Resets SSI and Decimator Counters; Active Low Substrate Ground Reference Frequency Input for Both Synthesizers Ground for LO Synthesizer Ground for LO Synthesizer Charge Pump LO Synthesizer Charge Pump Output Current Charge Pump Positive Power Supply for LO Synthesizer Charge Pump Positive Power Supply for LO Synthesizer External Filter Capacitor; DC Output of LNA LO Input to Mixer and LO Synthesizer, Negative LO Input to Mixer and LO Synthesizer, Positive External Bypass Capacitor for LNA Power Supply Ground for Mixer and LNA External Capacitor for Mixer V-I Converter Bias First IF Input (to LNA) Positive Power Supply for LNA and Mixer REV. 0 ­5­ AD9874 AD9874 DEFINITION OF SPECIFICATIONS/TEST METHODS Single-Sideband Noise Figure (SSB NF) Dynamic Range (DR) Dynamic range is the measure of a small target input signal (PTARGET) in the presence of a large unwanted interferer signal (PINTER). Typically, the large signal will cause some unwanted characteristic of the component or system to degrade, thus making it unable to detect the smaller target signal correctly. In the case of the AD9874 AD9874, it is often a degradation in Noise Figure at increased VGA attenuation settings that limits its dynamic range (refer to TPC 15a, 15b, and 15c). Noise figure (NF) is defined as the degradation in SNR performance (in dB) of an IF input signal after it passes through a component or system. It can be expressed with the following equation: Noise Figure = 10 × LOG(SNRIN SNROUT ) The term SSB is applicable for heterodyne systems containing a mixer. It indicates that the desired signal spectrum resides on only one side of the LO frequency (i.e. single sideband); thus a "noiseless" mixer has a noise figure of 3 dB. The test method for the AD9874 AD9874 is as follows. The small target signal (an unmodulated carrier) is input at the center of the IF frequency and its power level (PTARGET) is adjusted to achieve an SNRTARGET of 6 dB. The power of the signal is then increased by 3 dB prior to injecting the interferer signal. The offset frequency of the interferer signal is selected so that aliases produced by the decimation filter's response as well as phase noise from the LO (due to reciprocal mixing) do not fall back within the measurement bandwidth. For this reason, an offset of 110 kHz was selected. The interferer signal (also an unmodulated carrier) is then injected into the input and its power level is increased to the point (PINTER) where the target signal SNR is reduced to 6 dB. The dynamic range is determined from the following equation: The AD9874 AD9874's SSB noise figure is determined by the following equation: SSB NF = PIN ­ {10 × LOG ( BW )} ­ 174 dBm Hz ­ SNR where PIN is the input power of an unmodulated carrier, BW is the noise measurement bandwidth, ­174 dBm/Hz is the thermal noise floor at 293°K, and SNR is the measured signal-to-noise ratio in dB of the AD9874 AD9874. Note, PIN is set to ­85 dBm to minimize any degradation in measured SNR due to phase noise from the RF and LO signal generators. The IF frequency, CLK frequency, and decimation factors are selected to minimize any "spurious" components falling within the measurement bandwidth. Note, a bandwidth of 10 kHz is used for the data sheet specification on Page 2. Refer to Figures 22a and 22b for an indication of how NF varies with BW. Also, refer to the TPCs to see how NF is affected by different operating conditions. All references to noise figures within this data sheet imply single-sideband noise figure. DR = PINTER ­ PTARGET + SNRTARGET Note, the AD9874 AD9874's AGC is enabled for this test. IF Input Clip Point The IF input clip point is defined to be 2 dB below the input power level (PIN), resulting in the "clipping" of the AD9874 AD9874's ADC. Unlike other linear components that typically exhibit a "soft" compression (characterized by its 1 dB compression point), an ADC exhibits a "hard" compression once its input signal exceeds its rated maximum input signal range. In the case of the AD9874 AD9874, which contains a - ADC, "hard" compression should be avoided since it causes severe SNR degradation. Input Third Order Intercept (IIP3) IIP3 is a figure of merit to determine a component's or system's susceptibility to intermodulation distortion (IMD) from its third order nonlinearities. Two unmodulated carriers' at a specified frequency relationship (f1 and f2) are injected into a nonlinear system exhibiting third order nonlinearities producing IMD components at 2f1 ­ f2 and 2f2 ­ f1. IIP3 graphically represents the extrapolated intersection of the carrier's input power with the third order IMD component when plotted in dB. The difference in power (D in dBc) between the two carriers and the resulting third order IMD components can be determined from the following equation: D = 2 × ( IIP 3 ­ PIN ) ­6­ REV. 0 Typical Performance Characteristics­AD9874 AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz, TA = 25C, LO = ­5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1 9.5 100 9.5 9.0 9.0 +85C ­40C +25C 8.5 +85C +85C 8.5 40 NF ­ dB +25C 60 NF ­ dB PERCENTAGE ­ % 80 8.0 7.5 8.0 +25C 7.5 ­40C 7.0 7.0 6.5 6.5 20 ­40C 0 7.2 7.5 7.8 8.1 8.4 8.7 NOISE FIGURE ­ dB 6.0 2.7 9.0 3.0 3.3 6.0 2.7 3.6 3.0 3.3 VDDx ­ V TPC 1a. CDF of SSB Noise Figure (VDDx = 3.0 V, High Bias2) TPC 1b. SSB Noise Figure vs. Supply (High Bias2) TPC 1c. SSB Noise Figure vs. Supply (Low Bias3) 1.5 100 3.6 VDDx ­ V 0 1.0 +85C +25C 0 +85C 60 40 ­0.5 ­1.0 ­1.5 ­40C ­2.0 20 ­4 +25C IIP3 ­ dBm ­40C IIP3 ­ dBm PERCENTAGE ­ % ­2 0.5 80 +85C ­6 +25C ­8 ­40C ­2.5 ­10 ­3.0 0 ­3 ­2 ­1 0 IIP3 ­ dBm 1 ­3.5 2.7 2 3.0 3.3 ­12 2.7 3.6 TPC 2a. CDF of IIP3 (VDDx = 3.0 V, High Bias2) 98 97 97 ­40C +25C 96 DR ­ dB 96 DR ­ dB PERCENTAGE ­ % 80 40 95 +85C +25C 94 94 +85C 93 93 +85C +25C 0 93 94 95 96 DYNAMIC RANGE ­ dB 97 TPC 3a. CDF of Dynamic Range (VDDx = 3.0 V, High Bias2) 98 92 2.7 3.0 3.3 3.6 VDDx ­ V TPC 3b. Dynamic Range vs. Supply (High Bias2) Data taken with Toko FSLM series 10 µH inductors High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01 3 Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01 1 2 REV. 0 ­40C 95 20 92 3.6 TPC 2c. IIIP3 vs. Supply (Low Bias3) 98 ­40C 3.3 VDDx ­ V TPC 2b. IIP3 vs. Supply (High Bias2) 100 60 3.0 VDDx ­ V ­7­ 92 2.7 3.0 3.3 3.6 VDDx ­ V TPC 3c. Dynamic Range vs. Supply (Low Bias3) AD9874 AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz, TA = 25C, LO = ­5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1 ­17.5 ­17.5 ­18.0 ­18.0 PERCENTAGE ­ % 80 ­40C +25C +85C 60 40 20 ­18.5 INPUT CLIP POINT ­ dBm INPUT CLIP POINT ­ dBm 100 +85C ­19.0 +25C ­19.5 ­40C ­20.5 2.7 ­19.4 ­19.2 ­19.0 ­18.8 ­18.6 ­18.4 IFIN CLIP POINT ­ dBm TPC 4a. CDF of Maximum VGA Attenuation "Clip Point" (VDDx = 3.0 V, High Bias2) ­19.0 ­19.5 ­40C 3.0 3.3 ­20.5 2.7 3.6 TPC 4b. Maximum VGA Attenuation "Clip Point" vs. Supply (High Bias2) +85C 40 20 3.6 ­29.5 ­30.0 ­30.0 ­30.5 +85C ­31.0 +25C ­31.5 ­40C ­30.5 +85C ­31.0 +25C ­31.5 ­40C 0 ­31.6 ­31.4 ­31.2 ­31.0 ­30.8 ­30.6 ­30.4 ­32.0 2.7 3.0 TPC 5a. CDF of Minimum VGA Attenuation "Clip Point" (VDDx = 3.0 V, High Bias2) 3.3 3.6 ­32.0 2.7 TPC 5c. Minimium VGA Attenuation "Clip Point" vs. Supply (Low Bias3) ANALOG (IDDA, IDDF, AND IDDI) 40 20 12 10 8 6 DIGITAL (IDDD, IDDC, AND IDDL) 4 DIGITAL INTERFACE (IDDH) 2 0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 SUPPLY CURRENT ­ mA TPC 6a. CDF of Supply Current (VDDx = 3.0 V, High Bias2) SUPPLY CURRENT ­ mA 60 SUPPLY CURRENT ­ mA +85C 0 13 15 17 19 21 fCLK ­ MHz ANALOG (IDDA, IDDF, AND IDDI) 16 14 +25C 3.6 18 16 ­40C 3.3 VDDx ­ V TPC 5b. Minimium VGA Attenuation "Clip Point" vs. Supply (High Bias2) 100 80 3.0 VDDx ­ V IFIN CLIP POINT ­ dBm PERCENTAGE ­ % 3.3 TPC 4c. Maximum VGA Attenuation "Clip Point" vs. Supply (Low Bias3) INPUT CLIP POINT ­ dBm +25C INPUT CLIP POINT ­ dBm ­40C 60 3.0 VDDx ­ V ­29.5 80 +25C VDDx ­ V 100 PERCENTAGE ­ % +85C ­20.0 ­20.0 0 ­18.5 23 14 12 10 8 DIGITAL (IDDD, IDDC, AND IDDL) 6 4 DIGITAL INTERFACE (IDDH) 2 25 TPC 6b. Supply Current vs. fCLK (VDDx = 3.0 V, High Bias2) 0 2.7 3.0 3.3 3.6 VDDx ­ V TPC 6c. Supply Current vs. Supply (High Bias2) Data taken with Toko FSLM series 10 µH inductors High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01 3 Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01 1 2 ­8­ REV. 0 AD9874 AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz, TA = 25C, LO = ­5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1 0.1 0 8.8 ­12 ­10 9.0 0 ­15 NOISE FIGURE ­ dBc ­0.2 HIGH BIAS ­0.3 ­0.4 ­0.5 ­20 NF-HIGH BIAS 8.4 ­30 8.2 NF-LOW BIAS 8.0 ­40 7.8 ­50 IMD-LOW BIAS 7.6 ­60 ­0.6 7.4 ­0.7 7.2 ­0.8 ­20 ­17 ­14 ­11 LO DRIVE ­ dBm ­8 IMD-HIGH BIAS 7.0 ­20 ­5 TPC 7a. Normalized Gain Variation vs. LO Drive (VDDx = 3.0 V) ­15 0 ­20 NBW = 3.66kHz fCLK = 18MHz MAX VGA ATTEN DEC­BY­120 ­27 ­30 ­80 5 0 ­33 ­36 ­36 ­33 ­30 ­27 ­24 ­21 ­18 ­15 ­12 ­9 ­6 ­3 ­60 0 FS ­80 3.6V 3.3V ­4 3.0V 2.7V ­8 ADC DOES NOT GO INTO "HARD COMPRESSION" ­2 3.6V ­6 dBFS ­40 TPC 7c. Gain Compression vs. IFIN with 16 dB LNA Attenuator Enabled 3.3V ­4 0 IFIN ­ dBm ADC GOES INTO "HARD COMPRESSION" ­2 ­24 ­70 ­5 ­10 LO DRIVE ­ dBm LOW BIAS ­21 TPC 7b. Noise Figure and IMD vs. LO Drive (VDDx = 3.0 V) 0 ­2.8 dBFS OUTPUT ­18 dBFS GAIN VARIATION ­ dB LOW BIAS dBm 8.6 ­0.1 IMD w/ IFIN = ­36 dBm ­ dBc HIGH BIAS ­6 3.0V 2.7V ­8 ­100 ­10 ­10 ­120 ­12 ­12 ­60 ­40 ­20 0 20 40 FREQUENCY ­ kHz 60 TPC 8a. Complex FFT of Baseband I/Q for Single-Tone (High Bias) 0 ­20 ­18.2dBFS OUTPUT ­14 ­30 80 ­28 ­26 ­24 ­22 IFIN ­ dBm ­20 ­18 TPC 8b. Gain Compression vs. IFIN (High Bias2) TPC 8c. Gain Compression vs. IFIN (Low Bias3) ­70 ­15 ­55 ­76 NBW = 3.66kHz fCLK = 18MHz MAX VGA ATTEN DEC­BY­120 ­18 ­61 ­21 ­67 ­73 PIN ­82 ­27 IMD = 74dBc 3.0V ­100 3.3V ­106 ­18 PIN ­33 ­24 ­27 3.0V ­85 3.3V ­91 ­97 ­39 ­103 ­42 3.6V ­118 ­21 2.7V ­79 ­36 ­112 ­100 ­30 IMD ­ dBc ­60 ­94 PIN ­ dBFS ­24 IMD ­ dBc ­88 ­80 ­15 2.7V ­40 dBFS ­14 ­30 ­28 ­26 ­24 ­22 ­20 ­18 ­16 ­14 IFIN ­ dBm ­16 ­109 ­30 ­33 ­36 3.6V ­39 ­120 ­124 ­140 ­80 ­60 ­40 ­20 0 20 40 FREQUENCY ­ kHz 60 80 TPC 9a. Complex FFT of Baseband I/Q for Dual Tone IMD (High Bias with each IFIN Tone @ ­35 dBm) ­130 ­51 ­48 ­45 ­42 ­39 IFIN ­ dBm ­33 TPC 9b. IMD vs. IFIN (High Bias2) Data taken with Toko FSLM series 10 µH inductors High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01 3 Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01 1 2 REV. 0 ­36 ­9­ ­45 ­30 ­115 ­51 ­42 ­48 ­45 ­42 ­39 IFIN ­ dBm ­36 ­33 TPC 9c. IMD vs. IFIN (Low Bias3) ­45 ­30 PIN ­ dBFS ­140 ­80 AD9874 AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz, TA = 25C, LO = ­5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1 10.0 10.0 9.5 9.0 8.5 9.5 16-BIT 16-BIT DATA 16-BIT 16-BIT DATA w/ DVGA ENABLED 9.0 8.5 8.0 8.0 7.5 10 24-BIT 24-BIT DATA 9.0 16-BIT 16-BIT DATA 8.5 8.0 24-BIT 24-BIT I/Q DATA 24-BIT 24-BIT DATA 100 CHANNEL BANDWIDTH ­ kHz 7.5 10 1000 TPC 10a. Noise Figure vs. BW (Minimum Attenuation, fCLK = 13 MSPS) 100 CHANNEL BANDWIDTH ­ kHz 7.5 10 1000 TPC 10b. Noise Figure vs. BW (Minimum Attenuation, fCLK = 18 MSPS) 11.5 BW = 12.04kHz (K = 0, M = 8) 9.5 9.0 BW = 6.78kHz (K = 0, M = 15) 8.5 13 BW = 75kHz (K = 0, M = 1) 12 NOISE FIGURE ­ dB 10.0 NOISE FIGURE ­ dB BW = 27.08kHz (K = 0, M = 3) 1000 14 13 10.5 100 CHANNEL BANDWIDTH ­ kHz TPC 10c. Noise Figure vs. BW (Minimum Attenuation, fCLK = 26 MSPS) 14 11.0 NOISE FIGURE ­ dB NOISE FIGURE ­ dB 16-BIT 16-BIT I/Q DATA w/ DVGA ENABLED NOISE FIGURE ­ dB NOISE FIGURE ­ dB 16-BIT 16-BIT DATA w/ DVGA ENABLED 16-BIT 16-BIT I/Q DATA 9.5 10.0 BW = 50kHz (K = 0, M = 2) 11 10 BW = 15kHz (K = 0, M = 9) 9 12 BW = 135.42kHz (K = 1, M = 1) BW = 90.28kHz (K = 1, M = 2) 11 10 BW = 27.08kHz (K = 1, M = 9) 9 8.0 8 7.5 7 0 7.0 12 TPC 11a. Noise Figure vs. VGA Attenuation (fCLK = 13 MSPS) TPC 11b. Noise Figure vs. VGA Attenuation (fCLK = 18 MSPS) 6 3 9 VGA ATTENUATION ­ dB 12 TPC 11c. Noise Figure vs. VGA Attenuation (fCLK = 26 MSPS) ­30 ­5 ­30 ­5 ­10 ­40 ­40 ­10 ­40 ­10 ­50 ­50 ­15 PIN ­50 ­15 PIN ­60 ­25 ­90 ­30 HIGH BIAS ­100 ­20 ­70 LOW BIAS ­80 ­25 HIGH BIAS ­90 ­30 ­100 ­35 ­110 ­40 ­120 ­42 ­39 ­36 ­33 ­30 ­27 ­24 ­45 LOW BIAS ­80 ­25 HIGH BIAS ­90 ­30 ­35 ­35 ­110 ­40 ­120 ­42 ­39 IFIN ­ dBm TPC 12a. IMD vs. IFIN (fCLK = 13 MSPS) ­20 ­70 ­100 ­110 ­130 ­45 IMD ­ dBc ­80 ­60 PIN ­ dBFS LOW BIAS IMD ­ dBc ­20 ­70 ­15 PIN ­60 POUT ­ dBFS IMD ­ dBc 7 0 12 ­5 ­30 ­130 ­45 6 3 9 VGA ATTENUATION ­ dB PIN ­ dBFS 6 3 9 VGA ATTENUATION ­ dB 0 8 ­36 ­33 ­30 ­27 ­24 ­45 IFIN ­ dBm TPC 12b. IMD vs. IFIN (fCLK = 18 MSPS) ­40 ­120 ­130 ­45 ­42 ­39 ­36 ­33 ­30 ­27 ­24 ­45 IFIN ­ dBm TPC 12c. IMD vs. IFIN (fCLK = 26 MSPS) Data taken with Toko FSLM series 10 µH inductors High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01 3 Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01 1 2 ­10­ REV. 0 AD9874 AD9874 (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz, TA = 25C, LO = ­5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1 13 4 13 16-BIT 16-BIT w/DVGA 16-BIT 16-BIT w/DVGA 12 12 2 11 0 10 24-BIT 24-BIT 9 10 9 24-BIT 24-BIT ­2 ­4 7 ­6 ­8 6 50 100 150 200 250 300 350 400 450 500 FREQUENCY ­ MHz 0 8 7 8 6 IIP3 ­ dBm NOISE FIGURE ­ dB NOISE FIGURE ­ dB HIGH BIAS 11 TPC 13a. Noise Figure vs. Frequency (Minimum Attenuation, fCLK = 18 MSPS, BW = 10 kHz, High Bias) 0 ­10 50 100 150 200 250 300 350 400 450 500 FREQUENCY ­ MHz 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY ­ MHz TPC 13b. Noise Figure vs. Frequency (Minimum Attenuation, fCLK = 18 MSPS, BW = 10 kHz, Low Bias) 13 LOW BIAS TPC 13c. Input IP3 vs. Frequency (fCLK = 18 MSPS) 2 13 16-BIT 16-BIT w/DVGA 16-BIT 16-BIT w/DVGA 10 9 8 0 11 ­2 IIP3 ­ dBm 11 10 9 ­4 ­6 8 LOW BIAS 24-BIT 24-BIT 24-BIT 24-BIT 7 6 HIGH BIAS 12 NOISE FIGURE ­ dB NOISE FIGURE ­ dB 12 ­8 7 0 6 50 100 150 200 250 300 350 400 450 500 FREQUENCY ­ MHz TPC 14a. Noise Figure vs. Frequency (Minimum Attenuation, fCLK = 26 MSPS, BW = 24 kHz, High Bias) 20.0 0 ­10 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY ­ MHz FREQUENCY ­ MHz TPC 14b. Noise Figure vs. Frequency (Minimum Attenuation, fCLK = 26 MSPS, BW = 24 kHz, Low Bias) 128 50 100 150 200 250 300 350 400 450 500 TPC 14c. Input IP3 vs. Frequency (fCLK = 26 MSPS) 256 16 15 224 15 14 192 13 160 12 128 16 AGC 128 AGC ATTN 18.5 112 17.0 96 15.5 80 14.0 64 16 8.0 0 ­55 ­50 ­45 ­40 ­35 ­30 ­25 ­20 ­15 ­10 ­5 INTERFERER LEVEL ­ dBm TPC 15a. Noise Figure vs. Interferer Level (16-Bit Data, BW = 12.5 kHz, AGCR = 1, finterferer = fIF + 110 kHz) 10 64 9 32 8 0 ­50 ­45 ­40 ­35 ­30 ­25 ­20 ­15 ­10 INTERFERER LEVEL ­ dBm TPC 15b. Noise Figure vs. Interferer Level (16-Bit Data with DVGA, BW = 12.5 kHz, AGCR = 1, finterferer = fIF + 110 kHz) Data taken with Toko FSLM series 10 µH inductors High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01 3 Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01 1 2 REV. 0 ­11­ 96 13 12 64 NOISE FIGURE 11 10 32 9 8 ­65 ­55 ­45 ­35 ­25 ­15 0 ­5 INTERFERER LEVEL ­ dBm TPC 15c. Noise Figure vs. Interferer Level (24-Bit Data, BW = 12.5 kHz, AGCR = 1, finterferer = fIF + 110 kHz) MEAN AGC ATTN VALUE 32 9.5 96 NOISE FIGURE NOISE FIGURE ­ dBc 11.0 11 MEAN AGC ATTN VALUE 48 NOISE FIGURE NOISE FIGURE ­ dBc 12.5 MEAN AGC ATTN VALUE NOISE FIGURE ­ dBc AGC ATTN 14 AD9874 AD9874 SERIAL PERIPHERAL INTERFACE (SPI) The serial peripheral interface (SPI) is a bidirectional serial port. It is used to load configuration information into the registers listed below as well as to read back their contents. Table I provides a list of the registers that may be programmed through the SPI port. Addresses and default values are given in hexadecimal form. Table I. SPI Address Map Address Bit (Hex) Breakdown Width Default Value Name Description POWER CONTROL REGISTERS 0x00 (7:0) 8 0xFF STBY Standby Control Bits (REF, LO, CKO, CK, GC, LNAMX, Unused, and ADC) 0x01 (7:6) (5:4) (3:2) (1:0) 2 2 2 2 0 0 0 0 LNAB MIXB CKOB ADCB LNA Bias Current (0 = 0.5 mA, 1 = 1 mA, 2 = 2 mA, 3 = 3 mA) Mixer Bias Current (0 = 0.5 mA, 1 = 1.5 mA, 2 = 2.7 mA, 3 = 4 mA) CK Oscillator Bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.40 mA, 3 = 0.65 mA) Do Not Use 0x02 (7:0) 8 0x00 TEST Factory Test Mode. Do not use. 0x03 (7) (6:0) 1 7 0 0x00 ATTEN Apply 16 dB Attenuation in the Front End AGCG(14:8) AGC Attenuation Setting (7 MSBs of a 15-Bit Unsigned Word) 0x04 (7:0) 8 0x00 AGCG(7:0) AGC Attenuation Setting (8 LSBs of a 15-Bit Unsigned Word) Default corresponds to maximum gain 0x05 (7:4) (3:0) 4 4 0 0 AGCA AGCD AGC Attack Bandwidth Setting. Default yields 50 Hz raw loop bandwidth. AGC Decay Time Setting. Default is decay time = attack time. 0x06 (7) (6:4) (3) (2:0) 1 3 1 3 0 0 0 0 AGCV AGCO AGCF AGCR Enable Digital VGA to increase AGC Range by 12 dB AGC Overload Update Setting. Default is slowest update Fast AGC (Minimizes resistance seen between GCP and GCN) AGC Enable/Reference Level (Disabled, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB below Clip) 3 1 4 0 4 Unused K M Decimation Factor = 60 × (M + 1), if K = 0; 48 × (M + 1), if K = 1 Default is Decimate-by-300 AGC DECIMATION FACTOR 0x07 (7:5) (4) (3:0) LO SYNTHESIZER 0x08 (5:0) 6 0x00 LOR(13:8) Reference Frequency Divisor (6 MSBs of a 14-Bit Word) 0x09 (7:0) 8 0x38 LOR(7:0) Reference Frequency Divisor (8 LSBs of a 14-Bit Word) Default (56) Yields 300 kHz from fREF = 16.8 MHz 0x0A (7:5) (4:0) 3 5 0x5 0x00 LOA LOB(12:8) "A" Counter (Prescaler Control Counter) "B" Counter MSBs (5 MSBs of a 13-Bit Word) Default LOA and LOB values yield 300 kHz from 73.35 MHz­2.25 MHz 0x0B (7:0) 8 0x1D LOB(7:0) "B" Counter LSBs (8 LSBs of a 13-Bit Word) 0x0C (6) (5) (4:2) (1:0) 1 1 3 2 0 0 0 3 LOF LOINV LOI LOTM Enable Fast Acquire Invert Charge Pump (0 = Source Current to Increase VCO Frequency) Charge Pump Current in Normal Operation. IPUMP = (LOI + 1) × 0.625 mA Manual Control of LO Charge Pump (0 = Off, 1 = Up, 2 = Down, 3 = Normal) 0x0D (5:0) 4 0x0 LOFA(13:8) LO Fast Acquire Time Unit (6 MSBs of a 14-Bit Word) 0x0E (7:0) 8 0x04 LOFA(7:0) LO Fast Acquire Time Unit (8 LSBs of a 14-Bit Word) ­12­ REV. 0 AD9874 AD9874 Table I. SPI Address Map (continued) Address (Hex) Bit Breakdown Width Default Value Name Description CLOCK SYNTHESIZER 0x10 (5:0) 6 00 CKR(13:8) Reference Frequency Divisor (6 MSBs of a 14-Bit Word) 0x11 (7:0) 8 0x38 CKR(7:0) Reference Frequency Divisor (8 LSBs of a 14-Bit Word) Default Yields 300 kHz from fREF =16.8 MHz; Min = 3, Max = 16383. 0x12 (4:0) 5 0x00 CKN(12:8) Synthesized Frequency Divisor (5 MSBs of a 13-Bit Word) 0x13 (7:0) 8 0x3C CKN(7:0) Synthesized Frequency Divisor (8 LSBs of a 13-Bit Word) Default Yields 300 kHz from fCLK = 18 MHz; Min = 3, Max = 8191 0x14 (6) (5) (4:2) (1:0) 1 1 3 2 0 0 0 3 CKF CKINV CKI CKTM Enable Fast Acquire Invert Charge Pump (0 = Source Current to Increase VCO Frequency) Charge Pump Current in Normal Operation. IPUMP = (CKI + 1) × 0.625 mA Manual Control of CLK Charge Pump (0 = Off, 1 = Up, 2 = Down, 3 = Normal) 0x15 (5:0) 6 0x0 CKFA(13:8) CK Fast Acquire Time Unit (6 MSBs of a 14-Bit Word) 0x16 (7:0) 8 0x04 CKFA(7:0) CK Fast Acquire Time Unit (8 LSBs of a 14-Bit Word) SSI CONTROL 0x18 (7:0) 8 0x12 SSICRA SSI Control Register A. See Table III. (Default is FS and CLKOUT Three-Stated) 0x19 (7:0) 8 0x07 SSICRB SSI Control Register B. See Table III. (16-bit data, maximum drive strength) 0x1A (3:0) 4 1 SSIORD Output Rate Divisor. fCLKOUT = fCLK/SSIORD ADC TUNING 0x1C (1) (0) 1 1 0 0 TUNE_LC TUNE_RC Perform Tuning on the LC Portion of the ADC (Cleared When Done) Perform Tuning on the RC Portion of the ADC (Cleared When Done) 0x1D (2:0) 3 0 CAPL1(2:0) Coarse Capacitance Setting for LC Tank (LSB is 25 pF, Differential) 0x1E (5:0) 6 0x00 CAPL0(5:0) Fine Capacitance Setting for LC Tank (LSB is 0.4 pF, Differential) 0x1F (7:0) 8 0x00 CAPR Capacitance Setting for RC Resonator (64 LSBs of Fixed Capacitance) TEST REGISTERS AND SPI PORT READ ENABLE 0x37­0x39 (7:0) 8 0x00 TEST Factory Test Mode. Do not use. 0x3A (7:4, 2:0) (3) 7 1 0x0 0 TEST SPIREN Factory Test Mode. Do not use. Enable Read from SPI Port 0x3B (7:4, 2:0) (3) 7 1 0x0 0 TEST TRI Factory Test Mode. Do not use. Three-state DOUTB 0x3C­0x3E (7:0) 1 0x00 TEST Factory Test Mode. Do not use. 0x3F (7:0) 8 Subject to Change ID Revision ID (Read-Only); A write of 0x99 to this register is equivalent to a power-on reset. REV. 0 ­13­ AD9874 AD9874 read, the eight data bits pertaining to the specified register are shifted into the data pin (PD) on the rising edge of the next eight clock cycles. PE stays low during the operation and goes high at the end of the transfer. If PE rises before the eight clock cycles have passed, the operation is aborted. SERIAL PORT INTERFACE (SPI) The serial port of the AD9874 AD9874 has 3-wire or 4-wire SPI capability, allowing read/write access to all registers that configure the device's internal parameters. The default 3-wire serial communication port consists of a clock (PC), peripheral enable (PE), and a bidirectional data (PD) signal. The inputs to PC, PE, and PD contain a Schmitt trigger with a nominal hysteresis of 0.4 V centered about the digital interface supply (i.e., VDDH/2). If PE stays low for an additional eight clock cycles, the destination address is incremented and another eight bits of data are shifted in. Again, should PE rise early, the current byte is ignored. By using this implicit addressing mode, the entire chip can be configured with a single write operation. Registers identified as being subject to frequent updates, namely those associated with power control and AGC operation, have been assigned adjacent addresses to minimize the time required to update them. Note, multibyte registers are "big-endian" (the most significant byte has the lower address) and are updated when a write to the least significant byte occurs. A 4-wire SPI interface can be enabled by setting the MSB of the SSICRB register ( Reg. 0x19, Bit 7) resulting in the output data also appearing on the DOUTB Pin. Note, since the default power-up state sets DOUTB low, bus contention is possible for systems sharing the SPI output line. To avoid any bus contention, the DOUTB Pin can be three-stated by setting the fourth control bit in the three-state bit (Reg 0x3B, Bit 3). This bit can then be toggled to gain access to the shared SPI output line. Figure 1b illustrates the timing for a read operation to the SPI port. Although the AD9874 AD9874 does not require read access for proper operation, it is often useful in the product development phase or for system authentication. Note, the readback enable bit (Register 0x3A, Bit 3) must be set for a read operation with a 3-wire SPI interface. After the peripheral enable (PE) signal goes low, data (PD) pertaining to the instruction header is read on the rising edges of the clock (PC). A read operation occurs if the read/notwrite indicator is set high. After the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the data pin (PD) on the falling edges of the next eight clock cycles. If the 4-wire SPI interface is enabled, the eight data bits will also appear on the DOUTB Pin with the same timing relationship as those appearing at PD. After the last data bit is shifted out, the user should return PE high, causing PD to become three-stated and return to its normal status as an input pin. Since the auto-increment mode is not supported for read operations, an instruction header is required for each register read operation and PE must return high before initiating the next read operation. An 8-bit instruction header must accompany each read and write SPI operation. Only the write operation supports an auto-increment mode allowing the entire chip to be configured in a single write operation. The instruction header is shown in Table I. It includes a read/not-write indicator bit, 6 address bits, and a Don't Care bit. The data bits immediately follow the instruction header for both read and write operations. Note, address and data are always given MSB first. Table II. Instruction Header Information MSB I7 I6 R/W A5 I5 A4 I4 A3 I3 A2 I2 A1 I1 A0 LSB I0 X Figure 1a illustrates the timing requirements for a write operation to the SPI port. After the peripheral enable (PE) signal goes low, data (PD) pertaining to the instruction header is read on the rising edges of the clock (PC). To initiate a write operation, the read/not-write bit is set low. After the instruction header is tS tCLK tH PE tHI tLOW PC tDS tDH PD A5 R/W A4 A0 DON'T CARE D7 D6 D1 D0 Figure 1a. SPI Write Operation Timing tS tCLK tH PE tHI tLOW PC tDS tDH PD R/W A5 A4 A0 DON'T CARE D7 D6 D1 D0 Figure 1b. SPI Read Operation Timing ­14­ REV. 0 AD9874 AD9874 The AD9874 AD9874 provides a high degree of programmability of its SSI output data format, control signals, and timing parameters to accommodate various digital interfaces. In a 3-wire digital interface, the AD9874 AD9874 provides a frame sync signal (FS), a clock output (CLKOUT), and a serial data stream (DOUTA) signal to the host device. In a 2-wire interface, the frame sync information is embedded into the data stream, thus only a CLKOUT and DOUTA output signal are provided to the host device. The SSI control registers are SSICRA, SSICRB, and SSIORD. Table III shows the different bit fields associated with these registers. The primary output of the AD9874 AD9874 is the converted I and Q demodulated signal available from the SSI port as a serial bit stream contained within a frame. The output frame rate is equal to the modulator clock frequency (fCLK) divided by the digital filter's decimation factor that is programmed in the Decimator Register (0x07). The bit stream consists of an I word followed by a Q word, where each word is either 24 bits or 16 bits long and is given MSB first in two's complement form. Two optional bytes may also be included within the SSI frame following the Q word. One byte contains the AGC attenuation and the other byte contains both a count of modulator reset events and an estimate of the received signal amplitude (relative to full scale of the AD9874 AD9874's ADC). Figure 2 illustrates the structure of the SSI data frames in a number of SSI modes. The two optional bytes follow the I and Q data as a 16-bit word providing that the AAGC bit of SSICRA is not set. If the AAGC bit is set, the two bytes follow the I and Q data in an alternating fashion. In this alternate AGC data mode, the LSB of the byte containing the AGC attenuation is a 0, while the LSB of the byte containing reset and RSSI information is always a 1. In a 2-wire interface, the embedded frame sync bit (EFS) within the SSICRA Register is set to 1. In this mode, the framing information is embedded in the data stream with each eight bits of data surrounded by a start bit (low) and a stop bit (high), and each frame ends with at least 10 high bits. FS remains either low or three-stated (default) depending on the state of the SFST bit. Other control bits can be used to invert the frame sync (SFSI), to delay the frame sync pulse by one clock period (SLFS), to invert the clock (SCKI), or to three-state the clock (SCKT). Note that if EFS is set, SLFS is a don't care. Table III. SSI Control Registers Name Width Default SSICRA (ADDR = 0x18) AAGC EAGC EFS SFST SFSI SLFS SCKT SCKI 24-Bit I AND Q, EAGC = 0, AAGC = X: 48 DATA BITS I (24:0) Description Q (24:0) 1 1 1 1 1 1 1 1 0 0 0 1 0 0 1 0 AAGC EAGC EFS SFST SFSI SLFS SCKT SCKI SYNCHRONOUS SERIAL INTERFACE (SSI) Alternate AGC Data Bytes Embed AGC Data Embed Frame Sync Three-State Frame Sync Invert Frame Sync Late Frame Sync (1 = Late, 0 = Early) Three-State CLKOUT Invert CLKOUT SSI(5:0) SSICRB (ADDR = 0x19) RESET COUNT 16-Bit I AND Q, EAGC = 0, AAGC = X:32 DATA BITS 4_SPI 1 0 DW I (15:0) 1 0 DS 3 7 Q (15:0) 16-Bit I AND Q, EAGC = 1, AAGC = 0:48 DATA BITS I (15:0) Q (15:0) ATTN (7:0) SSI(5:0) Enable 4-Wire SPI Interface for SPI Read operation via DOUTB I/Q data-word width (0 = 16 bit, 1 bit­24 bit) Automatically 16-bit when the AGCV=1 FS, CLKOUT, and DOUT Drive Strength 16-Bit I AND Q, EAGC = 1, AAGC = 1:40 DATA BITS I (15:0) Q (15:0) ATTN (7:1) 0 I (15:0) Q (15:0) SSI(5:1) 1 SSIORD (ADDR = 0x1A) DIV RESET COUNT Figure 2. SSI Frame Structure The two optional bytes are output if the EAGC bit of SSICRA is set. The first byte contains the 8-bit attenuation setting (0 = no attenuation, 255 = 24 dB of attenuation), while the second byte contains a 2-bit reset field and 6-bit received signal strength signal field. The reset field contains the number of modulator reset events since the last report, saturating at 3. The received signal strength (RSSI) field is a linear estimate of the signal strength at the output of the first decimation stage; 60 corresponds to a full-scale signal. REV. 0 4 1 DW DS_2 DS_1 DS_0 ATTN (7:0) Q (24:0) DIV_3 DIV_2 DIV_1 DIV_0 I (24:0) 4_SPI 24-Bit I AND Q, EAGC = 1, AAGC = 0:64 DATA BITS Output Bit Rate Divisor fCLKOUT = fCLK/SSIORD The SSIORD Register controls the output bit rate (fCLKOUT) of the serial bit stream. fCLKOUT can be set to equal the modulator clock frequency (fCLK) or an integer fraction of it. It is equal to fCLK divided by the contents of the SSIORD Register. Note, fCLKOUT should be chosen such that it does not introduce harmful spurs within the pass band of the target signal. Users must verify that the output bit rate is sufficient to accommodate the required number of bits per frame for a selected word size and decimation factor. Idle (high) bits are used to fill out each frame. ­15­ AD9874 AD9874 An example helps illustrate how the maximum SSIORD setting is determined. Suppose a user selects a decimation factor of 600 (Register 0x07, K = 0, M = 9) and prefers a 3-wire interface with a dedicated frame sync (EFS = 0) containing 24-bit data (DW = 1) with nonalternating embedded AGC data included (EAGC = 1, AAGC = 0). Referring to Table IV, each frame will consist of 64 data bits. Using Equation 1, the maximum SSIORD setting is 9 (= TRUNC(600/64). Thus, the user can select any SSIORD setting between 1 and 9. Table IV. Number of Bits per Frame for Different SSICR Settings DW EAGC EFS AAGC Number of Bits per Frame 0 (16-bit) 0 0 1 1 1 1 0 1 0 0 1 1 NA NA 0 1 0 1 32 49* 48 40 69* 59* 0 0 1 1 1 1 0 1 0 0 1 1 NA NA 0 1 0 1 48 69* 64 56 89* 79* 1 (24-bit) Figure 3a illustrates the output timing of the SSI port for several SSI control register settings with 16-bit I/Q data, while Figure 3b shows the associated timing parameters. Note, the same timing relationship holds for 24-bit I/Q data, with the exception that I and Q word lengths now become 24 bits. In the default mode of the operation, data is shifted out on rising edges of CLKOUT after a pulse equal to a clock period is output from the Frame Sync (FS) Pin. As described above, the output data consists of a 16- or 24-bit I sample followed by a 16- or 24-bit Q sample, plus two optional bytes containing AGC and status information. *The number of bits per frame with embedded frame sync (EFS = 1) assume at least 10 idle bits are desired. The maximum SSIORD setting can be determined by the following equation: tCLK tHI SSIORD TRUNC{(Dec. Factor ) / (# of Bits per Frame )}(1) CLKOUT where TRUNC is the truncated integer value. tLOW tV FS Table IV lists the number of bits within a frame for 16-bit and 24-bit output data formats for all of the different SSICR settings. The decimation factor is determined by the contents of Register 0x07. tDV I15 DOUT I14 Figure 3b. Timing Parameters for SSI Timing* *Timing parameters also apply to inverted CLKOUT or FS modes with t DV relative to the falling edge of the CLK and/or FS. CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS I15 DOUT Q15 I0 Q14 Q0 SCKI = 0, SCKT = 0, SLFS = 1, SFSI = 0, EFS = 0, SFST = 0, EAGC = 0 CLKOUT FS DOUT I15 I0 Q15 Q14 Q0 ATTN7 ATTEN6 RSSI0 SCKI = 0, SCKT = 0, SLFS = 0, SFSI = 0, EFS = 0, SFST = 0, EAGC = 1, AAGC = 0 CLKOUT HI-Z FS DOUT IDLE (HIGH) BITS START BIT I15 I8 STOP BIT START BIT I7 I0 STOP BIT START BIT Q15 SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 1, EAGC = 0 SCKI = 0, SCKT = 0, SLFS = X, SFSI = X, EFS = 1, SFST = 0, EAGC = 0: AS ABOVE, BUT FS IS LOW Figure 3a. SSI Timing for Several SSICRA Settings with 16-Bit I/Q Data ­16­ REV. 0 AD9874 AD9874 The AD9874 AD9874 also provides the means for controlling the switching characteristics of the digital output signals via the DS (drive strength) field of the SSICRB. This feature is useful in limiting switching transients and noise from the digital output that may ultimately couple back into the analog signal path, potentially degrading the AD9874 AD9874's sensitivity performance. Figures 3c and 3d show how the NF can vary as a function of the SSI setting for an IF frequency of 109.65 MHz. The following two observations can be made from these figures: Table V. Typical Rise/Fall times (± 25 %) with a 10 pF Capacitive Load for Each DS Setting DS · The NF is dependent on the number of bits within an SSI frame, becoming more sensitive to the SSI output drive strength level as the number of bits is increased. As a result, one should select the lowest possible SSI drive strength setting that still meets the SSI timing requirements. 10.0 9.8 NOISE FIGURE ­ dB 9.6 16-BIT 16-BIT I/O DATA 9.4 9.2 9.0 24-BIT 24-BIT I/O DATA 8.8 8.6 8.4 16-BIT 16-BIT I/O DATA w/DVGA ENABLED 8.2 8.0 1 2 3 4 5 6 SSI OUTPUT DRIVE STRENGTH SETTING 7 Figure 3c. NF vs. SSI Output Drive Strength (VDDx = 3.0 V, fCLK = 18 MSPS, BW = 10 kHz) 14 13.5 1 7.2 2 5.0 3 3.7 4 3.2 5 2.8 6 2.3 7 · The NF becomes more sensitive to the SSI output drive strength level at higher signal bandwidth settings. typ (ns) 0 2.0 Synchronization Applications, such as receiver diversity, employing more than one AD9874 AD9874 device may desire synchronization of the digital output data. SYNCB can be used for this purpose and applied upon system initialization. It is an active-low signal that clears the clock counters in both the decimation filter and the SSI port. The counters in the clock synthesizers are not reset, since it is presumed that the CLK signals of multiple chips would be connected together. SYNCB also clears the registers in the decimation filter and resets the modulator. As a result, valid data representative of the input signal will be available once the digital filters have been flushed. Figure 4a shows the timing relationship between SYNCB and the SSI port's CLKOUT and FS signals. SYNCB is an asynchronous active-low signal that must remain low for at least half an input clock period (i.e., 1/(2 × fCLK) ). CLKOUT returns high while FS remains low upon SYNCB going low. CLKOUT will become active within 1 to 2 output clock periods upon SYNCB returning high. FS will reappear several output clock cycles later, depending on the digital filter's decimation factor and the SSIORD setting. To verify proper synchronization, the FS signals of the multiple AD9874 AD9874 devices should be monitored. 13 NOISE FIGURE ­ dB 24-BIT 24-BIT I/O DATA SYNCB 12 CLKOUT 16-BIT 16-BIT I/O DATA w/DVGA ENABLED 11 10 FS Figure 4a. SYNCB Timing 16-BIT 16-BIT I/O DATA 9 INTERFACING TO DSPs 8 7 1 2 3 4 5 6 SSI OUTPUT DRIVE STRENGTH SETTING 7 Figure 3d. NF vs. SSI Output Drive Strength (VDDx = 3.0 V, fCLK = 18 MSPS, BW = 75 kHz) Table V lists the typical output rise/fall times as a function of DS for a 10 pF load. Rise/fall times for other capacitor loads can be determined by multiplying the typical values presented in Table V by a scaling factor equal to the desired capacitive load divided by 10 pF. The AD9874 AD9874 connects directly to an Analog Devices programmable digital signal processor (DSP). Figure 4b illustrates an example with the Blackfin® series of ADSP-2153x processors. The Blackfin DSP series is a family of 16-bit products optimized for telecommunications applications with its dynamic power management feature making it well suited for portable radio products. The code compatible family members share the fundamental core attributes of high performance, low power consumption, and the ease-of-use advantages of microcontroller instruction set. *Blackfin is a registered trademark of Analog Devices, Inc. REV. 0 ­17­ AD9874 AD9874 SPI SSI PC PE PD DOUTB CLKOUT FS DOUTA The AD9874 AD9874 also allows control over the bias current in the LNA, mixer, and clock oscillator. The effects on current consumption and system performance are described in the section dealing with the affected block. ADSP-2153X ADSP-2153X AD9874 AD9874 SCK SEL MOSI MISO RSCLK RFS DR SPI-PORT LO Synthesizer SERIAL PORT Figure 4b. Example of AD9874 AD9874 and ADSP-2153x Interface As shown in Figure 4b, AD9874 AD9874's synchronous serial interface (SSI) links the receive data stream to the DSP's Serial Port (SPORT). For AD9874 AD9874 set-up and register programming, the device connects directly to ADSP-2153x's SPI-PORT. Dedicated select lines (SEL) allow the ADSP-2153x to program and read back registers of multiple devices using only one SPI port. The DSP driver code pertaining to this interface is available on the AD9874 AD9874 web page ( ). POWER CONTROL To allow power consumption to be minimized, the AD9874 AD9874 possesses numerous SPI-programmable power-down and bias control bits. The AD9874 AD9874 powers up with all of its functional blocks placed into a standby state (i.e., STBY Register default is 0xFF). Each major block may then be powered up by writing a 0 to the appropriate bit of the STBY Register. This scheme provides the greatest flexibility for configuring the IC to a specific application as well as for tailoring the IC's power-down and wake-up characteristics. Table VI summarizes the function of each of the STBY bits. Note, when all the blocks are in standby, the master reference circuit is also put into standby and thus the current is reduced by a further 0.4 mA. The LO Synthesizer shown in Figure 5 is a fully programmable PLL capable of 6.25 kHz resolution at input frequencies up to 300 MHz and reference clocks of up to 25 MHz. It consists of a low noise digital phase-frequency detector (PFD), a variable output current charge pump (CP), a 14-bit reference divider, programmable A and B counters, and a dual-modulus 8/9 prescaler. The A (3-bit) and B (13-bit) counters, in conjunction with the dual 8/9 modulus prescaler, implement an N divider with N = 8 B + A. In addition, the 14-bit reference counter (R Counter) allows selectable input reference frequencies, fREF, at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). The A, B, and R counters can be programmed via the following registers: LOA, LOB, and LOR. The charge pump output current is programmable via the LOI Register from 0.625 mA to 5.0 mA using the following equation: IPUMP = ( LOI + 1) × 0.625 mA An on-chip fast acquire function (enabled by the LOF bit) automatically increases the output current for faster settling during channel changes. The synthesizer may also be disabled using the LO standby bit located in the STBY Register. fREF REF BUFFER FREF R Table VI. Standby Control Bits STBY Bit Effect LOR Current Reduction Wake-Up (mA)1 Time (ms) 7:REF Voltage Reference OFF; all biasing shut down. 0.6 LO Synthesizer OFF, IOUTL three-state. 1.2 Clock Oscillator OFF 1.1 Note 2 4:CK Clock Synthesizer OFF, IOUTC three-state. Clock buffer OFF if ADC is OFF. 1.3 Note 2 3:GC Gain Control DAC OFF. GCP and GCN three-state. 0.2 Depends on CGC 8.2 1/{2 (LOSC (C VARACTOR//COSC)1/2} CKO = 1 EXT CLK ­110 ­120 ­25 CLK OSC. BIAS 2 IBIAS = 0.15 mA, 0.25 mA, 0.40 mA, OR 0.65 mA ­20 ­15 ­10 ­5 0 5 10 15 20 25 FREQUENCY OFFSET ­ kHz Figure 7b. CLK Phase Noise vs. IBIAS Setting (CKO) (CLK SYN Settings: CKI = 7, CLR = 56, and CLN = 60 with fREF = 100kHz) Figure 7a. External Loop Filter, Varactor, and LC Tank Are Required to Realize a Complete Clock Synthesizer The AD9874 AD9874 clock synthesizer circuitry includes a negativeresistance core so that only an external LC tank circuit with a varactor is needed to realize a voltage controlled clock oscillator (VCO). Figure 7a shows the external components required to complete the clock synthesizer along with the equivalent input circuitry of the CLK input. The resonant frequency of the VCO is approximately determined by LOSC and the series equivalent capacitance of COSC and CVAR. As a result, LOSC, COSC, and CVAR should be selected to provide a sufficient tuning range to ensure proper locking of the clock synthesizer. ­20­ REV. 0 AD9874 AD9874 2.7V TO 3.6V 0 ­10 50 ­20 ­30 ­40 L L C dBFS ­50 ­60 VDDI CKI = 4 MXOP M X ON ­70 ­80 CKI = 0 ­90 CKI = 6 CKI = 2 EXT CLK ­100 ­110 ­120 ­25 RBIAS ­20 ­15 ­10 ­5 0 5 10 15 20 CXVL 25 FREQUENCY OFFSET ­ kHz LO INPUT = 0.3V p-p TO 1.0V p-p RGAIN Figure 7c. CLK Phase Noise vs. Charge Pump Setting Bias (CLK SYN Settings: CKO Bias = 3, CKR = 56, and CKN = 60 with fREF = 100kHz) MULTI-TANH V­I STAGE RF CXIF CXVM IFIN Table VIII. SPI Registers Associated with CLK Synthesizer DC SERVO LOOP Address (Hex) Bit Breakdown Width Default Value Name 0x00 (7:0) 8 0xFF STBY 0x01 (3:2) 2 0 CKOB 0x10 (5:0) 6 00 CKR(13:8) Figure 8. Simplified Schematic of AD9874 AD9874's LNA/Mixer 600 LNA BIAS = 0 550 8 0x38 0x12 (4:0) 5 0x00 CKN(12:8) 0x13 (7:0) 8 0x3C CKN(7:0) 0x14 (6) (5) (4:2) (1:0) 1 1 3 1 0 0 0 0 CKF CKINV CKI CKTM 0x15 (3:0) 4 0x0 CKFA(13:8) 0x16 (7:0) 8 0x04 CKFA(7:0) LNA BIAS = 1 CKR(7:0) LNA BIAS = 2 RESISTANCE ­ (7:0) 500 450 LNA BIAS = 3 400 350 300 IF LNA/MIXER The AD9874 AD9874 contains a single-ended LNA followed by a Gilberttype active mixer, shown in Figure 8 with the required external components. The LNA uses negative shunt feedback to set its input impedance at the IFIN Pin, thus making it dependent on the LNA bias setting and input frequency. It can be modeled as approximately 370 //1.4 pF (20%) for the higher bias settings below 100 MHz. Figures 9a and 9b show the equivalent input impedance versus frequency characteristics of the AD9874 AD9874 with all the LNA bias settings. The increase in shunt resistance versus frequency can be attributed to the reduction in bandwidth, thus the amount of negative feedback of the LNA. Note, the input signal into IFIN should be ac-coupled via a 10 nF capacitor since the LNA input is self-biasing. 0 50 100 200 150 250 FREQUENCY ­ MHz 300 350 Figure 9a. The Shunt Input Resistance vs. the Frequency of the AD9874 AD9874's IF1 Input 2.5 LNA BIAS = 3 2.0 LNA BIAS = 2 CAPACITANCE ­ pF 0x11 LNA BIAS = 1 1.5 1.0 LNA BIAS = 0 0.5 0 0 50 100 200 150 250 FREQUENCY ­ MHz 300 Figure 9b. The Shunt Capacitance vs. the Frequency of the AD9874 AD9874's IF1 Input REV. 0 ­21­ 350 AD9874 AD9874 The mixer's differential LO port is driven by the LO buffer stage shown in Figure 6 that can be driven single-ended or differential. Since it is self-biasing, the LO signal level can be ac-coupled and range from 0.3 V p-p to 1.0 V p-p with negligible effect on performance. The mixer's open-collector outputs, MXOP and MXON, drive an external resonant tank consisting of a differential LC network tuned to the IF of the band-pass - ADC (i.e., fIF2_ADC = fCLK/8). The two inductors provide a dc bias path for the mixer core via a series resistor of 50 , which is included to dampen the common-mode response. The mixer's output must be ac-coupled to the input of the band-pass - ADC, IF2P and IF2N, via two 100 pF capacitors to ensure proper tuning of the LC center frequency. INPUT REFERRED POWER ­ dBm PIN ­40 ­60 TOKO INDUCTOR PIMD = 2.64 PIN + 4.6 ­80 ­100 COILCRAFT PIMD = 2.92 PIN + 6.9 ­120 ­140 ­54 ­36 ­42 ­48 ­30 ­24 ­18 Figure 10. IMD Performance between Different Inductors with LNA and Mixer at Full Bias and fCLK of 18 MHz Both the LNA and mixer have four programmable bias settings so that current consumption can be minimized for a given application. Figures 11a, 11b, and 11c show how the LNA and mixer's noise figure (NF), linearity (IIP3), IF clip point, current consumption, and frequency response are all affected for a given LNA/mixer bias setting. The measurements were taken at an IF = 73.35 MHz and LO = 71.1 MHz with supplies set to 3 V. ­20 CLIP POINT ­18 11 ­16 10 ­14 NOISE FIGURE ­12 9 8 1_0 CLIP POINT ­ dBm 12 1_1 1_2 1_3 2_0 2_1 2_2 2_3 3_0 3_1 3_2 ­10 3_3 LNA_MIXER BIAS SETTING Figure 11a. LNA/Mixer Noise Figure and Conversion Gain vs. Bias Setting 9.50 5 0 8.25 LNA_MIXER CURRENT ­5 7.00 ­10 5.75 IDDI ­ mA The selection of the inductors is an important consideration in realizing the full linearity performance of the AD9874 AD9874. This is especially the case when operating the LNA and mixer at maximum bias and low clock frequency. Figure 10 shows how the two-tone input-referred IMD versus the input level performance at an IF of 109 MHz and fCLK of 18 MHz varies between Toko's FSLM series and Coilcraft's 1812CS 1812CS series inductors. The graph also shows the extrapolated point of intersection used to determine the IIP3 performance. Note, the Coilcraft inductor provides a 7 dB­8 dB improvement in performance and closely approximates the 3:1 slope associated with a third order linearity compared to the 2.65:1 slope associated with the Toko inductor. The Coilcraft 1008CS 1008CS series showed similar performance to the 1812CS 1812CS series. It is worth noting that the difference in IMD performance between these two inductor families with an fCLK of 26 MHz is insignificant. 13 NOISE FIGURE ­ dB For example, at fCLK = 18 MHz and L = 10 µH, a capacitance of 250 pF is needed. However, in order to accommodate an inductor tolerance of ± 10%, the tank capacitance must be adjustable from 227 pF to 278 pF. Selecting an external capacitor of 180 pF ensures that even with a 10% tolerance and stray capacitances as high as 30 pF, the total capacitance will be less than the minimum value needed by the tank. Extra capacitance is supplied by the AD9874 AD9874's on-chip programmable capacitor array. Since the programming range of the capacitor array is at least 160 pF, the AD9874 AD9874 has plenty of range to make up for the tolerances of low cost external components. Note, if fCLK is increased by a factor of 1.44 MHz to 26 MHz so that fCLK/8 becomes 3.25 MHz, reducing L and C by approximately the same factor (i.e., L = 6.9 µH and C = 120 pF), the above stated requirements are satisfied. FIN = 109.65MHz ­20 INPUT IIP3 ­ dBm The external differential LC tank forms the resonant element for the first resonator of the band-pass - modulator, and so must be tuned to the fCLK/8 center frequency of the modulator. The inductors should be chosen such that their impedance at fCLK/8 is about 140 (i.e., L = 180/fCLK). An accuracy of 20% is considered to be adequate. For example, at fCLK = 18 MHz, L = 10 µH is a good choice. Once the inductors have been selected, the required tank capacitance may be calculated using the relation fCLK/8 = 1/{2 (2L C)1/2}. 0 IIP3 ­15 4.50 ­20 3.25 ­25 1_0 1_1 1_2 1_3 2_0 2_1 2_2 2_3 3_0 3_1 3_2 2.00 3_3 LNA_MIXER BIAS SETTING Figure 11b. LNA/Mixer IIP3 and Current Consumption vs. Bias Setting ­22­ REV. 0 AD9874 AD9874 Based on these characterization curves, a LNA/mixer bias setting of 3_3 is suitable for most applications since it will provide the greatest dynamic range in the presence of multiple unfiltered interferers. However, portable radio applications demanding the lowest possible power may benefit by changing the LNA/mixer bias setting based on the received signal strength power (i.e., RSSI) available from the SSI output data. For instance, selecting an LNA_Mixer bias setting of 1_2 for nominal input strength conditions (i.e., ­18 dBm) from overdriving the - modulator. In such instances, the - modulator will become unstable, thus severely desensitizing the receiver. The 16 dB step attenuator can be invoked by setting the ATTEN bit (Register 0x03, Bit 7), causing the mixer gain to be reduced by 16 dB. The 16 dB step attenuator could be used in applications in which a potential target or blocker signal could exceed the IF input clip point. Although the LNA will be driven into compression, it may still be possible to recover the desired signal if it is FM. Refer to TPC 7c to see the gain compression characteristics of the LNA and mixer with the 16 dB attenuator enabled. Figure 13a shows the measured power spectral density measured at the output of the undecimated band-pass - modulator. Note, the wide dynamic range achieved at the center frequency, fCLK/8, is achieved once the LC and RC resonators of the - modulator have been successfully tuned. The out-of-band noise is removed by the decimation filters following quadrature demodulation. Table IX. SPI Registers Associated with LNA/Mixer Address (Hex) Bit Breakdown Width Default Value Name 0x00 0x01 0x01 0x03 (7:0) (7:6) (5:4) (7) 8 2 2 1 0xFF 0 0 0 STBY LNAB MIXB ATTEN 0 ­2 dBFS OUTPUT fCLK = 18MHz NBW = 3.3kHz ­10 ­20 ­30 dBFS/NBW 0 ­40 ­50 ­60 ­70 ­80 ­90 ­100 0 1 2 3 4 5 6 7 8 9 FREQUENCY ­ MHz Figure 13a. Measured Undecimated Spectral Output of - Modulator ADC with fCLK = 18 MSPS and Noise Bandwidth of 3.3 kHz REV. 0 ­23­ AD9874 AD9874 The signal transfer function of the AD9874 AD9874 possesses inherent antialias filtering by virtue of the continuous-time portions of the loop filter in the band-pass - modulator. Figure 13b illustrates this property by plotting the nominal signal transfer function of the ADC for frequencies up to 2fCLK. The notches that naturally occur for all frequencies that alias to the fCLK/8 pass band are clearly visible. Even at the widest bandwidth setting, the notches are deep enough to provide greater than 80 dB of alias protection. Thus, the wideband IF filtering requirements preceding the AD9874 AD9874 will be mostly determined by the mixer's image band that is offset from the desired IF input frequency by fCLK/4 (i.e., 2 fCLK/8), rather than any aliasing associated with the ADC. 0 ­10 ­20 dB ­30 ­50 ­60 ­70 0 0.5 1.0 1.5 When tuning the LC tank, the sampling clock frequency must be stable and the LNA/mixer, LO synthesizer, and ADC must all be placed in standby. Tuning is triggered when the ADC is taken out of standby if the TUNE_LC bit of register 0x1C has been set. This bit will clear when the tuning operation is complete (less than 6 ms). The tuning codes can be read from the 3-bit CAPL1 (0x1D) and the 6-bit CAPL0 (0x1E) Registers. In a similar manner, tuning of the RC resonator is activated if the TUNE_RC bit of register 0x1C is set when the ADC is taken out of standby. This bit will clear when tuning is complete. The tuning code can be read from the CAPR (0x1F) Register. Setting both the TUNE_LC and TUNE_RC bits tunes the LC tank and the active RC resonator in succession. During tuning, the ADC is not operational and neither data nor a clock is available from the SSI port. Table X lists the recommended sequence of the SPI commands for tuning the ADC, while Table XI lists all of the SPI Registers associated with band-pass - ADC. NOTCH AT ALL ALIAS FREQUENCIES ­40 ­80 Tuning of the - modulator's two continuous-time resonators is essential in realizing the ADC's full dynamic range and must be performed upon system startup. To facilitate tuning of the LC tank, a capacitor array is internally connected to the MXOP and MXON pins. The capacitance of this array is programmable from 0 pF to 200 pF ± 20% and can be programmed either automatically or manually via the SPI port. The capacitors of the active RC resonator are similarly programmable. Note, the AD9874 AD9874 can be placed in and out of its standby mode without retuning since the tuning codes are stored in the SPI Registers. 2.0 NORMALIZED FREQUENCY ­ RELATIVE TO fOUT Table X. Tuning Sequence Figure 13b. Signal Transfer Function of the Band-Pass - Modulator from 0 fCLK to 2 fCLK Address Figure 13c shows the nominal signal transfer function magnitude for frequencies near the fCLK/8 pass band. The width of the pass band determines the transfer function droop, but even at the lowest oversampling ratio (48) where the pass band edges are at fCLK/192 ( .005 fCLK), the gain variation is less than 0.5 dB. Note, the amount of attenuation offered by the signal transfer function near fCLK /8 should also be considered when determining the narrow-band IF filtering requirements preceding the AD9874 AD9874. Value Comments 0x01 0x45 LO synthesizer, LNA/mixer, and ADC are placed in standby.* 0x01 0x03 Set TUNE_LC and TUNE_RC. Wait for CLK to stabilize if CLK synthesizer used. 0x03 0x44 Take the ADC out of standby. Wait for 0x1C to clear ( ­18 dBm at LNA input) to prevent overloading of the ADC. The lower 15 bits specify the attenuation in the remainder of the signal path. If the DVGA is enabled, the attenuation range is from ­12 dB to +12 dB since the DVGA provides 12 dB of digital gain. In this case, all 15 bits are significant. However, with the DVGA disabled the attenuation range extends from 0 dB to 12 dB and only the lower 14 bits are useful. Figure 19 shows the relationship between the amount of attenuation and the AGC Register setting for both cases. It is worth noting that the VGA imparts negligible phase error upon the desired signal as its gain is varied over a 12 dB range. This is due to the bandwidth of the VGA being far greater than the down converted desired signal (centered about fCLK/8) and remaining relatively independent of gain setting. As a result, phase modulated signals should experience minimal phase error as the AGC varies the VGA gain while tracking an interferer or the desired signal under fading conditions. Note, the envelope of the signal will still be affected by the AGC settings. REV. 0 12 ONLY VGA ENABLED AGC ATTENUATION ­ dB VARIABLE GAIN AMPLIFIER OPERATION WITH AUTOMATIC GAIN CONTROL VGA RANGE 6 DVGA AND VGA ENABLED 0 DVGA RANGE ­6 ­12 0000 1FFF 3FFF 5FFF 7FFF AGCG SETTING ­ HEX Figure 19. AGC Gain Range Characteristics vs. AGCG Register Setting with and without DVGA Enabled ­27­ AD9874 AD9874 Referring to Figure 18, the gain of the VGA is set by an 8-bit control DAC that provides a control signal to the VGA appearing at the gain control pin (GCP). For applications implementing automatic gain control, the DAC's output resistance can be reduced by a factor of 9 to decrease the attack time of the AGC response for faster signal acquisition. An external capacitor, CDAC, from GCP to analog ground is required to "smooth" the DAC's output each time it updates as well as to filter wideband noise. Note, CDAC, in combination with the DAC's programmable output resistance, sets the ­3 dB bandwidth and time constant associated with this RC network. A linear estimate of the received signal strength is performed at the output of the first decimation stage (DEC1) and output of the DVGA (if enabled) as discussed in the AGC section. This data is available as a 6-bit RSSI field within an SSI frame with 60 corresponding to a full-scale signal for a given AGC attenuation setting. The RSSI field is updated at fCLK/60 and can be used with the 8-bit attenuation field (or AGCG attenuation setting) to determine the absolute signal strength. The accuracy of the mean RSSI reading (relative to the IF input power) depends on the input signal's frequency offset relative to the IF frequency since both DEC1 filter's response as well as the ADC's signal transfer function attenuates the mixer's downconverted signal level centered at fCLK/8. As a result, the estimated signal strength of input signals falling within proximity to the IF is reported accurately, while those signals at increasingly higher frequency offsets incur larger measurement errors. Figure 20 shows the normalized error of the RSSI reading as a function of the frequency offset from the IF frequency. Note, the significance of this error becomes apparent when determining the maximum input interferer (or blocker) levels with the AGC enabled. 0 MEASURED RSSI ERROR ­ dB ­3 ­6 ­9 ­12 ­15 ­18 0 0.01 0.02 0.03 0.04 0.05 NORMALIZED FREQUENCY OFFSET ­ (fIN ­ fIF) fCLK Figure 20. Normalized RSSI Error vs. Normalized IF Frequency Offset Automatic Gain Control (AGC) The gain of the VGA (and DVGA) is automatically adjusted when the AGC is enabled via the AGCR field of Register 0x06. In this mode, the gain of the VGA is continuously updated at fCLK/60 in an attempt to ensure that the maximum analog signal level into the ADC does not exceed the ADC clip level and that the rms output level of the ADC is equal to a programmable reference level. With the DVGA enabled, the AGC control loop also attempts to minimize the effects of 16-bit truncation noise prior to the SSI output by continuously adjusting the DVGA's gain to ensure maximum digital gain while not exceeding the programmable reference level. This programmable level can be set at 3 dB, 6 dB, 9 dB, 12 dB, and 15 dB below the ADC saturation (clip) level by writing values from 1 to 5 to the 3-bit AGCR field. Note, the ADC clip level is defined to be 2 dB below its full scale (i.e., ­18 dBm at the LNA input for a matched input and maximum attenuation). If AGCR is 0, automatic gain control is disabled. Since clipping of the ADC input will degrade the SNR performance, the reference level should also take into consideration the peak-to-rms characteristics of the target (or interferer) signals. Referring again to Figure 18, the majority of the AGC loop operates in the discrete time domain. The sample rate of the loop is fCLK/60; therefore, registers associated with the AGC algorithm are updated at this rate. The number of overload and ADC reset occurrences within the final I/Q update rate of the AD9874 AD9874, as well as the AGC value (8 MSBs), can be read from the SSI data upon proper configuration. The AGC performs digital signal estimation at the output of the first decimation stage (DEC1) as well as the DVGA output that follows the last decimation stage (DEC3). The rms power of the I and Q signal is estimated by the following equation: [] ( [ ]) ( [ ]) Xest n = Abs I n + Abs Q n (7) Signal estimation after the first decimation stage allows the AGC to cope with out-of-band interferers and in-band signals that could otherwise overload the ADC. Signal estimation after the DVGA allows the AGC to minimize the effects of the 16-bit truncation noise. When the estimated signal level falls within the range of the AGC, the AGC loop adjusts the VGA (or DVGA) attenuation setting so that the estimated signal level is equal to the programmed level specified in the AGCR field. The absolute signal strength can be determined from the contents of the ATTN and RSSI field that is available in the SSI data frame when properly configured. Within this AGC tracking range, the 6-bit value in the RSSI field remains constant while the 8-bit ATTN field varies according to the VGA/DVGA setting. Note, the ATTN value is based on the 8 MSBs contained in the AGCG field of Registers 0x03 and 0x04. A description of the AGC control algorithm and the user adjustable parameters follows. First, consider the case in which the in-band target signal is bigger than all out-of-band interferers and the DVGA is disabled. With the DVGA disabled, a control loop based only on the target signal power measured after DEC1 is used to control the VGA gain, and the target signal will be tracked to the programmed reference level. If the signal is too large, the attenuation is increased with a proportionality constant determined by the AGCA setting. Large AGCA values result in large gain changes, thus rapid tracking of changes in signal strength. If the target signal is too small relative to the reference level, the attenuation is reduced; but now the pr