AD9852 12-BIT 14-BIT 00634-C-001 AD9854 AD9852ASQ AD9852AST SUPPLY10 - Datasheet Archive

 

Complete DDS

 

CMOS 300 MSPS Complete DDS AD9852 AD9852 300 MHz toggle rate, low jitter, sensitive input, built-in hysteresis. It also has an output level of 1 V p-p minimum into 50 or CMOS logic levels into high impedance loads. The comparator can be separately powered down to conserve power. This comparator is used in clock generator applications to square up the filtered sine wave generated by the DDS. Power-Down Several individual stages may be powered down to reduce power consumption via the programming registers while still maintaining functionality of desired stages. These stages are identified in the Register Layout table, address 1D hex. Powerdown is achieved by setting the specified bits to logic high. A logic low indicates that the stages are powered up. Furthermore, and perhaps most significantly, the Inverse Sinc filters and the digital multiplier stages, can be bypassed to achieve significant power reduction through programming of the control registers in address 20 hex. Again, logic high causes the stage to be bypassed. Of particular importance is the inverse sinc filter as this stage consumes a significant amount of power. A full power-down occurs when all four PD bits in control register 1D hex are set to logic high. This reduces power consumption to approximately 10 mW (3 mA). Rev. C | Page 26 of 48 AD9852 AD9852 PROGRAMMING THE AD9852 AD9852 The AD9852 AD9852 Register Layout, shown in Table 7, contains the information that programs a chip for the desired functionality. While many applications require very little programming to configure the AD9852 AD9852, some make use of all 12 accessible register banks. The AD9852 AD9852 supports an 8-bit parallel I/O operation or an SPI compatible serial I/O operation. All accessible registers can be written and read back in either I/O operating mode. S/P SELECT, Pin 70, is used to configure the I/O mode. Systems that use the parallel I/O mode must connect the S/P SELECT pin to VDD. Systems that operate in the serial I/O mode must tie the S/P SELECT pin to GND. Regardless of mode, the I/O port data is written to a buffer memory that does not affect operation of the part until the contents of the buffer memory are transferred to the register banks. This transfer of information occurs synchronously to the system clock and occurs in one of two ways: 1. 2. The transfer is internally controlled at a rate programmable by the user. The transfer is externally controlled by the user. I/O operations can occur in the absence of REFCLK but the data cannot be moved from the buffer memory to the register bank without REFCLK. (See the Internal and External Update Clock section for details.) MASTER RESET Logic high active must be held high for a minimum of 10 system clock cycles. This causes the communications bus to be initialized and loads default values listed in Table 7. PARALLEL I/O OPERATION With the S/P SELECT pin tied high, the parallel I/O mode is active. The I/O port is compatible with industry-standard DSPs and microcontrollers. Six address bits, eight bidirectional data bits, and separate write/read control inputs make up the I/O port pins. Parallel I/O operation allows write access to each byte of any register in a single I/O operation up to 1/10.5 ns. Read back capability for each register is included to ease designing with the AD9852 AD9852. Reads are not guaranteed at 100 MHz as they are intended for software debugging only. Parallel I/O operation timing diagrams are shown in Figure 49 and Figure 50. Table 6. REFCLK Multiplier Control Register Values Ref Mult Multiplier Value 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Bit 3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 Bit 2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 SERIAL PORT I/O OPERATION With the S/P SELECT pin tied low, the serial I/O mode is active. The AD9852 AD9852 serial port is a flexible, synchronous, serial communications port allowing easy interface to many industrystandard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola 6905/11 SPI and Intel® 8051 SSR protocols. The interface allows read/write access to all 12 registers that configure the AD9852 AD9852 and can be configured as a single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO). Data transfers are supported in most significant bit (MSB) first format or least significant bit (LSB) first format at up to 10 MHz. When configured for serial I/O operation, most pins from the AD9852 AD9852 parallel port are inactive; some are used for the serial I/O. Table 8 describes pin requirements for serial I/O. Note: When operating in the serial I/O mode, it is best to use the external I/O update CLK mode to avoid an I/O update CLK during a serial communication cycle. Such an occurrence could cause incorrect programming due to partial data transfer. Thus, the user would want to write between I/O update CLKs. To exit the default internal update mode, program the device for external update operation at power-up, before starting the REFCLK signal, but after a master reset. Starting the REFCLK causes this information to transfer to the register bank, putting the device in external update mode. Rev. C | Page 27 of 48 AD9852 AD9852 Table 7. Register Layout Shaded sections comprise the control register. Parallel Address Serial Address Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D Hex 0 2 3 4 5 6 7 1F 20 8 9 A B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Phase Adjust Register #1 (Bits 15, 14, don't care) Phase 1 Phase Adjust Register #1 Phase Adjust Register #2 (Bits 15, 14, don't care) Phase 2 Phase Adjust Register #2 Frequency 1 Frequency tuning word 1 Frequency tuning word 1 Frequency tuning word 1 Frequency tuning word 1 Frequency tuning word 1 Frequency tuning word 1 Frequency 2 Frequency tuning word 2 Frequency tuning word 2 Frequency tuning word 2 Frequency tuning word 2 Frequency tuning word 2 Frequency tuning word 2 Delta frequency word Delta frequency word Delta frequency word Delta frequency word Delta frequency word Delta frequency word Update clock Update clock Update clock Update clock Ramp rate clock (Bits 23, 22, 21, 20, don't care) Ramp rate clock Ramp rate clock Don't care CR [31] Don't Don't Comp Reserved, Control care care PD always DAC PD low Don't care Ref mult 2 PLL Bypass Ref Ref mult range PLL mult 3 4 CLR ACC 1 Triangle Don't Mode 2 Mode 1 CLR ACC 2 care Bit 1 Don't care 1 1E 21 22 23 24 25 26 27 AD9852 AD9852 Register Layout LSB first Don't care Bypass OSK EN OSK Don't inv INT care sinc Output Shape Key Mult (Bits 15,14,13,12 don't care) Output Shape Key Mult Don't care Don't care Output shape key ramp rate Control DAC (Bits 15, 14, 13, 12 don't care) Control DAC (Data is required to be in twos complement format) Rev. C | Page 28 of 48 Bit 0 Default Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 40h 00h 00h 00h DAC PD DIG PD 10h Ref mult 1 Ref mult 0 64h Mode 0 INT/EXT Update Clk SDO active CR [0] 01h 20h 00h 00h 00h 00h 80h 00h 00h AD9852 AD9852 A A1 A2 A3 D D1 D2 D3 RD TRDHOZ TAHD TRDLOV TADV VALUE DESCRIPTION TADV TAHD TRDLOV TRDHOZ 15ns 5ns 15ns 10ns ADDRESS TO DATA VALID TIME (MAXIMUM) ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM) RD LOW TO OUTPUT VALID (MAXIMUM) RD HIGH TO DATA THREE-STATE (MAXIMUM) 00634-C-049 00634-C-049 SPECIFICATION Figure 49. Parallel Port Read Timing Diagram TWR A D A1 A2 D1 A3 D2 D3 WR TASU TDSU TWRHIGH TAHD TWRLOW TDHD VALUE DESCRIPTION TASU TDSU TADH TDHD TWRLOW TWRHIGH TWR 8.0ns 3.0ns 0ns 0ns 2.5ns 7ns 10.5ns ADDRESS SETUP TIME TO WR SIGNAL ACTIVE DATA SETUP TIME TO WR SIGNAL ACTIVE ADDRESS HOLD TIME TO WR SIGNAL INACTIVE DATA HOLD TIME TO WR SIGNAL INACTIVE WR SIGNAL MINIMUM LOW TIME WR SIGNAL MINIMUM HIGH TIME MINIMUM WRITE TIME Figure 50. Parallel Port Write Timing Diagram Table 8. Serial I/O Pin Requirements Pin Number 1, 2, 3, 4, 5, 6, 7, 8 14, 15, 16 17 18 19 20 21 22 Mnemonic D[7:0] A[5:3] A2 A1 A0 I/O UD CLOCK WRB RDB Serial I/O Description The parallel data pins are not active, tie to VDD or GND. The parallel address Pins A5, A4, A3 are not active; tie to VDD or GND. I/O RESET SDO SDIO Update Clock. Same functionality for serial mode as parallel mode. SCLK CSB-Chip Select Rev. C | Page 29 of 48 00634-C-050 00634-C-050 SPECIFICATION AD9852 AD9852 GENERAL OPERATION OF THE SERIAL INTERFACE Figure 51 and Figure 52 are useful in understanding the general operation of the AD9852 AD9852 Serial Port. CS INSTRUCTION BYTE INSTRUCTION CYCLE A B Register Name Phase Offset Tuning Word Register #1 Phase Offset Tuning Word Register #2 Frequency Tuning Word #1 Frequency Tuning Word #2 Delta Frequency Register Update Clock Rate Register Ramp Rate Clock Register Control Register Digital Multiplier Register Shaped On/Off Keying Ramp Rate Register Control DAC Register Number of Bytes Transferred 2 2 6 6 6 4 3 4 2 DATA BYTE 2 DATA BYTE 3 DATA TRANSFER Figure 51. Using SDIO as a Read/Write Transfer CS INSTRUCTION BYTE SDIO INSTRUCTION CYCLE Table 9. Register Address vs. Data Bytes Transferred Serial Register Address 0 1 2 3 4 5 6 7 8 DATA BYTE 1 SDIO 00634-C-051 00634-C-051 The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9852 AD9852. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9852 AD9852 and the system controller. The number of data bytes transferred in Phase 2 of the communication cycle is a function of the register address. The AD9852 AD9852 internal serial I/O controller expects every byte of the register being accessed to be transferred. Table 9 describes how many bytes must be transferred. All data input to the AD9852 AD9852 is registered on the rising edge of SCLK. All data is driven out of the AD9852 AD9852 on the falling edge of SCLK. DATA TRANSFER DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 SDO DATA TRANSFER 00634-C-052 00634-C-052 There are two phases to a serial communication cycle with the AD9852 AD9852. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9852 AD9852, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9852 AD9852 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, and the register address to be acted upon. Figure 52. Using SDIO as an Input, SDO as an Output INSTRUCTION BYTE The instruction byte contains the following information. Table 10. Instruction Byte Information MSB R/W D6 X D5 X D4 X D3 A3 D2 A2 D1 A1 LSB A0 R/W Bit 7 of the instruction byte determines whether a read or write data transfer occurs following the instruction byte. Logic high indicates read operation. Logic 0 indicates a write operation. 1 2 At the completion of any communication cycle, the AD9852 AD9852 serial port controller expects the next eight rising SCLK edges to be the instruction byte of the next communication cycle. In addition, an active high input on the I/O RESET pin immediately terminates the current communication cycle. After I/O RESET returns low, the AD9852 AD9852 serial port controller requires the next eight rising SCLK edges to be the instruction byte of the next communication cycle. Note that Bits 6, 5, and 4 of the instruction byte are dummy bits (don't care). A3, A2, A1, A0 Bits 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. See Table 9 for register address details. Rev. C | Page 30 of 48 AD9852 AD9852 SERIAL INTERFACE PORT PIN DESCRIPTIONS Table 11. Pin SCLK CS SDIO SDO I/O RESET Description Serial Clock (Pin 21). The serial clock pin is used to synchronize data to and from the AD9852 AD9852 and to run the internal state machines. SCLK maximum frequency is 10 MHz. Chip Select (Pin 22). Active low input that allows more than one device on the same serial communications lines. The SDO and SDIO pins go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip select can be tied low in systems that maintain control of SCLK. Serial Data I/O (Pin 19). Data is always written into the AD9852 AD9852 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 0 of register address 20h. The default is logic zero, which configures the SDIO pin as bidirectional. Serial Data Out (Pin 18). Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9852 AD9852 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Synchronize I/O Port (Pin 17). Synchronizes the I/O port state machines without affecting the contents of the addressable registers. An active high input on I/O RESET pin causes the current communication cycle to terminate. After I/O RESET returns low (Logic 0) another communication cycle may begin, starting with the instruction byte. Notes on Serial Port Operation MSB/LSB TRANSFERS The AD9852 AD9852 serial port configuration bits reside in Bit 1 and Bit 0 of register address 20h. It is important to note that the configuration changes immediately upon a valid I/O update. For multibyte transfers, writing this register may occur during the middle of a communication cycle. Care must be taken to compensate for this new configuration for the remainder of the current communication cycle. The AD9852 AD9852 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by Bit 1 of serial register bank 20h. When this bit is set active high, the AD9852 AD9852 serial port is in LSB first format. This bit defaults low, to the MSB first format. The instruction byte must be written in the format indicated by Bit 1 of serial register bank 20h. That is, if the AD9852 AD9852 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. TPRE TSCLK CS TDSU TSCLKPWH TSCLKPWL SCLK TDHLD FIRST BIT SDIO SECOND BIT SYMBOL In cases where synchronization is lost between the system and the AD9852 AD9852, the I/O RESET pin provides a means to reestablish synchronization without reinitializing the entire chip. Asserting the I/O RESET pin (active high) resets the AD9852 AD9852 serial port state machine, terminating the current I/O operation and putting the device into a state in which the next eight SCLK rising edges are understood to be an instruction byte. The I/O RESET pin must be deasserted (low) before the next instruction byte write can begin. Any information that had been written to the AD9852 AD9852 registers during a valid communication cycle prior to loss of synchronization remains intact. MIN DEFINITION TPRE TSCLK TDSU TSCLKPWH TSCLKPWL TDHLD 30ns 100ns 30ns 40ns 40ns 0ns CS SETUP TIME PERIOD OF SERIAL DATA CLOCK SERIAL DATA SETUP TIME SERIAL DATA CLOCK PULSE WIDTH HIGH SERIAL DATA CLOCK PULSE WIDTH LOW SERIAL DATA HOLD TIME 00634-C-053 00634-C-053 The system must maintain synchronization with the AD9852 AD9852 or the internal control logic is not able to recognize further instructions. For example, if the system sends the instruction to write a 2-byte register, then pulses the SCLK pin for a 3-byte register (24 additional SCLK rising edges), communication synchronization is lost. In this case, the first 16 SCLK rising edges after the instruction cycle properly write the first two data bytes into the AD9852 AD9852, but the next eight rising SCLK edges are interpreted as the next instruction byte, not the final byte of the previous communication cycle. Figure 53. Timing Diagram for Data Write to AD9852 AD9852 CS SCLK SDIO SDO FIRST BIT SECOND BIT SYMBOL MAX DEFINITION TDV 30ns DATA VALID TIME Figure 54. Timing Diagram for Read from AD9852 AD9852 Rev. C | Page 31 of 48 00634-C-054 00634-C-054 TDV AD9852 AD9852 CONTROL REGISTER DESCRIPTIONS The Control Register is located at address 1D through 20 hex, shown in the shaded portion of Table 7. It is composed of 32 bits. Bit 31 is located at the top left position and Bit 0 is located in the lower right position of the shaded table portion. The register has been subdivided below to make it easier to locate the text associated with specific control categories. Table 12. Bit CR[31:29] CR[28] CR[27] CR[26] CR[25] CR[24] CR[23] CR[22] CR[21] CR[20:16] CR[15] CR[14] CR[13] CR[12] CR[11:9] CR[8] CR[7] CR[6] CR[5] CR[4] CR[3:2] CR[1] CR[0] Description Open. The comparator power-down bit. When set (Logic 1), this signal indicates to the comparator that a power-down mode is active. This bit is an output of the digital section and is an input to the analog section. Must always be written to logic zero. Writing this bit to Logic 1 causes the AD9852 AD9852 to stop working until a master reset is applied. The control DAC power-down bit. When set (Logic 1), it indicates to the control DAC that power-down mode is active. The full DAC power-down bit. When set (Logic 1), this signal indicates to both the cosine and control DACs as well as the reference that a power-down mode is active. The digital power-down bit. When set (Logic 1), this signal indicates to the digital section that a power-down mode is active. Within the digital section, the clocks are forced to dc, effectively powering down the digital section. The PLL still accepts the REFCLK signal and continue to output the higher frequency. Reserved. Write to zero. The PLL range bit. The PLL range bit controls the VCO gain. The power-up state of the PLL range bit is Logic 1, higher gain for frequencies above 200 MHz. The bypass PLL bit, active high. When active, the PLL is powered down and the REFCLK input is used to drive the system clock signal. The power-up state of the bypass PLL bit is Logic 1, PLL bypassed. The PLL multiplier factor. These bits are the REFCLK multiplication factor unless the bypass PLL bit is set.The PLL multiplier valid range is from 4 to 20, inclusive. The clear accumulator 1 bit. This bit has a one-shot-type function. When written active, Logic 1, a clear accumulator 1 signal is sent to the DDS logic, resetting the accumulator value to zero. The bit is then automatically reset, but the buffer memory is not reset. This bit allows the user to easily create a saw tooth frequency sweep pattern with minimal user intervention. This bit is intended for chirp mode only, but its function is still retained in other modes. The clear accumulator bit. This bit, active high, holds both the accumulator 1 and accumulator 2 values at zero for as long as the bit is active. This allows the DDS phase to be initialized via the I/O port. The triangle bit. When this bit is set, the AD9852 AD9852 automatically performs a continuous frequency sweep from F1 to F2 frequencies and back. The effect is a triangular frequency sweep. When this bit is set, the operating mode must be set to ramped FSK. Don't care. The three bits that describe the five operating modes of the AD9852 AD9852: 0h = Single-Tone mode 1h = FSK mode 2h = Ramped FSK mode 3h = Chirp mode 4h = BPSK mode The internal update active bit. When this bit is set to Logic 1, the I/O UD pin is an output and the AD9852 AD9852 generates the I/O UD signal. When Logic 0, external I/O UD functionality is performed, the I/O UD pin is configured as an input. Reserved. Write to zero. is the inverse sinc filter BYPASS bit. When set, the data from the DDS block goes directly to the output shaped-keying logic and the clock to the inverse sinc filter is stopped. Default is clear, filter enabled. The shaped-keying enable bit. When set, the output ramping function is enabled and is performed in accordance with the CR[4] bit requirements. The internal/external output shaped-keying control bit. When set to Logic 1, the shaped-keying factor is internally generated and applied to the cosine DAC path. When cleared (default), the output shaped-keying function is externally controlled by the user and the shaped-keying factor is the shaped keying factor register's value. The two registers that are the shaped-keying factors also default low such that the output is off at power-up and until the device is programmed by the user. Reserved. Write to zero. The serial port MSB/LSB first bit. Defaults low, MSB first. The serial port SDO active bit. Defaults low, inactive. Rev. C | Page 32 of 48 AD9852 AD9852 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I7 I6 I5 I4 I3 I2 I1 I0 D6 D7 D5 D4 D3 D2 D1 00634-C-055 00634-C-055 SCLK D0 Figure 55. Serial Port Write Timing-Clock Stall Low DATA TRANSFER CYCLE INSTRUCTION CYCLE CS SCLK I7 I6 I5 I4 I3 I2 I1 I0 DON'T CARE DO7 SDO DO6 DO5 DO4 DO3 DO2 DO1 00634-C-056 00634-C-056 SDIO DO0 Figure 56. Three-Wire Serial Port Read Timing-Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I6 I7 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 00634-C-057 00634-C-057 SCLK D0 Figure 57. Serial Port Write Timing-Clock Stall High INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I7 I6 I5 I4 I3 I2 I1 I0 DO7 DO6 DO5 DO4 Figure 58. Two-Wire Serial Port Read Timing-Clock Stall High Rev. C | Page 33 of 48 DO3 DO2 DO1 DO0 00634-C-058 00634-C-058 SCLK AD9852 AD9852 POWER DISSIPATION AND THERMAL CONSIDERATIONS The AD9852 AD9852 is a multifunctional, very high speed device that targets a wide variety of synthesizer and agile clock applications. The set of numerous innovative features contained in the device each consume incremental power. If enabled in combination, the safe thermal operating conditions of the device may be exceeded. Careful analysis and consideration of power dissipation and thermal management is a critical element in the successful application of the AD9852 AD9852 device. The AD9852 AD9852 device is specified to operate within the industrial temperature range of ­40°C to +85°C. This specification is conditional, however, such that the absolute maximum junction temperature of 150°C is not exceeded. At high operating temperatures, extreme care must be taken in the operation of the device to avoid exceeding the junction temperature which results in a potentially damaging thermal condition. and ground pins of the device being soldered directly to a copper plane on a PCB. In addition, the thermally enhanced package of the AD9852ASQ AD9852ASQ contains a heat sink on the bottom that must be soldered to a ground pad on the PCB surface. This pad must be connected to a large copper plane which, for convenience, may be the ground plane. Sockets for either package style of the AD9852 AD9852 device are not recommended. JUNCTION TEMPERATURE CONSIDERATIONS The power dissipation (PDISS) of the AD9852 AD9852 device in a given application is determined by many operating conditions. Some of the conditions have a direct relationship with PDISS, such as supply voltage and clock speed, but others are less deterministic. The total power dissipation within the device, and its effect on the junction temperature, must be considered when using the device. The junction temperature of the device is given by Junction Temperature = (Thermal Impedance × Power Consumption) + Ambient Temperature Many variables contribute to the operating junction temperature within the device, including Given that the junction temperature should never exceed 150°C for the AD9852 AD9852, and that the ambient temperature can be 85°C, the maximum power consumption for the AD9852AST AD9852AST is 1.7 W and the AD9852ASQ AD9852ASQ (thermally enhanced package) is 4.1 W. Factors affecting the power dissipation are described next. 1. Package style. 2. Selected mode of operation. 3. Internal system clock speed. 4. Supply voltage. 5. Ambient temperature. The combination of these variables determines the junction temperature within the AD9852 AD9852 device for a given set of operating conditions. Supply Voltage The AD9852 AD9852 device is available in two package styles: a thermally enhanced, surface-mount package with an exposed heat sink, and a nonthermally enhanced surface-mount package. The thermal impedance of these packages is 16°C/W and 38°C/W, respectively, measured under still-air conditions. THERMAL IMPEDANCE The thermal impedance of a package can be thought of as a thermal resistor that exists between the semiconductor surface and the ambient air. The thermal impedance of a package is determined by package material and its physical dimensions. The dissipation of the heat from the package is directly dependent upon the ambient air conditions and the physical connection made between the IC package and the PCB. Adequate dissipation of power from the AD9852 AD9852 relies upon all power Supply voltage obviously affects power dissipation and junction temperature since PDISS equals V × I. Users should design for 3.3 V nominal; however, the device is guaranteed to meet specifications over the full temperature range and over the supply voltage range of 3.135 V to 3.465 V. Clock Speed Clock speed directly and linearly influences the total power dissipation of the device, and, therefore, junction temperature. As a rule, the user should always select the lowest internal clock sp