AD9761 AD9281 AD9201 AD9761ARS RS-28 AD9761-EB HP3589A AWG-2021 AWG2021 40MSPS - Datasheet Archive

 

FEATURES Complete 10-Bit, 40 MSPS Dual Transmit DAC Excellent Gain and Offset Matching Differential Nonlinearity Error: 0.5 LSB

 

a FEATURES Complete 10-Bit, 40 MSPS Dual Transmit DAC Excellent Gain and Offset Matching Differential Nonlinearity Error: 0.5 LSB Effective Number of Bits: 9.5 Signal-to-Noise and Distortion Ratio: 59 dB Spurious-Free Dynamic Range: 71 dB 2 Interpolation Filters 20 MSPS/Channel Data Rate Single Supply: +2.7 V to +5.5 V Low Power Dissipation: 200 mW (+3 V Supply @ 40 MSPS) On-Chip Reference 28-Lead SSOP Dual 10-Bit TxDAC+TM with 2 Interpolation Filters AD9761 AD9761 FUNCTIONAL BLOCK DIAGRAM DCOM SLEEP DVDD LATCH "I" CLOCK 2 ACOM AVDD "I" DAC IOUTA IOUTB REFERENCE LATCH "Q" WRITE INPUT SELECT INPUT MUX CONTROL REFLO FSADJ REFIO BIAS GENERATOR DAC DATA INPUTS (10 BITS) COMP1 COMP2 COMP3 2 "Q" DAC QOUTA QOUTB AD9761 AD9761 PRODUCT DESCRIPTION The AD9761 AD9761 is a complete dual channel, high speed, 10-bit CMOS DAC. The AD9761 AD9761 has been developed specifically for use in wide bandwidth communication applications (e.g., spread spectrum) where digital I and Q information is being processed during transmit operations. It integrates two 10-bit, 40 MSPS DACs, dual 2× interpolation filters, a voltage reference, and digital input interface circuitry. The AD9761 AD9761 supports a 20 MSPS per channel input data rate that is then interpolated by 2× up to 40 MSPS before simultaneously updating each DAC. PRODUCT HIGHLIGHTS 1. Dual 10-Bit, 40 MSPS DACs: A pair of high performance 40 MSPS DACs optimized for low distortion performance provide for flexible transmission of I and Q information. 2. 2× Digital Interpolation Filters: Dual matching FIR interpolation filters with 62.5 dB stop band rejection precede each DAC input thus reducing the DACs' reconstruction filter requirements. The interleaved I and Q input data stream is presented to the digital interface circuitry, which consists of I and Q latches as well as some additional control logic. The data is de-interleaved back into its original I and Q data. An on-chip state machine ensures the proper pairing of I and Q data. The data output from each latch is then processed by a 2× digital interpolation filter that eases the reconstruction filter requirements. The interpolated output of each filter serves as the input of their respective 10-bit DAC. 3. Low Power: Complete CMOS Dual DAC function operates on a low 200 mW on a single supply from 2.7 V to 5.5 V. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for power reduction during idle periods. The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. Each DAC provides differential current output thus supporting single-ended or differential applications. Both DACs are simultaneously updated and provide a nominal full-scale current of 10 mA. Also, the full-scale currents between each DAC are matched to within 0.07 dB (i.e., 0.75%), thus eliminating the need for additional gain calibration circuitry. 5. Single 10-Bit Digital Input Bus: The AD9761 AD9761 features a flexible digital interface allowing each DAC to be addressed in a variety of ways including different update rates. 4. On-Chip Voltage Reference: The AD9761 AD9761 includes a 1.20 V temperature-compensated bandgap voltage reference. 6. Small Package: The AD9761 AD9761 offers the complete integrated function in a compact 28-lead SSOP package. 7. Product Family: The AD9761 AD9761 Dual Transmit DAC has a pair of Dual Receive ADC companion products, the AD9281 AD9281 (8 bits) and AD9201 AD9201 (10 bits). The AD9761 AD9761 is manufactured on an advanced low cost CMOS process. It operates from a single supply of 2.7 V to 5.5 V and consumes 200 mW of power. To make the AD9761 AD9761 complete it also offers an internal 1.20 V temperature-compensated bandgap reference. TxDAC+ is a trademark of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 7817/326-8703 © Analog Devices, Inc., 2000 AD9761 AD9761­SPECIFICATIONS DC SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA, unless otherwise noted) Parameter Min RESOLUTION Typ Max 10 Units Bits 1 DC ACCURACY Integral Linearity Error (INL) TA = +25°C TMIN to TMAX Differential Nonlinearity (DNL) TA = +25°C TMIN to TMAX Monotonicity (10 Bit) ANALOG OUTPUT Offset Error Offset Matching between DACs Gain Error (without Internal Reference) Gain Error (with Internal Reference) Gain Matching between DACs Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance ­1.75 ­2.75 ± 0.5 ± 0.7 ­0.05 ­0.10 ­5.5 ­5.5 ­1.0 ± 0.025 ± 0.05 ± 1.0 ± 1.0 ± 0.25 10 ­1.0 0.05 0.10 5.5 5.5 1.0 1.25 100 5 1.14 REFERENCE INPUT Input Compliance Range Reference Input Resistance 0.1 1.20 100 % of FSR % of FSR % of FSR % of FSR % of FSR mA V k pF 1.26 V nA 1.25 1 V M 0 ± 50 ± 140 ± 25 ± 50 TEMPERATURE COEFFICIENTS Unipolar Offset Drift Gain Drift (without Internal Reference) Gain Drift (with Internal Reference) Gain Matching Drift (Between DACs) Reference Voltage Drift OPERATING RANGE LSB LSB ­1 ± 0.4 1.25 LSB ­1 ± 0.5 1.75 LSB GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE REFERENCE OUTPUT Reference Voltage Reference Output Current3 POWER SUPPLY AVDD Voltage Range Analog Supply Current (IAVDD ) DVDD Voltage Range Digital Supply Current at 5 V (IDVDD)4 Digital Supply Current at 3 V (IDVDD)4 Nominal Power Dissipation5 AVDD and DVDD at 3 V AVDD and DVDD at 5 V Power Supply Rejection Ratio (PSRR)­AVDD Power Supply Rejection Ratio (PSRR)­DVDD 1.75 2.75 ppm/°C ppm/°C ppm/°C ppm/°C ppm/°C 2.7 5.0 26 5.5 35 V mA 2.7 5.0 70 35 5.5 85 V mA mA 200 500 ­0.25 ­0.02 250 650 0.25 0.02 mW mW % of FSR/V % of FSR/V ­40 +85 °C NOTES 1 Measured at IOUTA and QOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS , is 16× the I REF current. 3 Use an external amplifier to drive any external load. 4 Measured at fCLOCK = 40 MSPS and fOUT = 1 MHz. 5 Measured as unbuffered voltage output into 50 RLOAD at IOUTA, IOUTB, QOUTA, and QOUTB, f CLOCK = 40 MSPS and f OUT = 8 MHz. Specifications subject to change without notice. ­2­ REV. A AD9761 AD9761 (TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA, Differential Transformer Coupled Output, 50 Doubly Terminated, unless otherwise noted) DYNAMIC SPECIFICATIONS Parameter Min DYNAMIC PERFORMANCE Maximum Output Update Rate Output Settling Time (tST to 0.025%) Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%) Output Fall Time (10% to 90%) Typ Max 40 Units 35 55 5 2.5 2.5 AC LINEARITY TO NYQUIST Signal-to-Noise and Distortion (SINAD) fOUT = 1 MHz; CLOCK = 40 MSPS Effective Number of Bits (ENOBs) Total Harmonic Distortion (THD) fOUT = 1 MHz; CLOCK = 40 MSPS Spurious-Free Dynamic Range (SFDR) fOUT = 1 MHz; CLOCK = 40 MSPS; 10 MHz Span Channel Isolation fOUT = 8 MHz; CLOCK = 40 MSPS; 10 MHz Span DIGITAL SPECIFICATIONS (T MIN 56 9.0 MSPS ns Input Clock Cycles pV-s ns ns 59 9.5 dB Bits ­68 59 ­58 dB 68 dB 90 dBC to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 10 mA unless otherwise noted) Parameter Min 3.5 2.4 DIGITAL INPUTS Logic "1" Voltage @ DVDD = +5 V Logic "1" Voltage @ DVDD = +3 V Logic "0" Voltage @ DVDD = +5 V Logic "0" Voltage @ DVDD = +3 V Logic "1" Current Logic "0" Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) CLOCK High CLOCK Low Invalid CLOCK/WRITE Window (tCINV)1 Typ 5 3 0 0 ­10 ­10 Max 1.3 0.9 +10 +10 5 3 2 5 5 1 5 Units V V V V µA µA pF ns ns ns ns ns NOTES 1 tCINV is an invalid window of 4 ns duration beginning 1 ns AFTER the rising edge of WRITE in which the rising edge of CLOCK MUST NOT occur. Specifications subject to change without notice. tS DB9­DB0 DAC INPUTS tH "I" DATA "Q" DATA SELECT NOTES: WRITE AND CLOCK CAN BE TIED TOGETHER. FOR TYPICAL EXAMPLES, REFER TO DIGITAL INPUTS AND INTERLEAVED INTERFACE CONSIDERATION SECTION. WRITE CLOCK tCINV Figure 1. Timing Diagram REV. A ­3­ AD9761 AD9761 (TMIN to TMAX, AVDD = +2.7 V to 5.5 V, DVDD = +2.7 V to 5.5 V, IOUTFS = 10 mA unless DIGITAL FILTER SPECIFICATIONS otherwise noted) Parameter Min MAXIMUM INPUT CLOCK RATE (fCLOCK) Typ Max 40 Units MSPS DIGITAL FILTER CHARACTERISTICS Passband Width1: 0.005 dB Passband Width: 0.01 dB Passband Width: 0.1 dB Passband Width: ­3 dB Linear Phase (FIR Implementation) Stopband Rejection: 0.3 fCLOCK to 0.7 fCLOCK Group Delay2 Impulse Response Duration3 ­40 dB ­60 dB 0.2010 0.2025 0.2105 0.239 fOUT/fCLOCK fOUT/fCLOCK fOUT/fCLOCK fOUT/fCLOCK ­62.5 32 dB Input Clock Cycles 28 40 Input Clock Cycles Input Clock Cycles NOTES 1 Excludes SINX/X characteristic of DAC. 2 Defined as the number of data clock cycles between impulse input and peak of output response. 3 55 input clock periods from input to I DAC, 56 to Q DAC. Propagation delay is delay from data input to DAC update. 0 Table I. Integer Filter Coefficients for 43-Tap Halfband FIR Filter ­20 OUTPUT ­ dBFS Lower Coefficient ­60 ­80 ­100 ­120 0 0.1 0.2 0.3 0.4 FREQUENCY RESPONSE ­ DC to fCLOCK/2 0.5 Figure 2a. FIR Filter Frequency Response 1 0.9 0.8 NORMALIZED OUTPUT 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Upper Coefficient Integer Value H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) ­40 H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) H(28) H(27) H(26) H(25) H(24) H(23) 1 0 ­3 0 8 0 ­16 0 29 0 ­50 0 81 0 ­131 0 216 0 ­400 0 1264 1998 0 ­0.1 ­0.2 ­0.3 0 5 10 15 20 25 TIME ­ Samples 30 35 40 Figure 2b. FIR Filter Impulse Response ­4­ REV. A AD9761 AD9761 ORDERING GUIDE Model Package Description THERMAL CHARACTERISTICS Thermal Resistance Package Option 28-Lead SSOP JA = 109°C/W AD9761ARS AD9761ARS 28-Lead Shrink Small Outline (SSOP) RS-28 RS-28 AD9761-EB AD9761-EB Evaluation Board ABSOLUTE MAXIMUM RATINGS* With Respect to AVDD DVDD ACOM AVDD CLOCK, WRITE SELECT, SLEEP Digital Inputs IOUTA, IOUTB QOUTA, QOUTB COMP1, COMP2 COMP3 REFIO, FSADJ REFLO Junction Temperature Storage Temperature Lead Temperature (10 sec) Min Max Units ACOM DCOM DCOM DVDD DCOM DCOM DCOM ACOM ACOM ACOM ACOM ACOM ACOM Parameter ­0.3 ­0.3 ­0.3 ­6.5 ­0.3 ­0.3 ­0.3 ­1.0 ­1.0 ­0.3 ­0.3 ­0.3 ­0.3 +6.5 +6.5 +0.3 +6.5 DVDD+0.3 DVDD+0.3 DVDD+0.3 AVDD+0.3 AVDD+0.3 AVDD+0.3 AVDD+0.3 AVDD+0.3 +0.3 +150 +150 +300 V V V V V V V V V V V V V °C °C °C ­65 *This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. +2.7V TO 5.5V +2.7V TO 5.5V 0.1F DVDD DCOM COMP3 LATCH "I" 0.1F AVDD AVSS COMP1 2x "I" DAC 0.1F MINI-CIRCUITS T1-1T COMP2 IOUTA TO HP3589A HP3589A SPECTRUM/NETWORK ANALYZER 50 INPUT 100 IOUTB REFLO TEKTRONIX AWG-2021 AWG-2021 50 DIGITAL DATA LATCH "Q" CLOCK OUT MARKER 1 SELECT WRITE RETIMED CLOCK OUTPUT* CLOCK 2x 20pF 50 20pF REFIO AD9761 AD9761 DB9­DB0 FSADJ "Q" DAC 0.1F RSET 2k MINI-CIRCUITS T1-1T QOUTA MUX CONTROL TO HP3589A HP3589A SPECTRUM/NETWORK ANALYZER 50 INPUT 100 QOUTB 50 20pF 50 20pF SLEEP *AWG2021 AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA LE CROY 9210 PULSE GENERATOR TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. Figure 3. Basic AC Characterization Test Setup CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9761 AD9761 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A ­5­ WARNING! ESD SENSITIVE DEVICE AD9761 AD9761 PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1 2­9 10 11 DB9 DB8­DB1 DB0 CLOCK 12 13 14 15 16 17 18 19 WRITE SELECT DVDD DCOM COMP3 QOUTA QOUTB REFLO 20 REFIO 21 22 23 24 25 26 27 28 FSADJ COMP2 AVDD ACOM IOUTB IOUTA COMP1 RESET/SLEEP Most Significant Data Bit (MSB). Data Bits 1-8. Least Significant Data Bit (LSB). Clock Input. Both DACs' outputs updated on positive edge of clock and digital filters read respective input registers. Write input. DAC input registers latched on positive edge of write. Select Input. Select high routes input data to I DAC, select low routes data to Q DAC. Digital Supply Voltage (+2.7 V to +5.5 V). Digital Common. Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor. Q DAC Current Output. Full-scale current when all data bits are 1s. Q DAC Complementary Current Output. Full-scale current when all data bits are 0s. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V reference output when internal reference activated. Requires 0.1 µF capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current. Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance. Analog Supply Voltage (+2.7 V to +5.5 V). Analog Common. I DAC Complementary Current Output. Full-scale current when all data bits are 0s. I DAC Current Output. Full-scale current when all data bits are 1s. Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1 µF capacitor. Power-Down control input if asserted for four clock cycles or longer. Reset control input if asserted for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/SLEEP section. PIN CONFIGURATION 28 RESET/SLEEP (MSB) DB9 1 DB8 2 27 COMP1 DB7 3 26 IOUTA DB6 4 25 IOUTB DB5 5 AD9761 AD9761 24 ACOM DB4 6 TOP VIEW 23 AVDD DB3 7 (Not to Scale) 22 COMP2 DB2 8 21 FSADJ DB1 9 20 REFIO (LSB) DB0 10 19 REFLO CLOCK 11 18 QOUTB WRITE 12 17 QOUTA SELECT 13 16 COMP3 DVDD 14 15 DCOM ­6­ REV. A AD9761 AD9761 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Channel Isolation Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Channel Isolation is a measure of the level of crosstalk between channels. It is measured by producing a full-scale 8 MHz signal output for one channel and measuring the leakage into the other channel. Differential Nonlinearity (or DNL) Spurious-Free Dynamic Range DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Monotonicity A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. THD is the ratio of the sum of the rms value of the first six harmonic components to the rms value of the measured output signal. It is expressed as a percentage or in decibels (dB). Offset Error Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. S/N+D is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Gain Error Effective Number of Bits (ENOB) The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, Output Compliance Range it is possible to get a measure of performance expressed as N, the effective number of bits. Total Harmonic Distortion N = (SINAD ­ 1.76)/6.02 The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Temperature Drift Passband Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either TMIN or TMAX . For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. Frequency band in which any input applied therein passes unattenuated to the DAC output. Stopband Rejection The amount of attenuation of a frequency outside the passband applied to the DAC, relative to a full-scale signal applied at the DAC input within the passband. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Group Delay Number of input clocks between an impulse applied at the device input and peak DAC output current. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Impulse Response Response of the device to an impulse applied to the input. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified the net area of the glitch in pV-s. REV. A ­7­ AD9761 AD9761 Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = +5 V, 50 Doubly Terminated Load, TA = +25C, fCLOCK = 40 MSPS, unless otherwise noted, worst of I or Q output performance shown) 65 0 10.5 80 9.67 75 ­10 DIFF ­6dBFS ­30 60 DIFF 0dBFS S/E 0dBFS S/E ­6dBFS dB ­50 ENOB ­40 dB 10dB ­ Div ­20 S/E 0dBFS ­60 55 ­70 8.84 DIFF ­6dBFS 70 ­80 S/E ­6dBFS DIFF 0dBFS ­90 50 ­100 START: 0Hz STOP: 40MHz Figure 4. Single-Tone SFDR (DC to 2 fDATA, f CLOCK = 2 fDATA) 0 2.0 4.0 6.0 fOUT ­ MHz 8.0 8.01 10.0 80 80 SFDR @ 40MSPS 40MSPS SFDR @ 40MSPS 40MSPS 75 SFDR @ 20MSPS 20MSPS 70 70 SFDR @ 20MSPS 20MSPS DIFF ­6dBFS 65 SFDR @ 10MSPS 10MSPS 65 SFDR @ 10MSPS 10MSPS 65 dB 60 dB DIFF 0dBFS dB 10.0 Figure 6. SFDR vs. f OUT (DC to f DATA/2) 75 70 5.0 fOUT ­ MHz Figure 5. SINAD (ENOBs) vs. fOUT (DC to fDATA/2) 75 65 0 55 60 60 55 50 50 S/E 0dBFS SINAD @ 40MSPS 40MSPS SINAD @ 20MSPS 20MSPS SINAD @ 10MSPS 10MSPS 45 55 40 S/E ­6dBFS 50 0 2.0 4.0 6.0 8.0 35 ­30 10.0 ­25 fOUT ­ MHz ­20 ­15 ­5 ­10 SINAD @ 40MSPS 40MSPS SINAD @ 20MSPS 20MSPS SINAD @ 10MSPS 10MSPS 45 40 35 ­30 ­0 ­25 ­20 AOUT ­ dBFS Figure 7. "Out-of-Band" SFDR vs. f OUT (fDATA/2 to 3/2 fDATA) Figure 8. SINAD vs. AOUT (DC to fDATA/2, Differential Output) SFDR @ 2.5mA ­10 ­5 0 Figure 9. SINAD vs. AOUT (DC to fDATA/2, Single-Ended Output) 80 80 ­15 AOUT ­ dBFS ­45 SFDR @ 5mA ­55 75 75 SFDR @ 10mA 70 70 dB dB SFDR @ 5mA 65 SFDR @ 2.5mA 65 SINAD @ 2.5mA SINAD @ 5mA SINAD @ 10mA ­95 SINAD @ 10mA 55 2 4 6 fOUT ­ MHz ­75 ­85 SINAD @ 5mA 60 0 ­65 SINAD @ 2.5mA 60 55 10dB ­ Div SFDR @ 10mA 8 10 Figure 10. SINAD/SFDR vs. I OUTFS (DC to fDATA/2, Differential Output) 0 2 4 6 fOUT ­ MHz 8 10 Figure 11. SINAD/SFDR vs. I OUTFS (DC to fDATA/2, Single-Ended Output) ­8­ ­105 START: 0Hz STOP: 20MHz Figure 12. Wideband SpreadSpectrum Spectral Plot (DC to fDATA) REV. A AD9761 AD9761 Typical AC Characterization Curves @ +3 V Supplies (AVDD = +3 V, DVDD = +3 V, 50 Doubly Terminated Load, TA = +25C, fCLOCK = 10 MSPS, unless otherwise noted, worst of I or Q output performance shown) 65 0 10.5 85 ­10 DIFF ­6dBFS 80 DIFF 0dBFS 9.67 75 ENOB S/E 0dBFS ­40 S/E ­6dBFS ­50 dB 60 ­30 dB 10dB ­ Div ­20 70 DIFF ­6dBFS 55 ­60 8.84 DIFF 0dBFS ­70 65 S/E ­6dBFS S/E 0dBFS ­80 ­90 50 START: 0Hz STOP: 10MHz Figure 13. Single-Tone SFDR (DC to 2 fDATA, f CLOCK = 2 fDATA) 0 0.5 1.0 1.5 fOUT ­ MHz 2.0 8.01 2.5 Figure 14. SINAD (ENOBs) vs. fOUT (DC to fDATA/2) 80 80 DIFF ­6dBFS 60 0 0.5 75 SFDR @ 20MSPS 20MSPS 2.5 SFDR @ 20MSPS 20MSPS 70 SFDR @ 10MSPS 10MSPS SFDR @ 10MSPS 10MSPS 65 70 S/E 0dBFS 2.0 Figure 15. SFDR vs. fOUT (DC to fDATA/2) 75 75 1.0 1.5 fOUT ­ MHz 60 65 SFDR @ 40MSPS 40MSPS S/E ­6dBFS dB 70 dB dB SFDR @ 40MSPS 40MSPS 60 55 55 45 45 65 50 50 DIFF 0dBFS 40 SINAD @ 40MSPS 40MSPS SINAD @ 20MSPS 20MSPS SINAD @ 10MSPS 10MSPS 40 60 0 0.5 1.0 1.5 fOUT ­ MHz 2.0 35 ­30 2.5 Figure 16. "Out-of-Band" SFDR vs. fOUT (f DATA/2 to 3/2fDATA) ­25 ­20 ­15 ­10 AOUT ­ dBFS 35 30 ­30 0 ­5 Figure 17. SINAD vs. AOUT (DC to fDATA/2, Differential Output) 80 ­25 ­20 ­15 ­10 AOUT ­ dBFS ­5 0 Figure 18. SINAD vs. AOUT (DC to fDATA/2, Single-Ended Output) 80 0 SFDR @ 10mA ­10 SFDR @ 5mA 75 SINAD @ 40MSPS 40MSPS SINAD @ 20MSPS 20MSPS SINAD @ 10MSPS 10MSPS 75 ­20 70 70 dB dB SFDR @ 2.5mA 10dB ­ Div SFDR @ 10mA SFDR @ 5mA SFDR @ 2.5mA 65 65 SINAD @ 2.5mA SINAD @ 5mA SINAD @ 10mA 60 SINAD @ 2.5mA SINAD @ 5mA SINAD @ 10mA ­30 ­40 ­50 ­60 60 ­70 55 0 2 4 6 fOUT ­ MHz 8 10 Figure 19. SINAD/SFDR vs. I OUTFS (DC to fDATA/2, Differential Output) REV. A 55 0 2 4 6 fOUT ­ MHz 8 10 Figure 20. SINAD/SFDR vs. I OUTFS (DC to fDATA/2, Single-Ended Output) ­9­ ­80 START: 0Hz STOP: 10MHz Figure 21. Narrowband SpreadSpectrum Spectral Plot (DC to f DATA) AD9761 AD9761 FUNCTIONAL DESCRIPTION four most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value are 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle-bits current sources. All of these current sources are switched to one or the other of two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. Figure 22 shows a simplified block diagram of the AD9761 AD9761. The AD9761 AD9761 is a complete dual channel, high speed, 10-bit CMOS DAC capable of operating up to a 40 MHz clock rate. It has been optimized for the transmit section of wideband communication systems employing I and Q modulation schemes. Excellent matching characteristics between channels reduces the need for any external calibration circuitry. Dual matching 2× interpolation filters included in the I and Q data path simplify any post, bandlimiting filter requirements. The AD9761 AD9761 interfaces with a single 10-bit digital input bus that supports interleaved I and Q input data. DCOM SLEEP CLOCK DVDD LATCH "I" ACOM AVDD IOUTA "I" DAC 2 IOUTB REFERENCE LATCH "Q" WRITE INPUT SELECT INPUT COMP1 COMP2 COMP3 QOUTA "Q" DAC 2 MUX CONTROL The I and Q DACs are simultaneously updated on the rising edge of CLOCK with digital data from their respective 2× digital interpolation filters. The 2× interpolation filters essentially multiplies the input data rate of each DAC by a factor of two, relative to its original input data rate while simultaneously reducing the magnitude of first image associated with the DAC's original input data rate. Since the AD9761 AD9761 supports a single 10-bit digital bus with interleaved I and Q input data, the original I and Q input data rate before interpolation is one-half the CLOCK rate. After interpolation, the data rate into each I and Q DAC becomes equal to the CLOCK rate. REFLO FSADJ REFIO BIAS GENERATOR DAC DATA INPUTS (10 BITS) The full-scale output current, IOUTFS, of each DAC is regulated from the same voltage reference and control amplifier, thus ensuring excellent gain matching and drift characteristics between DACs. IOUTFS can be set from 1 mA to 10 mA via an external resistor, RSET . The external resistor in combination with both the reference control amplifier and voltage reference, VREFIO, sets the reference current, IREF, which is mirrored over to the segmented current sources with the proper scaling factor. IOUTFS is exactly sixteen times the value of IREF. QOUTB AD9761 AD9761 Figure 22. Dual DAC Functional Block Diagram The benefits of an interpolation filter are clearly seen in Figure 23, which shows an example of the frequency and time domain representation of a discrete time sine wave signal before and after it is applied to a digital interpolation filter. Images of the sine wave signal appear around multiples of the DAC's input data rate as predicted by the sampling theory. These undesirable images will also appear at the output of a reconstruction DAC, although modified by the DAC's sin(x)/(x) response. In many bandlimited applications, these images must be suppressed by an analog filter following the DAC. The complexity of this analog filter is typically determined by the proximity of the desired fundamental to the first image and the required amount of image suppression. Referring to Figure 22, the AD9761 AD9761 consists of an analog section and a digital section. The analog section includes matched I and Q 10-bit DACs, a 1.20 V bandgap voltage reference and a reference control amplifier. The digital section includes: two 2× interpolation filters; segment decoding logic; and some additional digital input interface circuitry. The analog and digital sections of the AD9761 AD9761 have separate power supply inputs (i.e., AVDD and DVDD) that can operate over a 2.7 V to 5.5 V range. Each DAC consists of a large PMOS current source array capable of providing up to 10 mA of full-scale current, IOUTFS. Each array is divided into 15 equal currents that make up the TIME DOMAIN 2 1 fCLOCK fCLOCK FUNDAMENTAL 1ST IMAGE FUNDAMENTAL DIGITAL FILTER DACs "NEW" 1ST IMAGE "SINX" X FREQUENCY DOMAIN fCLOCK fCLOCK 2 INPUT DATA LATCH SUPPRESSED "OLD" 1ST IMAGE fCLOCK fCLOCK 2 2x INTERPOLATION FILTER fCLOCK fCLOCK 2 DAC 2x fCLOCK fCLOCK 2 Figure 23. Time and Frequency Domain Example of Digital Interpolation Filter ­10­ REV. A AD9761 AD9761 Referring to Figure 23, the "new" first image associated with the DAC's higher data rate after interpolation is "pushed" out further relative to the input signal. The "old" first image associated with the lower DAC data rate before interpolation is suppressed by the digital filter. As a result, the transition band for the analog reconstruction filter is increased thus reducing the complexity of the analog filter. Note, the full-scale value of VIOUTA and VIOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. The digital interpolation filters for I and Q paths are identical 43 tap halfband symmetric FIR filters. Each filter receives deinterleaved I or Q data from the digital input interface. The input CLOCK signal is internally divided by two to generate the filter clock. The filters are implemented with two parallel paths running at the filter clock rate. The output from each path is selected on opposite phases of the filter clock, thus producing interpolated filtered output data at the input clock rate. The frequency response and impulse response of these filters are shown in Figures 2a and 2b. Table I lists the idealized filter coefficients that correspond to the filter's impulse response. Substituting the values of IIOUTA, I IOUTB, and IREF; VIDIFF can be expressed as: The digital section of the AD9761 AD9761 also includes an input interface section designed to support interleaved I and Q input data from a single 10-bit bus. This section de-interleaves the I and Q input data while ensuring its proper pairing for the 2× interpolation filters. A SLEEP/RESET input serves a dual function by providing a reset function for this section as well as providing power down functionality. Refer to the DIGITAL INPUT AND INTERFACE CONSIDERATIONS and SLEEP/RESET sections for a more detailed discussion. VIDIFF =(IIOUTA ­ IIOUTB) × RLOAD Each I and Q DAC provides complementary current output pins: IOUT(A/B) and QOUT(A/B) respectively. Note, QOUTA and QOUTB operate identically to IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 1023) while IOUTB, the complementary output, provides no current. The current output of IOUTA and IOUTB are a function of both the input code and IOUTFS and can be expressed as: VIDIFF ={(2 DAC CODE ­ 1023)/1024)} × (16 R LOAD/R SET) × VREFIO The AD9761 AD9761 contains an internal 1.20 V bandgap reference which can be easily disabled and overridden by an external reference. REFIO serves as either an input or output depending on whether the internal or an external reference is selected. If REFLO is tied to ACOM as shown in Figure 24, the internal reference is activated and REFIO provides a 1.20 V output. In this case, the internal reference must be filtered externally with a ceramic chip capacitor of 0.1 µF or greater from REFIO to REFLO. Also, REFIO should be buffered with an external amplifier having a low input bias current (i.e.,