AD9748 AD9748ACP CP-32 AD9748ACP-PCB EIA/JESD51-7 AWG2021 FSEA30 AWG-2021

TxDAC D/A Converter AD9748* ® FEATURES High Performance Member of Pin Compatible TxDAC Product Family Linearity: 0.1 LSB DNL

8-Bit, 165 MSPS TxDAC D/A Converter AD9748 AD9748* ® FEATURES High Performance Member of Pin Compatible TxDAC Product Family Linearity: 0.1 LSB DNL 0.1 LSB INL Twos Complement or Straight Binary Data Format Differential Current Outputs: 2 mA to 20 mA SINAD @ 5 MHz Output: 50 dB Power Dissipation: 135 mW @ 3.3 V Power-Down Mode: 15 mW @ 3.3 V On-Chip 1.20 V Reference CMOS Compatible Digital Interface 32-Lead LFCSP Edge-Triggered Latches Fast Settling: 11 ns to 0.1% Full Scale FUNCTIONAL BLOCK DIAGRAM 3.3V AVDD 150pF 0.1F REFIO CURRENT SOURCE ARRAY FS ADJ RSET 3.3V AD9748 AD9748 DVDD DCOM IOUTA SEGMENTED SWITCHES CLK CLK LSB SWITCHES LATCHES 3.3V ACOM +1.20V REF IOUTB MODE CMODE CLKVDD CLKCOM SLEEP DIGITAL DATA INPUTS (DB7DB0) APPLICATIONS Communications Direct Digital Synthesis (DDS) Instrumentation GENERAL DESCRIPTION The AD9748 AD9748 is an 8-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9748 AD9748 offers exceptional ac and dc performance while supporting update rates up to 165 MSPS. The AD9748 AD9748's low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families. PRODUCT HIGHLIGHTS 1. 32-lead LFCSP package. 2. The AD9748 AD9748 is the 8-bit member of the pin compatible TxDAC family, which offers excellent INL and DNL performance. 3. Differential or single-ended clock input (LVPECL or CMOS), supports 165 MSPS conversion rate. 4. Data input supports twos complement or straight binary data coding. 5. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 6. On-chip voltage reference: The AD9748 AD9748 includes a 1.2 V temperature-compensated band gap voltage reference. *Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD9748 AD9748SPECIFICATIONS DC SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.) Parameter Min RESOLUTION Typ Max 8 Unit Bits 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current 3 REFERENCE INPUT Input Compliance Range Reference Input Resistance (External Reference) Small Signal Bandwidth ± 0.25 ± 0.25 ± 0.25 ± 0.25 LSB LSB +0.02 +0.5 +0.5 20.0 +1.25 % of FSR % of FSR % of FSR mA V kW pF 1.26 V nA 1.25 1 0.5 V MW MHz 0 ± 50 ± 100 ± 50 0.02 0.5 0.5 2.0 1.0 ± 0.1 ± 0.1 ppm of FSR/C ppm of FSR/C ppm of FSR/C ppm/C ± 0.1 ± 0.1 100 5 1.14 1.20 100 0.1 TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD CLKVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)4 Clock Supply Current (ICLKDVDD) Supply Current Sleep Mode (IAVDD) Power Dissipation4 Power Dissipation5 Power Supply Rejection Ratio-AVDD6 Power Supply Rejection Ratio-DVDD6 1 0.04 +1 +0.04 V V V mA mA mA mA mW mW % of FSR/V % of FSR/V OPERATING RANGE 40 +85 C 2.7 2.7 2.7 3.3 3.3 3.3 33 8 5 5 135 145 3.6 3.6 3.6 36 9 7 6 145 NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 times the I REF current. 3 An external buffer amplifier with an input bias current