AD9549 OC-192 AD9514 AVDD31600 AVDD3800 AVDD3400 192FSC R040F - Datasheet Archive

 

Generator/Synchronizer AD9549 Preliminary Technical Data FEATURES APPLICATIONS Flexible Reference Inputs Input frequencies 8 kHz

 

Dual Input Network Clock Generator/Synchronizer AD9549 AD9549 Preliminary Technical Data FEATURES APPLICATIONS Flexible Reference Inputs Input frequencies 8 kHz to 750 MHz Two reference inputs Loss of Reference indicators Auto and Manual Holdover modes Auto and Manual Switchover modes Smooth A to B phase transition on outputs Excellent stability in holdover mode Programmable 16+1-bit Input Divider, R Differential HSTL Clock Output Output frequencies to 750 MHz Low Jitter clock doubler for frequencies > 400 MHz Single-ended CMOS output; frequencies < 50MHz Programmable Digital Loop Filter (< 1 Hz to ~100 kHz) High Speed Digitally Controlled Oscillator (DCO) core DDS with integrated 14 bit DAC Excellent Dynamic Performance Programmable 16+1-bit Feedback Divider, S Software controlled power-down 64-lead LFCSP package Network Synchronization Reference Clock Jitter Cleanup SONET/SDH Clocks up to OC-192 OC-192, Including FEC Stratum 3/3E Reference Clocks Wireless Base Stations, Controllers Cable Infrastructure Data Communications GENERAL DESCRIPTION The AD9549 AD9549 provides synchronization for many systems including synchronous optical networks (SONET/SDH). The AD9549 AD9549 generates an output clock, synchronized to one of two external input references. The external references may contain significant time jitter, also specified as phase noise. Using a digitally controlled loop and holdover circuitry, the AD9549 AD9549 continues to generate a clean (low jitter), valid output clock during a `loss of reference' condition, even when both references have failed. The AD9549 AD9549 operates over an industrial temperature range, spanning -40°C to +85°C. Figure 1: Basic Block Diagram Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD9549 AD9549 Preliminary Technical Data SAMPLE APPLICATION CIRCUIT Figure 2: AD9549 AD9549 + AD9514 AD9514 Precision Clock Distribution Circuit Features: Input Frequencies Down to 8 kHz. Output Frequencies Up to 400 MHz. Programmable Loop Bandwidth Down to < 1 Hz Automatic Redundant Clock Switchover with User Selectable Rate of Phase Adjustment. Automatic Stratum 2/3/3E Clock Holdover, Depending on Configuration. Phase Noise (Fc=122.3 MHz & 100 Hz loop BW): 100 Hz offset: -107 dBc/Hz. 1 KHz offset: -142 dBc/Hz. 100 kHz offset: -157 dBc/Hz. Two Zero-delay Outputs with Programmable Post-Divider and Synchronization. Two Additional Outputs (non-zero delay) on AD9549 AD9549. Programmable Skew Adjustment on One AD9514 AD9514 Output. Rev. PrA | Page 2 of 78 Preliminary Technical Data AD9549 AD9549 TABLE OF CONTENTS Features.1 Phase Lock Detection.31 Applications .1 Frequency Lock Detection .32 General Description.1 Reference Monitors .33 Sample Application Circuit.2 Loss of Reference .33 DC Specifications .5 Reference Frequency Monitor.33 AC Specifications .7 Reference Switchover .34 Typical Performance Characteristics .13 Use of Line Card Mode to Eliminate Runt Pulses.35 Absolute Maximum Ratings .17 Holdover .36 ESD Caution .17 Holdover Control.36 Pin Configuration and Function Descriptions .18 Holdover & Reference Switchover State Machine.36 Input / Output Termination Recommendations.21 Reference Recovery Timers.37 Theory of Operation .22 Holdover Operation .38 Overview .22 Holdover Sampler and Averager.39 PLL Core (DPLLC) .23 Output Frequency Range Control .39 Feedforward Divider (Divide-by-R).23 Reconstruction Filter.39 Feedback Divider (Divide-by-S) .23 Use of Narrowband Filter for High Performance.40 Forward and Reverse FEC Clock Scaling .24 FDBK Inputs.41 Phase Detector.24 Reference Inputs .41 Digital Loop Filter.24 Reference Clock Receiver .41 Direct Digital Synthesizer .26 SysClk Inputs.42 DAC Output.27 Functional Description .42 Phase Detector.27 Bipolar Edge Detector .42 Coarse Phase Detector .27 SysClk PLL Multiplier .42 Fine Phase Detector.27 External Loop Filter (SysClk PLL) .43 Phase Detector Gain Matching .28 Detail of SysClk Differential Inputs .43 Phase Detector Pin Connections .28 Harmonic Spur Reduction.45 Digital Loop Filter Coefficients .28 Output Clock Drivers & 2x frequency Multiplier .46 Closed Loop Phase Offset.30 Primary 1.8V Differential HSTL Driver.46 Lock Detection .31 2x Frequency Multiplier.46 Rev. PrA | Page 3 of 78 AD9549 AD9549 Preliminary Technical Data Single-Ended CMOS Output. 46 Read . 54 Frequency Slew Limiter. 46 The Instruction Word (16 Bits). 54 Frequency Estimator. 47 MSB/LSB First Transfers . 54 Status and Warnings . 48 I/O Register Map . 58 1 Status Pins . 48 Types of Registers:. 65 Reference Monitor Status . 49 I/O Register Description . 66 Default DDS Output Frequency on Power-Up . 49 Serial Port Configuration (0000 ­ 0005). 66 Interrupt Request (IRQ). 49 Power Down and Reset . 66 Power-On Reset. 51 System Clock. 67 AD9549 AD9549 Power Up and Programming Sequence. 51 Digital PLL Control and Dividers. 68 Power Management. 52 Digital PLL Loop Filter. 69 3.3V Supplies. 52 Free-Run (Single-Tone) Mode. 70 1.8V Supplies. 52 Reference Selector / Holdover . 70 Serial Control Port. 53 Doubler and Output Drivers . 71 Serial Control Port Pin Descriptions. 53 Monitor. 72 Operation of Serial Control Port. 53 Calibration (User Accessible Trim) . 75 Framing a Communication Cycle with CSB . 53 Harmonic Spur Reduction. 77 Communication Cycle-Instruction Plus Data . 53 Outline Dimensions . 78 Write. 53 Ordering Guide. 78 Rev. PrA | Page 4 of 78 Preliminary Technical Data AD9549 AD9549 DC SPECIFICATIONS Unless otherwise noted, AVDD=1.8±5%, AVDD3=3.3±5%, DVDD=1.8±5%, DVDD_I/O=3.3±5%. Table 1. Parameter SUPPLY VOLTAGE DVDD_I/O (pin 1) DVDD (pin 3, 5, 7) AVDD3 (pin 14, 46, 47, 49) AVDD3 (pin 37) AVDD (pin 11,19, 23-26,29,30,36,42,44,45,53) SUPPLY CURRENT I-AVDD3 (pin 14) I-AVDD3 (pin 37) I-AVDD3 (pin 46, 47, 49) I-AVDD (pin 36) I-AVDD (pin 42) I-AVDD (pin 11) I-AVDD (pin 19, 23-26, 29, 30, 44, 45) I-AVDD (pin 53) I-DVDD (pin 3, 5, 7) I-DVDD_I/O (pin 1) LOGIC INPUTS (Except Pin 32) Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IINH, IINL) Maximum Input Capacitance (CIN) CLKMODESEL (Pin 32) LOGIC INPUT Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IINH, IINL) Maximum Input Capacitance (CIN) LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) REFERENCE INPUTS Input Capacitance Input Resistance Common Mode Input Voltage1 Differential Input Voltage Swing1 Input Voltage High (VIH) Input Voltage Low (VIL) Input Current Internal Bias Voltage FDBK INPUT Input Capacitance Input Resistance Common Mode Input Voltage2 Differential Input Voltage Swing2 Min Typ Max Unit 3.135 1.71 3.135 1.71 1.71 3.30 1.80 3.30 3.30 1.80 3.465 1.89 3.465 3.465 1.89 V V V V V 6 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA mA mA mA mA mA mA mA 0.8 ±100 V V µA pF 0.4 ±100 V V µA pF 25 8 10 10 170 35 200 3 2.0 ±30 3 Test Conditions/Comments (with respect to DVSS) (with respect to DVSS) (with respect to AVSS) (with respect to AVSS) (with respect to AVSS) REFA, REFB Buffers CMOS Output Clock Driver at 3.3V DAC output current source HSTL Output Clock Driver FDBK SYSCLK aggregate analog supply DAC Power Supply Digital Core Digital I/O (varies dynamically) Pins 56-61, 64, 9, 10, 54, 55, 63 At Vin=0V and Vin=DVDD_I/O Pin 32 only. 1.4 ±30 3 2.7 0.4 3 16 AVDD31600 AVDD31600 AVDD3800 AVDD3800 AVDD3400 AVDD3400 V V pF K V mV V V mA mV At Vin=0V and Vin=DVDD_I/O Pin 62, & bi-dir. pins 9, 10, 54, 55, 63 IOH = 1 mA w/ VOH =DVDD_I/O-0.4V IOL = 1mA w/ VOL =0.4V Pins 12, 13, 15, 16 Differential at Vbias=AVDD3-800mV differential operation differential operation single-ended operation single-ended operation single-ended operation programmable (see text) Pins 40, 41 3 30 Rev. PrA | Page 5 of 78 pF K V mV Differential differential operation differential operation AD9549 AD9549 SYSTEM CLOCK INPUT SYSCLK PLL BYPASSED Input Capacitance (DC) Input Impedance (DC) Common Mode Input Voltage3 Differential Input Voltage Swing3 Input Voltage High (VIH) Input Voltage Low (VIL) Input Current SYSCLK PLL ENABLED Input Capacitance (DC) Input Impedance (DC) Common Mode Input Voltage3 Differential Input Voltage Swing3 Input Voltage High (VIH) Input Voltage Low (VIL) Input Current CRYSTAL RESONATOR WITH SYSCLK PLL ENABLED Motional Resistance CLOCK OUTPUT DRIVERS HSTL OUTPUT DRIVER Differential Output Voltage Swing4 Common Mode Output Voltage4 Continuous Output Current CMOS OUTPUT DRIVER Output Voltage High (VOH) Output Voltage Low (VOL) Output High Current (IOH) Output Low Current (IOL) TOTAL POWER DISSIPATION All Blocks Running Power-Down Mode Preliminary Technical Data 1.5 1 pF K single-ended, each pin differential differential operation differential operation single-ended operation single-ended operation single-ended operation 3 2 pF K single-ended, each pin differential differential operation differential operation single-ended operation single-ended operation single-ended operation k TBD 700 mV TBD 0.9 7.2 V mA 0.4 V V µA µA TBD TBD TBD TBD mW mW Default with SysClk PLL Enabled TBD TBD mW Default with SysClk PLL Disabled TBD TBD mW TBD TBD TBD TBD TBD mW mW mW mW mW - with Digital Power Down - with REFA or REFB Power Down - with HSTL Clock Driver Power Down - with CMOS Clock Driver Power Down - with HSTL 2x Freq. Multiplier Power Down Must be 0V relative to AVDD3 (pin 14) and 0V relative to AVSS (pins 33, 43). Must be 0V relative to AVDD (pin 42) and 0V relative to AVSS (pins 33, 43). Relative to AVSS (pins 33, 43). 4 Must be 0V relative to AVDD (pin 36) and 0V relative to AVSS (pins 33, 43). 5 See "Power Management" Section for details about power profiles. 1 2 3 Rev. PrA | Page 6 of 78 Both pins AC-coupled using 0.01uF, then 50 to GND, TBD Using either the Power Down Register or PWRDOWN pin. After reset or power up with fS=1GHz, S4=0, S1-S3=1, fSYSCLK=25MHz After reset or power up with fS=1GHz, S4-S4=1, & Sysclk PLL powered down. One reference still powered up. Preliminary Technical Data AD9549 AD9549 AC SPECIFICATIONS Unless otherwise noted: fS=1GHz. DAC RSET=10K. Power supply pins within the range specified in "DC SPECIFICATIONS." Table 2. Parameter REFERENCE INPUTS Frequency Range Minimum Slew Rate Minimum Pulse Width High Minimum Pulse Width Low FDBK INPUT Input Frequency Range Min Typ Unit 750 .008 Max MHz V/ns ps ps MHz Minimum Slew Rate Minimum Differential Input Level SYSTEM CLOCK INPUT SYSCLK PLL BYPASSED Input Frequency Range Minimum Pulse Width High Minimum Pulse Width Low Minimum Differential Input Level SYSCLK PLL ENABLED VCO Frequency Range ­ Low Band VCO Frequency Range ­ High Band Maximum Input Rate of PFD Without Bipolar Edge Detector Input Frequency Range Multiplication Range Minimum Pulse Width High Minimum Pulse Width Low Minimum Differential Input Level With Bipolar Edge Detector Input Frequency Range Multiplication Range Input Duty Cycle Minimum Differential Input Level CRYSTAL RESONATOR WITH SYSCLK PLL ENABLED Crystal Resonator Frequency Range Maximum Crystal Motional Resistance V/ns V TBD 1000 MHz ps ps V 700 800 850 1000 100 TBD 66 Pins 40, 41 sinusoidal (without degrading phase noise performance) peak-to-peak (xxxdBm into 50) Pins 27, 28 peak-to-peak (xxxdBm into 50) MHz MHz MHz TBD 8 Test Conditions/Comments Pins 12, 13, 15, 16 MHz integer multiples of 2 ps ps V TBD 16 TBD 132 MHz integer multiples of 4 % V 10 40+ TBD Rev. PrA | Page 7 of 78 peak-to-peak (xxxdBm into 50) MHz peak-to-peak (xxxdBm into 50) fundamental mode resonator see text for recommendations AD9549 AD9549 CLOCK DRIVERS HSTL OUTPUT DRIVER Toggle Rate Output Duty Cycle Output Rise/Fall Time JITTER HSTL OUTPUT DRIVER WITH 2X MULTIPLIER Output Frequency Range Duty Cycle Sub-harmonic Spur Level JITTER CMOS OUTPUT DRIVER (AVDD3/PIN 37) @3.3V Toggle Rate Duty Cycle Output Rise/Fall Time JITTER CMOS OUTPUT DRIVER AT (AVDD3/PIN 37) @1.8V Toggle Rate Duty Cycle Output Rise/Fall Time JITTER HOLDOVER Frequency Accuracy (XTAL) Variation Over Temperature range Variation Over Supply range Frequency Accuracy (TCXO) Variation Over Temperature range Variation Over Supply range OUTPUT FREQUENCY SLEW LIMITER Slew Rate Resolution Slew Rate Range REFERENCE MONITORS LOSS OF REFERENCE MONITOR Operating Frequency Range Minimum Frequency Error for Continuous "REF" Present" Indication Minimum Frequency Error for Continuous "REF" Present" Indication Maximum Frequency Error for Continuous "REF Lost" Indication Maximum Frequency Error for Continuous "REF Lost" Indication REFERENCE QUALITY MONITOR Operating Frequency Range Frequency Resolution (normalized) Frequency Resolution (normalized) Preliminary Technical Data TBD 48 725 52 TBD 0.6 TBD 45 TBD 55 -35 55 100 60 MHz % ps ps 100 terminated, 5pF load Fin=25 MHz, Fout=200 MHz MHz % dBc without correction MHz % ps see plot for maximum toggle rate Fin=25 MHz, Fout=200 MHz see plot for maximum toggle rate With 20pF load and up to 50 MHz Fin=25 MHz, Fout=50 MHz 55 50 60 MHz % ps see plot for maximum toggle rate With 20pF load and up to 50 MHz Fin=25 MHz, Fout=50 MHz xxxMHz, xxxppm crystal resonator at SYSCLK pins ppm/oC ppm/V TCXO at SYSCLK pins 0 0 ppm/oC ppm/V 0.54 0 111 3x1016 Hz/sec Hz/sec 7.63x103 167x106 -16 Hz ppm -19 % -32 ppm -35 % 0.001 16 ppm 0.002 44.9 % VALIDATION TIMER Rev. PrA | Page 8 of 78 P=216 for minimum; P=25 for maximum P=216 for minimum; P=25 for maximum fREF= 8 kHz fREF= 155 MHz fREF= 8 kHz fREF= 155 MHz fREF= 8 kHz; M=15 for minimum; M=1 for maximum (see text) fREF= 155 MHz; M=15 for minimum; M=1 for maximum (see text) Preliminary Technical Data Timing range Timing range AD9549 AD9549 32x10-9 65x10-6 137 2.8x105 Rev. PrA | Page 9 of 78 s s PIO= 5 (see text) PIO= 16 (see text) AD9549 AD9549 DAC OUTPUT CHARACTERISTICS DCO Frequency range (1st Nyquist zone) Output Resistance Output Capacitance Full-Scale Output Current Gain Error Output Offset Voltage Compliance Range Preliminary Technical Data 10 450 50 5 10 TBD AVSS -0.50 +0.5V 31.7 TBD 0.6 AVSS +0.50 MHz pF mA %FS µA DPLL loop bandwidth sets lower limit single-ended (each pin internally terminated to AVSS) range depends on DAC RSET resistor Outputs not DC shorted to Vss Wideband SFDR (DC to Nyquist): SFDR may be improved by activating Harmonic Spur Suppression (see text) 10MHz Analog Out 40MHz Analog Out 80MHz Analog Out 120MHz Analog Out 160MHz Analog Out Narrowband SFDR 10 MHz Analog Out (±1 MHz) 40 MHz Analog Out (±1 MHz) 80 MHz Analog Out (±1 MHz) 120 MHz Analog Out (±1 MHz) 160 MHz Analog Out (±1 MHz) DIGITAL PLL Minimum open-loop bandwidth TBD TBD TBD TBD TBD dBc dBc dBc dBc dBc TBD TBD TBD TBD TBD dBc dBc dBc dBc dBc 0.0001 kHz Maximum open-loop bandwidth 100 kHz Minimum phase margin 10 degrees Maximum phase margin 85 degrees PFD input frequency range Feedforward divider ratio Feedback divider ratio LOCK DETECTION PHASE LOCK DETECTOR Time Threshold Programming Range Time Threshold Resolution Lock Time Programming Range Unlock Time Programming Range FREQUENCY LOCK DETECTOR Normalized Frequency Threshold Programming Range Normalized Frequency Threshold ~0.008 1 1 ~24.5 131,070 131,070 MHz 2097 0 µs ps s ms dependent on the frequency of REFA/B, the DAC sample rate, and the P, R, and S divider values dependent on the frequency of REFA/B, the DAC sample rate, and the P, R, and S divider values dependent on the frequency of REFA/B, the DAC sample rate, and the P, R, and S divider values (not a hard limit but bounded by 0°) dependent on the frequency of REFA/B, the DAC sample rate, and the P, R, and S divider values (not a hard limit but bounded by 90°) 0.488 32x10-9 64x10-6 68.7 16.8 0 0.0021 5x10-13 Rev. PrA | Page 10 of 78 1,2,.,65,535 or 2,4,.,131,070 1,2,.,65,535 or 2,4,.,131,070 FPFD_Gain=200 FPFD_Gain=200 in power-of-2 steps in power-of-2 steps FPFD_Gain=200; normalized to (fREF/R)2; see text for details FPFD_Gain=200; normalized to (fREF/R)2; Preliminary Technical Data Programming Resolution Lock Time Programming Range Unlock Time Programming Range AD9549 AD9549 32x10-9 64x10-6 68.7 16.8 Rev. PrA | Page 11 of 78 s ms see text for details in power-of-2 steps in power-of-2 steps AD9549 AD9549 Preliminary Technical Data DIGITAL TIMING SPECIFICATIONS Time Required to Enter Power Down Time Req'd to Recover from Power Down S0-4 Config Setup Time During Reset ns ns ns S0-4 Config Hold Time During Reset ns Reset assert to S0-4 High-Z Time ns Reset deassert to S0-4 Low-Z time ns CS to SCLK Setup Time Period of SCLK TDSU (Serial Data Setup Time) TDHD (Serial Data Hold Time) TDV (Data Valid Time) PROPAGATION DELAY FDBK to HSTL Output Driver FDBK to HSTL Output Driver with 2x Frequency Multiplier Enabled FDBK to HSTL Output Driver with 2x Frequency Multiplier Enabled FDBK to CMOS Output Driver FDBK through S-Divider to CMOS Output Driver TBD 10 TBD TBD TBD ns ns ns ns ns Rev. PrA | Page 12 of 78 Time S0-4 must be present before falling edge of signal on RESET pin. Time S0-4 must be held after falling edge of signal on RESET pin. Time from rising edge of RESET to High Z on S0-4 configuration pins. Time from falling edge of RESET to Low-Z on S0-4 configuration pins. Preliminary Technical Data AD9549 AD9549 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted: AVDD, AVDD3, and DVDD at nominal supply voltage; fS= 1 GHz, DAC RSET= 10k. Plot 1: Additive Phase Noise at HSTL Output Driver. Sysclk=1 GHz (SysClk PLL Bypassed). Ref=19.44 MHz., Fout=311.04 MHz. DPLL loop BW= 1 kHz. Plot 2: Additive Phase Noise at HSTL Output Driver. Sysclk=1 GHz (SysClk PLL Bypassed). Ref=19.44 MHz., Fout=622.08 MHz, DPLL loop BW= 1 kHz. HSTL Output Doubler Enabled Rev. PrA | Page 13 of 78 AD9549 AD9549 Preliminary Technical Data Plot 3: Additive Phase Noise at HSTL Output Driver. Sysclk = 1 GHz (SysClk PLL Enabled and driven by 25 MHz Wenzel Oscillator.) Ref=19.44 MHz., Fout=311.04 MHz, DPLL loop BW= 1 kHz. Plot 5: Additive Phase Noise at HSTL Output Driver. Sysclk = 1 GHz. (Sysclk PLL enabled and driven with 25MHz Wenzel Oscillator.) Fin=19.44 MHz, Fout=155.52 MHz. DPLL loop BW=1 kHz Plot 4: Additive Phase Noise at HSTL Output Driver. Sysclk= 1 GHz (SysClk PLL Enabled and driven by 25 MHz Wenzel Oscillator.). Ref=19.44 MHz., Fout=622.08 MHz, DPLL loop BW= 1 kHz. HSTL Doubler Enabled. Rev. PrA | Page 14 of 78 Plot 6: Additive Phase Noise at HSTL Output Driver. Sysclk = 500 MHz. Sysclk PLL disabled. Fin=8 kHz, Fout= 155.52 MHz. DPLL loop BW= 400 Hz. Preliminary Technical Data AD9549 AD9549 Plot 7: Additive Phase Noise at HSTL Output Driver. Sysclk = 1 GHz. (Sysclk PLL enabled and driven with 25MHz Fox Crystal Oscillator.) Fin=19.44 MHz, Fout=155.52 MHz. DPLL loop BW=1 kHz. Plot 9: SFDR vs Fout at Sysclk = 1GHz with and w/o recon filter. Fcut = Fout * 1.2 Plot 10: HSTL Output Amplitude vs. Toggle Rate (100 ohms across differential pair.,) Plot 8: Additive Phase Noise at CMOS Output Driver. Sysclk= 500 MHz. Sysclk PLL disabled. Fin=10.24 MHz, Fout=10.24 MHz. DPLL loop BW=1 kHz Rev. PrA | Page 15 of 78 AD9549 AD9549 Preliminary Technical Data AD9549 AD9549 CMOS 1.8V Driver w/ 20pF Load: Amplitude vs. Frequency Loaded with 20k Ohm Scope Probe 2.5 P k -P k ( V o lt s ) 2.0 1.5 1.0 Nom Skew 25ºC 1.8V Supply DUT 2 (20pF) 0.5 Slow Skew 90ºC 1.7V Supply DUT 3 (20pF) 0.0 0 20 40 60 80 100 Output Frequency (MHz) Plot 12: CMOS Output Driver Amplitude vs. Toggle Rate (AVDD3 = 3.3V). Plot 11: CMOS Output Driver Amplitude vs. Toggle Rate (AVDD3 = 1.8 V) with 20 pF Load. Rev. PrA | Page 16 of 78 Preliminary Technical Data AD9549 AD9549 ABSOLUTE MAXIMUM RATINGS Table 1. Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD_I/0) DAC Supply Voltage (DAC_VDD) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature 1 Thermal Resistance (JA) ESD CAUTION Rating 2V 2V 3.6 V 3.6 V -0.5 V to DVDD_I/O + 0.5 V -65°C to +150°C -40°C to +85°C 300°C 150°C 26°C/W typ. ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulates on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 The exposed pad on bottom of package must be soldered to ground in order to achieve the specified thermal performance. Rev. PrA | Page 17 of 78 AD9549 AD9549 Preliminary Technical Data SCLK SDIO SDO CSB IO_UPDATE RESET PWRDOWN HOLDOVER REFSELECT S4 S3 AVDD AVSS IOUTB IOUT AVDD3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD_I/O DVSS DVDD DVSS DVDD DVSS DVDD DVSS S1 S2 AVDD REFA_IN REFA_INB AVDD3 REFB_IN REFB_INB N/C N/C AVDD PFD_VRB PFD_VRT PFD_RSET AVDD AVDD AVDD AVDD SYSCLK SYSCLKB AVDD AVDD LOOP_FILTER CLKMODESEL DAC_RSET AVDD3 AVDD3 AVDD N/C AVSS AVDD FDBK_IN FDBK_INB AVSS OUT_CMOS AVDD3 AVDD OUT OUTB AVSS Figure 3: 64-Lead LFCSP Pin Configuration Table 2: Pin Function Descriptions Pin No. 1 2, 4, 6, 8 3, 5, 7 9, 10, 54, 55 11, 19, 2326, 29, 30, 36, 42, 45, 53 Input/ Output I I I I/O I Pin Type Power Power Power 3.3V CMOS Power Mnemonic Description DVDD_I/O DVSS DVDD S1, S2, S3, S4 I/O Digital Supply Digital Ground: Connect to Ground Digital Supply Configurable I/O pins: These pins are configured under program control (see "Status and Warnings" on Page 48. Analog Supply: Connect to a nominal 1.8V Supply AVDD Rev. PrA | Page 18 of 78 Preliminary Technical Data 12 I 13 I 14, 37, 46, 47, 49 15 I I REFB_IN 16 I REFB_INB 22 O N/C PFD_VRB, PFD_VRT PFD_RSET 27 28 31 I I 32 I 1.8V CMOS CLKMODESEL 33, 39, 43, 52 34 I GND AVSS O OUTB 35 O 38 O 1.8V HSTL 1.8V HSTL 3.3V CMOS 40 Diff Input Diff Input Power 17, 18 20, 21 I set Res REFA_IN REFA_INB AVDD3 SYSCLK SYSCLKB LOOP_FILTER AD9549 AD9549 Frequency/Phase Reference A Input. This internally biased input is typically AC-coupled, and when configured as such, can accept any differential signal. Complementary Frequency/Phase Reference A Input: Complementary signal to the input provided on pin 12 Analog Supply: Connect to a nominal 3.3V supply Frequency/Phase Reference B Input. This internally biased input is typically AC-coupled, and when configured as such, can accept any differential signal whose single-ended swing is between 0.4 and 3.3V. Complementary Frequency/Phase Reference B Input: Complementary signal to the input provided on pin 15 No Connects: These are excess, unused pins that may be left floating These pins must be capacitively decoupled. See the Phase Detector Pin Connections section for details. Connect a 5k resistor from this pin to Ground (see the Phase Detector Pin Connections section). System Clock Input Complementary System Clock: Complementary signal to the input provided on pin 27 System Clock Multiplier Loop Filter: When using the frequency multiplier to drive the System Clock, an external loop filter must be constructed and attached to this pin. Clock Mode Select. Set to GND when using a crystal. Pull up to 1.8V when using either an oscillator or external clock source. (See the SysClk Inputs section for details on the use of this pin). Analog Ground: Connect to Ground. NOTE: Pin 43 is a ground shield connection. OUT Complementary HSTL Output: See spec table and the OUTPUT DRIVERS AND MULTIPLIER section, under sub heading Primary (Differential) Driver, for details HSTL Output: See specification table and the CLOCK DRIVERS section OUT_CMOS CMOS Output: See specification table and the CLOCK DRIVERS section I FDBK_INB 41 I FDBK_IN 48 O DAC_RSET 50 O IOUT 51 O IOUTB 56 I/O 3.3V CMOS REFSELECT 57 I/O HOLDOVER 58 I 59 I 3.3V CMOS 3.3V CMOS 3.3V CMOS 60 I 3.3V IO_UPDATE Complementary Feedback input: In standard operating mode, this pin is connected to the filtered IOUTB output . This internally biased input is typically AC-coupled, and when configured as such, can accept any differential signal. Feedback Input: In standard operating mode, this pin is connected to the filtered IOUT output DAC output current setting resistor. Connect a resistor from this pin to GND . See the "DAC Output" section. DAC output: Output signal should be filtered and sent back on chip through FDBK_INB input Complimentary DAC output: Output signal should be filtered and sent back on chip through FDBK_IN input Reference Select input: In manual mode, the REFSELECT pin operates as a high impedance input pin, while in automatic mode, it operates as a low impedance output pin. Logic 0 (low) indicates/selects RefA. Logic 1 (high) indicates/selects RefB. Holdover: (Active high) In manual holdover mode, this pin is used to force the AD9549 AD9549 into holdover mode. In automatic holdover mode, it indicates holdover status. Power Down: When this active high pin is asserted, the device becomes inactive and enters a low power state. Chip Reset: When this active high pin is asserted, the chip goes into reset. Note: upon power up, a 10 us reset pulse is automatically generated when the power supplies reach a threshold and stabilize. I/O Update: A logic transition from 0 to 1 on this pin transfers data from the I/O port PWRDOWN RESET Rev. PrA | Page 19 of 78 AD9549 AD9549 Preliminary Technical Data CMOS 61 I 3.3V CMOS CSB 62 O SDO 63 I/O 64 O 3.3V CMOS 3.3V CMOS 3.3V CMOS SDIO SCLK registers to the control registers (see the Write subsection of the General Operation of Serial Control Port section). Chip Select: Active low. When programming a device, this pin must be held low. In systems where more than one AD9549 AD9549 is present this enables individual programming of each AD9549 AD9549 Serial Data Output: When the device is in three wire mode, data is read on this pin Serial Data Input/Output: When the device is in three-wire mode, data is written via this pin. In 2 wire mode, data reads and writes both occur on this pin Serial Programming Clock: data clock for serial programming. Rev. PrA | Page 20 of 78 Preliminary Technical Data AD9549 AD9549 INPUT / OUTPUT TERMINATION RECOMMENDATIONS 0.01 uF 100 0.01 uF Downstream Device (High-Z) AD9549 AD9549 1.8V HSTL Output 0.01 uF 100 (Opt.) AD9549 AD9549 Self-biasing REF Input 0.01 uF Figure 4: AC-Coupled HSTL Output Driver (Recommended) Figure 6: Reference Input. 50 AD9549 AD9549 1.8V HSTL Output + AVDD/2 - 50 Downstream Device (High-Z) 0.1 uF 100 AD9549 AD9549 Self-biasing FDBK Input 0.1 uF Figure 5: DC-Coupled HSTL Output Driver Figure 7: FDBK Input. Rev. PrA | Page 21 of 78 AD9549 AD9549 Preliminary Technical Data THEORY OF OPERATION CMOS CLK_OUT HSTL CLK_OUT 2X Digital PLL Core ÷S FDBK REF_SELECT Freq Est. REF_A ÷R PFD FREQ TUNING WORD PROG. DIGITAL LOOP FILTER SLEW LIMIT EXTERNAL ANALOG LOW-PASS FILTER DDS/DAC REF_B LOCK DETECT INPUT REF MONITOR HOLDOVER REF_CNTRL LOW NOISE CLOCK MULTIPLIER OOL&LOR CONTROL LOGIC S1-S4 IRQ & Status Logic AMP SYSCLK PORT DIGITAL INTERFACE HOLDOVER SYS_CLK Figure 8: Detailed Block Diagram OVERVIEW The AD9549 AD9549 provides a clocking output which is directly related in phase and frequency to the selected (active) reference (REF_A or REF_B), but having a phase noise spectrum primarily governed by the system clock. A wide band of reference frequencies is supported. Jitter existent on the active reference is greatly reduced by a programmable digital filter in the Digital Phase Locked Loop (PLL), which is the core of this product. The AD9549 AD9549 supports both manual and automatic holdover. While in holdover, the AD9549 AD9549 will continue to provide an output as long as the system clock is maintained. The frequency of the output during holdover is an average of the steady state output frequency prior to holdover. Also offered are manual and automatic switchover modes for changing between the two references should one become suspect or lost. A digitally controlled oscillator (DCO) is implemented using a Direct Digital Synthesizer (DDS) with an integrated output DAC, clocked by the system clock. A bypassable PLL based frequency multiplier is present enabling use of an inexpensive, low frequency source for the system clock. For best jitter performance, the system clock PLL should be bypassed, and a low-noise high-frequency system clock should be provided directly. Sampling theory sets an upper bound for the DDS output frequency at 50% of fS (where fS is the DAC sample rate), but a practical limitation of 40% of fS is generally recommended to allow for the selectivity of the required off-chip reconstruction filter. The output signal from the reconstruction filter is fed back to the AD9549 AD9549, both to complete the PLL, and to be processed through the output circuitry. The output circuitry includes HSTL and CMOS output buffers, as well as a frequency doubler for systems, which need to provide frequencies above the Nyquist level of the DDS. The individual functional blocks are described in the following sections. Rev. PrA | Page 22 of 78 Preliminary Technical Data AD9549 AD9549 PLL CORE (DPLLC) The Digital Phase Locked Loop Core (DPLLC) includes the frequency estimation block and the digital phase lock control block driving the DDS. The start of the DPLLC signal chain is the reference signal, fR, which appears on REF A or REF B inputs. The frequency of this signal can be divided by an integer factor of R via the feedforward divider. The output of the feedforward divider is routed to the phase/frequency detector (PFD). Therefore, the frequency at the input to the PFD is given by f PFD = fR R . The PFD outputs a time series of digital words that are routed to the digital loop filter. The digital filter implementation offers many advantages: The filter response is determined by numeric coefficients rather than discrete component values. There is no aging of components and therefore, no drift of component value over time. There is no thermal noise in the loop filter, and there is no control node leakage current (which causes reference feed through in a traditional analog PLL). The output of the loop filter is a time series of digital words. These words are applied to the frequency tuning input of a DDS to steer the DCO frequency. The DDS provides an analog output signal via an integrated DAC, effectively mimicking the operation of an analog VCO. The DPLLC can be programmed to operate in conjunction with an internal frequency estimator to help decrease the time required to achieve lock. When the frequency estimator is employed, frequency acquisition is accomplished in a two-step process: Step 1: An estimate is made of the frequency of fPFD. The phaselock control loop is essentially inoperative during the frequency estimation process. Once a frequency estimate is made, it is delivered to the DDS so that its output frequency is approximately equal to fPFD multiplied by S (the modulus of the feedback divider). Step 2: The phase-lock control loop becomes active and acts as a servo to acquire and hold phase lock with the reference signal. As mentioned in step 1) above, the DPLLC includes a feedback divider that allows the DCO to operate at an integer multiple (S) of fPFD. This establishes a nominal DCO frequency (fDDS) given by: S f DDS = ( R ) f R . Figure 9: AD9549 AD9549 Digital PLL Block Diagram Feedforward Divider (Divide-by-R) The feedforward divider is an integer divider allowing frequency prescaling of the REF Source input signal while maintaining the desired low jitter performance of the AD9549 AD9549. The feedforward divider is a programmable modulus divider with very low jitter injection. The divider is capable of handling input frequencies as high as 750 MHz. The divider depth is 16bits cascaded with an additional divide-by-two. The divider therefore is capable of integer division from 1 to 65,535 (index of 1) or 2 to 131,070 (index of 2). The divider is programmed via the I/O Register Map to trigger on either the rising (default) or falling edge of the REF Source input signal. There is a lower bound on the value of R imposed by the phasefrequency detector within the DPLLC which has a maximum operating frequency of fPFD[max] as explained in the Fine Phase Detector section. The "R Divider /2" bit must be set when REF_A or REF_B is greater than 400 MHz. The user must also ensure that R is chosen so that it satisfies the inequality: R ceil(fR / fPFD[max]) The upper bound is: R floor(fR /8 kHz) Where the ceil(x) function yields the nearest integer x. For example, if fR=155 MHz and fPFD[max] =24.5 MHz, then ceil (155/24.5) = 7, so R must be > 7. Feedback Divider (Divide-by-S) The feedback divider is an integer divider allowing frequency multiplication of the REF signal that appears at the input of the phase detector. It is capable of handling frequencies well above the Nyquist limit of the DDS. The divider depth is 16-bits cascaded with an additional divide-by-two. The divider is therefore capable of integer division from 1 to 65,535 (index of Rev. PrA | Page 23 of 78 AD9549 AD9549 Preliminary Technical Data 1) or 2 to 131,070 (index of 2). The divider is programmed via the I/O Register Map to trigger on either the rising (default) or falling edge of the feedback signal. condition, the phase error measurement uses the coarse phase detector instead. The feedback divider must be programmed within certain boundaries. The "S Divider /2" bit must be set when FDBK_IN is greater than 400 MHz. The upper boundary on the feedback divider is the lesser of the maximum programmable value of S and the maximum practical output frequency of the DDS (~ 40%fS). Two formulae are given: Smax1 for a feedback divider index of 1 and Smax2 for an index of 2: The digital loop filter integrates and low-pass filters the digital phase error values delivered by the phase detector. The loop filter response mimics that of a 2nd order, R-C network used to filter the output of a typical phase detector and charge pump combination as shown in the diagram below. ( = min [ ) S max 1 = min 40% f S R fR , 65535 S max 2 40% f S R fR , 131070 ] Digital Loop Filter Loop Filter CLK Phase/ Frequency Detector or Charge Pump VCO C1 R2 C2 Where R is the modulus of the feedforward divider, fS is the DAC sample rate, and fR is the input reference frequency. Figure 10: Typical Analog PLL Block Diagram The DCO has a minimum frequency (see DAC output Characteristics section of AC specification table). This imposes a lower bound, Smin, on the feedback divider value, as well. ( S min = max R f DCO min fR ), 1) NOTE: Reduced DCO frequencies result in worse jitter performance (a consequence of the reduced slew rate of the sinusoid generated by the DDS). Forward and Reverse FEC Clock Scaling The Feedforward (Divide-by-R) and Feedback Divider (Divideby-S) enable FEC clock scaling. For instance, to multiply the incoming signal by 255/237, set the S- divider to 255, and the R-divider to 237. One should be careful to abide by the limitations on the R- and S-Dividers, and make sure the Phase Detector input frequency is within specified limits. Phase Detector The phase detector is composed of two detectors: a coarse phase detector and a fine phase detector. The two detectors operate in parallel. Both detectors measure the duration (t) of the pulses generated by a conventional 3-state phase/frequency detector. Together, the fine and coarse phase detectors produce a digital word that is a time-to-digital conversion of the separation between the edge transitions of the pre-scaled reference signal and the feedback signal. The building blocks implemented on the AD9549 AD9549, however, are digital. A time-to-digital converter that produces digital values proportional to the edge timing error between the CLK and feedback signals replaces the phase-frequency detector and charge pump. A digital filter that processes the edge timing error samples from the time-to-digital converter replaces the loop filter. A DDS replaces the VCO, which produces a frequency that is linearly related to the digital value provided by the loop filter. This is shown in Figure 11 on Page 26 with some additional detail. The samples provided by the time-to-digital converter are delivered to the loop filter at a sample rate equal to the CLK frequency (i.e., fR/R). The loop filter is intended to oversample the time-to-digital converter output at a rate determined by the "P"-divider. The value of P is programmable via the I/O Register Map. It is stored as a 5-bit number, PIO. The value of PIO is related to P by the equation: P = 2P IO (where 5 PIO 16) Hence, the "P"-divider can provide divide ratios between 32 and 65536 in power-of-2 steps. With a DAC sample rate of 1GHz the loop filter sample rate can range from as low as 15.26kHz to a maximum of 31.25MHz. Coupled to the loop filter is a cascaded comb-integrator (CCI) filter that provides a sample rate translation between the loop filter sample rate (fS/P) and the DDS sample rate, fS. If the fine phase detector is able to produce a valid result, then this result alone serves as the phase error measurement. If the fine phase detector is either in an overflow or underflow Rev. PrA | Page 24 of 78 Preliminary Technical Data AD9549 AD9549 The choice of P is important because it controls both the response of the CCI filter and the sample rate of the loop filter. In order to understand the method for determining a useful value for P, it is first necessary to examine the transfer function of the CCI filter: H ( ) CCI = [ 1- e - jP P (1- e - j ) ] PIOMAX = max 5, 2 or ( 1 1- cos(P ) P 2 1- cos( ) ), >0 To evaluate the response in terms of absolute frequency, make the substitution: = f S 2 fS , floor log 2 min 16, floor log 2 3f 80 f REF LOOP With a properly chosen value for P, the closed-loop response of the digital PLL is primarily determined by the response of the digital loop filter. Flexibility in controlling the loop filter response translates directly into flexibility in the range of applications satisfied by the architecture of the AD9549 AD9549. =0 1, H CCI ( ) = define PMAX in terms of PIO, so that PIOMAX may be determined. The condition, PIO PIOMAX, ensures that the impact of the phase delay of the CCI filter on the phase margin of the loop will not exceed 5°. PIOMAX may be expressed as: 2f fS (where fS is the DAC sample rate and f is the frequency at which HCCI is to be evaluated) Analysis of this function reveals that the CCI magnitude response follows a low pass characteristic that consists of a series of P lobes. The lobes are bounded by null points occurring at frequency multiples of fS/P. The peak of each successive lobe is lower that its predecessor over the frequency range between DC and ½fS. For frequencies greater than ½fS, the response is a reflection about the vertical at ½fS. Furthermore, the first lobe (which appears between DC and fS/P) exhibits a monotonically decreasing response. That is, the magnitude is unity at DC and it steadily decreases with frequency until it vanishes at the first null point (fS/P). The null points imply the existence of transmission zeros placed at finite frequencies. While transmission zeros placed at infinity yield minimal phase delay, zeros placed closer to DC result in increased phase delay. Hence, the position of the first null point has a significant impact on the phase delay introduced by the CCI filter. This is an important consideration, because excessive phase delay negatively impacts the overall closed loop response. As a rule of thumb, choose a value for P so that the frequency of the first null point (fS/P) is the greater of: 80 times the desired loop bandwidth, or 1.5 times the frequency of CLK (fR/R) The value of P thus calculated (PMAX) is the largest usable value in practice. Since P is programmed as PIO, it is necessary to Rev. PrA | Page 25 of 78 AD9549 AD9549 Preliminary Technical Data = 2 Direct Digital Synthesizer One of the primary building blocks of the digital PLL is a direct digital synthesizer (DDS). The DDS behaves like a sinusoidal signal generator. The frequency of the sinusoid generated by the DDS is determined by a frequency tuning word (FTW), which is a digital (i.e., numeric) value. Unlike an analog sinusoidal generator, a DDS uses digital building blocks and operates as a sampled system. Thus, it requires a sampling clock (fS) that serves as the DDS's fundamental timing source. The accumulator behaves as a modulo-248 counter with a programmable step size (FTW). A block diagram of the DDS is shown below. Phase Offset 48-bit Accumulator 48 Frequency Tuning Word (FTW) 48 19 D I-Set 16 48 19 Q Angle to Amplitude Conversion 14 DAC DAC+ (14-bit) DAC- fS Figure 11: DDS Block Diagram The input to the DDS is a 48-bit FTW that provides the accumulator with a seed value. On each cycle of fS, the accumulator adds the value of the FTW to the running total of its output. For example, given an FTW=5, the accumulator would count by 5's, incrementing on each fS cycle. Over time, the accumulator will reach the upper end of its capacity (248 in this case). At which point it rolls over, retaining the excess. The average rate at which the accumulator rolls over establishes the frequency of the output sinusoid. The average rollover rate of the accumulator is given by the formula below, and establishes the output frequency (fDDS) of the DDS. f DDS = ( )f FTW 2 48 phase 216 ) The DDS can be operated in either open loop or closed loop mode, via the Close Loop bit in the DPLL Register. There are two open loop modes: Single Tone and Holdover. In Single Tone Mode, the DDS behaves like a frequency synthesizer, and uses the value stored in the FTW0 register to determine its output frequency. Alternatively, the FTW and phase values can be determined by the device itself using the frequency estimator. Because Single Tone mode ignores the reference inputs, it is very useful for generating test signals to aid in debugging. Single Tone mode must be activated manually via register programming. In Holdover mode, the AD9549 AD9549 uses past tuning words when the loop was closed to determine its output frequency. Therefore, the loop must have been successfully closed in order for Holdover Mode to work. Switching in and out of Holdover Mode can be either automatic or manual, depending on register settings. Typically, the AD9549 AD9549 operates in closed loop mode. In closed loop mode, the FTW values come from the output of the digital loop filter and vary with time. The DDS frequency is steered in a manner similar to a conventional VCO-based PLL. NOTE: In "closed loop" mode, the DDS phase offset capability is inoperative. S Solving this equation for FTW yields: f FTW = round 2 48 DDS fS ( For example, given that fS=1GHz and fDDS=19.44MHz, then FTW=5,471,873,547,255 (04FA05143BF7h). The relative phase of the sinusoid can be controlled numerically, as well. This is accomplished using the phase offset input to the DDS (a programmable 16-bit value (phase); see the I/O Register Map). The resulting phase offset, (radians), is given by: Rev. PrA | Page 26 of 78 Preliminary Technical Data AD9549 AD9549 I DAC _ FS = I DAC _ REF (72 + 192FSC 192FSC ) 1024 DAC Output The output of the digital core of the DDS is a time series of numbers representing a sinusoidal waveform. This series is translated to an analog signal by means of a digital-to-analog converter (DAC). The DAC outputs its signal to two pins driven by a balanced current source architecture (see DAC output diagram below). The peak output current derives from the combination of two factors. The first is a reference current (IDAC_REF) established at the DAC_RSET pin and the second is a scale factor programmed into the I/O Register map. AVDD3 49 Current Switch Array IFS/2 IFS/2 + ICODE IOUT IOUTB 50 50 ( )(2 fS fR PDS + 6 PDG ) The fine phase detector operates on a divided down version of fS as its sampling time base. The sample rate of the fine phase detector is set using a 4-bit word (PFD_Div) in the I/O Register Map and is given by: Fine Phase Detector Sample Rate = 50 52 fS 4 ( PFD _ Div ) The default value of PFD_Div is 5, so for fS=1GHz, the default sample rate of the fine phase detector is 50MHz. The upper bound on the maximum allowable input frequency to the phase detector (fPFD[max]) is 49% of the sample rate, or: AVSS Figure 12: DAC Output Pins The value of IDAC_REF is set by connecting a resistor (RDAC_REF) between the DAC_RSET pin and ground. The DAC_RSET pin is internally connected to a virtual voltage reference of 1.2v nominal, so the reference current can be calculated by: I DAC _ REF = The coarse phase detector uses the DAC sample rate (fS) to determine the edge timing deviation between the REF signal and the feedback signal generated by the DDS. Hence, fS sets the timing resolution of the coarse phase detector. At the recommended rate of fS=1GHz, the coarse phase detector spans a range of over 131µs (sufficient to accommodate REF signal frequencies as low as 8 kHz). Fine Phase Detector IFS/2 - ICODE CODE 51 Coarse Phase Detector Phase GainCPD = R Current Switch Array Switch Control PHASE DETECTOR The phase gain of the coarse phase detector is controlled via the I/O Registers by means of two numeric entries. The first is a 3bit power-of-2 scale factor, PDS. The second is a 6-bit linear scale factor, PDG. IFS IFS/2 Using the recommended value of RDAC_REF the full-scale DAC output current can be set with 10-bit granularity over a range of approximately 8.6mA to 31.7mA. 1.2 RDAC _ REF NOTE: The recommended value of IDAC_REF is 120µA, which leads to a recommended value of RDAC_REF of 10k. f PFD[max] = fS 8( PFD _ Div ) Therefore, fPFD[max] is 25MHz in the example above. The fine phase detector uses a proprietary technique to determine the phase deviation between the REF signal and feedback signal. The scale factor consists of a 10-bit binary number (FSC) programmed into the DAC FS Current register in the I/O Register Map. The full-scale DAC output current (IDAC_FS) is then given by: Rev. PrA | Page 27 of 78 AD9549 AD9549 Preliminary Technical Data The phase gain of the fine phase detector is controlled by an 8bit scale factor (FPFD_Gain) in the I/O Register Map. The nominal (default) value of FPFD_Gain is 200, and establishes R (210107 )( FPFD _ Gain ) the phase gain as: PhaseGainFPD = f R Phase Detector Gain Matching Although the fine and coarse phase detectors use different means to make a timing measurement, it is essential that both have equivalent phase gain. Without proper gain matching the closed-loop dynamics of the system cannot be properly controlled. Hence, the goal is to make PhaseGainCPD= PhaseGainFPD. This leads to: S ) ( Phase Detector Pin Connections There are three pins associated with the phase detector that must be connected to external components. The diagram below shows the recommended component values and their connections. AD9549 AD9549 PFD_VRB ) PFD_VRT 22 10µF Which simplifies to: 7 2 PDS PDG = (1610 )FPFD _ Gain fS 0.1µF Typically, FPFD_Gain is established first and then PDG and PDS are calculated. The proper choice for PDS is given by: [ ( PDS = round log 2 7 10 FPFD _ Gain 2 fS 10 7 FPFD _ Gain 2 PDS - 4 f S PFD_RSET ) The final value of PDG must satisfy 0 PDG 63. For example, let fS=700MHz and FPFD_Gain=200, then PDS=1 and PDG=23. 0.1µF Figure 13: Phase Detector Pin Connections )] The final value of PDS must satisfy 0 PDS 7. The proper choice for PDG is calculated using this equation: ( 21 0.1µF 2 PDS + 6 PDG = 21010 7 FPFD _ Gain PDG = round 20 4K99 (f Note that the AD9549 AD9549 Evaluation Software will calculate register values that have the phase detector gains already matched. DIGITAL LOOP FILTER COEFFICIENTS In order to provide the desired flexibility, the loop filter has been designed with three programmable coefficients (, and ). The coefficients along with P (where P=2Pio) completely defines the response of the filter, which is given by: H ( ) LoopFilter = ( e j + ( - -1) e j 2 + ( - - 2 ) e j + ( +1) ) To evaluate the response in terms of absolute frequency substitute: = 2Pf fS Where P is the divide ratio of the "P"-divider, fS is the DAC sample rate, and f is the frequency at which the function is to be evaluated. Rev. PrA | Page 28 of 78 Preliminary Technical Data AD9549 AD9549 The loop filter coefficients are determined by the AD9549 AD9549 evaluation software according to three parameters: : desired closed-loop phase margin (0 < < /2 rad) desired open-loop bandwidth (Hz) fLOOP: desired output frequency of the DDS (Hz) fDDS: Note that fDDS can also be expressed as fDDS = fR(S/R). The three coefficients are calculated according to parameters via the equations below: = -4Pf C tan( ) = 1 F ( ) 2 ( = - 10 Where 238 7 FPFD _ Gain )f The quantized coefficient is composed of three factors, where 0, 1 and 2 are the programmed values for the coefficient: quantized = (2048 )(2 )(2 - 0 1 2 ) The boundary values for each are 0 0 4095, 0 1 22, and 0 2 7. The optimal values of 0, 1 and 2 are: 1 = max[0, min{22, ceil (log 2 2048 4095 )}] 2 = max[0, min{7, floor (log 2 ( 4095 ) + 1 - 11)}] DDS 0 = max [0, min{4095, round ( 2 f C F ( ) 1 F ( ) = 1 + sin( ) , f C = f LOOP fS , and FPFD_Gain is the value of the gain scale factor for the Fine Phase Detector as programmed into the I/O Register Map. 2 -1 +11 )}] The magnitude of the quantized coefficient is composed of two factors: quantized = ( 0 )(2 - ( +15 ) ) 1 Where 0 and 1 are the programmed values for the coefficient, The boundary values for each are 0 0 4095 and 0 1 7. The optimal values of 0 and 1 are: NOTE: The range of loop filter coefficients is limited as follows: 0 < < 223 (~8.39·106) [ ( ( )- 15)}] { 1 = max 0, min 7, floor log 2 -0.125 < < 0 4095 0 = max[0, min{4095, round ( 2 +15 )}] -0.125 < < 0 1 The above constraints on and constrain the closed-loop phase margin such that both and will assume negative values. Even though and are limited to negative quantities, the values as programmed are positive. The negative sign is assumed internally. NOTE: The closed-loop phase margin is limited to the range of 0° < < 90° because and are negative. The three coefficients are implemented as digital elements, necessitating quantized values. Determination of the programmed coefficient values in this context follows. The magnitude of the quantized coefficient is composed of - ( +15 ) two factors: quantized = 0 2 1 ( )( ) Where 0 and 1 are the programmed values for the coefficient, the boundary values for each are 0 0 4095 and 0 1 7. The optimal values of 0 and 1 are: [ { ( ( )- 15)}] 1 = max 0, min 7, floor log 2 4095 0 = max[0, min{4095, round ( 2 +15 )}] Rev. PrA | Page 29 of 78 1 AD9549 AD9549 Preliminary Technical Data The min(), max(), floor(), ceil() and round() functions are defined as follows. The function, min(x1, x2, . xn), chooses the smallest value in the list of arguments. The function, max(x1, x2, . xn), chooses the largest value in the list of arguments. The function, ceil(x), increases x to the next higher integer if x is NOT an integer, otherwise x is unchanged. The function, floor(x), reduces x to the next lower integer if x is NOT an integer, otherwise x is unchanged. The function, round(x), rounds x to the nearest integer. To demonstrate the wide programmable range of the loop filter bandwidth, consider the following design example. The system clock frequency (fS) is 1GHz, the input reference frequency (fR) is 19.44MHz, the DDS output frequency (fDDS) is 155.52MHz, and the required phase margin () is 45°. fR is within the nominal bandwidth of the phase detector (25MHz), and fDDS/fR, is an integer (8), so the prescalar is not required. We can therefore use R=1 and S=8 for the feedforward and feedback dividers, respectively. NOTE: If fDDS/fR is a non- integer, then R and S must be chosen such that S/R= fDDS/fR with S and R both constrained to integer values. For example, if fR=10MHz and fDDS=155.52MHz, then the optimal choice for S and R is 1944 and 125, respectively. The resulting loop filter coefficients for the lower loop bandwidth along with the necessary programming values are shown below. = 0.005883404361345 0 = 16 (10h) 0 = 1542 (606h) 1 = 7 (7h) 1 = 0 (00h) = -0.00000461136116 2 = 7 (7h) 0 = 19 (13h) = -0.000003820176667 1 = 7 (7h) Details on exactly how these coefficients are derived can be obtained by contacting Analog Devices Inc. directly. CLOSED LOOP PHASE OFFSET The AD9549 AD9549 provides for limited control over the phase offset between the reference input signal and the output signal by adding a constant phase offset value to the output of the phase detector. An adder is included at the output of the phase detector as shown in the figure below to support this. The value of the constant (PLLOFFSET) is set via the PLL Offset register. The open loop bandwidth range under the defined conditions spans 9.5Hz to 257.5kHz. The wide dynamic range of the loop filter coefficients allows for programming of any open loop bandwidth within this range under these conditions. The resulting closed loop bandwidth range under the same conditions is approximately 12Hz to 359kHz. The resulting loop filter coefficients for the upper loop bandwidth along with the necessary programming values are shown below. Phase Offset Value CLK Feedback Phase Detector To CCI Filter Loop Filter Figure 14: Input Phase Offset Adder = 4322509.4784981 0 = 3393 (D41h) PLLOFFSET is a function of the phase detector gain and the desired amount of timing offset (tOFFSET). It is given by: 0 = 2111 (83Fh) 1 = 0 (0h) PLLOFFSET = t OFFSET 21010 7 FPFD _ Gain 1 = 22 (16h) = -0.12499215775201 2 = 0 (0h) 0 = 4095 (FFFh) NOTE: FPFD_Gain is described in the Fine Phase Detector section. = -0.10354689386232 1 = 0 (0h) ( Rev. PrA | Page 30 of 78 ) Preliminary Technical Data AD9549 AD9549 For example, suppose that FPFD_Gain=200, fCLK=3MHz, and 1° of phase offset is desired. First, we must find the value of tOFFSET, which is: t OFFSET = deg 360 TCLK = 1 360 ( 1 3 MHz RESET Phase Detector Samples ) = 925.9 ps Absolute Value Control Logic Digital Comparator Having determined tOFFSET, we have: ( ) Unlock Timer Phase Lock Detect Lock Timer P-Divider Clock PLLOFFSET = 925.9 ps 210 10 7 200 = 1896 3 The result has been rounded because PLLOFFSET is restricted to integer values. I/O Registers Phase Lock Detect Threshold 5 Y X Close Loop Figure 15: Phase Lock Detector Block Diagram NOTE: The PLLOFFSET value is programmed as a 14-bit, twoscomplement number. However, the user must ensure that the magnitude is constrained to 12 bits, such that: 11 -2 PLLOFFSET < +2 11 The above constraint yields a timing adjustment range of ±1ns. This ensures that the phase offset remains within the bounds of the fine phase detector. LOCK DETECTION Phase Lock Detection During the phase locking process, the output of the phase detector tends toward a value of zero, which indicates perfect alignment of the phase detector input signals. As the control loop works to maintain the alignment of the phase detector input signals, the output of the phase detector wanders around zero. The phase lock detector tracks the absolute value of the digital samples generated by the phase detector. These samples are compared to the Phase Lock Detect Threshold value programmed in the I/O Register Map. A false state at the output of the comparator indicates the absolute value of a sample exceeds the value in the threshold register. A true state at the output of the comparator indicates alignment of the phase detector input signals to the degree specified by the lock detection threshold. The Phase Lock Detect Threshold value (PLDT) is a 32-bit number stored in the I/O Register Map: ( PLDT = round t 210 10 7 FPFD _ Gain ) Where t is the maximum allowable timing error between the signals at the input to the phase detector and the value of FPFD_Gain is as described in the Fine Phase Detector section. For example, suppose that fR/R=3MHz, FPFD_Gain=200, and the maximum timing deviation is given as 1°. This yields a t value of: t = 1o 360o (R TR ) = 360R f R = 1 360 3106 ( ) The resulting phase lock detect threshold is: 2 10 10 7 200 PLDT = round 360 3 10 6 = 1896 ( ) Hence, 1896 (00000768h) is the value that must be stored in the Phase Lock Detect Threshold register. The "phase lock detect" signal is generated once the control logic observes that the output of the comparator has been in the true state for 2X periods of the P-Divider clock (see the Digital Loop Filter section for a description of the P-Divider). Once the phase lock detect signal is asserted, it remains asserted until cleared by an "unlock" event or by a device RESET. The duration of the lock detection process is programmable via the Phase Lock Watchdog Timer register. The interval is controlled by a 5-bit number, X (0 X 20). The absolute duration of the phase lock detect interval is: TLOCK = Rev. PrA | Page 31 of 78 2X P fS AD9549 AD9549 Preliminary Technical Data The time required to declare an unlock event is programmable via the Phase Lock Watchdog Timer register. The interval is controlled by a 3-bit number, Y (0 Y 7). The absolute duration of the unlock detection interval is: Hysteresis in the phase lock detection process is controlled by specifying the minimum duration that qualifies as an unlock event. An unlock event is declared when the control logic observes that the output of the comparator has been in the false state for 2Y+1 periods of the P-Divider clock (provided that the phase lock detect signal has been asserted). Detection of an unlock event clears the phase lock detect signal, and the phase lock detection process is automatically restarted. TUNLOCK = 2Y + 1 P fS Figure 16 below shows the basic timing relationship between the reference signal at the input to the phase detector, the phase error magnitude, the output of the comparator, and the output of the phase lock detector. The example shown here assumes that X=3 and Y=1. fR/R Phase Error Magnitude Samples Threshold 0 fS/P Threshold Comparator 8 Lock Timer (X=3) 8 LOCKED 4 Unlock Timer (Y=1) Figure 16: Lock/Unlock Detection Timing Frequency Lock Detection Frequency lock detection is similar to phase lock detection, with the exception that the difference between successive phase samples is the source of information. A running difference of the phase samples serves as a digital approximation to the timederivative of the phase samples, which is analogous to frequency. RESET Phase Detector Samples Differencer Absolute Value Control Logic Digital Comparator Unlock Timer Frequency Lock Detect Lock Timer I/O Registers Frequency Lock Detect Threshold Y 5 X 2 R FLDT = round f 210107 FPFD _ Gain f R Where fR is the frequency of the active reference, R is the value of the reference prescaler, and f is the maximum frequency deviation of fR that is considered to indicate a frequency locked condition (f 0). For example, suppose that fR=3MHz, R=5, FPFD_Gain=200, and a frequency lock threshold of 1% is specified. Then the frequency lock detect threshold value is: 2 5 FLDT = round 1% 3 106 210107 200 = 170,667 6 3 10 ( P-Divider Clock 3 The formula for the Frequency Lock Detect Threshold value (FLDT) is: Close Loop Figure 17: Frequency Lock Detection ) Hence, 170667 (00029AABh) is the value that should be stored in the Frequency Lock Detect Threshold register. The duration of the frequency lock/unlock detection process is controlled in exactly the same way as the phase lock/unlock Rev. PrA | Page 32 of 78 Preliminary Technical Data AD9549 AD9549 detection process in the previous section. However, a different control register is used: the Frequency Lock Watchdog Timer register. REFERENCE MONITORS Loss of Reference The AD9549 AD9549 can set an alert when one or both of the reference signals are not present. Each of the two reference inputs (REFA, REFB) has a dedicated LOR (Loss of Reference) circuit enabled via the I/O Register Map. Detection of an LOR condition sets the appropriate LOR bit in both a status register and an IRQ register in the I/O Register Map. The LOR state is also internally available to the multi-purpose "status" pins (S1:4) of the AD9549 AD9549. By setting the appropriate bit in the I/O Register Map, the user can assign a status pin to each of the LOR flags. This provides a means to control external hardware based on the state of the LOR flags directly. The LOR circuits are internal `watchdog' timers with a programmable period. The period of the timer is set via the I/O register Map so that its period is longer than that of the monitored reference signal. The rising edge of the reference signal continuously resets the watchdog timer. If the timer reaches a full count, this indicates that the reference was either lost or its period was longer than the timer period. LOR does not differentiate between these. The period for each of the LOR timers is controlled by a 16-bit word in the I/O Register Map. The period of the timer clock (TCLK) is 2/fS. Therefore, the period of the watchdog timer (TWD) is: TWD = (2/fS)N Where N is the value of the 16-bit word stored in the I/O Register Map for the appropriate LOR circuit. Choose the value of N so that the watchdog period is greater than the input reference period, expressed mathematically as: N > floor ( ) Note that when N is chosen to be floor ( ) + 1 , the LOR fS 2 fR circuit is capable of indicating an LOR condition in little more than a single input reference period. For example, if fS=1GHz and fR=2.048MHz, then the smallest useable N value is: ( ) 10 N MIN = floor 2(2.048×106 ) + 1 = 245 9 Which yields values for fPRESENT and fLOST as: f PRESENT = 2,048,816 and f LOST = 2,032,520 NOTE: N should be chosen sufficiently large to account for any acceptable deviation in the period of the input reference signal. Notice that the value of N is inversely proportional to the reference frequency, meaning that as the reference frequency goes up, the precision for adjusting the threshold goes down. Proper operation of the LOR circuit requires that N be no less than 3. Therefore, the highest reference frequency for which the LOR circuit will function properly is given by: fLOR_MAX = fS/6. Reference Frequency Monitor The AD9549 AD9549 can set an alert whenever one or both of the reference inputs drift in frequency beyond user-specified limits. Each of the two references has a dedicated Out of Limits (OOL) circuit enabled/disabled via the I/O Register Map. Detection of an OOL condition sets the appropriate OOL bit in both a status register and an IRQ register in the I/O Register Map. The user can also assign a status pin (S1-S4) to each of the OOL flags by setting the appropriate bit in the I/O Register Map. This provides a means to control external hardware based on the state of the OOL flags directly. Each reference monitor contains three main building blocks: a programmable reference divider, a 32-bit counter, and a 32-bit digital comparator. fS 2 fR where fR is the frequency of the input reference. The value of N results in establishing two frequencies. One for which the LOR signal will never be triggered (fPRESENT), and one for which the LOR signal will always be active (fLOST). Between these frequencies the LOR signal will intermittently toggle between states. Figure 18: Reference Monitor The values of the two frequency bounds are: f PRESENT = fS 2N f LOST = fS 2 ( N +1) Four values are needed to calculate the correct values of the reference monitor: The system clock frequency, fS (usually Rev. PrA | Page 33 of 78 AD9549 AD9549 Preliminary Technical Data 1 GHz), the reference input frequency, fR (in Hz), the error bound, E (1%=0.01), and the monitor window size (W). The monitor window size is the difference between the maximum and minimum number of counts accumulated between adjacent edges of the reference input. If this window is too small, random variations will cause the OOL detector to indicate incorrectly that a reference is out of limits. However, the time required to determine if the reference frequency is valid increases with window size. A window size of at least 20 is a good starting point. the I/O Register Map. Transition to a newly selected reference depends on a number of factors: The four input values mentioned above are used to calculate the OOL Divider (D) and OOL nominal value (N), which in turn are used to calculate the OOL Upper Limit (U), and OOL Lower Limit (L) according to the following formulas: A functional diagram of the reference switchover and holdover logic is shown in Figure 19. State of the REFSELECT pin State of the "Ref_AB" control register bit State of the "Enable Ref Input Override" register bit Holdover status f W D = max(1, min(65535, ceil 4 * R * ) fS E N= fR D * fS 4 L = floor ( N ) - floor (W ) U = ceil ( N ) + floor (W ) The timing accuracy is dependent on two factors. The first is the inherent accuracy of fS, since it serves as the time base for the Reference Monitor. As such, the accuracy of the Reference Monitor can be no better than the accuracy of fS. Second, the value of W, which must be sufficiently large so that the timer resolves the deviation between a nominal value of fR and a value that is out of limits. As an example, let fR=10MHz, =1.0%, fS=1GHz, and W=20. The limits are then: Lower Limit = 1980 Upper Limit = 2020 Now let =0.01%, Then the limits are: Lower Limit = 199980 Upper Limit = 200020 Notice that the number of counts (and time) required to make this measurement has increased 100x. REFERENCE SWITCHOVER The AD9549 AD9549 supports dual input reference clocks. Reference switchover may be accomplished either automatically or manually by appropriately programming the "AutoRefSel" bit in Rev. PrA | Page 34 of 78 Preliminary Technical Data AD9549 AD9549 Active RefSel State REF SEL RefAB 1 0 AutoRefSel State Machine 0 1 Derived RefSel State AutoHold Derived Holdover State To Reference Switching Control Logic Override RefPin REFA In Override HldPin 1 0 0 1 an "Enable Line Card Mode" bit is provided in the I/O Register map. The Line Card Mode logic is shown in Figure 20 below. When Enable Line Card bit is 0, reference switch over occurs on command without consideration to the relative edge placement of the references. This means that there is the possibility of an extra pulse. However, when this bit is set to 1, the timing of the reference switch over is executed conditionally as shown in Figure 21 on Page 36. To Holdover Control Logic 0 REFB In 1 selected reference REF In Enable Line-Card Mode Hldovr HOLDOVER 0 Active Holdover State 1 Q D From Reference Selection Logic Figure 19: Reference Switchover and Holdover Logic In manual mode, the active reference is determined by an externally applied logic level to the REFSELECT pin. In automatic mode, an internal state machine determines which reference is active, and the REFSELECT pin becomes an output indicating which reference the state machine is using. The user may override the active reference chosen by the internal state machine via the "Enable Ref Input Override " bit in the I/O Register Map. The "Ref_AB" bit in the I/O Register Map is then used to select the desired reference. When in override, it is important to note that the REFSELECT pin does not indicate the physical reference selected by the "Ref_AB" bit. Instead, it indicates the reference that the internal state machine would select if the device were not in the override mode. This allows the user to force a reference switchover by means of the programming registers while monitoring the response of the state machine via the REFSELECT pin. 0 1 Figure 20: Reference Switchover Control Logic Note that when the line card mode is enabled, the rising edges of the alternate reference are used to clock a latch. The latch holds off the actual transition until the next rising edge of the alternate reference. Shown in Figure 21 is a timing diagram that demonstrates the difference between reference switchover with the line card mode enabled and disabled. If enabled, when the reference switchover logic is given the command to switch to the alternate reference, an actual transition does not occur until the next rising edge of the alternate reference. This action eliminates the spurious pulse that can occur when the line card mode is disabled. The same type of operation (manual/automatic and override) also applies to the holdover function, as shown in the Reference Switchover Logic diagram. The dashed arrows in the diagram indicate that the state machine output is available to the REFSELECT and HOLDOVER pins when in override mode. Use of Line Card Mode to Eliminate Runt Pulses When two references are not in exact phase alignment and a transition is made from one to the other, it is possible that an extra pulse can be generated. This depends on the relative edge placement of the two references and the point in time that a switch over is initiated. To eliminate the "extra pulse" problem, Rev. PrA | Page 35 of 78 AD9549 AD9549 Preliminary Technical Data REFA In 1 REFB In 2 1 3 1=Holdover). The HOLDOVER pin is configured as a high impedance (>100k) input pin in order to accommodate manual holdover operation. 4 2 3 4 Select REFB From Reference Selection Logic Select REFA Line Card Mode REF In 1 2 REF In 1 2 3 4 3 5 Disabled 4 Enabled REF selection stalled until next rising edge of REFB Figure 21: Reference Switchover Timing HOLDOVER Holdover Control Holdover functionality provides the user with a means of maintaining the output clock signal even in the absence of a reference signal at the REF A or B input. In holdover mode, the output clock is generated from the SysClk input (via the DDS) by directly applying a frequency tuning word to the DDS. Transfer from normal operation to holdover mode may be accomplished either manually or automatically by appropriately programming the "Automatic Holdover" bit (0=Manual, 1=Auto). The actual transfer to holdover operation, however, depends on the state of the HOLDOVER pin and the state of control register bits "Enable Holdover Override" and "Holdover On/Off ". Automatic holdover is invoked when the "AutoHold" bit is a logic 1. In automatic mode, the HOLDOVER pin is configured as a low impedance output with its logic state indicating the holdover state as determined by the internal state machine (0=Normal, 1=Holdover). In automatic holdover operation the user may override the internal state machine by programming the "Override HldPin" bit to a logic 1 and the "Hldovr" bit to the desired state (0=Normal, 1=Holdover). However, the HOLDOVER pin does not indicate the "forced" holdover state in the override condition, but continues to indicate the holdover state as chosen by the internal state machine (even though the state machine choice is overridden). This allows the user to force a holdover state by means of the programming registers while monitoring the response of the state machine via the HOLDOVER pin. A functional diagram of the reference switchover and holdover logic is shown in Figure 19 on Page 35. NOTE: The default state for the reference switchover bits is AutoHold=0, Override HldPin=0, and Hldovr=0. Holdover & Reference Switchover State Machine The interplay between the input reference signals and holdover is most readily demonstrated by means of a state diagram. In Figure 22, the various control signals and the four states are shown. Manual holdover is established when the "Automatic Holdover" bit is a logic 0 (default). In manual mode, holdover is determined by the state of the HOLDOVER pin (0=Normal, Rev. PrA | Page 36 of 78 Preliminary Technical Data AD9549 AD9549 Figure 22: Holdover state diagram Abbreviation Key RefA: RefB: HoldOver: FailA: FailB: ValidA: ValidB: Reference A selected Reference B selected Holdover state Reference A failed Reference B failed Reference A validated Reference B validated OvrdRefPin: OvrdHldPin: AutoRefSel: AutoRcov: AutoHold: || & % Override REF SEL pin Override HOLDOVER pin Automatic reference select Automatic holdover recovery Automatic holdover entry Logical OR Logical AND Logical NOT Figure 23: Holdover State Diagram Abbreviation Key States 1 or 2 are in effect when the device is not in the holdover condition, while states 3 & 4 are in effect when the holdover condition is active. When REF A is selected as the "active" reference, then states 1 or 3 are in effect. When REF B is selected as the "active" reference, then states 2 or 4 are in effect. A transition between states depends on the reference switchover and holdover control register settings, the logic state of the REFSELECT and HOLDOVER pins, and the occurrence of certain events (e.g., a reference failure). The state machine and its relationship to control register and external pin stimuli are shown in the diagram below. The state machine generates a "derived" reference selection and holdover state. The actual control signal sent to the reference switchover logic and the holdover logic, however, depends on the control signals applied to the MUXes. The "dashed" path leading to the REFSELECT and HOLDOVER pins is active when the "auto" mode is selected for reference selection and/or holdover assertion. Reference Recovery Timers Each of the two reference inputs has a dedicated recovery timer. The status of these timers is used by the holdover state machine as part of the decision making process for reverting to a previously faulty reference. For example, suppose that a reference fails (i.e., an LOR or OOL condition is in effect) and Rev. PrA | Page 37 of 78 AD9549 AD9549 Preliminary Technical Data that the device is programmed to revert automatically to a valid reference when it recovers. When a reference returns to normal operation, the LOR and OOL conditions will no longer be true. However, the state machine is not immediately notified of the clearing of the LOR and OOL condition. Instead, once both the LOR and OOL conditions are cleared, the recovery timer for that particular reference is started. Expiration of the recovery timer is an indication to the state machine that the reference is now available for selection. However, even though the reference is now flagged as "valid", actual transition to the recovered reference depends on the programmed settings of the various holdover control bits. The recovery timers are controlled via the I/O Register Map. Although there are two independent recovery timers, the programmed information is shared among both. The desired time interval is controlled via a 5-bit word (T) such that 0 T 31 (default is T=0). The duration of the recovery timers is given by: ( ) signal with the reference input signal, and will start to adjust the phase/frequency using the holdover signal as its starting point. The behavior of the holdover state machine when it is in automatically exiting holdover mode is very similar. The primary difference is that reference monitor is continuously monitoring both reference inputs and as soon as one becomes valid, it automatically switches to that input. The output frequency in Holdover mode depends on the frequency of the SysClk input source and the value of the frequency tuning word applied to the DDS. Therefore, the stability of the output signal is completely dependent on the stability of the SysClk source (and the SysClk PLL Multiplier, if enabled). Note: It is very important to power down an unused reference input to avoid chattering on that input. Also, the reference validation timer must be set to at least one full cycle of the signal coming out of the reference divider. TRECOVER = T0 2 T +1 - 1 Where T0 is the sample rate of the digital loop filter, which has a period of: T0 = 2 PIO fS (see the Digital Loop Filter section) A single bit, Disable Recovery Timer, causes the state machine to ignore the status of the recovery timers. Instead, the state machine relies on the user to validate the recovery of the faulty reference and then to set the Validate RefA (or RefB) bit manually in the I/O Register Map. That is, the state machine treats the setting of the "Validate" bits as though the associated timer had expired. Holdover Operation When the holdover condition is asserted, the DDS output frequency is no longer controlled by the phase lock feedback loop. Instead, a static frequency tuning word (FTW) is applied to the DDS to hold it at a specified frequency. The source of the static FTW depends on the status of the appropriate control register bits. During normal operation, the Averager & Sampler monitors and accumulates up to 65000 FTW values as they are generated, and upon entering holdover, the holdover state machine can use the averaged tuning word, or the last valid tuning word. Holdover mode is exited in a similar manner that it is entered. If manual holdover control is used, then when the holdover pin is de-asserted, the phase detector starts comparing the holdover Rev. PrA | Page 38 of 78 Preliminary Technical Data AD9549 AD9549 Holdover Sampler and Averager If activated via the I/O Register Map, the HSA continuously monitors the data generated by the digital loop filter in the background. It should be noted that the loop filter data is a time sequence of frequency adjustments (f) to the DDS. The output of the HSA is routed to a read-only register in the I/O Register Map and to the holdover control logic. The first of these destinations (the read-only register) serves as a "trace buffer" that may be read by the user and the data processed externally. The second destination (the holdover control logic) uses the output of the HSA to "peg" the DDS at a specific frequency upon entry into the holdover state. Hence, the DDS will assume a frequency specified by the last value generated by the HSA just prior to entering the holdover state. between DC and fS/2 (with 48-bit resolution). However, the user is given the option of placing limits on the tuning range of the DDS via two 48-bit registers in the I/O Register Map: FTW Upper Limit and FTW Lower Limit. If the tuning word input exceeds the upper or lower frequency limit boundaries, the tuning word is clipped to the appropriate value. The default setting for these registers is fS/2 and DC, respectively. It may be desirable to limit the output range of the DDS to a narrow band of frequencies (for example, to achieve better jitter performance in conjunction with a band pass filter). See "Use of Narrowband Filter for High Performance" on Page 40 for more information about this feature. REF IN R The state of the output MUX is established by programming the I/O Register Map. The default state is such that the f values pass through the HSA unaltered. In this mode, the output sample rate is fS/P, the same as the sample rate of the digital loop filter. Phase Detector Loop Filter External Reconstruction Filter S Low Pass Frequency Limiter NOTE: P is the divide ratio of the "P"-divider (see "Digital Loop Filter" on Page 24) and fS is the DAC sample rate. Alternatively, the MUX can be set to select the averaging path. In this mode, a "block average" is performed on a sequence of samples. The length of the sequence is determined by programming the value of Y (a 4-bit number stored in the I/O Register Map), and has a value of 2Y+1. In the "averaging" mode, the output sample rate is given by fS/ (P2Y+1). When the number of f samples specified by Y has been collected, the averaged result is delivered to a 2-stage pipeline. The last stage of the pipeline contains the value that will be delivered to the holdover control logic when a transition into the holdover state occurs. The pipeline is a guarantee that the averaged f value delivered to the holdover control logic has not been interrupted by the transition into the holdover state. The pipeline provides an inherent delay of t = P2Y+1/fS. Hence, the DDS "hold" frequency is the average as it appeared t to 2t seconds prior to entering the holdover state. Note that the user has some control over the duration of t because it is dependent on the programmed value of Y. OUTPUT FREQUENCY RANGE CONTROL Under normal operating conditions, its output frequency is dynamically changing in response to the output of the digital loop filter. The loop filter can steer the DDS to any frequency DDS/DAC REF IN R Phase Detector S Loop Filter DDS/DAC External Reconstruction Filter Band Pass Figure 24: Application of the Frequency Limiter RECONSTRUCTION FILTER The origin of the output clock signal produced by the AD9549 AD9549 is the combined DDS and DAC. The DAC output signal appears as a sinusoid sampled at fS. The frequency of the sinusoid is determined by the frequency tuning word (FTW) that appears at the input to the DDS. The DAC output is typically passed through an external reconstruction filter that serves to remove the artifacts of the sampling process and other spurs outside the filter bandwidth. The signal is then brought back on-chip to be converted to a square wave that is routed internally to the output clock driver or the 2x DLL multiplier. Since the DAC constitutes a sampled system, its output must be filtered so that the analog waveform accurately represents the digital samples supplied to the DAC input. The unfiltered DAC output contains the desired base band signal, which extends from DC to the Nyquist frequency (fS/2). It also contains Rev. PrA | Page 39 of 78 AD9549 AD9549 Preliminary Technical Data images of the base band signal that theoretically extend to infinity. Notice that the odd images (shown in Figure 25 below) are mirror images of the base band signal. Furthermore, the entire DAC output spectrum is affected by a sin(x)/x response, which is caused by the "sample and hold" nature of the DAC output signal. Magnitude (dB) 0 -20 -40 Image 0 Image 1 primary signal Image 2 filter response Image 4 sin(x)/x envelope -60 -80 Image 3 spurs f -100 fS/2 fS 3fS/2 2fS 5fS/2 base band Figure 25: DAC Spectrum vs. Reconstruction Filter Response The response of the reconstruction filter should preserve the base band signal (image 0), while completely rejecting all other images. However, a practical filter implementation will typically exhibit a relatively flat pass band that covers the desired output frequency plus 20%, roll off as steeply as possible, and then maintain significant (though not complete) rejection of the remaining images. Plot 14: Filtered DAC Output Using 7th order elliptical with Fc=186 MHz. Same Conditions as previous plot. Since the DAC output signal serves as the feedback signal for the digital PLL, the design of the reconstruction filter can have a significant impact on the overall jitter performance. Hence, good filter design and implementation techniques are important for obtaining the best possible jitter results. Use of Narrowband Filter for High Performance A distinct advantage of the AD9549 AD9549 architecture is its ability to constrain the frequency output range of the DDS. This allows the user to employ a narrow band reconstruction filter instead of the low pass response shown above resulting in less jitter on the output. For example, suppose that the nominal output frequency of the DDS is 150MHz. One might then choose a 5MHz narrow band filter centered at 150MHz. By using the AD9549 AD9549's DDS frequency limiting feature, the user could constrain the output frequency to 150MHz ± 4.9MHz (which allows for a 100kHz margin at the pass band edges). This will ensure that a feedback signal is always present for the digital PLL. Such a design would be extremely difficult to implement with conventional PLL architectures. Plot 13: DAC Output without Reconstruction Filter. fOUT=155.52 MHz. Sysclk=25 MHz. Sysclk PLL = x40. Spur reduction disabled. DPLL Loop Closed. Freq Span for Plot: 500 MHz. Rev. PrA | Page 40 of 78 Preliminary Technical Data AD9549 AD9549 FDBK INPUTS VDD The FDBK pins serve as the input to the feedback path of the digital PLL. Typically, these pins are used to receive the signal generated by the DDS after it has been band-limited by the external reconstruction filter. FDBK_IN Vb ~1pF 8K REFA_IN (or REFB_IN) To Reference Monitor and Switching Logic GND ~1pF 8K A diagram of the FDBK input pins is provided here, which includes some of the internal components used to bias the input circuitry. Note that the FDBK input pins are internally biased to a DC level of ~1V. Care should be taken to ensure that any external connections do not disturb the DC bias, as this may significantly degrade performance. + 1pF REFA_INB (or REFB_INB) 15K ~1pF FDBK_INB VSS To S-Divider and Clock Output Section 15K VSS ~1pF Figure 27: Reference Inputs NOTE: Support for redundant reference clocks is achieved by using the two Reference Clock receivers (REFA & REFB). + ~1V ~2pF VSS Figure 26: Differential FDBK Inputs In order to accommodate a variety of input signal conditions the value of Vb is programmable via a pair of bits in the I/O Register Map. Table 3 below gives the value of Vb for the bit pattern in Register 040F. Reference Bias Level R040F R040F[1:0] REFERENCE INPUTS Reference Clock Receiver The Reference Clock receiver is the point at which the user supplies the input clock signal that the Synchronizer will synthesize into an output clock. The clock receiver circuit is able to handle a relatively broad range of input levels as well as frequencies from 8 kHz up to 750 MHz. The following is a diagram of the REFA/B input pins, which includes some of the internal components used to bias the input circuitry. Note that the REF input pins are internally biased by a DC source, Vb. Care should be taken to ensure that any external connections do not disturb the DC bias, as this may significantly degrade performance. Rev. PrA | Page 41 of 78 Vb 00 (default) AVDD3-800mV 01 AVDD3-400mV 10 AVDD3-1600mV 11 AVDD3-1200mV Table 3: Setting of Input Bias Voltage (Vb) AD9549 AD9549 Preliminary Technical Data SYSCLK INPUTS Functional Description The SysClk pins are where an external timebase is connected to the AD9549 AD9549 for generating the internal high frequency system clock (fS). The SysClk inputs can be operated in one of three modes: 1) SysClk PLL Bypassed, 2) SysClk PLL Enabled with input signal generated externally, or 3) Crystal Resonator with SysClk PLL Enabled. A functional diagram of the system clock generator is shown below. frequency as the SysClk input signal, and the magnitude of the sub-harmonic can be quite large. When employing the BED care must be taken to ensure that the loop bandwidth of the SysClk PLL Multiplier will adequately suppress the subharmonic. The benefit offered by the BED depends on the magnitude of the sub-harmonic, the loop bandwidth of the SysClk PLL Multiplier, and the overall phase noise requirements of the specific application. In many applications, the AD9549 AD9549 clock output is applied to the input of another PLL, and the subharmonic is often suppressed by the relatively narrow bandwidth of the downstream PLL. NOTE: Generally, the benefits of the Bipolar Edge Detector are realized for SysClk input frequencies of 25MHz and above. SysClk PLL Multiplier Figure 28: System Clock Generator Block Diagram The SysClk PLL multiplier path is enabled by a logic 0 (default) in the PD SysClk PLL location of the I/O Register Map. The SysClk PLL multiplier can be driven from the SysClk input pins by one of two means depending on the logic level applied to the 1.8V CMOS CLKMODESEL pin. When CLKMODESEL=0, a crystal can be connected directly across the SysClk pins. When CLKMODESEL=1, the maintaining amp is disabled, and an external frequency source (oscillator, signal generator, etc.) can be connected directly to the SysClk input pins. Note that CLKMODESEL=1 does not disable the system clock PLL. When the SysClk PLL Multiplier path is employed, the frequency applied to the SysClk input pins must be limited so as not to exceed the maximum input frequency of the SysClk PLL phase detector. A block diagram of the SysClk generator appears in Figure 29 below. When the SysClk PLL multiplier path is disabled, the AD9549 AD9549 must be driven by a high frequency signal source (up to 1GHz). The signal thus applied to the SysClk input pins becomes the internal DAC sampling clock (fS) after passing through an internal buffer. Bipolar Edge Detector The SysClk PLL Multiplier path offers an optional Bipolar Edge Detector (BED). This block acts as a frequency doubler by generating a pulse on each edge of the SysClk input signal. The SysClk PLL Multiplier locks to the falling edges of this regenerated signal. The impetus for doubling the frequency at the inp