AD9238 IS-95 IMT-2000 AD9238-65 MSPS/40 MSPS/65 AD9238-40 AD9238-20 - Datasheet Archive

 

Dual A/D Converter AD9238 APPLICATIONS Ultrasound Equipment IF Sampling in Communications Receivers: IS-95, CDMA-ONE, IMT-2000

 

12-Bit, 20/40/65 MSPS Dual A/D Converter AD9238 AD9238 APPLICATIONS Ultrasound Equipment IF Sampling in Communications Receivers: IS-95 IS-95, CDMA-ONE, IMT-2000 IMT-2000 Battery-Powered Instruments Hand-Held Scopemeters Low Cost Digital Oscilloscopes FUNCTIONAL BLOCK DIAGRAM DRVDD AVDD VIN­_A OEB_A OTR_A SHA A/D REFT_A REFB_A O/P BUFFERS VIN+_A CLOCK DUTY CYCLE STABILIZER VREF SENSE 0.5V MODE SELECT AGND REFT_B VIN­_B VIN+_B D11_A D0_A MUX_SELECT CLK_A CLK_B DCS DFS PDWN_A PDWN_B SHARED_REF OEB_B OTR_B REFB_B SHA A/D AGND O/P BUFFERS FEATURES Integrated Dual 12-Bit Analog to Digital Converters Single 3 V Supply Operation (2.7 V to 3.6 V) SNR = 70 dBc (to Nyquist, AD9238-65 AD9238-65) SFDR = 85 dBc (to Nyquist, AD9238-65 AD9238-65) Low Power: 600 mW at 65 MSPS Differential Input with 500 MHz 3 dB Bandwidth On-Chip Reference and SHA Flexible Analog Input: 1 V p-p to 2 V p-p Range Offset Binary or Twos Complement Data Format Clock Duty Cycle Stabilizer D11_B D0_B DRGND GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9238 AD9238 is a dual, 3 V, 12-bit, 20/40/65 MSPS analog-todigital converter. It features dual high performance sample-andhold amplifiers and an integrated voltage reference. The AD9238 AD9238 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy and guarantee no missing codes over the full operating temperature range at up to 65 MSPS data rates. 1. Integrated, dual version of the AD9235-a 12-bit, 20 MSPS/40 MSPS/40 MSPS/65 MSPS/65 MSPS ADC. The wide bandwidth, differential SHA allows for a variety of user selectable input ranges and offsets including single-ended applications. It is suitable for various applications including multiplexed systems that switch full-scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate. The AD9238 AD9238 is suitable for applications in communications, imaging, and medical ultrasound. Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available on the AD9238-65 AD9238-65 and can compensate for wide variations in the clock duty cycle, allowing the converters to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format. Out-of-range signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9238 AD9238 is available in a space saving 64-lead LQFP and is specified over the industrial temperature range (­40°C to +85°C). 2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS allow flexibility between power, cost, and performance to suit an application. 3. The AD9238 AD9238 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. 4. Low power consumption: AD9238-65 AD9238-65 operating at 65 MSPS consumes a low 600 mW. AD9238-40 AD9238-40 operating at 40 MSPS consumes a low 330 mW. AD9238-20 AD9238-20 operating at 20 MSPS consumes a low 180 mW. 5. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz and can be configured for single-ended or differential operation. 6. Typical channel isolation of 80 dB @ fIN = 10 MHz. 7. The clock duty cycle stabilizer (AD9238-65 AD9238-65 only) maintains performance over a wide range of clock duty cycles. 8. The OTR output bits indicate when either input signal is beyond the selected input range. 9. Multiplexed data output option enables single-port operation from either data port A or data port B. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD9238 AD9238­SPECIFICATIONS (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = ­0.5 dBFS Differential Input, MIN to TMAX, unless otherwise noted.) DC SPECIFICATIONS 1.0 V Internal Reference, T Parameter Test Temp Level AD9238BST-20 AD9238BST-20 Min Typ Max AD9238BST-40 AD9238BST-40 Min Typ Max AD9238BST-65 AD9238BST-65 Min Typ Max Unit RESOLUTION Full VI 12 12 12 Bits Full Full Full Full 25C Full 25C VI VI IV V V VI I 12 TEMPERATURE DRIFT Offset Error Gain Error1 Full Full V V ±2 ± 12 INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA Full Full Full Full VI V V V ±5 0.8 ± 2.5 0.1 INPUT REFERRED NOISE Input Span = 1 V Input Span = 2.0 V 25°C 25°C V V 0.54 0.27 0.54 0.27 0.54 0.27 LSB rms LSB rms ANALOG INPUT Input Span = 1.0 V Input Span = 2.0 V Input Capacitance3 Full Full Full IV IV V 1 2 7 1 2 7 1 2 7 V p-p V p-p pF REFERENCE INPUT RESISTANCE Full V 7 7 7 k Full Full IV IV Full Full Full V V V 60 4 ± 0.01 Full Full Full V VI V 180 190 2.0 V V ± 0.1 ± 0.05 ACCURACY No Missing Codes Guaranteed Offset Error Gain Error1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL) 2 POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD2 IDRVDD2 PSRR POWER CONSUMPTION DC Input4 Sine Wave Input2 Standby Power5 MATCHING CHARACTERISTICS Offset Error Full Gain Error Full 2.7 2.25 ± 0.30 ± 0.30 ± 0.35 ± 0.35 ± 0.45 ± 0.40 3.0 3.0 ± 1.2 ± 2.2 12 ± 0.9 ± 1.4 ± 0.50 ± 0.50 ± 0.35 ± 0.35 ± 0.60 ± 0.50 ± 1.1 ± 2.4 12 ± 0.8 ± 1.4 ±2 ± 12 ± 35 3.6 3.6 ±5 0.8 ± 2.5 0.1 2.7 2.25 3.0 3.0 330 360 2.0 ± 0.1 ± 0.05 Bits % FSR % FSR LSB ± 1.0 LSB LSB ± 1.75 LSB ± 1.1 ± 2.5 ±3 ± 12 ± 35 3.6 3.6 110 10 ± 0.01 212 ± 0.50 ± 0.50 ± 0.35 ± 0.35 ± 0.70 ± 0.55 ±5 0.8 ± 2.5 0.1 2.7 2.25 3.0 3.0 ppm/°C ppm/°C ± 35 3.6 3.6 200 14 ± 0.01 397 600 640 2.0 ± 0.1 ± 0.05 mV mV mV mV V V mA mA % FSR 698 mW mW mW % FSR % FSR NOTES 1 Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 2 for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND). Specifications subject to change without notice. ­2­ REV. 0 AD9238 AD9238 (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLKIN1 = CLKIN2; AIN = ­0.5 dBFS Differential Input, MIN to TMAX, unless otherwise noted.) DC SPECIFICATIONS 1.0 V Internal Reference, T Parameter Test Temp Level AD9238BST-20 AD9238BST-20 Min Typ Max AD9238BST-40 AD9238BST-40 Min Typ Max AD9238BST-65 AD9238BST-65 Min Typ Max LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Full Full Full Full Full IV IV IV IV V 2.0 2.0 2.0 Full IV 3.29 3.29 3.29 V Full IV 3.25 3.25 3.25 V Full IV 0.05 0.05 0.05 V Full IV 0.2 0.2 0.2 V Full IV 2.49 2.49 2.49 V Full IV 2.45 2.45 2.45 V Full IV 0.05 0.05 0.05 V Full IV 0.2 0.2 0.2 V LOGIC OUTPUTS* DRVDD = 3.3 V High Level Output Voltage (IOH = 50 A) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 50 A) Low Level Output Voltage (IOL = 1.6 mA) DRVDD = 2.5 V High Level Output Voltage (IOH = 50 A) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 50 A) Low Level Output Voltage (IOL = 1.6 mA) 0.8 +10 +10 ­10 ­10 0.8 +10 +10 ­10 ­10 2 0.8 +10 +10 ­10 ­10 2 2 Unit V V µA µA pF *Output Voltage Levels measured with 5 pF load on each output. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Parameter Test Temp Level AD9238BST-20 AD9238BST-20 Min Typ Max AD9238BST-40 AD9238BST-40 Min Typ Max AD9238BST-65 AD9238BST-65 Min Typ Max SWITCHING PERFORMANCE Max Conversion Rate Min Conversion Rate CLK Period CLK Pulsewidth High1 CLK Pulsewidth Low1 Full Full Full Full Full VI V V V V 20 40 65 DATA OUTPUT PARAMETERS Output Delay2 (tPD) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (tJ) Wake-Up Time3 Full Full Full Full Full V V V V V 3.5 7 1.0 0.5 2.5 3.5 7 1.0 0.5 2.5 3.5 7 1.0 0.5 2.5 ns Cycles ns ps rms ms OUT-OF-RANGE RECOVERY TIME Full V 1 1 2 Cycles 1 1 50.0 15.0 15.0 1 25.0 8.8 8.8 15.4 6.2 6.2 NOTES 1 The AD9238-65 AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycle (See TPC 20). 2 Output delay is measured from CLOCK 50% transition to DATA 50% transition, with 5 pF load on each output. 3 Wake-up time is dependent on value of decoupling capacitors, typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. Specifications subject to change without notice. N N+1 N+8 N+2 N­1 N+3 ANALOG INPUT N+7 N+4 N+5 N+6 CLOCK DATA OUT N­9 N­8 N­7 N­6 N­5 N­4 Figure 1. Timing Diagram REV. 0 ­3­ N­3 N­2 N­1 N tOD = 3.5ns TYP Unit MSPS MSPS ns ns ns AD9238 AD9238 (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = ­0.5 dBFS Differential Input, 1.0 V MIN to TMAX, unless otherwise noted.) AC SPECIFICATIONS Internal Reference, T Parameter SIGNAL-TO-NOISE RATIO fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz TOTAL HARMONIC DISTORTION fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz WORST HARMONIC (2nd or 3rd) fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz SPURIOUS FREE DYNAMIC RANGE fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz CROSSTALK Test Temp Level 25°C Full 25°C Full 25°C Full 25°C 25°C V V IV V IV V IV V 25°C Full 25°C Full 25°C Full 25°C 25°C V V IV V IV V IV V 25°C Full 25°C Full 25°C Full 25°C 25°C AD9238BST-20 AD9238BST-20 Min Typ Max AD9238BST-40 AD9238BST-40 Min Typ Max AD9238BST-65 AD9238BST-65 Min Typ Max 70.4 70.2 70.4 70.4 70.3 69.7 69.7 68.7 69.3 dBc dBc dBc dBc dBc dBc dBc dBc 70.1 70.3 68.3 69.3 69.5 67.6 70.2 70.1 70.2 70.2 70.4 68.7 69.4 dBc dBc dBc dBc dBc dBc dBc dBc 69.9 70.1 67.9 67.9 68.9 69.1 66.6 V V I V I V I V ­83.0 ­81.0 ­83.0 ­83.0 ­83.0 Full Full Full V V V ­84.0 25°C Full 25°C Full 25°C Full 25°C 25°C V V I V I V I V 86.0 84.0 86.0 Full V 68.1 ­74.6 ­81.0 ­83.0 ­77.0 ­75.5 ­78.0 ­80.0 ­74.0 ­79.0 ­85.0 ­80.0 76.1 86.0 76.7 86.0 85.0 86.0 79.0 81.0 80.0 83.0 75.0 ­80 ­80 ­80 72.5 Unit ­71.7 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB Specifications subject to change without notice. ­4­ REV. 0 AD9238 AD9238 ABSOLUTE MAXIMUM RATINGS 1 Pin Name ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF, OEB, DFS VINA, VINB VREF SENSE REFB, REFT PDWN EXPLANATION OF TEST LEVELS With Respect To Min Max Unit AGND DRGND DRGND DRVDD DRGND ­0.3 ­0.3 ­0.3 ­3.9 ­0.3 +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 V V V V V AGND AGND AGND AGND AGND AGND ­0.3 ­0.3 ­0.3 ­0.3 ­0.3 ­0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 V V V V V V ­45 +85 +150 +300 +150 °C °C °C °C ENVIRONMENTAL2 Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature ­65 I 100% production tested. II 100% production tested at +25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at +25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances (64-lead LQFP); JA = 54°C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7 EIA/JESD51-7. ORDERING GUIDE Model Temperature Range Package Description Package Option AD9238BST-20 AD9238BST-20 AD9238BST-40 AD9238BST-40 AD9238BST-65 AD9238BST-65 AD9238-20PCB AD9238-20PCB AD9238-40PCB AD9238-40PCB AD9238-65PCB AD9238-65PCB ­40°C to +85°C ­40°C to +85°C ­40°C to +85°C 64-Lead Low Profile Quad Flat Pack (LQFP) 64-Lead Low Profile Quad Flat Pack (LQFP) 64-Lead Low Profile Quad Flat Pack (LQFP) Evaluation Board with AD9238BST-20 AD9238BST-20 Evaluation Board with AD9238BST-40 AD9238BST-40 Evaluation Board with AD9238BST-65 AD9238BST-65 ST-64 ST-64 ST-64 ST-64 ST-64 ST-64 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9238 AD9238 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 ­5­ AD9238 AD9238 D6_A D5_A DRVDD D7_A DRGND D9_A D8_A D10_A OTR_A D11_A (MSB) PDWN_A OEB_A SHARED_REF MUX_SELECT AVDD CLK_A PIN CONFIGURATION 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGND 1 VIN+_A 2 48 D4_A 47 D3_A PIN 1 IDENTIFIER VIN­_A 3 46 D2_A AGND 4 45 D1_A AVDD 5 44 D0_A REFT_A REFB_A VREF SENSE REFB_B 6 43 DNC 7 42 DNC AD9238 AD9238 8 41 DRVDD 64-LEAD 64-LEAD LQFP TOP VIEW (Not to Scale) 9 10 40 DRGND 39 OTR_B REFT_B 11 AVDD 12 38 D11_B (MSB) 37 D10_B AGND 13 VIN­_B 14 36 D9_B VIN+_B 15 AGND 16 34 D7_B 35 D8_B 33 D6_B D5_B D4_B D3_B DRVDD DRGND D2_B D1_B D0_B DNC DNC OEB_B PDWN_B DCS DFS AVDD CLK_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DNC = DO NOT CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Name Description 2 3 15 14 6 7 11 10 8 9 18 63 19 20 21 60 22 59 44­51, 54­57 25­27, 30­38 39 58 62 VIN+_A VIN­_A VIN+_B VIN­_B REFT_A REFB_A REFT_B REFB_B VREF SENSE CLK_B CLK_A DCS DFS PDWN_B PDWN_A OEB_B OEB_A D0_A (LSB)­D11_A (MSB) D0_B (LSB)­D11_B (MSB) OTR_B OTR_A SHARED_REF 61 MUX_SELECT 5, 12, 17, 64 1, 4, 13, 16 28, 40, 53 29, 41, 52 AVDD AGND DRGND DRVDD 23, 24, 42, 43 DNC Analog Input Pin (+) for Channel A Analog Input Pin (­) for Channel A Analog Input Pin (+) for Channel B Analog Input Pin (­) for Channel B Differential Reference (+) for Channel A Differential Reference (­) for Channel A Differential Reference (+) for Channel B Differential Reference (­) for Channel B Voltage Reference Input/Output Reference Mode Selection Clock Input Pin for Channel B Clock Input Pin for Channel A Enable Duty Cycle Stabilizer (DCS) Mode Data Output Format select bit (Low for Offset Binary, High for Twos Complement) Power-Down Function Selection for Channel B (Active High) Power-Down Function Selection for Channel A (Active High) Output Enable Bit for Channel B Output Enable Bit for Channel A (Low Setting Enables Channel A Output Data Bus) Channel A Data Output Bits Channel B Data Output Bits Out of Range Indicator for Channel B Out of Range Indicator for Channel A Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode) Data Multiplexed Mode (See description for how to enable; high setting disables output data Multiplexed mode) Analog Power Supply Analog Ground Digital Output Ground Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor. Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF. Do Not Connect Pins. Should be left floating. ­6­ REV. 0 AD9238 AD9238 AVDD DRVDD D11_A ­ D0_A D11_B ­ D0_B OTR_A, OTR_B VIN+_A, VIN­_A, VIN+_B, VIN­_B, Figure 3. Equivalent Digital Output Circuit Figure 2. Equivalent Analog Input Circuit AVDD CLK_A, CLK_B DCS, DFS, MUX_SELECT SHARED_REF Figure 4. Equivalent Digital Input Circuit REV. 0 ­7­ AD9238 AD9238 DEFINITION OF TERMS Effective Number of Bits (ENOB) Aperture Delay Using the following formula: Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. ENOB = (SINAD - 1.76 ) 6.02 effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Aperture Jitter The variation in aperture delay for successive samples, which is manifested as noise on the input to the A/D converter. Signal-to-Noise Ratio (SNR) The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels relative to the peak carrier signal (dBc). Integral Nonlinearity (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Spurious Free Dynamic Range (SFDR) The difference in dB between the rms amplitude of the input signal and the peak spurious signal. Differential Nonlinearity (DNL, No Missing Codes) Nyquist Sampling An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. When the frequency components of the analog input are below the Nyquist frequency (fCLOCK/2), this is often referred to as Nyquist sampling. Offset Error IF Sampling The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN­. Offset error is defined as the deviation of the actual transition from that point. Due to the effects of aliasing, an ADC is not necessarily limited to Nyquist sampling. Higher sampled frequencies will be aliased down into the first Nyquist zone (DC ­ fCLOCK/2) on the output of the ADC. Care must be taken that the bandwidth of the sampled signal does not overlap Nyquist zones and alias onto itself. Nyquist sampling performance is limited by the bandwidth of the input SHA and clock jitter (jitter adds more noise at higher input frequencies). Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Temperature Drift The temperature drift for zero error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Out-of-Range Recovery Time Out-of-range recovery time is the time it takes for the A/D converter to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Power Supply Rejection The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Crosstalk Coupling onto one channel being driven by a (­0.5 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components. Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels relative to the peak carrier signal (dBc). Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels relative to the peak carrier signal (dBc). ­8­ REV. 0 Typical Performance Characteristics­AD9238 AD9238 0 100 95 ­20 SFDR 85 ­40 SFDR/SNR ­ dBc MAGNITUDE ­ dBFS 90 ­60 THIRD HARMONIC SECOND HARMONIC ­80 80 75 SNR 70 65 CROSSTALK 60 ­100 55 ­120 50 0 5 10 15 20 25 30 40 45 50 55 ADC SAMPLE RATE ­ MSPS FREQUENCY ­ MHz 60 65 TPC 4. AD9238-65 AD9238-65 Single-Tone SNR/SFDR vs. FS with fIN = 32.5 MHz TPC 1. Single-Tone FFT of Channel A Digitizing fIN = 12.5 MHz while Channel B is Digitizing fIN 10 MHz 0 100 95 ­20 90 SFDR/SNR ­ dBc dB SFDR SNR 85 ­40 SECOND HARMONIC ­60 CROSSTALK ­80 80 75 SNR SNR 70 65 60 ­100 55 ­120 0 5 10 15 20 FREQUENCY ­ Hz 25 50 20 30 25 40 30 35 ADC SAMPLE RATE ­ MSPS TPC 5. AD9238-40 AD9238-40 Single-Tone SNR/SFDR vs. FS with fIN = 20 MHz TPC 2. Single-Tone FFT of Channel A Digitizing fIN = 70 MHz while Channel B is Digitizing fIN 76 MHz 0 100 95 ­20 90 SFDR/SNR ­ dBc ­40 CROSSTALK dB SFDR 85 SECOND HARMONIC ­60 ­80 80 75 SNR 70 65 60 ­100 55 ­120 0 5 10 15 20 FREQUENCY ­ Hz 25 50 0.00E + 00 30 2.00E + 01 TPC 6. AD9238-20 AD9238-20 Single-Tone SNR/SFDR vs. FS with fIN = 10 MHz TPC 3. Single-Tone FFT of Channel A Digitizing fIN = 120 MHz while Channel B is Digitizing fIN = 126 MHz REV. 0 1.50E + 01 1.00E + 01 5.00E + 00 ADC SAMPLE RATE ­ MSPS ­9­ AD9238 AD9238 100 95 90 90 80 SFDR/SNR ­ dBc SFDR/SNR ­ dBc SFDR SNR 70 SNR 60 SNR SFDR 80 75 70 50 40 ­35 85 SNR 65 ­30 ­25 ­20 ­15 ­10 INPUT AMPLITUDE ­ dBFS ­5 0 0 TPC 7. AD9238-65 AD9238-65 Single-Tone SNR/SFDR vs. AIN with fIN = 32.5 MHz 20 40 60 80 100 INPUT FREQUENCY ­ MHz 120 140 TPC 10. AD9238-65 AD9238-65 Single-Tone SNR/SFDR vs. fIN 100 95 90 90 80 SNR SFDR SFDR/SNR ­ dBc SFDR/SNR ­ dBc SNR SFDR 70 SNR 60 85 80 75 SNR 70 50 40 ­35 65 ­30 ­25 ­20 ­15 ­10 INPUT AMPLITUDE ­ dBFS ­5 0 0 TPC 8. AD9238-40 AD9238-40 Single-Tone SNR/SFDR vs. AIN with fIN = 20 MHz 20 120 140 TPC 11. AD9238-40 AD9238-40 Single-Tone SNR/SFDR vs. fIN 95 100 90 90 SNR SFDR SFDR SNR 80 SFDR/SNR ­ dBc SFDR/SNR ­ dBc 40 60 80 100 INPUT FREQUENCY ­ MHz 70 SNR 60 85 80 75 SNR 70 50 40 ­35 65 ­30 ­25 ­20 ­15 ­10 INPUT AMPLITUDE ­ dBFS ­5 0 0 TPC 9. AD9238-20 AD9238-20 Single-Tone SNR/SFDR vs. AIN with fIN = 10 MHz 20 40 60 80 100 INPUT FREQUENCY ­ MHz 120 140 TPC 12. AD9238-20 AD9238-20 Single-Tone SNR/SFDR vs. fIN ­10­ REV. 0 AD9238 AD9238 0 100 SNR SFDR 95 ­20 SFDR/SNR ­ dBFS MAGNITUDE ­ dBFS 90 ­40 ­60 ­80 85 80 75 70 SNR ­100 65 ­120 0 5 10 15 20 FREQUENCY ­ MHz 25 60 ­24 30 TPC 13. Dual-Tone FFT with fIN1 = 45 MHz and fIN2 = 46 MHz ­21 ­18 ­15 ­12 INPUT AMPLITUDE ­ dBFS ­9 ­6 TPC 16. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz 100 0 SNR SFDR 95 ­20 MAGNITUDE ­ dBFS 90 SFDR/SNR ­ dBFS ­40 ­60 ­80 85 80 75 SNR 70 ­100 65 ­120 0 5 10 15 20 25 60 ­24 30 ­21 FREQUENCY ­ MHz ­9 ­6 TPC 17. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 70 MHz and fIN2 = 71 MHz TPC 14. Dual-Tone FFT with fIN1 = 70 MHz and fIN2 = 71 MHz 100 0 95 ­20 90 ­40 SFDR/SNR ­ dBFS MAGNITUDE ­ dBFS ­18 ­15 ­12 INPUT AMPLITUDE ­ dBFS ­60 ­80 SNR SFDR 85 80 75 SNR 70 ­100 65 ­120 0 5 10 15 20 25 60 ­24 30 FREQUENCY ­ MHz ­18 ­15 ­12 INPUT AMPLITUDE ­ dBFS ­9 TPC 18. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 200 MHz and fIN2 = 201 MHz TPC 15. Dual-Tone FFT with fIN1 = 200 MHz and fIN2 = 201 MHz REV. 0 ­21 ­11­ ­6 AD9238 AD9238 74 12 ­65 AVDD POWER ­ mW 600 SINAD ­ dBc 72 11.5 SINAD ­20 70 SINAD ­40 20 40 CLOCK FREQUENCY ­40 300 ­20 100 11 0 400 200 SINAD ­65 68 500 0 60 10 20 30 40 SAMPLE RATE ­ MSPS 50 60 TPC 19. SINAD vs. FS with Nyquist Input TPC 22. Analog Power Consumption vs. FS 95 1.0 DCS ON ­ SFDR 0.8 90 0.6 DCS OFF ­ SFDR 0.4 80 DCS ON ­ SINAD INL ­ LSB SINAD/SFDR ­ dBc 85 75 70 65 0 ­0.2 ­0.4 DCS OFF ­ SINAD 60 ­0.6 55 50 30 0.2 ­0.8 ­1.0 35 40 45 50 DUTY CYCLE ­ % 55 60 65 0 TPC 20. SINAD/SFDR vs. Clock Duty Cycle 1000 1500 2000 CODE 2500 3000 3500 4000 3500 4000 TPC 23. AD9238-65 AD9238-65 Typical INL 84 1.0 SFDR 82 0.8 0.6 80 0.4 78 DNL ­ LSB SINAD/SFDR ­ dB 500 76 74 72 0.2 0 ­0.2 ­0.4 70 ­0.6 SINAD 68 ­0.8 66 ­50 ­1.0 0 50 TEMPERATURE ­ C 100 0 TPC 21. SINAD/SFDR vs. Temperature with FIN = 32.5 MHz ­12­ 500 1000 1500 2000 CODE 2500 3000 TPC 24. AD9238-65 AD9238-65 Typical DNL REV. 0 AD9238 AD9238 THEORY OF OPERATION H The AD9238 AD9238 consists of two high performance analog-to-digital converters (ADCs) that are based on the AD9235 AD9235 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC's paths consists of a proprietary front end sample-and-hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined through the digital correction logic block into a final 12-bit result. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the respective clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage's input signal and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or single-ended modes. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. 5pF VIN+ CPAR T 5pF VIN­ CPAR T H Figure 5. Switched Capacitor Input An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as follows: REFT = 1 / 2 ( AVDD + VREF ) REFB = 1 / 2 ( AVDD - VREF ) Span = 2 × ( REFT - REFB ) = 2 × VREF It can be seen from the equations above that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V, or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance will be achieved with the AD9238 AD9238 set to the largest input span of 2 V p-p. The relative SNR degradation will be 3 dB when changing from 2 V p-p mode to 1 V p-p mode. ANALOG INPUT The analog input to the AD9238 AD9238 is a differential switched capacitor, SHA, that has been designed for optimum performance while processing a differential input signal. The SHA input accepts inputs over a wide common-mode range. An input common-mode voltage of midsupply is recommended to maintain optimal performance. The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as follows: The SHA input is a differential switched capacitor circuit. In Figure 5, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network will create a low-pass filter at the ADC's input; therefore, the precise values are dependant on the application. In IF undersampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN­ should be matched such that common-mode settling errors are symmetrical. These errors will be reduced by the common-mode rejection of the ADC. REV. 0 T T VCM MIN = VREF 2 VCM MAX = ( AVDD + VREF ) 2 The minimum common-mode input level allows the AD9238 AD9238 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source may be driven into VIN+ or VIN­. In this configuration, one input will accept the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+ while a 1 V reference is applied to VIN­. The AD9238 AD9238 will then accept an input signal varying between 2 V and 0 V. In the singleended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect will be less noticeable at lower input frequencies and in the lower speed grade models (AD9238-40 AD9238-40 and AD9238-20 AD9238-20). Differential Input Configurations As previously detailed, optimum performance will be achieved while driving the AD9238 AD9238 in a differential input configuration. ­13­ AD9238 AD9238 For baseband applications, the AD8138 AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen Key filter topology to provide band limiting of the input signal. At input frequencies in the second Nyquist zone and above, the performance of most amplifiers will not be adequate to achieve the true performance of the AD9238 AD9238. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 6. 50 AVDD VINA 2V p-p 10pF 49.9 AD9238 AD9238 50 VINB 10pF 1k 0.1F AGND 1k Figure 6. Differential Transformer Coupling The signal characteristics must be considered when selecting a transformer. Most RF transformers will saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. Single-Ended Input Configuration A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there will be a degradation in SFDR and in distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. CLOCK INPUT AND CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9238 AD9238 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously may degrade performance significantly. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD9238 AD9238's separate clock inputs allow for clock timing skew (typically ± 1 ns) between the channels without significant performance degradation. The AD9238-65 AD9238-65 contains two clock duty cycle stabilizers, one for each converter that retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle (DCS is not available on the ­40 MSPS or ­20 MSPS versions). Input clock rates of over 40 MHz can use the DCS so that a wide range of input clock duty cycles can be accommodated. Maintaining a 50% duty cycle clock is particularly important in high speed applications, when proper track-and-hold times for the converter are required to maintain high performance. The DCS can be enabled by tying the DCS pin high. The duty cycle stabilizer utilizes a delay locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency will require approximately 2 to 3 microseconds to allow the DLL to acquire and settle to the new rate. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated with the following equation: [ SNR degradation = 20 × log 10 1 / 2 × × fINPUT × t J ] In the equation, the rms aperture jitter, tJ, represents the rootsum-square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. The clock input is a digital signal that should be treated as an analog signal with logic level threshold voltages, especially in cases where aperture jitter may affect the dynamic range of the AD9238 AD9238. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. POWER DISSIPATION AND STANDBY MODE The power dissipated by the AD9238 AD9238 is proportional to its sampling rates. The digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by: IDRVDD = VDRVDD × CLOAD × fCLOCK × N where N is the number of bits changing and CLOAD is the average load on the digital pins that changed. The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases with clock frequency. Either channel of the AD9238 AD9238 can be placed in standby mode independently by asserting the PWDN_A or PDWN_B pin. It is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which will result in a typical power consumption of 1 mW for the ADC. Note: if DCS is enabled, it is mandatory to disable the clock of an independently powered-down channel. Otherwise, significant distortion will result on the active channel. If the clock inputs remain active while in total standby mode, the typical power dissipation of 12 mW will result. The minimum standby power is achieved when both channels are placed in full power-down mode (PDWN_A = PDWN_B = HI). Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time will be directly related to the recharging of the REFT and REFB decoupling capacitors and the duration of the power-down. Typically, it takes approximately 5 ms to restore full operation with fully discharged 0.1 µF and 10 µF decoupling capacitors on REFT and REFB. A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain ­14­ REV. 0 AD9238 AD9238 powered. Because the buffer and voltage reference remain powered, the wake-up time is reduced to several clock cycles. The output data from the dual A/D converters can be multiplexed onto a single 12-bit output bus. The multiplexing is accomplished by toggling the MUX_SELECT bit, which directs channel data to the same or opposite channel data port. When MUX_SELECT is logic high, the Channel A data is directed to Channel A output bus, and channel B data is directed to the Channel B output bus. When MUX_SELECT is logic low, the channel data is reversed, i.e., channel A data is directed to Channel B out bus and channel B data is directed to the Channel A output bus. By toggling the MUX_SELECT bit, multiplexed data is available on either of the output data ports. DIGITAL OUTPUTS The AD9238 AD9238 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan-outs may require external buffers or latches. If the ADCs are run with synchronized timing, this same clock can be applied to the MUX_SELECT bit. After the MUX_SELECT rising edge either data port will have the data for its respective channel, and after the falling edge the alternate channels data will be placed on the bus. Typically, the other unused bus would be disabled by setting the appropriate OEB high to reduce power consumption and noise. Figure 7 shows an example of multiplex mode. When multiplexing data, the data rate is two times the sample rate. The data format can be selected for either offset binary or twos complement. This is discussed later in the Data Format section. TIMING The AD9238 AD9238 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 1 for a detailed timing diagram. The internal duty cycle stabilizer can be enabled on the AD9238-65 AD9238-65 using the DCS pin. This provides a stable 50% duty cycle to internal circuits. VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD9238 AD9238. The input range can be adjusted by varying the reference voltage applied to the AD9238 AD9238, using either the internal reference with different external resistor configurations or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9238 AD9238. These transients can detract from the converter's dynamic performance. The lowest typical conversion rate of the AD9238 AD9238 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade. If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage). DATA FORMAT A Shared Reference mode allows the user to connect the references from the dual ADCs together externally for superior gain and offset matching performance. If the ADCs are to function independently, the reference decoupling can be treated independently and provide superior isolation between the dual channels. To enable the Shared Reference mode, the SHARED_REF pin must be tied high and external differential references must be externally shorted. (REFT_A must be externally shorted to REFT_B and REFB_A must be shorted to REFB_B.) The AD9238 AD9238 data output format can be configured for either twos complement or offset binary. This is controlled by the Data Format Select pin (DFS). Connecting DFS to AGND will produce offset binary output data. Conversely, connecting DFS to AVDD will format the output data as twos complement. A1 A0 A­1 A7 A3 A4 B1 B0 B­1 ANALOG INPUT ADC A A8 A2 A6 A5 B8 B2 ANALOG INPUT ADC B B7 B3 B4 B6 B5 CLK_A = CLK_B = MUX_SELECT B­8 A­7 tODF B­7 A­6 B­6 A­5 B­5 A­4 B­4 A­3 B­3 A­2 B­2 A­1 B­1 A0 B0 A1 D0_A ­D11_A tODR Figure 7. Example of Multiplexed Data Format Using the Channel A Output Port and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT REV. 0 ­15­ AD9238 AD9238 Table I. Reference Configuration Summary Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p) External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference AVDD VREF 0.2 V to VREF AGND to 0.2 V N/A 0.5 0.5 (1 + R2/R1) 1.0 2 External Reference 1.0 2 VREF (See Figure 7) 2.0 Internal Reference Connection External Reference Operation A comparator within the AD9238 AD9238 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table I. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 7), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected as shown in Figure 8, the switch will again be set to the SENSE pin. This will put the reference amplifier in a noninverting mode with the VREF output defined as follows: The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. A high precision external reference may also be selected to provide lower gain and offset temperature drift. Figure 10 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. VREF = 0.5 × (1 + R2 R1) In all reference configurations, REFT and REFB drive the ADC core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. VIN+ When the SENSE pin is tied to AVDD, the internal reference will be disabled, allowing the use of an external reference. An internal reference buffer will load the external reference with an equivalent 7 k load. The internal buffer will still generate the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span will always be twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V. If the internal reference of the AD9238 AD9238 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 11 depicts how the internal reference voltage is affected by loading. VIN­ REFT VIN+ 0.1F ADC CORE 0.1F VIN­ 10F REFT REFB 0.1F 0.1F ADC CORE 0.1F 10F REFB VREF 0.1F 10F 0.1F SELECT LOGIC 0.5V SENSE VREF 10F 0.1F R2 SELECT LOGIC 0.5V SENSE AD9238 AD9238 R1 Figure 8. Internal Reference Configuration AD9238 AD9238 Figure 9. Programmable Reference Configuration ­16­ REV. 0 AD9238 AD9238 1.2 0.05 1.0 0 0.8 ­0.05 ERROR ­ % VREF ERROR ­ % VREF = 1V VREF = 0.5V 0.6 0.5V ERROR ­0.10 1V ERROR 0.4 ­0.15 0.2 ­0.20 0 ­40 ­30 ­20 ­10 ­0.25 0 10 20 30 40 50 TEMPERATURE ­ C 60 70 80 0.5 0 Figure 10. Typical VREF Drift 1.0 1.5 LOAD ­ mA 64-Lead Quad Flat Pack [LQFP] (ST-64 ST-64) Dimensions shown in millimeters 0.75 0.60 0.45 9.00 BSC 1.60 MAX 64 49 1 48 SEATING PLANE TOP VIEW 7.00 BSC (PINS DOWN) 0.15 0.05 0.20 0.09 SEATING PLANE 7 3.5 0 0.08 MAX COPLANARITY VIEW A 16 33 32 17 0.40 BSC VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026BBD MS-026BBD REV. 0 2.5 Figure 11. VREF Accuracy vs. Load OUTLINE DIMENSIONS 1.45 1.40 1.35 2.0 ­17­ 0.23 0.18 0.13 3.0 ­18­ ­19­ ­20­ PRINTED IN U.S.A. C02640 C02640­0­2/03(0)