AD9125 CDMA2000 ADL5375-15 16-BIT AVDD33 DVDD18 CVDD18 125MSPS 250MSPS - Datasheet Archive

 

TxDAC+ Digital-to-Analog Converter AD9125 FEATURES GENERAL DESCRIPTION Flexible CMOS interface allows dual-word, word, or byte

 

Dual, 16-Bit, 1000 MSPS, TxDAC+ Digital-to-Analog Converter AD9125 AD9125 FEATURES GENERAL DESCRIPTION Flexible CMOS interface allows dual-word, word, or byte load Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 to 50 Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Gain and phase adjustment for sideband suppression Multichip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter Low power: 900 mW at 500 MSPS, full operating conditions 72-lead, exposed paddle LFCSP The AD9125 AD9125 is a dual, 16-bit, high dynamic range TxDAC+® digital-to-analog converter (DAC) that provides a sample rate of 1000 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface allows programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9125 AD9125 comes in a 72-lead LFCSP. APPLICATIONS PRODUCT HIGHLIGHTS Wireless infrastructure W-CDMA, CDMA2000 CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point Cable modem termination systems 1. 2. 3. 4. Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. The flexible CMOS digital interface allows the standard 32-wire bus to be reduced to a 16-wire bus. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF DC fIF LO ­ fIF 2 2/4 I DAC SIN DIGITAL BASEBAND PROCESSOR ANTIALIASING FILTER AQM PA COS 2/4 Q DAC LO 09016-001 2 NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. AD9125 AD9125 TABLE OF CONTENTS Features . 1 NCO Modulation . 35 Applications . 1 Datapath Configuration . 35 General Description . 1 Determining Interpolation Filter Modes . 36 Product Highlights . 1 Datapath Configuration Example . 37 Typical Signal Chain. 1 Data Rates vs. Interpolation Modes . 38 Revision History . 2 Coarse Modulation Mixing Sequences. 38 Functional Block Diagram . 3 Quadrature Phase Correction. 39 Specifications. 4 DC Offset Correction . 39 DC Specifications . 4 Inverse Sinc Filter . 39 Digital Specifications . 5 DAC Input Clock Configurations . 40 Latency and Power-Up Timing Specifications . 5 DAC Input Clock Configurations . 40 AC Specifications. 6 Analog Outputs. 42 Absolute Maximum Ratings. 7 Transmit DAC Operation. 42 Thermal Resistance . 7 Auxiliary DAC Operation . 43 ESD Caution . 7 Baseband Filter Implementation . 44 Pin Configuration and Function Descriptions . 8 Driving the ADL5375-15 ADL5375-15 . 44 Typical Performance Characteristics . 10 Reducing LO Leakage and Unwanted Sidebands . 44 Terminology . 16 Device Power Dissipation. 45 Theory of Operation . 17 Temperature Sensor . 46 Serial Port Operation . 17 Multichip Synchronization. 47 Data Format . 17 Synchronization with Clock Multiplication . 47 Serial Port Pin Descriptions . 17 Synchronization with Direct Clocking . 49 Serial Port Options . 18 Data Rate Mode Synchronization . 49 Device Configuration Register Map . 19 FIFO Rate Mode Synchronization . 50 Device Configuration Register Descriptions . 21 Additional Synchronization Features . 51 CMOS Input Data Ports . 29 Interrupt Request Operation . 52 Dual-Word Mode . 29 Interrupt Service Routine . 52 Word Mode . 29 Interface Timing Validation . 53 Byte Mode . 29 SED Operation. 53 Interface Timing . 30 SED Example . 53 FIFO Operation . 30 Example Start-Up Routine . 54 Digital Datapath. 32 Outline Dimensions . 55 Premodulation . 32 Ordering Guide . 55 Interpolation Filters . 32 REVISION HISTORY 6/10-Revision 0: Initial Version Rev. 0 | Page 2 of 56 AD9125 AD9125 FUNCTIONAL BLOCK DIAGRAM 1.2G DATA RECEIVER D[31:0] IOUT1P DAC 1 AUX 16-BIT 16-BIT 16 IOUT1N 16 FIFO fDATA /2 PRE MOD NCO AND MOD HB1 HB2 10 HB3 I OFFSET Q OFFSET INV SINC DACCLK 16 DCI 1.2G IOUT2N GAIN 2 GAIN 1 INVSINC_CLK PHASE CORRECTION INTP FACTOR HB3_CLK HB2_CLK HB1_CLK MODE 10 IOUT2P DAC 1 AUX 16-BIT 16-BIT 16 FRAME 10 REF AND BIAS REFIO FSADJ INTERNAL CLOCK TIMING AND CONTROL LOGIC DAC CLK_SEL PLL CONTROL POWER-ON RESET MULTICHIP SYNCHRONIZATION SYNC DACCLK CLOCK MULTIPLIER (2× TO 16×) DACCLKP DACCLKN CLK RCVR REFCLKP REFCLKN 09016-002 RESET CS IRQ SCLK SDO CLK RCVR 0 1 PLL_LOCK SDIO PROGRAMMING REGISTERS SERIAL INPUT/OUTPUT PORT Figure 2. AD9125 AD9125 Functional Block Diagram Rev. 0 | Page 3 of 56 AD9125 AD9125 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 AVDD33 = 3.3 V, DVDD18 DVDD18 = 1.8 V, CVDD18 CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Output Resistance Gain DAC Monotonicity Settling Time to Within ±0.5 LSB MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 AVDD33 CVDD18 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD18 DVDD18 IOVDD POWER CONSUMPTION 2× Mode, fDAC = 491.52 MSPS, IF = 10 MHz, PLL Off 2× Mode, fDAC = 491.52 MSPS, IF = 10 MHz, PLL On 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off AVDD33 AVDD33 CVDD18 CVDD18 DVDD18 DVDD18 Power-Down Mode Power Supply Rejection Ratio, AVDD33 AVDD33 OPERATING RANGE 1 Min Typ 16 Max ±2.1 ±3.7 -0.001 -3.6 8.66 -1.0 0 ±2 19.6 Unit Bits LSB LSB +0.001 +3.6 31.66 +1.0 10 Guaranteed 20 % FSR % FSR mA V M ns 0.04 100 30 ppm/°C ppm/°C ppm/°C 1.2 5 V k 3.13 1.71 3.3 1.8 3.47 1.89 V V 1.71 1.71 1.8 1.8/3.3 1.89 3.47 V V 1227 58 85 490 2.7 +0.3 +85 mW mW mW mA mA mA mW % FSR/V °C 834 913 1114 55 78 440 1.5 -0.3 -40 Based on a 10 k external resistor. Rev. 0 | Page 4 of 56 +25 AD9125 AD9125 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 DVDD18 = 1.8 V, CVDD18 CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter CMOS DATA INPUTS Input VIN Logic High Input VIN Logic Low Maximum Bus Speed SERIAL PORT OUTPUT LOGIC LEVELS Output VOUT Logic High Output VOUT Logic Low SERIAL PORT INPUT LOGIC LEVELS Input VIN Logic High Input VIN Logic Low DACCLK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage Maximum Clock Rate REFCLK INPUT (REFCLKP, REFCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage REFCLKx Frequency, PLL Mode REFCLKx Frequency, SYNC Mode SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High (tPWH) Minimum Pulse Width Low (tPWOL) Setup Time, SDI to SCLK (tDS) Hold Time, SDI to SCLK (tDH) Data Valid, SDO to SCLK (tDV) Setup Time, CS to SCLK (tDCS) Conditions Min Typ Max Unit 0.6 250 V V MHz IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 3.3 V IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 3.3 V 1.4 1.8 2.0 V V V IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 3.3 V IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 3.3V 1.2 1.6 2.4 1.2 0.4 0.4 0.4 0.6 0.8 0.8 100 V V V V V V V V 500 1.25 2000 mV V MHz 500 1.25 Self biased input, ac couple 2000 mV V MHz MHz 1000 100 1 GHz fVCO 2.1 GHz See the Multichip Synchronization section for conditions 15.625 0 600 600 40 12.5 12.5 1.9 0.2 2.3 1.4 LATENCY AND POWER-UP TIMING SPECIFICATIONS Table 3. Parameter LATENCY (DACCLK Cycles) 1× Interpolation (with or Without Modulation) 2× Interpolation (with or Without Modulation) 4× Interpolation (with or Without Modulation) 8× Interpolation (with or Without Modulation) Inverse Sinc Fine Modulation Power-Up Time Min Typ 64 135 292 608 20 8 260 Rev. 0 | Page 5 of 56 Max Unit Cycles Cycles Cycles Cycles Cycles Cycles ms MHz ns ns ns ns ns ns AD9125 AD9125 AC SPECIFICATIONS TMIN to TMAX, AVDD33 AVDD33 = 3.3 V, DVDD18 DVDD18 = 1.8 V, CVDD18 CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 100 MSPS, fOUT = 20 MHz fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 70 MHz fDAC = 800 MSPS, fOUT = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 60 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 100 MHz NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING fDAC = 200 MSPS, fOUT = 80 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 80 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz fDAC = 491.52 MSPS, fOUT = 122.88 MHz fDAC = 983.04 MSPS, fOUT = 122.88 MHz W-CDMA SECOND ACLR, SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz fDAC = 491.52 MSPS, fOUT = 122.88 MHz fDAC = 983.04 MSPS, fOUT = 122.88 MHz Min Typ Max 78 80 69 72 dBc dBc dBc dBc 84 86 84 81 dBc dBc dBc dBc -162 -163 -164 dBm/Hz dBm/Hz dBm/Hz 82 80 81 dBc dBc dBc 88 86 88 dBc dBc dBc Table 5. Interface Speeds Mode Byte Mode Word Mode Dual-Word Mode Interpolation 1× 2× (HB1) 2× (HB2) 4× 8× 1× 2× (HB1) 2× (HB2) 4× 8× 1× 2× (HB1) 2× (HB2) 4× 8× Unit fBUS 250 250 250 250 250 250 250 250 250 250 250 250 250 250 125 Rev. 0 | Page 6 of 56 fDATA 62.5 62.5 62.5 62.5 62.5 125 125 125 125 125 250 250 250 250 125 fDAC 62.5 125 125 250 500 125 250 250 500 1000 250 500 500 1000 1000 AD9125 AD9125 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter AVDD33 AVDD33 IOVDD DVDD18 DVDD18, CVDD18 CVDD18 AVSS EPAD CVSS DVSS FSADJ, REFIO, IOUT1P/IOUT1N, IOUT2P/IOUT2N D[31:0], FRAME, DCI DACCLKP/DACCLKN, REFCLKP/REFCLKN RESET, IRQ, CS, SCLK, SDIO, SDO Junction Temperature Storage Temperature Range The exposed paddle (EPAD) must be soldered to the ground plane for the 72-lead LFCSP. The EPAD performs as an electrical and thermal connection to the board. With Respect To AVSS, EPAD, CVSS, DVSS AVSS, EPAD, CVSS, DVSS AVSS, EPAD, CVSS, DVSS EPAD, CVSS, DVSS AVSS, CVSS, DVSS AVSS, EPAD, DVSS AVSS, EPAD, CVSS AVSS -0.3 V to AVDD33 AVDD33 + 0.3 V EPAD, DVSS DVSS -0.3 V to DVDD18 DVDD18 + 0.3 V -0.3 V to CVDD18 CVDD18 + 0.3 V EPAD, DVSS -0.3 V to IOVDD + 0.3 V Rating -0.3 V to +3.6 V Typical JA, JB, and JC values are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing JA and JB. -0.3 V to +3.6 V -0.3 V to +2.1 V Table 7. Thermal Resistance -0.3 V to +0.3 V Package 72-Lead LFCSP -0.3 V to +0.3 V -0.3 V to +0.3 V ESD CAUTION -0.3 V to +0.3 V 125°C -65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 56 JA 20.7 JB 10.9 JC 1.1 Unit °C/W Conditions EPAD soldered AD9125 AD9125 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 CVDD18 CVDD18 CVDD18 CVDD18 REFCLKP REFCLKN AVDD33 AVDD33 IOUT1P IOUT1N AVDD33 AVDD33 AVSS FSADJ REFIO AVSS AVDD33 AVDD33 IOUT2N IOUT2P AVDD33 AVDD33 AVSS NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9125 AD9125 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 RESET CS SCLK SDIO SDO DVDD18 DVDD18 D0 D1 D2 D3 DVSS DVDD18 DVDD18 D4 D5 D6 D7 D8 D9 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD MUST BE CONNECTED TO AVSS. 09016-003 D23 D22 D21 D20 D19 D18 D17 D16 DCI NC DVDD18 DVDD18 DVSS D15 D14 D13 D12 D11 D10 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 CVDD18 DACCLKP DACCLKN CVSS FRAME NC IRQ D31 D30 NC IOVDD DVDD18 DVDD18 D29 D28 D27 D26 D25 D24 Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Mnemonic CVDD18 CVDD18 DACCLKP DACCLKN CVSS FRAME NC IRQ (INT) D31 D30 NC IOVDD DVDD18 DVDD18 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 DCI Description 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. DAC Clock Input, Positive. DAC Clock Input, Negative. Clock Supply Common. Frame Input. No Connect Interrupt Request. Open Drain, Active Low Output. Connect external pull-up to IOVDD. Data Bit 31. Data Bit 30. No Connect. Supply for Serial Port Pin, RESET Pin, and IRQ Pin. 1.8 V to 3.3 V can be applied to this pin. 1.8 V Digital Supply. Supplies power to digital core and digital data ports. Data Bit 29. Data Bit 28. Data Bit 27. Data Bit 26. Data Bit 25. Data Bit 24. Data Bit 23. Data Bit 22. Data Bit 21. Data Bit 20. Data Bit 19. Data Bit 18. Data Bit 17. Data Bit 16. Data Clock Input. Rev. 0 | Page 8 of 56 AD9125 AD9125 Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Mnemonic NC DVDD18 DVDD18 DVSS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 DVDD18 DVDD18 DVSS D3 D2 D1 D0 DVDD18 DVDD18 SDO SDIO SCLK CS RESET NC AVSS AVDD33 AVDD33 IOUT2P IOUT2N AVDD33 AVDD33 AVSS REFIO FSADJ AVSS AVDD33 AVDD33 IOUT1N IOUT1P AVDD33 AVDD33 REFCLKN REFCLKP CVDD18 CVDD18 CVDD18 CVDD18 EPAD Description No Connect. 1.8 V Digital Supply. Digital Common. Data Bit 15. Data Bit 14. Data Bit 13. Data Bit 12. Data Bit 11. Data Bit 10. Data Bit 9. Data Bit 8. Data Bit 7. Data Bit 6. Data Bit 5. Data Bit 4. 1.8 V Digital Supply. Digital Supply Common. Data Bit 3. Data Bit 2. Data Bit 1. Data Bit 0. 1.8 V Digital Supply. Serial Port Data Output (CMOS levels with respect to IOVDD). Serial Port Data Input/Output (CMOS levels with respect to IOVDD). Serial Port Clock Input (CMOS levels with respect to IOVDD). Serial Port Chip Select. Active Low (CMOS levels with respect to IOVDD). Reset. Active Low (CMOS levels with respect to IOVDD). No Connect. Analog Supply Common. 3.3 V Analog Supply. Q DAC Positive Current Output. Q DAC Negative Current Output. 3.3 V Analog Supply. Analog Supply Common. Voltage Reference. Nominally 1.2 V output. Should be decoupled to analog common. Full-Scale Current Output Adjust. Place a 10 k resistor on the analog common. Analog Common. 3.3 V Analog Supply. I DAC Negative Current Output. I DAC Positive Current Output. 3.3 V Analog Supply. PLL Reference Clock Input, Negative. This pin has a secondary function as the SYNC input. PLL Reference Clock Input, Positive. This pin has a secondary function as the SYNC input. 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. Exposed pad must be connected to AVSS. This provides an electrical, thermal, and mechanical connection to the PCB. Rev. 0 | Page 9 of 56 AD9125 AD9125 TYPICAL PERFORMANCE CHARACTERISTICS 0 ­10 ­20 0dBFS ­6dBFS ­12dBFS ­18dBFS ­55 ­60 ­30 HARMONICS (dBc) HARMONICS (dBc) ­50 fDATA = 125MSPS 125MSPS, SECOND HARMONIC fDATA = 125MSPS 125MSPS, THIRD HARMONIC fDATA = 250MSPS 250MSPS, SECOND HARMONIC fDATA = 250MSPS 250MSPS, THIRD HARMONIC ­40 ­50 ­60 ­70 ­65 ­70 ­75 ­80 ­80 ­85 ­90 50 100 150 200 250 300 fOUT (MHz) 09016-101 0 200 250 300 0dBFS ­6dBFS ­12dBFS ­18dBFS ­55 ­60 ­30 ­40 ­50 ­60 ­70 ­65 ­70 ­75 ­80 ­85 ­80 ­90 ­90 ­95 100 200 300 400 500 600 fOUT (MHz) 09016-102 0 100 150 200 250 300 fOUT (MHz) ­50 fDATA = 125MSPS 125MSPS, SECOND HARMONIC fDATA = 125MSPS 125MSPS, THIRD HARMONIC ­10 50 Figure 8. Third Harmonic vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 250 MSPS, fSC = 20 mA Figure 5. Harmonics vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 0 09016-105 ­100 ­100 ­55 ­20 ­60 HARMONICS (dBc) ­30 ­40 ­50 ­60 ­70 ­65 ­70 ­75 ­80 10mA, 20mA, 30mA, 10mA, 20mA, 30mA, ­85 ­80 ­90 ­90 SECOND HARMONIC SECOND HARMONIC SECOND HARMONIC THIRD HARMONIC THIRD HARMONIC THIRD HARMONIC 0 100 200 300 400 500 fOUT (MHz) 600 0 50 100 150 200 250 fOUT (MHz) Figure 9. Harmonics vs. fOUT over fSC, 2× Interpolation, fDATA = 250 MSPS, Digital Scale = 0 dBFS Figure 6. Harmonics vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA Rev. 0 | Page 10 of 56 300 09016-106 ­95 ­100 09016-103 HARMONICS (dBc) 150 ­50 HARMONICS (dBc) HARMONICS (dBc) ­20 100 fOUT (MHz) fDATA = 125MSPS 125MSPS, SECOND HARMONIC fDATA = 125MSPS 125MSPS, THIRD HARMONIC fDATA = 250MSPS 250MSPS, SECOND HARMONIC fDATA = 250MSPS 250MSPS, THIRD HARMONIC ­10 50 Figure 7. Second Harmonic vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 250 MSPS, fSC = 20 mA Figure 4. Harmonics vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 0 09016-104 ­90 ­100 AD9125 AD9125 ­50 fDATA = 125MSPS 125MSPS fDATA = 250MSPS 250MSPS HIGHEST DIGITAL SPUR (dBc) ­55 2× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 250MSPS 250MSPS, fOUT = 101MHz ­60 ­65 ­70 ­75 ­80 ­85 0 50 100 150 200 250 300 fOUT (MHz) 09016-107 ­95 fDATA = 125MSPS 125MSPS fDATA = 250MSPS 250MSPS HIGHEST DIGITAL SPUR (dBc) ­55 VBW 10kHz STOP 500.0MHz SWEEP 6.017s (601 PTS) Figure 13. 2× Interpolation, Single-Tone Spectrum Figure 10. Highest Digital Spur vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA ­50 START 1.0MHz #RES BW 10kHz 09016-110 ­90 4× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 125MSPS 125MSPS, fOUT = 101MHz ­60 ­65 ­70 ­75 ­80 0 100 200 300 400 500 600 fOUT (MHz) 09016-108 ­90 fDATA = 125MSPS 125MSPS STOP 500.0MHz SWEEP 6.017s (601 PTS) 8× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 125MSPS 125MSPS, fOUT = 131MHz ­55 ­60 ­65 ­70 ­75 ­80 ­85 ­95 0 50 100 150 200 250 300 350 400 fOUT (MHz) START 1.0MHz #RES BW 10kHz VBW 10kHz STOP 1.0GHz SWEEP 12.05s (601 PTS) Figure 15. 8× Interpolation, Single-Tone Spectrum Figure 12. Highest Digital Spur vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA Rev. 0 | Page 11 of 56 09016-112 ­90 09016-109 HIGHEST DIGITAL SPUR (dBc) VBW 10kHz Figure 14. 4× Interpolation, Single-Tone Spectrum Figure 11. Highest Digital Spur vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA ­50 START 1.0MHz #RES BW 10kHz 09016-111 ­85 AD9125 AD9125 ­50 ­50 fDATA = 125MSPS 125MSPS fDATA = 250MSPS 250MSPS ­55 ­65 IMD (dBc) ­60 ­65 ­70 ­70 ­75 ­75 ­80 ­80 ­85 ­85 50 100 150 200 250 300 fOUT (MHz) 0 150 200 250 300 Figure 19. IMD vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 250 MSPS, fSC = 20 mA ­50 fDATA = 125MSPS 125MSPS fDATA = 250MSPS 250MSPS ­55 100 fOUT (MHz) Figure 16. IMD vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA ­50 50 09016-116 ­90 0 09016-113 ­90 20mA 30mA 10mA ­55 ­60 ­65 ­65 IMD (dBc) ­60 ­70 ­70 ­75 ­75 ­80 ­80 ­85 ­85 ­90 0 100 200 300 400 500 600 fOUT (MHz) 09016-114 ­90 0 100 150 200 250 300 fOUT (MHz) Figure 17. IMD vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA ­50 50 09016-117 IMD (dBc) ­60 IMD (dBc) 0dBFS ­6dBFS ­12dBFS ­18dBFS ­55 Figure 20. IMD vs. fOUT over fSC, 2× Interpolation, fDATA = 250 MSPS, Digital Scale = 0 dBFS ­40 fDATA = 125MSPS 125MSPS ­45 ­55 ­50 ­60 ­55 IMD (dBc) ­70 ­75 PLL ON ­60 ­65 PLL OFF ­70 ­75 ­80 ­80 ­85 ­85 ­90 0 100 200 300 400 500 fOUT (MHz) 600 Figure 18. IMD vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 50 100 150 200 250 fOUT (MHz) Figure 21. IMD vs. fOUT, PLL On vs. PLL Off Rev. 0 | Page 12 of 56 300 09016-118 ­90 09016-115 IMD (dBc) ­65 AD9125 AD9125 ­154 ­160 ­156 2×, fDATA = 250MSPS 250MSPS 4×, fDATA = 125MSPS 125MSPS 8×, fDATA = 125MSPS 125MSPS ­161 ­158 NSD (dBm/Hz) NSD (dBm/Hz) ­162 ­160 ­162 ­163 ­164 ­164 2×, fDATA = 250MSPS 250MSPS 4×, fDATA = 125MSPS 125MSPS 8×, fDATA = 125MSPS 125MSPS ­166 ­165 100 200 300 400 500 600 fOUT (MHz) 0 ­161.5 200 250 300 350 400 450 500 0dBFS ­6dBFS ­12dBFS ­18dBFS ­162.0 ­162.5 ­158 ­163.0 NSD (dBm/Hz) NSD (dBm/Hz) 150 Figure 25. Eight-Tone NSD vs. fOUT over Interpolation Rate and fDATA, Digital Scale = 0 dBFS, fSC = 20 mA, PLL Off 0dBFS ­6dBFS ­12dBFS ­18dBFS ­156 100 fOUT (MHz) Figure 22. One-Tone NSD vs. fOUT over Interpolation Rate and fDATA, Digital Scale = 0 dBFS, fSC = 20 mA, PLL Off ­154 50 09016-122 ­166 0 09016-119 ­168 ­160 ­162 ­163.5 ­164.0 ­164.5 ­165.0 ­164 ­165.5 ­166 ­166.0 ­168 100 150 200 250 fOUT (MHz) Figure 23. One-Tone NSD vs. fOUT over Digital Scale, fDATA = 200 MSPS, 4× Interpolation, fSC = 20 mA, PLL Off 0 50 100 150 200 250 fOUT (MHz) 09016-123 50 09016-120 ­166.5 0 Figure 26. Eight-Tone NSD vs. fOUT over Digital Scale, fDATA = 200 MSPS, 4× Interpolation, fSC = 20 mA, PLL Off ­158 ­160 8×, fDATA = 125MSPS 125MSPS 8×, fDATA = 125MSPS 125MSPS ­159 ­161 ­160 ­162 NSD (dBm/Hz) ­162 ­163 ­163 ­164 ­164 ­165 ­165 ­166 ­166 0 100 200 300 400 500 600 fOUT (MHz) Figure 24. One-Tone NSD vs. fOUT over Interpolation Rate and fDATA, Digital Scale = 0 dBFS, fSC = 20 mA, PLL On 0 100 200 300 400 500 600 fOUT (MHz) Figure 27. Eight-Tone NSD vs. fOUT over Interpolation Rate and fDATA, Digital Scale = 0 dBFS, fSC = 20 mA, PLL On Rev. 0 | Page 13 of 56 09016-124 ­167 ­167 09016-121 NSD (dBm/Hz) ­161 AD9125 AD9125 ­77 ­50 0dBFS ­3dBFS ­6dBFS ­78 ACLR (dBc) ­80 ­81 ­82 ­65 ­70 ­75 ­80 ­83 ­85 ­84 50 100 150 200 250 fOUT (MHz) 09016-125 ­90 0 Figure 28. One-Carrier W-CDMA ACLR vs. fOUT over Digital Cutback, Adjacent Channel, PLL Off 0 100 200 300 400 500 fOUT (MHz) 09016-128 ACLR (dBc) PLL OFF PLL OFF PLL ON PLL ON ­60 ­79 Figure 31. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation Rate, Adjacent Channel, PLL On vs. PLL Off ­78 ­70 0dBFS ­3dBFS ­6dBFS ­80 2×, 4×, 2×, 4×, ­72 ­74 PLL OFF PLL OFF PLL ON PLL ON ­76 ACLR (dBc) ­82 ACLR (dBc) 2×, 4×, 2×, 4×, ­55 ­84 ­86 ­78 ­80 ­82 ­84 ­86 ­88 ­88 ­90 100 150 200 250 fOUT (MHz) Figure 29. One-Carrier W-CDMA ACLR vs. fOUT over fDAC, Alternate Channel, PLL Off 0 200 300 400 500 fOUT (MHz) Figure 32. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation Rate, Alternate Channel, PLL On vs. PLL Off ­70 ­70 2×, 4×, 2×, 4×, 0dBFS ­3dBFS ­6dBFS ­75 ACLR (dBc) ­75 ­80 ­85 ­90 PLL OFF PLL OFF PLL ON PLL ON ­80 ­85 ­90 ­95 0 50 100 150 200 fOUT (MHz) Figure 30. One-Carrier W-CDMA ACLR vs. fOUT over fDAC, Second Alternate Channel, PLL Off 250 0 100 200 300 fOUT (MHz) 400 500 09016-130 ­95 09016-127 ACLR (dBc) 100 09016-129 50 09016-126 ­90 0 Figure 33. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation Rate, Second Alternate Channel, PLL On vs. PLL Off Rev. 0 | Page 14 of 56 AD9125 AD9125 FREQ OFFSET 5.00MHz 10.00MHz 15.00MHz REF BW 3.840MHz 3.840MHz 2.888MHz LOWER dBc dBm ­75.96 ­85.96 ­85.33 ­95.33 ­95.81 ­95.81 UPPER dBc dBm ­77.13 ­87.13 ­85.24 ­95.25 ­85.43 ­95.43 VBW 30kHz STOP 174.42MHz SWEEP 206.9ms (601 PTS) TOTAL CARRIER POWER: ­11.19dBm/15.3600MHz RRC FILTER: OFF FILTER ALPHA 0.22 REF CARRIER POWER: ­16.89dBm/3.84000MHz 1 2 3 4 Figure 34. Four-Carrier W-CDMA ACLR Performance, IF 150 MHz ­16.92dBm ­16.89dBm ­17.43dBm ­17.64dBm OFFSET FREQ 5.000MHz 10.00MHz 15.00MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz LOWER dBc dBm ­65.88 ­82.76 ­68.17 ­85.05 ­70.42 ­87.31 UPPER dBc dBm ­67.52 ­84.40 ­69.91 ­86.79 ­71.40 ­88.28 09016-132 RMS RESULTS CARRIER POWER ­10.00dBm/ 3.840MHz START 125.88MHz #RES BW 30kHz VBW 30kHz STOP 166.94MHz SWEEP 143.6ms (601 PTS) 09016-131 START 133.06MHz #RES BW 30kHz Figure 35. One-Carrier W-CDMA ACLR Performance, IF 150 MHz Rev. 0 | Page 15 of 56 AD9125 AD9125 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Settling Time The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Spurious-Free Dynamic Range (SFDR) The difference in decibels between the peak amplitude of the output signal and the peak spurious signal within the dc to the Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output. Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUT1P, 0 mA output is expected when the inputs are all 0s. For IOUT1N, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the difference between the outputs when all inputs are set to 1 vs. when all inputs are set to 0. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Adjacent Channel Leakage Ratio (ACLR) The ratio in decibels relative to the carrier (dBc) between the measured power within a channel and that of its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Power Supply Rejection (PSR) The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. 16 16 2 LATCH INPUT DATA FORMAT 32 2 2 2 SIN NCO COS FIFO 16 16 2 DCI WRITE POINTER fINTERFACE I DAC READ POINTER fDATA /fHB1 CLOCK GENERATOR AND DISTRIBUTOR fNCO /fHB2 Figure 36. Defining Data Rates Rev. 0 | Page 16 of 56 Q DAC fHB3 DACCLK fDAC 09016-136 DATA 2 AD9125 AD9125 THEORY OF OPERATION The AD9125 AD9125 combines many features that make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband transmitters. The speed and performance of the AD9125 AD9125 allows wider bandwidths and more carriers to be synthesized than in previously available DACs. In addition, these devices include an innovative low power, 32-bit, complex NCO that greatly increases the ease of frequency placement. The AD9125 AD9125 offers features that allow simplified synchronization with incoming data and between multiple devices. Auxiliary DACs are also provided on chip for output dc offset compensation (for local oscillator [LO] compensation in single sideband [SSB] transmitters) and for gain matching (for image rejection optimization in SSB transmitters). SERIAL PORT OPERATION The serial port is a flexible, synchronous serial communication port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9125 AD9125. Single- or multiple-byte transfers are supported, as well as MSBfirst or LSB-first transfer formats. The serial interface ports can be configured as a single-pin I/O (SDIO) or two unidirectional pins for input/output (SDIO/SDO). CS 53 SPI PORT 09016-010 SCLK 52 DATA FORMAT The instruction byte contains the information shown in Table 9. Table 9. Serial Port Instruction Byte I7 (MSB) R/W I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 I0 (LSB) A0 R/W, Bit 7 of the instruction byte, determines whether a read or write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation, and Logic 0 indicates a write operation. A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A6 is the starting byte address. The remaining register addresses are generated by the device based on the LSB_FIRST bit (Register 0x00, Bit 6). SERIAL PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. SDO 50 SDIO 51 The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word and NCO phase offsets, which only change when the frequency update bit (Register 0x36, Bit 0) is set. Chip Select (CS) Figure 37. Serial Port Interface Pins An active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communication lines. The SDO and SDIO pins go to a high impedance state when this input is high. During the communication cycle, the CS pin should stay low. There are two phases of a communication cycle with the AD9125 AD9125. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), which is coincident with the first eight SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the device. Serial Data I/O (SDIO) A logic high on the CS pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next eight rising SCLK edges represent the instruction bits of the current I/O operation. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the device operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, configuring the SDIO pin as unidirectional. Serial Data Out (SDO) Rev. 0 | Page 17 of 56 AD9125 AD9125 SERIAL PORT OPTIONS INSTRUCTION CYCLE The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by the LSB_FIRST bit (Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0). DATA TRANSFER CYCLE CS SCLK SDIO When LSB_FIRST = 1 (LSB-first), the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle. SCLK The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first mode is active. The serial port controller address increments from the data address written toward 0x7F for multibyte I/O operations if the LSB-first mode is active. R/W A6 A5 A4 A3 A2 A1 A0 D30 D20 D10 D00 D7 D6N D5N SDO D7 D6N D5N D30 D20 D10 D00 09016-011 When LSB_FIRST = 0 (MSB-first), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow from the high address to the low address. In MSB-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. Figure 38. Serial Register Interface Timing, MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CS A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4N D5N D6N D7N D00 D10 D20 D4N D5N D6N D7 N SDO 09016-012 SDIO Figure 39. Serial Register Interface Timing, LSB First tDS tSCLK CS tPWH tPWL tDS SDIO tDH INSTRUCTION BIT 7 INSTRUCTION BIT 6 09016-013 SCLK Figure 40. Timing Diagram for Serial Port Register Write (tDS to tDCS) CS tDV SDIO, SDO DATA BIT n DATA BIT n ­ 1 Figure 41. Timing Diagram for Serial Port Register Read Rev. 0 | Page 18 of 56 09016-014 SCLK AD9125 AD9125 DEVICE CONFIGURATION REGISTER MAP Table 10. Device Configuration Register Map Register Name Comm Power Control Addr (Hex) 0x00 0x01 Data Format 0x03 Interrupt Enable 1 0x04 Interrupt Enable 2 Bit 7 SDIO Powerdown DAC I Binary data format Enable PLL lock lost Bit 6 LSB_FIRST Powerdown DAC Q Q data first Bit 5 Reset Powerdown data receiver MSB swap Enable PLL lock 0x05 0 0 Enable sync signal lost 0 Event Flag 1 0x06 PLL lock lost PLL locked Event Flag 2 0x07 Clock Receiver Control 0x08 PLL Control 1 0x0A PLL Control 2 0x0C PLL Control 3 0x0D PLL Status 1 0x0E PLL Status 2 Sync Control 1 0x0F 0x10 Sync Control 2 0x12 Sync Status 2 0x18 FIFO Status 2 0x19 Datapath Control 0x1B HB1 Control Bit 0 Data bus width[1:0] Enable sync phase lock Enable AED compare fail Sync phase locked Enable soft FIFO sync Enable SED compare fail Soft FIFO sync AED compare pass REFCLK crosscorrection AED compare fail 1 SED compare fail 1 0x00 0 0 0x00 FIFO Warning 1 FIFO Warning 2 N/A N/A 1 1 0x3F 0x40 N0[1:0] 0x1C 0x00 Enable FIFO Warning 2 PLL charge pump current[4:0] PLL lock Default 0x00 0x10 Enable FIFO Warning 1 Manual VCO band[5:0] 0x17 FIFO Status 1 Bit 1 PLL lock status PLL cross control enable 0x13 FIFO Control Bit 2 Powerdown aux ADC 0x11 Sync Status 1 REFCLK DACCLK duty crosscorrection correction PLL manual enable PLL loop bandwidth[2:0] N2[1:0] Bit 3 Enable sync signal lock Enable AED compare pass Sync signal locked Sync signal lost DACCLK duty correction PLL enable Bit 4 0xD1 N1[1:0] VCO control voltage[3:0] 0xD9 0x00 Data/FIFO rate toggle Sync lost 0x00 0x48 Sync phase request[5:0] Sync enable VCO band readback[5:0] Rising Sync Averaging[2:0] edge sync 0x00 Sync locked N/A Sync phase readback[7:0] (6.2 format) N/A FIFO phase offset[2:0] FIFO Warning 1 FIFO Warning 2 FIFO soft align ack FIFO soft align request FIFO reset aligned FIFO level[7:0] Bypass premod Bypass sinc-1 Bypass NCO NCO gain 0x04 N/A N/A Bypass Select sideband phase compensation and dc offset HB1[1:0] Send I data to Q data 0xE4 Bypass HB1 0x00 HB2 Control 0x1D HB2[5:0] Bypass HB2 0x00 HB3 Control 0x1E HB3[5:0] Bypass HB3 0x00 Chip ID 0x1F Chip ID[7:0] Rev. 0 | Page 19 of 56 0x08 AD9125 AD9125 Register Name FTW 1 (LSB) Addr (Hex) 0x30 FTW 2 0x31 FTW[15:8] 0x00 FTW 3 0x32 FTW[23:16] 0x00 FTW 4 (MSB) 0x33 FTW[31:24] 0x00 NCO Phase Offset LSB NCO Phase Offset MSB NCO FTW Update 0x34 NCO phase offset[7:0] 0x00 0x35 NCO phase offset[15:8] 0x00 I Phase Adj LSB 0x38 I Phase Adj MSB 0x39 Q Phase Adj LSB 0x3A Q Phase Adj MSB 0x3B I DAC Offset LSB 0x3C I DAC offset[7:0] 0x00 I DAC Offset MSB 0x3D I DAC offset[15:8] 0x00 Q DAC Offset LSB 0x3E Q DAC offset[7:0] 0x00 Q DAC Offset MSB 0x3F Q DAC offset[15:8] 0x00 I DAC FS Adjust 0x40 I DAC FS adjust[7:0] 0xF9 I DAC Control 0x41 Aux DAC I Data 0x42 I Aux DAC Control 0x43 Bit 7 Bit 6 0x36 Bit 5 Bit 4 Frame FTW ack Bit 3 FTW[7:0] Bit 2 Frame FTW request Bit 1 Bit 0 Update FTW ack Update FTW request I phase adjust[7:0] Default 0x00 0x00 0x00 I phase adjust[9:8] 0x00 Q phase adjust[9:8] 0x00 Q phase adjust[7:0] 0x00 I DAC sleep I DAC FS adjust[9:8] I aux DAC[7:0] I Aux DAC sign I Aux DAC current direction 0x01 0x00 I aux DAC sleep I aux DAC[9:8] 0x00 Q DAC FS adjust[9:8] 0x01 Q DAC FS Adjust 0x44 Q DAC Control 0x45 Q DAC FS adjust[7:0] 0xF9 Aux DAC Q Data 0x46 Q Aux DAC Control 0x47 Die Temperature Range Control Die Temperature LSB Die Temperature MSB SED Control 0x48 0x67 Compare I0 LSBs 0x68 Autoclear enable Compare Value I0[7:0] Compare I0 MSBs Compare Q0 LSBs Compare Q0 MSBs Compare I1 LSBs 0x69 Compare Value I0[15:8] 0x7A 0x6A Compare Value Q0[7:0] 0x45 0x6B Compare Value Q0[15:8] 0xEA 0x6C Compare Value I1[7:0] 0x16 Compare I1 MSBs 0x6D Compare Value I1[15:8] 0x1A Compare Q1 LSBs 0x6E Compare Value Q1[7:0] 0xC6 Q DAC sleep Q aux DAC[7:0] Q Aux DAC sign Q Aux DAC current direction Q aux DAC sleep FS current[2:0] 0x00 Q aux DAC[9:8] Reference current[2:0] Capacitor value 0x00 0x02 0x49 Die temperature[7:0] N/A 0x4A Die temperature[15:8] N/A SED compare enable Sample error detected Rev. 0 | Page 20 of 56 Compare fail Compare pass 0x00 0xB6 AD9125 AD9125 Register Name Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Die Revsion Addr (Hex) 0x6F Bit 7 Bit 6 Bit 5 0x70 0x71 0x72 0x73 0x7F Bit 4 Bit 3 Compare Value Q1[15:8] Bit 2 Bit 1 Bit 0 Default 0xAA Errors detected I_BITS[7:0] Errors detected I_BITS[15:8] Errors detected Q_BITS[7:0] Errors detected Q_BITS[15:8] Revision[3:0] 0x00 0x00 0x00 0x00 0x0C DEVICE CONFIGURATION REGISTER DESCRIPTIONS Table 11. Device Configuration Register Descriptions Register Name Comm Address (Hex) 0x00 LSB_FIRST 5 Reset 7 6 5 0 7 Power-down DAC I Power-down DAC Q Power-down data receiver Power-down auxiliary ADC PLL lock status Binary data format 6 Q data first 5 MSB swap [1:0] 0x01 Name SDIO 6 Power Control Bits 7 Data bus width 7 6 5 4 3 Enable PLL lock lost Enable PLL lock Enable sync signal lost Enable sync signal lock Enable sync phase locked Enable soft FIFO sync 4 Data Format Interrupt Enable 1 0x03 0x04 2 Description SDIO operation. 0 = SDIO operates as an input only. 1 = SDIO operates as a bidirectional input/output. Serial port communication LSB or MSB first. 0 = MSB first. 1 = LSB first. 1 = device is held in reset when this bit is written high and is held there until the bit is written low. 1 = powers down DAC I. 1 = powers down DAC Q. 1 = powers down the input data receiver. 1 = powers down the auxiliary ADC for temperature sensor. 1 = PLL is locked. 0 = input data is in twos complement format. 1 = input data is in binary format. Indicates I/Q data pairing on data input. 0 = I data sent to data receiver first. 1 = Q data sent to data receiver first. Swaps the bit order of the data input port. 0 = order of the data bits corresponds to the pin descriptions. 1 = bit designations are swapped; most significant bits become the least significant bits. Data receiver interface mode. 00 = dual-word mode; 32-bit interface bus width. 01 = word mode; 16-bit interleaved interface bus width. 10 = byte mode; 8-bit interleaved interface bus width. 11 = invalid. See the CMOS Input Data Ports section for details on the operation of the different interface modes. 1 = enables interrupt for PLL lock lost. 1 = enables interrupt for PLL lock. 1 = enables interrupt for sync signal lock lost. 1 = enables interrupt for sync signal lock. 1 = enables interrupt for clock generation ready. 1 = enables interrupt for soft FIFO reset. Rev. 0 | Page 21 of 56 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD9125 AD9125 Register Name Address (Hex) Interrupt Enable 2 0x05 Bits 1 0 7 6 5 4 1 0 7 Name Enable FIFO Warning 1 Enable FIFO Warning 2 Set to 0 Set to 0 Set to 0 Enable AED comparison pass Enable AED comparison fail Enable SED comparison fail Set to 0 Set to 0 PLL lock lost 6 PLL locked 5 Sync signal lost 4 Sync signal locked 3 Sync phase locked 2 Soft FIFO sync 1 FIFO Warning 1 0 FIFO Warning 2 4 AED comparison pass 3 AED comparison fail 2 SED comparison fail 7 6 5 DACCLK duty correction REFCLK duty correction DACCLK cross-correction 4 REFCLK cross-correction 3 2 Event Flag 1 1 Event Flag 21 Clock Receiver Control 0x06 0x07 0x08 Description 1 = enables interrupt for FIFO Warning 1. 1 = enables interrupt for FIFO Warning 2. Set this bit to 0. Set this bit to 0. Set this bit to 0. 1 = enables interrupt for AED comparison pass. Default 0 0 0 0 0 0 1 = enables interrupt for AED comparison fail. 0 1 = enables interrupt for SED comparison fail. 0 Set this bit to 0. Set this bit to 0. 1 = indicates that the PLL, which had been previously locked, has unlocked from the reference signal. This is a latched signal. 1 = indicates that the PLL has locked to the reference clock input. 1 = indicates that the sync logic, which had been previously locked, has lost alignment. This is a latched signal. 1 = indicates that the sync logic did achieve sync alignment. This is indicated when no phase changes were requested for at least a few full averaging cycles. 1 = indicates that the internal digital clock generation logic is ready. This occurs when internal clocks are present and stable. 1 = indicates that a FIFO reset originating from a serial port-based request has successfully completed. This is a latched signal. 1 = indicates that the difference between the FIFO read and write pointers is 1. 1 = indicates that the difference between the FIFO read and write pointers is 2. 1 = indicates that the SED logic detected a valid input data pattern compared with the preprogrammed expected values. This is a latched signal. 1 = indicates that the SED logic detected an invalid input data pattern compared with the preprogrammed expected values. This is a latched signal that automatically clears when eight valid I/Q data pairs are received. 1 = indicates that the SED logic detected an invalid input data pattern compared with the preprogrammed expected values. This is a latched signal. 1 = enables duty-cycle correction on the DACCLK input. 1 = enables duty-cycle correction on the REFCLK input. 1 = enables differential crossing correction on the DACCLK input. 1 = enables differential crossing correction on the REFCLK input. 0 0 0 Rev. 0 | Page 22 of 56 0 0 0 0 0 0 0 0 0 0 0 1 1 AD9125 AD9125 Register Name PLL Control 1 Address (Hex) 0x0A 0x0E PLL charge pump current[4:0] [7:6] N2[1:0] PLL cross control enable N0[1:0] N1[1:0] 7 PLL lock [3:0] PLL Status 1 Manual VCO band PLL loop bandwidth[2:0] [1:0] 0x0D [5:0] [7:5] 4 [3:2] PLL Control 3 PLL manual enable [4:0] 0x0C Name PLL enable 6 PLL Control 2 Bits 7 PLL Status 2 0x0F [5:0] Sync Control 1 0x10 7 6 VCO control voltage[3:0] VCO band readback[5:0] Sync enable Data/FIFO rate toggle 3 Rising edge sync [2:0] Sync averaging[2:0] Description 1 = enables the PLL clock multiplier. REFCLK input is used as the PLL reference clock signal. Enables the manual selection of the VCO band. 1 = manual mode; the correct VCO band must be determined by the user. Selects the VCO band to be used. Selects the PLL loop filter bandwidth. 000 = loop bandwidth is nominally 200 kHz 010 = loop bandwidth is nominally 450 kHz 100 = loop bandwidth is nominally 950 kHz 110 = loop bandwidth is nominally 2 MHz Sets the nominal PLL charge-pump current. 00000 = lowest current setting. 11111 = highest current setting. PLL control clock divider. These bits determine the ratio of the DACCLK rate to the PLL controller clock rate. fPC_CLK must always be less than 80 MHz. 00 = fDACCLK/fPC_CLK = 2. 01 = fDACCLK/fPC_CLK = 4. 10 = fDACCLK/fPC_CLK = 8. 11 = fDACCLK/fPC_CLK = 16. Enables PLL cross-point controller. PLL VCO divider. These bits determine the ratio of the VCO output to the DACCLK frequencies. 00 = fVCO/fDACCLK = 1. 01 = fVCO/fDACCLK = 2. 10 = fVCO/fDACCLK = 4. 11 = fVCO/fDACCLK = 4. PLL loop divider. These bits determine the ratio of the DACCLK to the REFCLK frequencies. 00 = fDACCLK/fREFCLK = 2. 01 = fDACCLK/fREFCLK = 4. 10 = fDACCLK/fREFCLK = 8. 11 = fDACCLK/fREFCLK = 16. The PLL generated clock is tracking the REFCLK input signal. VCO control voltage readback (see Table 25). Default 0 1 0 110 10001 3 1 10 01 R R Indicates the VCO band currently selected. R 1 = enables the synchronization logic. 0 = operates the synchronization at the FIFO reset rate. 1 = operates the synchronization at the data rate. 0 = sync is initiated on the falling edge of the sync input. 1 = sync is initiated on the rising edge of the sync input. Sets the number of input samples that are averaged for determining the sync phase. 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 0 1 Rev. 0 | Page 23 of 56 1 0 AD9125 AD9125 Register Name Address (Hex) Bits Name Sync Control 2 0x11 5:0 Sync phase request[5:0] Sync Status 1 0x12 7 Sync lost Sync Status 2 0x13 6 [7:0] Sync locked Sync phase readback[7:0] FIFO Control 0x17 [2:0] FIFO phase offset[2:0] FIFO Status 1 0x18 7 6 2 1 FIFO Warning 1 FIFO Warning 2 FIFO soft align acknowledge FIFO soft align request 0 FIFO reset aligned [7:0] 7 6 5 3 FIFO level[7:0] Bypass premod Bypass sinc-1 Bypass NCO NCO gain 2 Bypass phase compensation and dc offset FIFO Status 2 Datapath Control 0x19 0x1B Description 110 = 64. 111 = 128. This sets the requested clock phase offset after sync. The offset unit is in DACCLK cycles. This enables repositioning of the DAC output with respect to the sync input. The offset can also be used to skew the DAC outputs between the synchronized DACs. 000000 = 0 DACCLK cycles. 000001 = 1 DACCLK cycle. . 111111 = 63 DACCLK cycles. 1 = indicates that synchronization had been attained but was subsequently lost. 1 = indicates that synchronization has been attained. Indicates the averaged sync phase offset (6.2 format). If the value differs from the requested sync phase value, this indicates sync timing errors. 00000000 = 0.0. 00000001 = 0.25. . 11111110 = 63.50. 11111111 = 63.75. FIFO write pointer phase offset following FIFO reset. This is the difference between the read pointer and the write pointer values upon FIFO reset. The optimal value is nominally 4. 000 = 0. 001 = 1. . 111 = 7. FIFO read and write pointers within ±1. FIFO read and write pointers within ±2. FIFO read and write pointers are aligned after a serial port initiated FIFO reset. Request FIFO read and write pointers alignment via the serial port. FIFO read and write pointers aligned after a hardware reset. Thermometer encoded measure of the FIFO level. 1 = bypasses fS/2 premodulator. 1 = bypasses inverse sinc filter. 1 = bypasses NCO. 0 = default. No gain scaling is applied to the NCO input to the internal digital modulator. 1 = gain scaling of 0.5 is applied to the NCO input to the internal digital modulator. This can eliminate saturation of the modulator output for some combinations of data inputs and NCO signals. 1 = bypasses phase compensation and dc offset. Rev. 0 | Page 24 of 56 Default 0 R R R 4 0 0 0 0 0 1 1 1 0 1 AD9125 AD9125 Register Name Address (Hex) Send I data to Q data [2:1] HB1[1:0] 0 0x1C Name Select sideband 0 HB1 Control Bits 1 Bypass HB1 HB2 Control 0x1D [6:1] HB2[5:0] 0 Bypass HB2 HB3 Control 0x1E [6:1] HB3[5:0] Chip ID 0x1F 0 [7:0] Bypass HB3 Chip ID[7:0] Description 0 = the modulator outputs high-side image. 1 = the modulator outputs low-side image. The image is spectrally inverted compared with the input data. 1 = ignores Q data from the interface and disables the clocks to the Q datapath. Sends I data to both the I and Q DACs. 00 = input signal is not modulated; filter pass band is from -0.4 to +0.4 of fIN1. 01 = input signal is not modulated; filter pass band is from 0.1 to 0.9 of fIN1. 10 = input signal is modulated by fIN1; filter pass band is from 0.6 to 1.4 of fIN1. 11 = input signal is modulated by fIN1; filter pass band is from 1.1 to 1.9 of fIN1. 1 = bypasses first-stage interpolation filter. Default 0 Modulation mode for I Side Half-Band Filter 2. 000000 = input signal is not modulated; filter pass band is from -0.25 to +0.25 of fIN2. 001001 = input signal is not modulated; filter pass band is from 0.0 to 0.5 of fIN2. 010010 = input signal is not modulated; filter pass band is from 0.25 to 0.75 of fIN2. 011011 = input signal is not modulated; filter pass band is from 0.5 to 1.0 of fIN2. 100100 = input signal is modulated by fIN2; filter pass band is from 0.75 to 1.25 of fIN2. 101101 = input signal is modulated by fIN2; filter pass band is from 1.0 to 1.5 of fIN2. 110110 = input signal is modulated by fIN2; filter pass band is from 1.25 to 1.75 of fIN2. 111111 = input signal is modulated by fIN2; filter pass band is from 1.5 to 2.0 of fIN2. 1 = bypasses second stage interpolation filter. 0 Modulation mode for I Side Half-Band Filter 3. 000000 = input signal is not modulated; filter pass band is from -0.2 to +0.2 of fIN3. 001001 = input signal is not modulated; filter pass band is from 0.05 to 0.45 of fIN3. 010010 = input signal is not modulated; filter pass band is from 0.3 to 0.7 of fIN3. 011011 = input signal is not modulated; filter pass band is from 0.55 to 0.95 of fIN3. 100100 = input signal is modulated by fIN3; filter pass band is from 0.8 to 1.2 of fIN3. 101101 = input signal is modulated by fIN3; filter pass band is from 1.05 to 1.45 of fIN3. 110110 = input signal is modulated by fIN3; filter pass band is from 1.3 to 1.7 of fIN3. 111111 = input signal is modulated by fIN3; filter pass band is from 1.55 to 1.95 of fIN3. 1 = bypasses third-stage interpolation filter. This register identifies the device as an AD9125 AD9125. Rev. 0 | Page 25 of 56 0 0 0 0 0 0 8 AD9125 AD9125 Register Name FTW 1 (LSB) Address (Hex) 0x30 Bits [7:0] Name FTW[7:0] FTW 2 FTW 3 FTW 4 (MSB) NCO Phase Offset LSB 0x31 0x32 0x33 0x34 [7:0] [7:0] [7:0] [7:0] FTW[15:8] FTW[23:16] FTW[31:24] NCO phase offset[7:0] NCO Phase Offset MSB NCO FTW Update 0x35 [7:0] NCO phase offset[15:8] 0x36 5 FRAME FTW acknowledge FRAME FTW request 4 1 Update FTW acknowledge Update FTW request I phase adjust[7:0] I Phase Adj LSB 0x38 0 [7:0] I Phase Adj MSB Q Phase Adj LSB 0x39 0x3A [1:0] [7:0] I phase adjust[9:8] Q phase adjust[7:0] Q Phase Adj MSB I DAC Offset LSB 0x3B 0x3C [1:0] [7:0] Q phase adjust[9:8] I DAC offset[7:0] I DAC Offset MSB Q DAC Offset LSB 0x3D 0x3E [7:0] [7:0] I DAC offset[15:8] Q DAC offset[7:0] Q DAC Offset MSB I DAC FS Adjust 0x3F 0x40 [7:0] [7:0] Q DAC offset[15:8] I DAC FS adjust[7:0] I DAC Control 0x41 7 I DAC sleep 0x42 [1:0] [7:0] I DAC FS adjust[9:8] I aux DAC[7:0] Aux DAC I Data Description FTW[31:0] is the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when Bit 0 of Register 0x36 transitions from 0 to 1. See Register 0x30. See Register 0x30. See Register 0x30. NCO phase offset[15:0] sets the phase of the complex carrier signal when the NCO is reset. The phase offset spans between 0° and 360°. Each bit represents an offset of 0.0055°. The value is in twos complement format. See Register 0x34. Default 0 0 0 0 0 0 1 = indicates that the NCO has been reset due to an extended FRAME pulse signal. 0 1 = the NCO is reset on the first extended FRAME pulse after this bit transitions from 0 to 1. 1 = indicates that the FTW has been updated. 0 0 1 = the FTW is updated on 0-to-1 transition of this bit. I phase adjust[9:0] is used to insert a phase offset between the I and Q datapaths. This can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for details. Register 0x38. Q phase adjust[9:0] is used to insert a phase offset between the I and Q datapaths. This can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for details. See Register 0x3A. I DAC offset[15:0] is a value added directly to the samples written to the I DAC. See Register 0x3C. Q DAC offset[15:0] is a value added directly to the samples written to the Q DAC. See Register 0x3E. I DAC FS adjust[9:0] sets the full-scale current of the I DAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 A. 0x000 = 8.64 mA. . 0x200 = 20.14 mA. . 0x3FF = 31.66 mA. 1 = puts the I-channel DAC into sleep mode (fast wakeup mode). See Register 0x40. I aux DAC[9:0] sets the magnitude of the auxiliary DAC current. The range is 0 mA to 2 mA, and the step size is 2 A. 0x000 = 0.000 mA. 0x001 = 0.002 mA. . 0x3FF = 2.046 mA. 0 0 Rev. 0 | Page 26 of 56 0 0 0 0 0 0 0 0 0 F9 0 1 0 AD9125 AD9125 Register Name I Aux DAC Control Address (Hex) 0x43 Bits 7 Name I aux DAC sign 6 I aux DAC current direction I aux DAC sleep I Aux DAC[9:8] Q DAC FS adjust[7:0] Q DAC FS Adjust 0x44 5 [1:0] [7:0] Q DAC Control 0x45 7 Q DAC sleep Aux DAC Q Data 0x46 [1:0] [7:0] Q DAC FS adjust[9:8] Q aux DAC[7:0] Q Aux DAC Control 0x47 7 Q aux DAC sign 6 Q aux DAC current direction 5 Reference current[2:0] 0 0x48 Q aux DAC[9:8] FS current[2:0] [3:1] Die Temp Range Control Q aux DAC sleep [1:0] [6:4] Capacitor value Die Temp LSB 0x49 [7:0] Die temp[7:0] Die Temp MSB 0x4A [7:0] Die temp[15:8] Description 0 = the auxiliary DAC I sign is positive, and the current is directed to the IOUT1P pin (Pin 67). 1 = the auxiliary DAC I sign is negative, and the current is directed to the IOUT1N pin (Pin 66). 0 = the auxiliary DAC I sources current. 1 = the auxiliary DAC I sinks current. I channel auxiliary DAC sleep. See Register 0x42. Q DAC FS adjust[9:0] sets the full-scale current of the I DAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 A. 0x000 = 8.64 mA. . 0x200 = 20.14 mA. . 0x3FF = 31.66 mA. 1 = puts the Q-channel DAC into sleep mode (fast wakeup mode). See Register 0x44. Q aux DAC[9:0] sets the magnitude of the aux DAC current. The range is 0 mA to 2 mA, and the step size is 2 A. 0x000 = 0.000 mA. 0x001 = 0.002 mA. . 0x3FF = 2.046 mA. 0 = the auxiliary DAC Q sign is positive, and the current is directed to the IOUT2P pin (Pin 58). 1 = the auxiliary DAC Q sign is negative, and the current is directed to the IOUT2N pin (Pin 59). 0 = the auxiliary DAC Q sources current. 1 = the auxiliary DAC Q sinks current. Q-channel auxiliary DAC sleep See Register 0x46. Auxiliary ADC full-scale current. 000 = lowest current. . 111 = highest current. Auxiliary ADC reference current. 000 = lowest current. 111 = highest current. Auxiliary ADC internal capacitor value. 0 = 5 pF. 1 = 10 pF. Die Temp[15:0] indicates the approximate die temperature. 0xADCC = -39.9°C. 0xC422 = 25.1°C. . 0xD8A8 = 84.8°C (see the Temperature Sensor section for details). See Register 0x49. Rev. 0 | Page 27 of 56 Default 0 0 0 0 F9 0 1 0 0 0 0 0 0 1 0 R R AD9125 AD9125 Register Name SED Control Address (Hex) 0x67 Bits 7 Name SED compare enable 5 Sample error detected 3 Autoclear enable 1 Compare fail Compare I0 MSBs Compare Q0 LSBs 0x69 0x6A [7:0] [7:0] Compare Value I0[15:8] Compare Value Q0[7:0] Compare Q0 MSBs 0x6B [7:0] Compare I1 LSBs 0x6C [7:0] Compare Value Q0[15:8] Compare Value I1[7:0] Compare I1 MSBs 0x6D [7:0] Compare Value I1[15:8] Compare Q1 LSBs 0x6E [7:0] Compare Value Q1[7:0] Compare Q1 MSBs 0x6F [7:0] SED I LSBs 0x70 [7:0] SED I MSBs 0x71 [7:0] SED Q LSBs 0x72 [7:0] SED Q MSBs 0x73 [7:0] Die Revision 1 Compare pass Compare Value I0[7:0] 0x7F [5:2] Compare Value Q1[15:8] Errors Detected I_BITS[7:0] Errors detected I_BITS[15:8] Errors detected Q_BITS[7:0] Errors detected Q_BITS[15:8] Revision[3:0] 16 Compare Value Q1[15:0] is the word that is compared with the Q1 input sample captured at the input interface. See Register 0x6E. C6 0 0 Corresponds to device die revision. 0 [7:0] Compare Value I1[15:0] is the word that is compared with the I1 input sample captured at the input interface. See Register 0x6C. Errors detected Q_BITS[15:0] indicates which bits were received in error. See Register 0x72. 0x68 Default 0 Errors detected I_BITS[15:0] indicates which bits were received in error. See Register 0x70. Compare I0 LSBs Description 1 = enables the SED circuitry. None of the flags in this register or the values in Register 0x70 through Register 0x73 are significant if the SED is not enabled. 1 = indicates an error is detected. The bit remains set until cleared. Any write to this register clears this bit to 0. 1 = enables autoclear mode. This activates Bit 1 and Bit 0 of this register and causes Register 0x70 through Register 0x73 to be autocleared whenever eight consecutive error-free sample data sets are received. 1 = indicates an error has been detected. This bit remains high until it is autocleared by the reception of eight consecutive error-free comparisons or until it is cleared by writing to this register. 1 = indicates that the last sample comparison was error free. Compare Value I0[15:0] is the word that is compared with the I0 input sample captured at the input interface. See Register 0x68. Compare Value Q0[15:0] is the word that is compared with the Q0 input sample captured at the input interface. See Register 0x6A 3 All bit event flags are cleared by writing the respective bit high. Rev. 0 | Page 28 of 56 0 0 0 0 B6 7A 45 EA 1A AA 0 0 AD9125 AD9125 CMOS INPUT DATA PORTS The AD9125 AD9125 input data port consists of a data clock (DCI), data bus, and FRAME signal. The data port can be configured to operate in three modes: dual-word mode, word mode, and byte mode. In dual-word mode, I and Q data is received simultaneously on two 16-pin buses. One bus receives I datapath input words, and the other bus receives Q datapath input words. In word mode, one 16-pin bus is used to receive interleaved I and Q input words. In byte mode, an 8-pin bus is used to receive interleaved I and Q input bytes. The pin assignments of the bus in each mode is described in Table 12. WORD MODE In word mode, the DCI signal is supplied as a qualifying clock that is time aligned with the input data. The rising edge of the DCI signal should be aligned with the changing data of the interleaved I and Q input data stream. The FRAME signal indicates to which DAC the data is sent. When FRAME is high, data is sent to the I DAC. When FRAME is low, data is sent to the Q DAC. For 14- and 12-bit resolution devices, the two and four LSBs are not significant, respectively. The complete timing diagram is shown in Figure 43. DCI Table 12. Data Bit Pin Assignments for Data Input Modes Data Bus Pin Assignments I data: D[31:16] Q data: D[15:0] I and Q data: D[29:28], D[25:24], D[21:20], D[17:16], D[15:14], D[11:10], D[7:6], D[3:2] I and Q data: D[21:20], D[17:16], D[15:14], D[11:10] Word Byte I AND Q DATA I1 Q1 I2 09016-143 Mode Dual Word FRAME Figure 43. Timing Diagram for Word Mode BYTE MODE In byte and word modes, a FRAME signal is required for controlling which DAC receives the data. In dual-word mode, the FRAME signal is not required because each DAC has a dedicated bus. DUAL-WORD MODE In dual-word mode, the DCI signal is supplied as a qualifying clock that is time aligned with the input data. The rising edge of the DCI signal should be aligned with the changing data of each of the I and Q input data streams. In byte mode, the DCI signal is supplied as a qualifying clock that is time aligned with the input data. The rising edge of the DCI signal should be aligned with the changing data of the interleaved I and Q input data stream. The FRAME signal indicates to which DAC the data is sent. When FRAME is high, data is sent to the I DAC. When FRAME is low, data is sent to the Q DAC. Both bytes must be written to each datapath for proper operation. For 14- and 12-bit resolution devices, the LSBs in the second byte are not significant. The complete timing diagram is shown in Figure 44. DCI DCI I2 Q DATA Q1 Q2 Q3 I AND Q Q DATA LSB I3 I1MSB I1LSB Q1MSB Q1LSB I2MSB I2LSB FRAME Figure 42. Timing Diagram for Dual-Word Mode Figure 44. Timing Diagram for Byte Mode Rev. 0 | Page 29 of 56 Q2MSB Q2LSB 09016-144 I1 09016-142 I DATA AD9125 AD9125 The data interface timing can be verified by using the sample error detection (SED) circuitry. See the Interface Timing Validation section for details. INTERFACE TIMING The timing diagram for the digital interface port is shown in Figure 45. The sampling point of the data bus occurs on the falling edge of the DCI signal and has an uncertainty of 2.1 ns, as illustrated by the sampling interval shown in Figure 45. The D[31:0] and FRAME signals must be valid throughout this sampling interval. FIFO OPERATION The AD9125 AD9125 contains a 2-channel, 16-bit wide, eight-word-deep FIFO designed to relax the timing relationship between the data arriving at the DAC input ports and the internal DAC data rate clock. The FIFO acts as a buffer that absorbs timing variations between the data source and DAC, such as the clock-to-data variation of an FPGA or ASIC, which significantly increases the timing budget of the interface. The setup (tS) and hold (tH) times with respect to the edges are shown in Figure 45. The minimum setup and hold times are shown in Table 13. Figure 47 shows the block diagram of the datapath through the FIFO. The data is latched into the device and is formatted, and then it is written into the FIFO register determined by the FIFO write pointer. The value of the write pointer is incremented every time a new word is loaded into the FIFO. Meanwhile, data is read from the FIFO register determined by the read pointer and fed into the digital datapath. The value of the read pointer is updated every time data is read into the datapath from the FIFO. This happens at the data rate, that is, the DACCLK rate divided by the interpolation ratio. DCI D[31:0] tH 09016-146 tS FRAME Figure 45. Timing Diagram for Input Data Ports Valid data is transmitted through the FIFO as long as the FIFO does not overflow or become empty. Note that an overflow or empty condition of the FIFO is the same as the write pointer and read pointer being equal. When both pointers are equal, an attempt is made to read and write a single FIFO register simultaneously. This simultaneous register access leads to unreliable data transfer through the FIFO and must be avoided. Table 13. Data Port Setup and Hold Times Minimum Setup Time, tS (ns) 0.86 Minimum Hold Time, tH (ns) 1.24 DCI Nominally, data is written to the FIFO at the same rate that data is read from the FIFO, which keeps the data level in the FIFO constant. If data is written to the FIFO faster than data is read, the data level in the FIFO increases. If data is written to the device slower than data is read, the data level in the FIFO decreases. For an optimum timing margin, the FIFO level should be maintained near half full, which is the same as maintaining a difference of four between the write pointer and read pointer values. tS-FRAME 09016-147 tH-FRAME FRAME Figure 46. Timing Diagram for Frame input Table 14. FRAME Setup and Hold Times Minimum Setup Time, tS-FRAME (ns) -0.04 Minimum Hold Time, tH_FRAME (ns) +1.05 32 BITS REG 0 REG 1 REG 2 DATA INPUT LATCH DATA ASSEMBLER REG 3 16 DATA PATHS 16 DACS REG 4 REG 5 REG 6 DCI WRITE POINTER 32 BITS READ POINTER Figure 47. Block Diagram of Datapath Through FIFO Rev. 0 | Page 30 of 56 ÷ INT DACCLK 09016-018 REG 7 AD9125 AD9125 The operation of the FRAME initiated FIFO reset depends on the synchronization mode chosen. When synchronization is disabled or when the device is configured for data rate mode synchronization, the FRAME strobe initiates a relative FIFO reset. When FIFO mode synchronization is chosen, the FRAME strobe initiates an absolute FIFO reset. More details on the synchronization function can be found in the Multichip Synchronization section. A summary of the synchronization modes and the type of FIFO reset employed is listed in Table 15. Table 15. Summary of FIFO Resets FIFO Reset Signal Serial Port FRAME Synchronization Mode Disabled Data Rate FIFO Rate Relative reset Relative reset Relative reset Relative reset Relative reset Absolute reset A serial port initiated FIFO reset can be issued in any mode and always results in a relative FIFO reset. To initialize the FIFO data level through the serial port, Bit 1 of Register 0x18 should be toggled from 0 to 1 and then back to 0. When the write to the register is complete, the FIFO data level is initialized. When the initialization is triggered, the next time the read pointer becomes 0, the write pointer is set to the value of the FIFO phase offset level (Register 0x17, Bits[2:0]) variable upon initialization. By default, this is 4, but it can be programmed to a value between 0 and 7. The recommended procedure for a serial port FIFO data level initialization is as follows: 3. 4. READ POINTER Request FIFO level reset by setting Register 0x18, Bit 1, to 1. Verify that the part acknowledges the request by ensuring that Register 0x18, Bit 2, is 1. Remove the request by setting Register 0x18, Bit 1, to 0. Verify that the part drops the acknowledge signal by ensuring that Register 0x18, Bit 2, is 0. FIFO Level Initialization via FRAME Signal The primary function of the FRAME input is indicating to which DAC the input data is written. Another function of the FRAME input is initializing the FIFO data level value. This is done by asserting the FRAME signal high for at least the time interval needed to load complete data to the I and Q DACs. This 0 1 2 3 WRITE POINTER 4 5 6 7 0 1 2 3 4 5 6 7 FIFO WRITE RESETS FRAME 3 4 5 6 7 0 1 2 Figure 48. FRAME Input vs. Write Pointer Value, Data Rate Mode Write Pointer Initialization via FRAME Signal In FIFO rate synchronization mode, the REFCLK/SYNC signal is used to reset the FIFO read pointer to 0. The edge of the DAC clock used to sample the SYNC signal is selected by Bit 3 of Register 0x10. The FRAME signal is used to reset the FIFO write pointer. In the FIFO rate synchronization mode, the FIFO write pointer is reset immediately after the FRAME signal is asserted high for at least the time interval needed to load complete data to the I and Q DACs. The FIFO write pointer is initialized to the value of the FIFO phase offset[2:0] (Register 0x17). FIFO rate synchronization is selected by setting Bit 6 of Register 0x10 to 0. SYNC READ POINTER FIFO Level Initialization via Serial Port 1. 2. To initiate a relative FIFO reset with the FRAME signal, the device must be configured in data rate mode (Register 0x10, Bit 6). When FRAME is asserted in data rate mode, the write pointer is set to 4 (by default or to the FIFO start level) the next time the read pointer becomes 0 (see Figure 48). 09016-019 To avoid a concurrent read and write to the same FIFO address and to ensure a fixed pipeline delay, it is important to initialize the FIFO pointers to known states. The FIFO pointers can be initialized in two ways: via a write sequence to the serial port or by strobing the FRAME input. There are two types of FIFO pointer resets: a relative reset and an absolute reset. A relative reset enforces a defined FIFO depth. An absolute reset enforces a particular write pointer value when the reset is initiated. A serial port initiated FIFO reset is always a relative reset. A FRAME strobe initiated reset can be either a relative or an absolute reset. corresponds to one DCI period in dual-word mode, two DCI periods in word mode, and four DCI periods in byte mode. FIFO READ RESET 0 FRAME WRITE POINTER 1 2 FIFO WRITE RESET 6 5 6 3 4 5 6 7 0 1 2 3 5 6 7 FIFO PHASE OFFSET[2:0] REGISTER 0x17, BITS[2:0] = 0b101 7 0 1 2 3 4 09016-148 Initializing the FIFO Data Level Figure 49. FRAME Input vs. Write Pointer Value, FIFO Rate Mode Monitoring the FIFO Status The FIFO initialization and status can be read from Register 0x18. This register provides information on the FIFO initialization method and whether the initialization was successful. The MSB of Register 0x18 is a FIFO warning flag that can optionally trigger a device interrupt (IRQ). This flag is an indication that the FIFO is close to emptying (FIFO level is 1) or overflowing (FIFO level is 7). This is an indication that data may soon be corrupted and action should be taken. The FIFO data level can be read from Register 0x19 at any time. The FIFO data level reported by the serial port is denoted as a 7-bit thermometer code of the write counter state relative to the absolute read counter being at 0. The optimum FIFO data level of 4 is, therefore, reported as a value of 00001111 in the status register. It should be noted that, depending on the timing relationship between DCI and the main DACCLK, the FIFO level value can be off by ±1 count. Therefore, it is important to keep the difference between the read and write pointers to at least 2. Rev. 0 | Page 31 of 56 AD9125 AD9125 DIGITAL DATAPATH The block diagram in Figure 50 shows the functionality of the digital datapath. The digital processing includes a premodulation block, three half-band interpolation filters, a quadrature modulator with a fine resolution NCO, a phase and offset adjustment block, and an inverse sinc filter. Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 51. The shape of the filter response is identical in each of the four modes. The four modes are distinguished by two factors: the filter center frequency and whether the input signal is modulated by the filter. MODE 0 HB1 HB2 HB3 MODE 2 MODE 1 MODE 3 0 09016-020 PREMOD PHASE AND OFFSET ADJUST SINC­1 ­20 ­40 ­60 The datapath can be used to process an input data stream representing two independent real data streams as well, but the functionality is somewhat restricted. The premodulation block can be used, as well as any of the nonshifted interpolation filter modes (see the Premodulation section for more details). ­80 ­100 0 0.2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 NORMALIZED FREQUENCY (× fIN1) PREMODULATION 2.0 Figure 51. HB1 Filter Modes The half-band interpolation filters have selectable pass bands that allow the center frequencies to be moved in increments of ½ of their input data rate. The premodulation block provides a digital upconversion of the incoming waveform by ½ of the incoming data rate, fDATA. This can be used to frequency-shift baseband input data to the center of the interpolation filters' pass band. INTERPOLATION FILTERS The transmit path contains three interpolation filters. Each of the three interpolation filters provides a 2× increase in output data rate. The half-band (HB) filters can be individually bypassed or cascaded to provide 1×, 2×, 4×, or 8× interpolation ratios. Each of the half-band filter stages offers a different combination of bandwidths and operating modes. The bandwidth of the three half-band filters with respect to the data rate at the filter input is as follows: · · · 0.4 09016-021 The digital datapath accepts I and Q data streams and processes them as a quadrature data stream. The signal processing blocks can be used when the input data stream is represented as complex data. GAIN (dB) Figure 50. Block Diagram of Digital Datapath As shown in Figure 51, the center frequency in each mode is offset by ½ the input data rate (fIN1) of the filter. Mode 0 and Mode 1 do not modulate the input signal. Mode 2 and Mode 3 modulate the input signal by fIN1. When HB1 operates in Mode 0 and Mode 2, the I and Q paths operate independently and no mixing of the data between channels occurs. When HB1 operates in Mode 1 and Mode 3, mixing of the data between the I and Q paths occurs; therefore, the data input into the filter is assumed complex. Table 16 summarizes the HB1 modes. Table 16. HB1 Filter Mode Summary Mode 0 1 2 3 Bandwidth of HB1 = 0.8 × fIN1 Bandwidth of HB2 = 0.5 × fIN2 Bandwidth of HB3 = 0.4 × fIN3 The usable bandwidth is defined as the frequency over which the filters have a pass-band ripple of less than ±0.001 dB and an image rejection of greater than +85 dB. As is discussed in the Half-Band Filter 1 (HB1) section, the image rejection usually sets the usable bandwidth of the filter, not the pass-band flatness. The half-band filters operate in several modes, providing programmable pass-band center frequencies as well as signal modulation. The HB1 filter has four modes of operation, and the HB2 and HB3 filters each have eight modes of operation. Rev. 0 | Page 32 of 56 fCENTER DC fIN/2 fIN 3fIN/2 fMOD None None fIN fIN Input Data Real or complex Complex Real or complex Complex AD9125 AD9125 Figure 52 shows the pass-band filter response for HB1. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection, not by the pass-band flatness. Table 17 shows the pass-band flatness and stop-band rejection that the HB1 filter supports at different bandwidths. Half-Band Filter 2 (HB2) HB2 has eight modes of operation, as shown in Figure 53 and Figure 54. The shape of the filter response is identical in each of the eight modes. The eight modes are distinguished by two factors: the filter center frequency and whether the input signal is modulated by the filter. 0.02 MODE 0 MODE 4 MODE 2 MODE 6 0 0 ­20 GAIN (dB) GAIN (dB) ­0.02 ­0.04 ­40 ­60 ­0.06 ­80 ­0.08 NORMALIZED FREQUENCY (× fIN1) 0 0.2 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.8 2.0 Figure 53. HB2, Even Filter Modes MODE 1 Table 17. HB1 Pass-Band Flatness and Stop-Band Rejection Stop-Band Rejection (dB) 85 80 70 60 50 40 MODE 3 MODE 5 MODE 7 0 ­20 GAIN (dB) Pass-Band Flatness (dB) 0.001 0.0012 0.0033 0.0076 0.0271 0.1096 0.6 NORMALIZED FREQUENCY (× fIN2) Figure 52. Pass-Band Detail of HB1 Bandwidth (% of fIN1) 80 80.4 81.2 82.0 83.6 85.6 0.4 09016-023 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 09016-022 0 09016-024 ­100 ­0.10 ­40 ­60 ­80 ­100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 NORMALIZED FREQUENCY (× fIN2) Figure 54. HB2, Odd Filter Modes As shown in Figure 53 and Figure 54, the center frequency in each mode is offset by ¼ of the input data rate (fIN2) of the filter. Mode 0 through Mode 3 do not modulate the input signal. Mode 4 through Mode 7 modulate the input signal by fIN2. When HB2 operates in Mode 0 and Mode 4, the I and Q paths operate independently and no mixing of the data between channels occurs. When HB2 operates in the other six modes, mixing of the data between the I and Q paths occurs; therefore, the data input to the filter is assumed complex. Rev. 0 | Page 33 of 56 AD9125 AD9125 Half-Band Filter 3 (HB3) Table 18 summarizes the HB2 and HB3 modes. HB3 has eight modes of operation that function the same as HB2. The primary difference between HB2 and HB3 is the filter bandwidths. Table 18. HB2 and HB3 Filter Mode Summary fCENTER DC fIN/4 fIN/2 3fIN/4 fIN 5fIN/4 6fIN/4 7fIN/4 fMOD None None None None fIN fIN fIN fIN Input Data Real or complex Complex Complex Complex Real or complex Complex Complex Complex Figure 56 shows the pass-band filter response for HB3. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection, not by the pass-band flatness. Table 20 shows the pass-band flatness and stop-band rejection that the HB3 filter supports at different bandwidths. 0.02 Figure 55 shows the pass-band filter response for HB2. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection, not by the pass-band flatness. Table 19 shows the pass-band flatness and stop-band rejection that the HB2 filter supports at different bandwidths. 0 ­0.02 GAIN (dB) Mode 0 1 2 3 4 5 6 7 ­0.04 ­0.06 0.02 ­0.08 0 0 GAIN (dB) 0.04 0.08 0.12 0.16 0.20 0.24 NORMALIZED FREQUENCY (× fIN3) 0.28 09016-026 ­0.10 ­0.02 Figure 56. Pass-Band Detail of HB3 ­0.04 Table 20. HB3 Pass-Band Flatness and Stop-Band Rejection ­0.06 ­0.08 0 0.04 0.08 0.12 0.16 0.20 0.24 0.28 NORMALIZED FREQUENCY (× fIN2) 0.32 09016-025 ­0.10 Figure 55. Pass-Band Detail of HB2 Table 19. HB2 Pass-Band Flatness and Stop-Band Rejection Complex Bandwidth (% of fIN2) 50 50.8 52.8 56.0 60 64.8 Pass-Band Flatness (dB) 0.001 0.0012 0.0028 0.0089 0.0287 0.1877 Complex Bandwidth (% of fIN3) 40 40.8 42.4 45.6 49.8 55.6 Stop-Band Rejection (dB) 85 80 70 60 50 40 Rev. 0 | Page 34 of 56 Pass-Band Flatness (dB) 0.001 0.0014 0.002 0.0093 0.03 0.1 Stop-Band Rejection (dB) 85 80 70 60 50 40 AD9125 AD9125 NCO MODULATION DATAPATH CONFIGURATION The digital quadrature modulator makes use of a numerically controlled oscillator, a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. A block diagram of the digital modulator is shown in Figure 57. The fine modulation provided by the digital modulator, in conjunction with the coarse modulation of the interpolation filters and premodulation block, allows the signal to be placed anywhere in the output spectrum with very fine frequency resolution. Configuring the AD9125 AD9125 datapath starts with the application requirements of the input data rate, the interpolation ratio, the output signal bandwidth, and the output signal center frequency. Given these four parameters, the first step in configuring the datapath is to verify that the device supports the bandwidth requirements. The modes of the interpolation filters are then chosen. Finally, any additional frequency offset requirements are determined and applied with premodulation and NCO modulation. Determining Datapath Signal Bandwidth I DATA INTERPOLATION The available signal bandwidth of the datapath is dependent on the center frequency of the output signal in relation to the center frequency of the interpolation filters used. Signal center frequencies that are offset from the center frequencies of the half-band filters lower the available signal bandwidth. COSINE FTW[31:0] NCO NCO PHASE OFFSET [15:0] I OUTPUT SINE Q OUTPUT ­ + ­1 Q DATA 0 1 INTERPOLATION 09016-027 SPECTRAL INVERSION When correctly configured, the available complex signal bandwidth for 2× interpolation is always 80% of the input data rate. The available signal bandwidth for 4× interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in Figure 58. Note that in 4× interpolation mode, fDAC = 4 × fDATA; therefore, the data shown in Figure 58 repeats four times from dc to fDAC. Figure 57. Digital Quadrature Modulator Block Diagram HB1 AND HB2 0.8 The NCO operating frequency, fNCO, is at either fDATA (HB1 bypassed) or twice fDATA (HB1 enabled). The frequency of the complex carrier signal can be set from dc up to fNCO. The frequency tuning word (FTW) is calculated as 0.5 HB2 AND HB3 0.3 0.2 0.4 0.6 fOUT/fDATA 0.8 1.0 09016-028 BANDWIDTH/ fDATA The quadrature modulator is used to mix the carrier signal generated by the NCO with the I and Q signal. The NCO produces a quadrature carrier signal to translate the input signal to a new center frequency. A complex carrier signal is a pair of sinusoidal waveforms of the same frequency, offset 90° from each other. The frequency of the complex carrier signal is set via FTW[31:0] in Register 0x30 through Register 0x33. Figure 58. Signal Bandwidth vs. Center Frequency of the Output Signal, 4× Interpolation f FTW = CARRIER × 2 32 f NCO The generated quadrature carrier signal is mixed with the I and Q data. The quadrature products are then summed into the I and Q datapaths, as shown in Figure 57. Updating the Frequency Tuning Word The frequency tuning word registers do not update immediately upon writing as other configuration registers. After loading the FTW registers with the desired values, Bit 0 of Register 0x36 must transition from 0 to 1 for the new FTW to take effect. Configuring 4× interpolation using the HB2 and HB3 filters can lower the power consumption of the device at the expense of reduced bandwidth. The lower curve in Figure 58 shows that the supported bandwidth in this mode varies from 30% to 50% of fDATA. The available signal bandwidth for 8× interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in Figure 59. Note that in 8× interpolation mode, fDAC = 8 × fDATA; therefore, the data shown in Figure 59 repeats eight times from dc to fDAC. Rev. 0 | Page 35 of 56 AD9125 AD9125 DETERMINING INTERPOLATION FILTER MODES HB1, HB2, AND HB3 Table 21 shows the recommended interpolation filter settings for a variety of filter interpolation factors, filter center frequencies, and signal modulation. The interpolation modes were chosen based on the final center frequency of the signal and by determining the frequency shift of the signal required. When these are known and put in terms of the input data rate (fDATA), the filter configuration that comes closest to matching should be chosen from Table 21. 0.6 0.5 0.1 0.25 0.4 0.50 0.6 0.75 fOUT/fDATA 0.9 1.00 09016-029 BANDWIDTH/ fDATA 0.8 Figure 59. Signal Bandwidth vs. Center Frequency of the Output Signal, 8× Interpolation Table 21. Recommended Interpolation Filter Modes (Register 0x1C through Register 0x1E) Interpolation Factor 8 8 82 8 8 8 8 8 8 8 8 8 8 8 8 8 4 43 4 4 4 4 4 4 2 2 2 2 HB1[1:0] 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) Filter Modes HB2[5:0] 000000 001001 010010 011011 100100 101101 110110 111111 000000 001001 010010 011011 100100 101101 110110 111111 000000 001001 010010 011011 100100 101101 110110 111111 Bypass Bypass Bypass Bypass HB3[5:0] 000000 000000 001001 001001 010010 010010 011011 011011 100100 100100 101101 101101 110110 110110 111111 111111 Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass 1 fSIGNAL Modulation DC DC 1 fDATA fDATA1 2 × fDATA 2 × fDATA1 3 × fDATA 3 × fDATA1 4 × fDATA 4 × fDATA1 5 × fDATA 5 × fDATA1 6 × fDATA 6 × fDATA1 7 × fDATA 7 × fDATA1 DC DC1 fDATA fDATA1 2 × fDATA 2 × fDATA1 3 × fDATA 3 × fDATA1 DC DC1 fDATA fDATA1 fCENTER Shift 0 fDATA/2 fDATA 3 × fDATA/2 2 × fDATA 5 × fDATA/2 3 × fDATA 7 × fDATA/2 4 × fDATA 9 × fDATA/2 5 × fDATA 11 × fDATA/2 6 × fDATA 13 × fDATA/2 7 × fDATA 15 × fDATA/2 0 fDATA/2 fDATA 3 × fDATA/2 2 × fDATA 5 × fDATA/2 3 × fDATA 7 × fDATA/2 0 fDATA/2 fDATA 3 × fDATA/2 When HB1 Mode 1 or Mode 3 is used, enabling premodulation provides an addition frequency translation of the input signal by fDATA/2, which centers a baseband input signal in the filter pass band. 2 This configuration was used in the 8× interpolation without NCO example. In addition, see the 8× Interpolation Without NCO section. 3 This configuration was used in the 4× interpolation with NCO example. In addition, see the 4× Interpolation with NCO section Rev. 0 | Page 36 of 56 AD9125 AD9125 DATAPATH CONFIGURATION EXAMPLE 4× Interpolation with NCO 8× Interpolation Without NCO Given the following conditions, the desired 140 MHz of bandwidth is 56% of fDATA: Given the following conditions, the desired 75 MHz of bandwidth is 75% of fDATA: · · · · fDATA = 100 MSPS 8× interpolation fBW = 75 MHz fCENTER = 100 MHz fDATA = 250 MSPS 4× interpolation fBW = 140 MHz fCENTER = 175 MHz As shown in Figure 58, the value at 0.7 × fDATA is 0.6. This is calculated as 0.8 - 2(0.7 - 0.6) = 0.6. Therefore, the AD9125 AD9125 supports a bandwidth of 60% of fDATA, which exceeds the required 56%. In this case, the ratio of fOUT/fDATA = 100/100 = 1.0. From Figure 59, the bandwidth supported at fDATA is 0.8, which verifies that the AD9125 AD9125 supports the bandwidth required in this configuration. The signal center frequency is 0.7 × fDATA, and assuming the input signal is at baseband, the frequency shift required is also 0.7 × fDATA. Using the settings detailed in the second row in the IF column in the 4× interpolation section in Table 21 selects the filter modes that give a center frequency of fDATA/2 and no frequency translation. The selected modes for the three halfband filters are HB1, Mode 1; HB2, Mode 1; and HB3, bypassed. The signal center frequency is fDATA, and assuming the input signal is at baseband, the frequency shift required is also fDATA. Using the settings detailed in the third row of the IF column from Table 21 (these settings use the configuration in the 8× interpolation without NCO example) selects filter modes that result in a center frequency of fDATA and a frequency translation of fDATA. The selected modes for the three half-band filters are HB1, Mode 2; HB2, Mode 2; and HB3, Mode 1. Figure 60 shows how the signal propagates through the interpolation filters. Because Mode 1 of HB1 was selected, the premodulation block should be enabled. This provides fDATA/2 modulation, which centers the baseband input data at the center frequency of HB1. The digital modulator can be used to provide the final frequency translation of 0.2 × fDATA to place the output signal at 0.7 × fDATA, as desired. Because 2 × fIN1 = fIN2 and 2 × fIN2 = fIN3, the signal appears frequency scaled by ½ into each consecutive stage. The output signal band spans 0.15 to 0.35 of fIN3 (400 MHz). Therefore, the output frequency supported is 60 MHz to 140 MHz, which covers the 75 MHz bandwidth centered at 100 MHz, as desired. The formula for calculating the FTW of the NCO is f CARRIER × 2 32 f NCO FTW = where: fCARRIER = 0.2 × fDATA. fNCO = 2 × fDATA. Therefore, FTW = 232/10. 0 2 1 0 3 HB1 0.1 ­0.5 0.4 0 3 2 0.25 ­0.5 0 3 0.2 0.3 0 1.75 1.5 4 5 2.0 × fIN2 7 6 0.7 0.5 0.15 1.25 1.0 2 ­0.2 ­0.5 7 6 0.7 1 HB3 2.0 × fIN1 1.5 5 4 0.75 0.5 0.3 0 1.0 1 0 HB2 0.6 0.5 1.0 0.35 1.5 2.0 × fIN3 09016-030 · · · · Figure 60. Signal Propagation for 8× Interpolation (fDATA Modulation) Rev. 0 | Page 37 of 56 AD9125 AD9125 DATA RATES VS. INTERPOLATION MODES Table 23 summarizes the maximum bus speed (fBUS), the supported input data rates, and the signal bandwidths for various combinations of bus width modes and interpolation rates. The maximum bus speed in any mode is 250 MHz. The maximum DAC update rate (fDAC) in any mode is 1000 MHz. The real signal bandwidth supported is a fraction of the input data rate, which depends on the interpolation filter (HB1, HB2, or HB3) selected. The complex signal bandwidth supported is twice t