AD9122 CDMA2000 ADL5375-15 D15P--D15N 16-BIT AVDD33 DVDD18 CVDD18 100MSPS - Datasheet Archive

 

TxDAC+® Digital-to-Analog Converter AD9122 FEATURES GENERAL DESCRIPTION Flexible LVDS interface allows word, byte, or nibble

 

Dual, 16-Bit, 1200 MSPS, TxDAC+® Digital-to-Analog Converter AD9122 AD9122 FEATURES GENERAL DESCRIPTION Flexible LVDS interface allows word, byte, or nibble load Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 to 50 Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Digital gain and phase adjustment for sideband suppression Multiple chip synchronization interfaces High performance, low noise PLL clock multiplier Digital inverse sinc filter Flexible LVDS interface allows word, byte, or nibble load Low power: 1.5 W @ 1.2 GSPS, 800 mW @ 500 MSPS, full operating conditions 72-lead, exposed paddle LFCSP The AD9122 AD9122 is a dual 16-bit, high dynamic range, digital-toanalog converter (DAC) that provides a sample rate of 1200 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9122 AD9122 comes in a 72-lead LFCSP. PRODUCT HIGHLIGHTS 1. APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000 CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point 2. 3. 4. Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. Flexible LVDS digital interface allows the standard 32-wire bus to be reduced to ½ or ¼ of the width. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF DC fIF LO ­ fIF 2 2/4 I DAC SIN DIGITAL BASEBAND PROCESSOR ANTIALIASING FILTER AQM PA COS 2/4 Q DAC LO 08281-001 2 NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD9122 AD9122 TABLE OF CONTENTS Features . 1 NCO Modulation . 37 Applications . 1 Datapath Configuration . 37 General Description . 1 Determining Interpolation Filter Modes . 38 Product Highlights . 1 Datapath Configuration Example . 39 Typical Signal Chain. 1 Data Rates vs. Interpolation Modes . 40 Revision History . 2 Coarse Modulation Mixing Sequences. 40 Functional Block Diagram . 3 Quadrature Phase Correction. 41 Specifications. 4 DC Offset Correction . 41 DC Specifications . 4 Inverse Sinc Filter . 41 Digital Specifications . 5 DAC Input Clock Configurations . 42 Digital Input Data Timing Specifications . 5 DAC Input Clock Configurations . 42 AC Specifications. 6 Analog Outputs. 44 Absolute Maximum Ratings. 7 Transmit DAC Operation. 44 Thermal Resistance . 7 Auxiliary DAC Operation . 45 ESD Caution . 7 Baseband Filter Implementation . 46 Pin Configuration and Function Descriptions . 8 Driving the ADL5375-15 ADL5375-15 . 46 Typical Performance Characteristics . 10 Reducing LO Leakage and Unwanted Sidebands . 47 Terminology . 16 Device Power Dissipation. 48 Theory of Operation . 17 Temperature Sensor . 49 Serial Port Operation . 17 Multichip Synchronization. 50 Data Format . 17 Synchronization with Clock Multiplication . 50 Serial Port Pin Descriptions . 17 Synchronization with Direct Clocking . 51 Serial Port Options . 18 Data Rate Mode Synchronization . 51 Device Configuration Register Map and Descriptions . 19 FIFO Rate Mode Synchronization . 52 LVDS Input Data Ports . 31 Additional Synchronization Features . 52 Word Interface Mode . 31 Interrupt Request Operation . 54 Byte Interface Mode . 31 Interrupt Service Routine . 54 Nibble Interface Mode . 31 Interface Timing Validation . 55 FIFO Operation . 31 SED Operation. 55 Interface Timing . 33 SED Example . 55 Digital Datapath. 34 Outline Dimensions . 56 Premodulation . 34 Ordering Guide . 56 Interpolation Filters . 34 REVISION HISTORY 9/09-Revision 0: Initial Version Rev. 0 | Page 2 of 56 AD9122 AD9122 FUNCTIONAL BLOCK DIAGRAM 1.2G D0P-D0N DATA RECEIVER D15P-D15N D15P-D15N IOUT1P DAC 1 AUX 16-BIT 16-BIT 16 IOUT1N 16 FIFO fDATA /2 PRE MOD NCO AND MOD HB1 HB2 I OFFSET 10 HB3 Q OFFSET INV SINC DAC CLK 16 DCI 1.2G IOUT2N GAIN 2 GAIN 1 INVSINC_CLK PHASE CORRECTION INTP FACTOR HB3_CLK HB2_CLK HB1_CLK MODE 10 IOUT2P DAC 1 AUX 16-BIT 16-BIT 16 FRAME 10 REF AND BIAS REFIO FSADJ INTERNAL CLOCK TIMING AND CONTROL LOGIC DAC CLK_SEL PLL CONTROL POWER-ON RESET MULTICHIP SYNCHRONIZATION SYNC DAC_CLK CLOCK MULTIPLIER (2× TO 16×) DACCLKP DACCLKN CLK RCVR REFCLKP REFCLKN 08281-002 RESET CS IRQ SCLK SDO CLK RCVR 0 1 PLL_LOCK SDIO PROGRAMMING REGISTERS SERIAL INPUT/OUTPUT PORT Figure 2. AD9122 AD9122 Functional Block Diagram Rev. 0 | Page 3 of 56 AD9122 AD9122 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 AVDD33 = 3.3 V, DVDD18 DVDD18 = 1.8 V, CVDD18 CVDD18 =1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Output Resistance Gain DAC Monotonicity Settling Time to Within ±0.5 LSB MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 AVDD33 CVDD18 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD18 DVDD18 IOVDD POWER CONSUMPTION 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL Off 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL On 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off AVDD33 AVDD33 CVDD18 CVDD18 DVDD18 DVDD18 Power-Down Mode Power Supply Rejection Ratio, AVDD33 AVDD33 OPERATING RANGE 1 Min Typ 16 Max ±2.1 ±3.7 -0.001 -3.6 8.66 -1.0 0 ±2 19.6 Unit Bits LSB LSB +0.001 +3.6 31.66 +1.0 10 Guaranteed 20 % FSR % FSR mA V M ns 0.04 100 30 ppm/°C ppm/°C ppm/°C 1.2 5 V k 3.13 1.71 3.3 1.8 3.47 1.89 V V 1.71 1.71 1.8 1.8/2.5 1.89 2.94 V V 1241 57 90 495 9.8 +0.3 +85 mW mW mW mA mA mA mW % FSR/V °C 834 913 1135 55 85 444 2.5 -0.3 -40 Based on a 10 k external resistor. Rev. 0 | Page 4 of 56 +25 AD9122 AD9122 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 AVDD33 = 1.8 V, IOVDD = 3.3 V, DVDD18 DVDD18 = 1.8 V, CVDD18 CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input VIN Logic High (IOVDD = 1.8 V) Input VIN Logic High (IOVDD = 2.5 V) Input VIN Logic Low (IOVDD = 1.8 V) Input VIN Logic Low (IOVDD = 2.5 V) CMOS OUTPUT LOGIC LEVEL Output VOUT Logic High Output VOUT Logic High Output VOUT Logic Low Output VOUT Logic Low LVDS RECEIVER INPUTS 1 Input Voltage Range, VIA or VIB Input Differential Threshold, VIDTH Input Differential Hysteresis, VIDTHH to VIDTHL Receiver Differential Input Impedance, RIN LVDS Input Rate DAC CLOCK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage Maximum Clock Rate REFCLK INPUT (REFCLKP, REFCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage REFCLK Frequency (PLL Mode) REFCLK Frequency (SYNC Mode) SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High (tPWH) Minimum Pulse Width Low (tPWOL) Setup Time, SDI to SCLK (tDS) Hold Time, SDI to SCLK (tDH) Data Valid, SDO to SCLK (tDV) Setup Time, CS to SCLK (tDCSB) 1 Conditions Min Typ Max Unit 0.6 0.8 V V V V 0.4 0.4 V V V V 1.2 1.6 IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 1.8 V IOVDD = 2.5 V 1.4 1.8 825 -100 1575 +100 20 80 120 mV mV mV See Table 5 100 500 1.25 2000 mV V MSPS 500 1.25 Self biased input, ac couple 2000 mV V MHz MHz 1200 100 1 GHz fVCO 26 Hz See Multichip Synchronization section for conditions 15.625 0 600 600 40 12.5 12.5 1.9 0.2 23 1.4 LVDS receiver is compliant to the IEEE 1596 reduced range link, unless otherwise noted. DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. Parameter LATENCY (DACCLK Cycles) 1× Interpolation (With or Without Modulation) 2× Interpolation (With or Without Modulation) 4× Interpolation (With or Without Modulation) 8× Interpolation (With or Without Modulation) Inverse Sinc Fine Modulation Power-Up Time Min Typ 64 135 292 608 20 8 260 Rev. 0 | Page 5 of 56 Max Unit Cycles Cycles Cycles Cycles Cycles Cycles ms MHz ns ns ns ns ns ns AD9122 AD9122 AC SPECIFICATIONS TMIN to TMAX, AVDD33 AVDD33 = 3.3 V, DVDD18 DVDD18 = 1.8 V, CVDD18 CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 100 MSPS, fOUT = 20 MHz fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 70 MHz fDAC = 800 MSPS, fOUT = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 60 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 100 MHz NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING fDAC = 200 MSPS, fOUT = 80 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 80 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz fDAC = 491.52 MSPS, fOUT = 122.88 MHz fDAC = 983.04 MSPS, fOUT = 122.88 MHz W-CDMA SECOND ACLR, SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz fDAC = 491.52 MSPS, fOUT = 122.88 MHz fDAC = 983.04 MSPS, fOUT = 122.88 MHz Min Typ Max Unit 78 80 69 72 dBc dBc dBc dBc 84 86 84 81 dBc dBc dBc dBc -162 -163 -164 dBm/Hz dBm/Hz dBm/Hz 84 82 83 dBc dBc dBc 88 86 88 dBc dBc dBc Table 5. Interface Speeds Bus Width Nibble (4 Bits) Byte (8 Bits) Word (16 Bits) Interpolation Factor 1× 2× (HB1) 2× (HB2) 4× 8× 1× 2× (HB1) 2× (HB2) 4× 8× 1× 2× (HB1) 2× (HB2) 4× 8× 1.8 V ± 5% 1100 1100 1100 1100 1100 1100 1100 1100 1100 550 1100 900 1100 550 275 Rev. 0 | Page 6 of 56 fBUS (Mbps) 1.8 V ± 2% 1200 1200 1200 1200 1200 1200 1200 1200 1200 600 1200 1000 1200 600 300 1.9 V ± 5% 1200 1200 1200 1200 1200 1200 1200 1200 1200 600 1200 1000 1200 600 300 AD9122 AD9122 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter AVDD33 AVDD33 IOVDD DVDD18 DVDD18, CVDD18 CVDD18 AVSS EPAD CVSS DVSS FSADJ, REFIO, IOUT1P/IOUT1N, IOUT2P/IOUT2N D[15:0]P/D[15:0]N, FRAMEP/FRAMEN, DCIP/DCIN DACCLKP/DACCLKN, REFCLKP/REFCLKN RESET, IRQ, CS, SCLK, SDIO, SDO Junction Temperature Storage Temperature Range The exposed paddle (EPAD) must be soldered to the ground plane for the 72-lead, LFCSP. The EPAD performs as an electrical and thermal connection to the board. With Respect To AVSS, EPAD, CVSS, DVSS AVSS, EPAD, CVSS, DVSS AVSS, EPAD, CVSS, DVSS EPAD, CVSS, DVSS AVSS, CVSS, DVSS AVSS, EPAD, DVSS AVSS, EPAD, CVSS AVSS -0.3 V to AVDD33 AVDD33 + 0.3 V EPAD, DVSS -0.3 V to DVDD18 DVDD18 + 0.3 V DVSS -0.3 V to CVDD18 CVDD18 + 0.3 V EPAD, DVSS -0.3 V to IOVDD + 0.3 V Rating -0.3 V to +3.6 V Typical JA, JB, and JC are specified for a 4-layer board in still air. Airflow increases heat dissipation effectively reducing JA and JB. -0.3 V to +3.3 V -0.3 V to +2.1 V Table 7. Thermal Resistance Package 72-Lead LFCSP_VQ -0.3 V to +0.3 V -0.3 V to +0.3 V ESD CAUTION -0.3 V to +0.3 V -0.3 V to +0.3 V 125°C -65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 56 JA 20.7 JB 10.9 JC 1.1 Unit °C/W Conditions EPAD soldered AD9122 AD9122 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 CVDD18 CVDD18 CVDD18 CVDD18 REFCLKP REFCLKN AVDD33 AVDD33 IOUT1P IOUT1N AVDD33 AVDD33 AVSS FSADJ REFIO AVSS AVDD33 AVDD33 IOUT2N IOUT2P AVDD33 AVDD33 AVSS NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9122 AD9122 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 RESET CS SCLK SDIO SDO DVDD18 DVDD18 D0N D0P D1N D1P DVSS DVDD18 DVDD18 D2N D2P D3N D3P D4N D4P NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD MUST BE CONNECTED TO AVSS. 08281-003 D11P D11N D10P D10N D9P D9N D8P D8N DCIP DCIN DVDD18 DVDD18 DVSS D7P D7N D6P D6N D5P D5N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 CVDD18 DACCLKP DACCLKN CVSS FRAMEP FRAMEN IRQ D15P D15N NC IOVDD DVDD18 DVDD18 D14P D14N D13P D13N D12P D12N Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Mnemonic CVDD18 CVDD18 DACCLKP DACCLKN CVSS FRAMEP FRAMEN IRQ D15P D15N NC IOVDD DVDD18 DVDD18 D14P D14N D13P D13N D12P D12N D11P D11N D10P D10N D9P D9N D8P D8N Description 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. DAC Clock Input, Positive. DAC Clock Input, Negative. Clock Supply Common. Frame Input, Positive. Frame Input, Negative. Interrupt Request. Open-drain, active low output. Data Bit 15 (MSB), Positive. Data Bit 15 (MSB), Negative. No connection to device. Supply Pin for Serial Ports, RESET and IRQ. 1.8 V to 2.8 V can be supplied to this pin. 1.8 V Digital Supply. Supplies power to digital core and digital data ports. Data Bit 14, Positive. Data Bit 14, Negative. Data Bit 13, Positive. Data Bit 13, Negative. Data Bit 12, Positive. Data Bit 12, Negative. Data Bit 11, Positive. Data Bit 11, Negative. Data Bit 10, Positive. Data Bit 10, Negative. Data Bit 9, Positive. Data Bit 9, Negative. Data Bit 8, Positive. Data Bit 8, Negative. Rev. 0 | Page 8 of 56 AD9122 AD9122 Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Mnemonic DCIP DCIN DVDD18 DVDD18 DVSS D7P D7N D6P D6N D5P D5N D4P D4N D3P D3N D2P D2N DVDD18 DVDD18 DVSS D1P D1N D0P D0N DVDD18 DVDD18 SDO SDIO SCLK CS RESET NC AVSS AVDD33 AVDD33 IOUT2P IOUT2N AVDD33 AVDD33 AVSS REFIO FSADJ AVSS AVDD33 AVDD33 IOUT1N IOUT1P AVDD33 AVDD33 REFCLKN REFCLKP CVDD18 CVDD18 CVDD18 CVDD18 EPAD Description Data Clock Input, Positive. Data Clock Input, Negative. 1.8 V Digital Supply. Digital Common. Data Bit 7, Positive. Data Bit 7, Negative. Data Bit 6, Positive. Data Bit 6, Negative. Data Bit 5, Positive. Data Bit 5, Negative. Data Bit 4, Positive. Data Bit 4, Negative. Data Bit 3, Positive. Data Bit 3, Negative. Data Bit 2, Positive. Data Bit 2, Negative. 1.8 V Digital Supply. Digital Common. Data Bit 1, Positive. Data Bit 1, Negative. Data Bit 0, Positive. Data Bit 0, Negative. 1.8 V Digital Supply. Serial Port Data Output (CMOS Levels with Respect to IOVDD). Serial Port Data Input/Output (CMOS Levels with Respect to IOVDD). Serial Port Clock Input (CMOS Levels With Respect to IOVDD). Serial Port Chip Select. Active Low (CMOS Levels With Respect to IOVDD). Reset. Active Low (CMOS Levels With Respect to IOVDD). No connection to device. Analog Supply Common. 3.3 V Analog Supply. Q DAC Positive Current Output. Q DAC Negative Current Output. 3.3 V Analog Supply. Analog Supply Common. Voltage Reference. Nominally 1.2 V output. Should be decoupled to analog common. Full-Scale Current Output Adjust. Place a 10 k resistor on the analog common. Analog Common. 3.3 V Analog Supply. I DAC Positive Current Output. I DAC Negative Current Output. 3.3 V Analog Supply. PLL Reference Clock Input, Negative. This pin has secondary function as SYNC input. PLL Reference Clock Input, Positive. This pin has secondary function as SYNC input. 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. Exposed pad must be connected to AVSS. This provides an electrical, thermal, and mechanical connection to the PCB. Rev. 0 | Page 9 of 56 AD9122 AD9122 TYPICAL PERFORMANCE CHARACTERISTICS 0 ­10 ­20 ­20 ­30 ­40 ­50 ­60 ­70 ­80 ­30 ­40 ­50 ­60 ­70 ­80 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) 150 200 250 300 350 400 450 0 0dBFS ­6dBFS ­12dBFS ­18dBFS ­10 ­20 ­30 HARMONICS (dBc) ­40 ­50 ­60 ­70 ­80 ­30 ­40 ­50 ­60 ­70 ­80 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) ­20 100 150 200 250 300 350 400 450 fOUT (MHz) 0 fDATA = 100MSPS 100MSPS, SECOND HARMONIC fDATA = 100MSPS 100MSPS, THIRD HARMONIC fDATA = 150MSPS 150MSPS, SECOND HARMONIC fDATA = 150MSPS 150MSPS, THIRD HARMONIC ­10 50 Figure 8. Third Harmonic vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 400 MSPS, fSC = 20 mA Figure 5. Harmonics vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 0 08281-105 ­90 ­100 08281-102 ­90 ­100 10mA, 20mA, 30mA, 10mA, 20mA, 30mA, ­10 ­20 HARMONICS (dBc) ­30 ­40 ­50 ­60 ­70 ­30 SECOND HARMONIC SECOND HARMONIC SECOND HARMONIC THIRD HARMONIC THIRD HARMONIC THIRD HARMONIC ­40 ­50 ­60 ­70 ­80 ­80 ­90 ­90 ­100 0 100 200 300 400 500 600 fOUT (MHz) 700 08281-103 ­100 Figure 6. Harmonics vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) Figure 9. Second Harmonic vs. fOUT over fSC, 2× Interpolation, fDATA = 400 MSPS, Digital Scale = 0 dBFS Rev. 0 | Page 10 of 56 08281-106 HARMONICS (dBc) ­20 100 fOUT (MHz) fDATA = 100MSPS 100MSPS, SECOND HARMONIC fDATA = 100MSPS 100MSPS, THIRD HARMONIC fDATA = 200MSPS 200MSPS, SECOND HARMONIC fDATA = 200MSPS 200MSPS, THIRD HARMONIC ­10 50 Figure 7. Second Harmonic vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 400 MSPS, fSC = 20 mA Figure 4. Harmonics vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 0 08281-104 ­90 ­100 08281-101 ­90 ­100 HARMONICS (dBc) 0dBFS ­6dBFS ­12dBFS ­18dBFS ­10 HARMONICS (dBc) HARMONICS (dBc) 0 fDATA = 250MSPS 250MSPS, SECOND HARMONIC fDATA = 250MSPS 250MSPS, THIRD HARMONIC fDATA = 400MSPS 400MSPS, SECOND HARMONIC fDATA = 400MSPS 400MSPS, THIRD HARMONIC AD9122 AD9122 0 fDATA = 250MSPS 250MSPS fDATA = 400MSPS 400MSPS ­20 ­30 ­40 ­50 ­60 2× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 250MSPS 250MSPS, fOUT = 101MHz ­70 ­80 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) 08281-107 ­90 Figure 10. Highest Digital Spur vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA ­64 START 1.0MHz #RES BW 10kHz VBW 10kHz STOP 500.0MHz SWEEP 6.017s (601 PTS) 08281-110 HIGHEST DIGITAL SPUR (dBc) ­10 Figure 13. 2× Interpolation, Single-Tone Spectrum fDATA = 100MSPS 100MSPS fDATA = 200MSPS 200MSPS ­68 ­70 ­72 ­74 4× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 200MSPS 200MSPS, fOUT = 151MHz ­76 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) 08281-108 ­78 START 1.0MHz #RES BW 10kHz VBW 10kHz STOP 800.0MHz SWEEP 9.634s (601 PTS) 08281-111 HIGHEST DIGITAL SPUR (dBc) ­66 Figure 14. 4× Interpolation, Single-Tone Spectrum Figure 11. Highest Digital Spur vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA ­64 fDATA = 100MSPS 100MSPS fDATA = 150MSPS 150MSPS ­68 ­70 ­72 ­74 ­76 0 100 200 300 400 500 600 700 fOUT (MHz) Figure 12. Highest Digital Spur vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA Rev. 0 | Page 11 of 56 START 1.0MHz #RES BW 10kHz VBW 10kHz STOP 800.0MHz SWEEP 9.634s (601 PTS) Figure 15. 8× Interpolation, Single-Tone Spectrum 08281-112 8× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 100MSPS 100MSPS, fOUT = 131MHz 08281-109 HIGHEST DIGITAL SPUR (dBc) ­66 AD9122 AD9122 0 0 fDATA = 250MSPS 250MSPS fDATA = 400MSPS 400MSPS ­10 ­20 ­30 ­30 IMD (dBc) ­20 ­40 ­50 ­40 ­50 ­60 ­60 ­70 ­70 ­80 ­80 ­90 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) 08281-113 ­90 0 150 200 250 300 350 400 450 Figure 19. IMD vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 400 MSPS, fSC = 20 mA ­50 fDATA = 100MSPS 100MSPS fDATA = 200MSPS 200MSPS ­10 100 fOUT (MHz) Figure 16. IMD vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 50 08281-116 IMD (dBc) 0dBFS ­6dBFS ­12dBFS ­18dBFS ­10 IFS = 20mA IFS = 30mA IFS = 10mA ­55 ­20 ­60 IMD (dBc) IMD (dBc) ­30 ­40 ­50 ­65 ­70 ­60 ­75 ­70 ­80 ­80 50 100 150 200 250 300 350 400 450 fOUT (MHz) 0 150 200 250 300 350 400 450 Figure 20. IMD vs. fOUT over fSC, 2× Interpolation, fDATA = 400 MSPS, Digital Scale = 0 dBFS ­40 fDATA = 100MSPS 100MSPS ­45 ­20 ­50 ­30 ­55 ­40 ­60 IMD (dBc) ­10 ­50 ­60 PLL ON ­65 PLL OFF ­70 ­70 ­75 ­80 ­80 ­90 ­85 ­90 0 50 100 150 200 250 300 350 400 fOUT (MHz) 450 Figure 18. IMD vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 50 100 150 200 250 300 350 fOUT (MHz) Figure 21. IMD vs. fOUT, PLL On vs. PLL Off Rev. 0 | Page 12 of 56 400 450 08281-118 ­100 08281-115 IMD (dBc) 100 fOUT (MHz) Figure 17. IMD vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 50 08281-117 ­85 0 08281-114 ­90 AD9122 AD9122 ­152 1×, fDATA 2×, fDATA 4×, fDATA 8×, fDATA ­154 ­161.0 = 200MSPS 200MSPS = 200MSPS 200MSPS = 200MSPS 200MSPS = 100MSPS 100MSPS 1×, fDATA 2×, fDATA 4×, fDATA 8×, fDATA ­161.5 ­162.0 = 200MSPS 200MSPS = 200MSPS 200MSPS = 200MSPS 200MSPS = 100MSPS 100MSPS ­156 NSD (dBm/Hz) NSD (dBm/Hz) ­162.5 ­158 ­160 ­163.0 ­163.5 ­164.0 ­162 ­164.5 ­164 ­165.0 50 100 150 200 250 300 350 400 450 fOUT (MHz) Figure 22. 1-Tone NSD vs. fOUT over Interpolation Rate, Digital Scale = 0 dBFS, fSC = 20 mA, PLL Off ­154 0 150 200 250 300 350 400 450 Figure 25. 8-Tone NSD vs. fOUT over Interpolation Rate, Digital Scale = 0 dBFS, fSC = 20 mA, PLL Off ­161.0 0dBFS ­6dBFS ­12dBFS ­18dBFS ­161.5 ­162.0 ­162.5 NSD (dBm/Hz) ­158 NSD (dBm/Hz) 100 fOUT (MHz) 0dBFS ­6dBFS ­12dBFS ­18dBFS ­156 50 08281-122 ­165.5 0 08281-119 ­166 ­160 ­162 ­164 ­163.0 ­163.5 ­164.0 ­164.5 ­165.0 ­165.5 ­166 ­166.0 50 100 150 200 250 300 350 400 450 fOUT (MHz) 0 150 200 250 300 350 400 450 Figure 26. 8-Tone NSD vs. fOUT over Digital Scale, fDATA = 200 MSPS, 4× Interpolation, fSC = 20 mA, PLL Off ­160 2×, fDATA = 200MSPS 200MSPS 4×, fDATA = 200MSPS 200MSPS 8×, fDATA = 100MSPS 100MSPS ­159 100 fOUT (MHz) Figure 23. 1-Tone NSD vs. fOUT over Digital Scale, fDATA = 200 MSPS, 4× Interpolation, fSC = 20 mA, PLL Off ­158 50 08281-123 ­166.5 0 08281-120 ­168 2×, fDATA = 200MSPS 200MSPS 4×, fDATA = 200MSPS 200MSPS 8×, fDATA = 100MSPS 100MSPS ­161 ­160 NSD (dBm/Hz) NSD (dBm/Hz) ­162 ­161 ­162 ­163 ­163 ­164 ­164 ­165 ­165 ­166 100 150 200 250 fOUT (MHz) 300 350 400 450 Figure 24. 1-Tone NSD vs. fOUT over Interpolation Rate, Digital Scale = 0 dBFS, fSC = 20 mA, PLL On 0 50 100 150 200 250 fOUT (MHz) 300 350 400 450 08281-124 50 08281-121 ­166 0 Figure 27. 8-Tone NSD vs. fOUT over Interpolation Rate, Digital Scale = 0 dBFS, fSC = 20 mA, PLL On Rev. 0 | Page 13 of 56 AD9122 AD9122 ­77 ­50 0dBFS ­3dBFS ­6dBFS ­78 ACLR (dBc) ­80 ­81 ­82 ­65 ­70 ­75 ­80 ­83 ­85 ­90 0 50 100 150 200 250 fOUT (MHz) 08281-125 ­84 0 100 200 300 400 500 fOUT (MHz) Figure 28. 1-Carrier W-CDMA ACLR vs. fOUT over fDAC, Adjacent Channel, PLL Off 08281-128 ACLR (dBc) PLL OFF PLL OFF PLL ON PLL ON ­60 ­79 Figure 31. 1-Carrier W-CDMA ACLR vs. fOUT, Adjacent Channel, PLL On vs. PLL Off ­78 ­70 0dBFS ­3dBFS ­6dBFS ­80 INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, ­72 ­74 PLL OFF PLL OFF PLL ON PLL ON ­76 ACLR (dBc) ­82 ACLR (dBc) INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, ­55 ­84 ­86 ­78 ­80 ­82 ­84 ­86 ­88 ­88 ­90 100 150 200 250 fOUT (MHz) 0 200 300 400 500 fOUT (MHz) Figure 29. 1-Carrier W-CDMA ACLR vs. fOUT over fDAC, Alternate Channel, PLL Off Figure 32. 1-Carrier W-CDMA ACLR vs. fOUT, Alternate Channel, PLL On vs. PLL Off ­70 ­70 INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, 0dBFS ­3dBFS ­6dBFS ­75 ACLR (dBc) ­75 ­80 ­85 ­90 PLL OFF PLL OFF PLL ON PLL ON ­80 ­85 ­90 ­95 0 50 100 150 200 fOUT (MHz) Figure 30. 1-Carrier W-CDMA ACLR vs. fOUT over fDAC, Second Alternate Channel, PLL Off 250 0 100 200 300 fOUT (MHz) 400 500 08281-130 ­95 08281-127 ACLR (dBc) 100 08281-129 50 08281-126 ­90 0 Figure 33. 1-Carrier W-CDMA ACLR vs. fOUT, Second Alternate Channel, PLL On vs. PLL Off Rev. 0 | Page 14 of 56 AD9122 AD9122 FREQ OFFSET 5.00MHz 10.00MHz 15.00MHz REF BW 3.840MHz 3.840MHz 2.888MHz LOWER dBc dBm ­75.96 ­85.96 ­85.33 ­95.33 ­95.81 ­95.81 UPPER dBc dBm ­77.13 ­87.13 ­85.24 ­95.25 ­85.43 ­95.43 VBW 30kHz STOP 174.42MHz SWEEP 206.9ms (601 PTS) TOTAL CARRIER POWER ­11.19dBm/15.3600MHz RRC FILTER: OFF FILTER ALPHA 0.22 REF CARRIER POWER ­16.89dBm/3.84000MHz 1 2 3 4 ­16.92dBm ­16.89dBm ­17.43dBm ­17.64dBm OFFSET FREQ 5.000MHz 10.00MHz 15.00MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz LOWER dBc dBm ­65.88 ­82.76 ­68.17 ­85.05 ­70.42 ­87.31 UPPER dBc dBm ­67.52 ­84.40 ­69.91 ­86.79 ­71.40 ­88.28 08281-132 RMS RESULTS CARRIER POWER ­10.00dBm/ 3.840MHz START 125.88MHz #RES BW 30kHz VBW 30kHz STOP 166.94MHz SWEEP 143.6ms (601 PTS) 08281-131 START 133.06MHz #RES BW 30kHz Figure 35. 1-Carrier W-CDMA ACLR Performance, IF = ~150 MHz Figure 34. 4-Carrier W-CDMA ACLR Performance, IF = ~150 MHz Rev. 0 | Page 15 of 56 AD9122 AD9122 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Settling Time The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to the Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output. Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUT1P, 0 mA output is expected when the inputs are all 0s. For IOUT1N, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection (PSR) The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) The ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. 0 | Page 16 of 56 AD9122 AD9122 THEORY OF OPERATION The AD9122 AD9122 combines many features that make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband transmitters. The speed and performance of the AD9122 AD9122 allows wider bandwidths and more carriers to be synthesized than in previously available DACs. In addition, these devices include an innovative low power, 32-bit complex NCO that greatly increases the ease of frequency placement. The AD9122 AD9122 offers features that allow simplified synchronization with incoming data and between multiple devices. Auxiliary DACs are also provided on chip for output dc offset compensation (for LO compensation in SSB transmitters) and for gain matching (for image rejection optimization in SSB transmitters). SERIAL PORT OPERATION The serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9122 AD9122. Single or multiple byte transfers are supported, as well as MSBfirst or LSB-first transfer formats. The serial interface ports can be configured as a single pin I/O (SDIO) or two unidirectional pins for input/output (SDIO/SDO). CS 53 SPI PORT 08281-010 SCLK 52 DATA FORMAT The instruction byte contains the information shown in Table 9. Table 9. Serial Port Instruction Byte I7 (MSB) R/W I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 I0 (LSB) A0 R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation, and Logic 0 indicates a write operation. A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A6 is the starting byte address. The remaining register addresses are generated by the device based on the LSB_FIRST bit (Register 0x00, Bit 6). SERIAL PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. SDO 50 SDIO 51 The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word and NCO phase offsets that only change when the frequency update bit (Register 0x36, Bit 0) is set. Chip Select (CS) Figure 36. Serial Port Interface Pins There are two phases to a communication cycle with the AD9122 AD9122. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first eight SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle, Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the device. A logic high on the CS pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next eight rising SCLK edges represent the instruction bits of the current I/O operation. An active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins go to a high impedance state when this input is high. During the communication cycle, chip select should stay low. Serial Data I/O (SDIO) Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, configuring the SDIO pin as unidirectional. Serial Data Out (SDO) Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the device operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Rev. 0 | Page 17 of 56 AD9122 AD9122 SERIAL PORT OPTIONS INSTRUCTION CYCLE DATA TRANSFER CYCLE CS The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by LSB_FIRST (Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0). SCLK SDIO When LSB_FIRST = 1 (LSB-first), the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle. SCLK The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first mode is active. The serial port controller address increments from the data address written toward 0x7F for multibyte I/O operations if the LSB-first mode is active. INSTRUCTION CYCLE A4 A3 A2 A1 D7 D6N D5N D30 D20 D10 D00 D4N D5N D6N D7N D00 D10 D20 D4N D5N D6N D7 N tSCLK tDS SDIO tPWL tDH INSTRUCTION BIT 7 INSTRUCTION BIT 6 08281-013 tPWH Figure 39. Timing Diagram for Serial Port Register Write CS tDV SDIO, SDO DATA BIT n DATA BIT n ­ 1 Figure 40. Timing Diagram for Serial Port Register Read Figure 37. Serial Register Interface Timing MSB-First Rev. 0 | Page 18 of 56 08281-014 SCLK D30 D20 D10 D00 D7 D6N D5N N0 N1 R/W D00 D10 D20 CS DATA TRANSFER CYCLE A0 A3 A4 tDS 08281-011 SDO A5 A2 Figure 38. Serial Register Interface Timing LSB-First SCLK R/W A6 A1 SDO CS SDIO A0 08281-012 When LSB_FIRST = 0 (MSB-first), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow from the high address to low address. In MSB-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. AD9122 AD9122 DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS Table 10. Device Configuration Register Map Reg Name Comm Power Control Addr (Hex) 0x00 0x01 Data Format 0x03 Interrupt Enable 0x04 Interrupt Enable Bit 7 SDIO Powerdown DAC I Binary data format Enable PLL lock lost Bit 6 LSB_FIRST Powerdown DAC Q Q data first Bit 5 Reset Powerdown data receiver MSB swap Bit 4 Enable PLL locked 0x05 0 0 Enable sync signal lost 0 Event Flag 0x06 PLL lock lost PLL locked Event Flag 0x07 Clock Receiver Control 0x08 Enable sync signal locked Enable AED compar pass Sync signal locked AED compar pass REFCLK crosscorrection PLL Control 0x0A PLL Control 0x0B PLL Control 0x0C PLL Control 0x0D PLL Status PLL Status 0x0E 0x0F PLL lock Sync Control 0x10 Sync enable Data/FIFO rate toggle Sync Control Sync Status 0x11 0x12 Sync lost Sync locked Sync Status 0x17 0x18 FIFO Status 0x19 DACCLK crosscorrection Bit 2 Bit 1 Bit 0 Powerdown aux ADC PLL lock status Data bus width[1:0] Enable sync phase locked Enable AED compar fail Sync phase locked AED compar fail 0 Enable soft FIFO sync Enable SED compar fail Soft FIFO sync SED compar fail 0 0x00 0 0 0x00 FIFO Warning 1 FIFO Warning 2 N/A N/A 0 0 0x3F 0x40 0x00 PLL Charge Pump Current[4:0] N0[1:0] PLL cross control enable 0xD1 N1[1:0] 0xD9 VCO Control Voltage[3:0] VCO Band Readback[5:0] 0x00 0x00 Sync Averaging[2:0] Rising edge sync Sync Phase Request[5:0] 0x48 Sync Phase Readback[7:0] (6.2 format) LVDS FRAME level high FIFO Warning 1 0x00 Enable FIFO Warning 2 Manual VCO Band[5:0] PLL Loop Bandwidth[1:0] N2[1:0] Default 0x00 0x10 Enable FIFO Warning 1 PLL VCO enable 0x15 FIFO Control FIFO Status REFCLK duty correction PLL manual enable 0x13 Data Receiver Status DACCLK duty correction PLL enable Sync signal lost Bit 3 LVDS FRAME level low LVDS DCI level high LVDS DCI level low N/A LVDS data level high LVDS data level low FIFO Phase Offset[2:0] FIFO FIFO soft FIFO reset soft align aligned align request ack FIFO Warning 2 FIFO Level[7:0] Rev. 0 | Page 19 of 56 0x00 N/A N/A 0x04 N/A N/A AD9122 AD9122 Reg Name Datapath Control Addr (Hex) 0x1B Bit 7 Bypass premod Bit 6 Bypass Sinc-1 Bit 5 Bypass NCO Bit 4 Bit 3 NCO gain Bit 2 Bit 1 Bypass Select phase sideband comp and dc offset HB1[1:0] Bit 0 Send I data to Q data Default 0xE4 Bypass HB1 0x00 Bypass HB2 Bypass HB3 0x00 0x00 0x08 0x00 0x00 0x00 0x08 0x00 HB1 Control 0x1C HB2 Control HB3 Control Chip ID FTW LSB FTW FTW FTW MSB NCO Phase Offset LSB NCO Phase Offset MSB NCO FTW Update 0x1D 0x1E 0x1F 0x30 0x31 0x32 0x33 0x34 HB2[5:0] HB3[5:0] Chip ID[7:0] FTW[7:0] FTW[15:8] FTW[23:16] FTW[31:24] NCO Phase Offset[7:0] 0x35 NCO Phase Offset[15:8] I Phase Adj LSB I Phase Adj MSB Q Phase Adj LSB Q Phase Adj MSB I DAC Offset LSB I DAC Offset MSB Q DAC Offset LSB Q DAC Offset MSB I DAC FS Adj. I DAC Control 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E I DAC Offset[7:0] I DAC Offset[15:8] Q DAC Offset[7:0] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x3F Q DAC Offset[15:8] 0x00 0x36 0x40 0x41 Aux DAC I Data I Aux DAC Control 0x42 0x43 Q DAC FS Adj. Q DAC Control 0x44 0x45 Aux DAC Q Data Q Aux DAC Control 0x46 0x47 Die Temp Range Control Die Temp LSB Die Temp MSB Update FTW ack Update FTW request I Phase Adj[9:8] Q Phase Adj[7:0] Q Phase Adj[9:8] I DAC FS Adj[7:0] 0xF9 0x01 I Aux DAC[9:8] 0x00 0x00 Q DAC FS Adj[9:8] 0xF9 0x01 I Aux DAC[7:0] I Aux DAC sign I Aux DAC current direction I Aux DAC Sleep Q DAC FS Adj[7:0] Q DAC sleep Q Aux DAC[7:0] Q Aux DAC sign Q Aux DAC current direction Q Aux DAC[9:8] Q Aux DAC Sleep FS Current[2:0] Ref Current[2:0] Capacitor value Die Temp[7:0] Die Temp[15:8] SED compare enable 0x00 I DAC FS Adj[9:8] I DAC sleep 0x49 0x4A 0x67 Frame FTW request I Phase Adj[7:0] 0x48 SED Control Frame FTW ack 0x00 Sample error detected Rev. 0 | Page 20 of 56 Autoclear enable 0x00 0x00 0x02 N/A N/A Compare fail Compare pass 0x00 AD9122 AD9122 Reg Name Compare I0 LSBs Compare I0 MSBs Compare Q0 LSBs Compare Q0 MSBs Compare I1 LSBs Compare I1 MSBs Compare Q1 LSBs Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Addr (Hex) 0x68 0x69 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Compare Value I0[7:0] Compare Value I0[15:8] Bit 2 Bit 1 Bit 0 Default 0xB6 0x7A 0x6A Compare Value Q0[7:0] 0x45 0x6B Compare Value Q0[15:8] 0xEA 0x6C 0x6D 0x6E Compare Value I1[7:0] Compare Value I1[15:8] Compare Value Q1[7:0] 0x16 0x1A 0xC6 0x6F Compare Value Q1[15:8] 0xAA 0x70 0x71 0x72 0x73 Errors Detected I_BITS[7:0] Errors Detected I_BITS[15:8] Errors Detected Q_BITS[7:0] Errors Detected Q_BITS[15:8] 0x00 0x00 0x00 0x00 Table 11. Device Configuration Register Descriptions Reg Name Comm Addr (Hex) 00 Control 01 Name SDIO 6 Power Bit 7 LSB_FIRST 5 7 6 5 Reset Power-down DAC I Power-down DAC Q Power-down data receiver Power-down auxiliary ADC PLL lock status 4 0 Description SDIO Operation. 0 = SDIO operates as an input only. 1 = SDIO operates as bidirectional input/output. Serial port communication LSB or MSB first. 0 = MSB first. 1 = LSB first. Reset is asserted when this bit transitions from 0 to 1. 1 = power down DAC I. 1 = power down DAC Q. 1 = power down the input data receiver. Default 0 1 = power down auxiliary ADC for temperature sensor. 0 1 = PLL is locked. 0 Rev. 0 | Page 21 of 56 0 0 0 0 0 AD9122 AD9122 Reg Name Data Format Addr (Hex) 03 Q data first 5 MSB swap 1:0 04 Name Binary data format 6 Interrupt Enable Bit 7 Data bus width 7 6 5 4 Enable PLL lock lost Enable PLL locked Enable sync signal lost Enable sync signal locked Enable sync phase locked Enable soft FIFO sync Enable FIFO Warning 1 Enable FIFO Warning 2 3 2 1 0 Interrupt Enable 05 7 6 5 4 3 2 1 0 Set to 0 Set to 0 Set to 0 Enable AED comparison pass Enable AED comparison fail Enable SED comparison fail Set to 0 Set to 0 Description 0 = input data is in twos complement format. 1 = input data is in binary format. Indicates I/Q data pairing on data input. 0 = I data sent to data receiver first. 1 = Q data sent to data receiver first. Swaps the bit order of the data input port. 0 = order of the data bits corresponds to the pin descriptions 1 = bit designations are swapped; most significant bits become the least significant bits Data receiver interface mode. 00 = word mode; 16-bit interface bus width. 01 = byte mode; 8-bit interface bus width. 10 = nibble mode; 4-bit interface bus width. 11 = invalid. See the LVDS Input Data Ports section for details on the operation of the different interface modes. 1 = enable interrupt for PLL lock lost. 1 = enable interrupt for PLL locked. 1 = enable interrupt for sync signal lock lost. 1 = enable interrupt for sync signal locked. Default 0 0 0 0 0 0 0 0 1 = enable interrupt for clock generation ready. 0 1 = enable interrupt for soft FIFO reset. 1 = enable interrupt for FIFO Warning 1. 1 = enable interrupt for FIFO Warning 2. 0 0 0 Set this bit to 0. Set this bit to 0. Set this bit to 0. 1 = enable interrupt for AED comparison pass. 0 0 0 0 1 = enable interrupt for AED comparison fail. 0 1 = enable interrupt for SED comparison fail. 0 Set this bit to 0. Set this bit to 0. 0 0 Rev. 0 | Page 22 of 56 AD9122 AD9122 Reg Name Event Flag Addr (Hex) 06 Bit 7 Name PLL lock lost 6 PLL locked 5 Sync signal lost 4 Sync signal locked 3 Sync phase locked 2 Soft FIFO sync 1 0 Event Flag 07 4 3 2 Clock Receiver Control 08 7 6 5 1 = indicates that a FIFO reset originating from a serial port-based request has successfully completed. This is a latched signal. FIFO Warning 1 1 = indicates that the difference between the FIFO read and write pointers is 1. FIFO Warning 2 1 = indicates that the difference between the FIFO read and write pointers is 2. Note that all bit event flags are cleared by writing the respective bit high. AED comparison pass 1 = indicates that the SED logic detected a valid input data pattern compared against the preprogrammed expected values. This is a latched signal. AED comparison fail 1 = indicates that the SED logic detected an invalid input data pattern comparison against the preprogrammed expected values. This is a latched signal that automatically clears when eight valid I/Q data pairs are received. SED comparison fail 1 = indicates that the SED logic detected an invalid input data pattern comparison against the preprogrammed expected values. This is a latched signal. Note that all bit event flags are cleared by writing the respective bit high. DACCLK duty correction 1 = enables duty-cycle correction on DACCLK input. 7 REFCLK duty correction DACCLK crosscorrection REFCLK crosscorrection PLL enable 6 PLL manual enable 5:0 Manual VCO band 5 PLL VCO enable 4 PLL Control PLL Control 0A 0B Description 1 = indicates that the PLL, which had been previously locked, has unlocked from the reference signal. This is a latched signal. 1 = indicates that the PLL has locked to the reference clock input. 1 = indicates that the sync logic, which had been previously locked, has lost alignment. This is a latched signal. 1 = indicates that the sync logic did achieve sync alignment. This is indicated when no phase changes were requested for at least a few full averaging cycles. 1 = indicates that the internal digital clock generation logic is ready. This occurs when internal clocks are present and stable. Default 0 0 0 0 0 0 0 0 0 0 0 1 = enables duty-cycle correction on REFCLK input. 1 = enables differential crossing correction on the CLK input. 0 0 1 = enables differential crossing correction on the REFCLK input. 1 = enables the PLL clock multiplier. REFCLK input is used as the PLL reference clock signal. Enables the manual selection of the VCO band. 1 = manual mode; the correct VCO band must be determined by the user. Selects the VCO band to be used. 0 0 = disables the PLL VCO. 1 = enables the PLL VCO. Set this bit high prior to enabling PLL. Rev. 0 | Page 23 of 56 0 1 0 AD9122 AD9122 Reg Name PLL Control Addr (Hex) 0C Bit 7:6 4:0 PLL Charge Pump Current[4:0] 7:6 N2[1:0] 4 3:2 PLL cross control enable N0[1:0] 1:0 PLL Control 0D Name PLL Loop Bandwidth[1:0] N1[1:0] PLL Status 0E 7 3:0 PLL Status Sync Control 0F 5:0 10 7 6 PLL lock VCO Control Voltage[3:0] VCO Band Readback[5:0] Sync enable Data/FIFO rate toggle 3 Rising edge sync 2:0 Sync Averaging[2:0] Description Selects the PLL loop filter bandwidth. Default 3 00 = narrowest bandwidth. 01 = narrow/medium bandwidth. 10 = medium/wide bandwidth. 11 = widest bandwidth. Sets the nominal PLL charge pump current. 001 00000 = lowest current setting. 11111 = highest current setting. PLL control clock divider. It determines the ratio of the DACCLK rate to the PLL controller clock rate. 00 = fDACCLK/fPC_CLK = 2. 01 = fDACCLK/fPC_CLK = 4. 10 = fDACCLK/fPC_CLK = 8. 11 = fDACCLK/fPC_CLK = 16. fPC_CLK must always be less than 50 MHz. Enable PLL cross point controller. PLL VCO divider. It determines the ratio of the VCO output to the DACCLK frequencies. 00 = fVCO/fDACCLK = 1. 01 = fVCO/fDACCLK = 2. 10 = fVCO/fDACCLK = 4. 11 = fVCO/fDACCLK = 4. PLL Loop divider. It determines the ratio of the DACCLK to the REFCLK frequencies. 00 = fDACCLK/fREFCLK = 2. 01 = fDACCLK/fREFCLK = 4. 10 = fDACCLK/fREFCLK = 8. 11 = fDACCLK/fREFCLK = 16. The PLL generated clock is tracking the REFCLK input signal. VCO Control Voltage readback. See Table 24. R R Indicates the VCO band currently selected. R 1 = enables the synchronization logic. 0 = operates the synchronization at the FIFO reset rate. 1 = operates the synchronization at the data rate. 0 = sync is initiated on the falling edge of the sync input. 1 = sync is initiated on the rising edge of the sync input. Sets the number of input samples that are averaged in determining the sync phase. 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 110 = 64. 111 = 128. 0 0 Rev. 0 | Page 24 of 56 3 0 01 01 1 0 AD9122 AD9122 Reg Name Sync Control Addr (Hex) 11 Bit 5:0 Name Sync Phase Request[5:0] Sync Status 12 7 Sync lost Sync Status 13 6 7:0 Sync locked Sync Phase Readback[7:0] 4 LVDS DCI level high LVDS DCI level low LVDS data level high LVDS data level low 2:0 FIFO Phase Offset[2:0] 1 FIFO Status FIFO Status 18 LVDS FRAME level low 0 17 LVDS FRAME level high 1 FIFO Control 15 5 3 2 Data Receiver Status 19 7 6 2 FIFO Warning 1 FIFO Warning 2 FIFO soft align acknowledge FIFO soft align request 0 7:0 FIFO reset aligned FIFO Level[7:0] Description This sets the requested clock phase offset after sync. The offset unit is in DACCLK cycles. 000000 = 0 DACCLK cycles. 000001 = 1 DACCLK cycle. . 111111 = 63 DACCLK cycles. This enables repositioning of the DAC output with respect to the sync input. The offset can also be used to skew the DAC outputs between the synchronized DACs. 1 = indicates that synchronization had been attained but has been lost. 1 = indicates that synchronization has been attained. Indicates the averaged sync phase offset (6.2 format). 00000000 = 0.0. 00000001 = 0.25. . 11111110 = 63.50. 11111111 = 63.75. If this value differs from the requested sync phase value, this indicates sync timing errors. One or both of the LVDS FRAME input signals have exceeded 1.7 V. One or both of the LVDS FRAME input signals have crossed below 0.7 V. One or both of the LVDS DCI input signals have exceeded 1.7 V. One or both of the LVDS DCI input signals have crossed below 0.7 V. One or more of the LVDS Dx input signals have exceeded 1.7 V. One or both of the LVDS Dx input signals have crossed below 0.7 V. FIFO write pointer phase offset following FIFO reset. 000 = 0. 001 = 1. . 111 = 7. This is the difference between the read pointer and the write pointer values upon FIFO reset. The optimal value is nominally 4. FIFO read and write pointers within ±1. FIFO read and write pointers within ±2. FIFO read and write pointers are aligned after serial port initiated FIFO reset. Request FIFO read and write pointers alignment via serial port. FIFO read and write pointers aligned after hardware reset. Thermometer encoded measure of the FIFO level. Rev. 0 | Page 25 of 56 Default 0 R R R R R R R R R 0 0 0 0 0 0 AD9122 AD9122 Reg Name Datapath Control Addr (Hex) 1B Bit 7 6 5 3 Name Bypass Premod Bypass Sinc-1 Bypass NCO NCO gain 2 1 Bypass phase compensation and dc offset Select sideband 0 Send I data to Q data HB1 Control 1C 2:1 HB1[1:0] 0 Bypass HB1 HB2 Control 1D 6:1 HB2[5:0] 0 Bypass HB2 Description 1 = bypasses fS/2 premodulator. 1 = bypasses inverse sinc filter. 1 = bypasses NCO. 0 = default. No gain scaling is applied to the NCO input to the internal digital modulator. 1 = gain scaling of 0.5 is applied to the NCO input to the internal digital modulator. This can eliminate saturation of the modulator output for some combinations of data inputs and NCO signals. 1 = bypasses phase compensation. Default 1 1 1 0 0 = the modulator outputs high-side image. 1 = the modulator outputs low-side image. The image is spectrally inverted compared to the input data. 1 = ignores Q data from interface and disables the clocks to Q datapath. Sends I data to both I and Q DACs. 00 = input signal not modulated, filter pass band is from -0.4 to +0.4 of fIN1. 01 = input signal not modulated, filter pass band is from 0.1 to 0.9 of fIN1. 10 = input signal modulated by fIN1, filter pass band is from 0.6 to 1.4 of fIN1. 11 = input signal modulated by fIN1, filter pass band is from 1.1 to 1.9 of fIN1. 1 = bypasses first stage interpolation filter. 0 Modulation mode for I Side Half-Band Filter 2. 000000 = input signal not modulated, filter pass band is from -0.25 to +0.25 of fIN2. 001001 = input signal not modulated, filter pass band is from 0.0 to 0.5 of fIN2. 010010 = input signal not modulated, filter pass band is from 0.25 to 0.75 of fIN2. 011011 = input signal not modulated, filter pass band is from 0.5 to 1.0 of fIN2. 100100 = input signal modulated by fIN2, filter pass band is from 0.75 to 1.25 of fIN2. 101101 = input signal modulated by fIN2, filter pass band is from 1.0 to 1.5 of fIN2. 110110 = input signal modulated by fIN2, filter pass band is from 1.25 to 1.75 of fIN2. 111111 = input signal modulated by fIN2, filter pass band is from 1.5 to 2.0 of fIN2. 1 = bypasses second stage interpolation filter. Rev. 0 | Page 26 of 56 1 0 0 0 0 0 AD9122 AD9122 Reg Name HB3 Control Addr (Hex) 1E Bit 6:1 Name HB3[5:0] Chip ID FTW LSB FTW FTW FTW MSB 1F 30 31 32 33 0 7:0 7:0 7:0 7:0 7:0 Bypass HB3 Chip ID[7:0] FTW[7:0] FTW[15:8] FTW[23:16] FTW[31:24] NCO Phase Offset LSB NCO Phase Offset MSB NCO FTW Update 34 7:0 NCO Phase Offset[7:0] 35 7:0 NCO Phase Offset[15:8] 36 5 FRAME FTW acknowledge FRAME FTW request 4 1 I Phase Adj LSB I Phase Adj MSB 38 0 7:0 Update FTW acknowledge Update FTW request I Phase Adj[7:0] 39 1:0 I Phase Adj[9:8] Q Phase Adj LSB Q Phase Adj MSB 3A 7:0 Q Phase Adj[7:0] 3B 1:0 Q Phase Adj[9:8] Description Modulation mode for I Side Half-Band Filter 3. 000000 = input signal not modulated, filter pass band is from -0.2 to +0.2 of fIN3. 001001 = input signal not modulated, filter pass band is from 0.05 to 0.45 of fIN3. 010010 = input signal not modulated, filter pass band is from 0.3 to 0.7 of fIN3. 011011 = input signal not modulated, filter pass band is from 0.55 to 0.95 of fIN3. 100100 = input signal modulated by fIN3, filter pass band is from 0.8 to 1.2 of fIN3. 101101 = input signal modulated by fIN3, filter pass band is from 1.05 to 1.45 of fIN3. 110110 = input signal modulated by fIN3, filter pass band is from 1.3 to 1.7 of fIN3. 111111 = input signal modulated by fIN3, filter pass band is from 1.55 to 1.95 of fIN3. 1 = bypasses third stage interpolation filter. Chip ID. See Register 0x33. See Register 0x33. See Register 0x33. FTW[31:0] is the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when Bit 0 of Register 0x36 transitions from 0 to 1. See Register 0x35. Default 0 The NCO sets the phase of the complex carrier signal when the NCO is reset. The phase offset spans between 0° and 360°. Each bit represents an offset of 0.0055°. Value is in twos complement format. 1 = indicates that the NCO has been reset due to an extended FRAME pulse signal. 0 1 = the NCO is reset on the first extended FRAME pulse after this bit transitions from 0 to 1. 1 = indicates that the FTW has been updated. 0 0 1 = the FTW is updated on 0-to-1 transition of this bit. See Register 0x39. 0 0 I Phase Adj[9:0] is used to insert a phase offset between the I and Q datapaths. This can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for details. See Register 0x3B. 0 Q Phase Adj[9:0] is used to insert a phase offset between the I and Q datapaths. This can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for details. 0 Rev. 0 | Page 27 of 56 0 8 0 0 0 0 0 0 0 0 0 AD9122 AD9122 Reg Name I DAC Offset LSB I DAC Offset MSB Q DAC Offset LSB Q DAC Offset MSB I DAC FS Adjust Addr (Hex) 3C Bit 7:0 Name I DAC Offset[7:0] Description I DAC Offset[15:0] is a value added directly to the samples written to the I DAC. Default 0 3D 7:0 I DAC Offset[15:8] See Register 0x3C. 0 3E 7:0 Q DAC Offset[7:0] Q DAC Offset[15:0] is a value added directly to the samples written to the Q DAC. 0 3F 7:0 Q DAC Offset[15:8] See Register 0x3E. 0 40 7:0 I DAC FS Adj[7:0] F9 I DAC Control 41 7 I DAC sleep 1:0 I DAC FS Adj[9:8] I DAC FS Adj[9:0] sets the full-scale current of the I DAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 A. 0x000 = 8.64 mA. . 0x200 = 20.14 mA. . 0x3FF = 31.66 mA. 1 = puts the I-channel DAC into sleep mode (fast wake-up mode). See Register 0x40. Aux DAC I Data 42 7:0 I Aux DAC[7:0] I Aux DAC Control 43 7 I aux DAC sign 6 I aux DAC current direction I aux DAC sleep I Aux DAC[9:8] Q DAC FS Adj[7:0] Q DAC FS Adj. 44 5 1:0 7:0 Q DAC Control 45 7 Q DAC sleep 1:0 Q DAC FS Adj[9:8] I Aux DAC[9:0] sets the magnitude of the auxiliary DAC current. The range is 0 mA to 2 mA and the step size is 2 A. 0x000 = 0.000 mA. 0x001 = 0.002 mA. . 0x3FF = 2.046 mA. 0 = the auxiliary DAC I sign is positive, and the current is directed to the IOUT1P pin (Pin 67). 1 = the auxiliary DAC I sign is negative, and the current is directed to the IOUT1N pin (Pin 66). 0 = the auxiliary DAC I sources current. 1 = the auxiliary DAC I sinks current. I channel auxiliary DAC sleep. See Register 0x42. Q DAC FS Adj[9:0] sets the full-scale current of the I DAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 A. 0x000 = 8.64 mA. . 0x200 = 20.14 mA. . 0x3FF = 31.66 mA. 1 = puts the Q-channel DAC into sleep mode (fast wake-up mode). See Register 0x44. Rev. 0 | Page 28 of 56 0 1 0 0 0 0 0 F9 0 1 AD9122 AD9122 Reg Name Aux DAC Q Data Addr (Hex) 46 Bit 7:0 Name Q Aux DAC[7:0] Q Aux DAC Control 47 7 Q aux DAC sign 6 Q aux DAC current direction 5 Q aux DAC sleep 1:0 6:4 Q Aux DAC[9:8] FS Current[2:0] 3:1 Reference Current[2:0] 0 Capacitor value 49 7:0 Die Temp[7:0] 4A 7:0 Die Temp[15:8] 67 7 SED compare enable 5 Sample error detected 3 Autoclear enable 1 Compare fail 68 0 7:0 Compare pass Compare Value I0[7:0] 69 7:0 Compare Value I0[15:8] 6A 7:0 Compare Value Q0[7:0] Die Temp Range Control Die Temp LSB Die 0x48 Temp MSB SED Control Compare I0 LSBs Compare I0 MSBs Compare Q0 LSBs Description Q Aux DAC[9:0] sets the magnitude of the aux DAC current. The range is 0 mA to 2 mA and the step size is 2 A. 0x000 = 0.000 mA. 0x001 = 0.002 mA. . 0x3FF = 2.046 mA. 0 = the auxiliary DAC Q sign is positive, and the current is directed to the IOUT2P pin (Pin 58). 1 = the auxiliary DAC Q sign is negative, and the current is directed to the IOUT2N pin (Pin 59). 0 = the auxiliary DAC Q sources current. 1 = the auxiliary DAC Q sinks current. Q-channel auxiliary DAC sleep See Register 0x46. Auxiliary ADC full-scale current. 000 = lowest current. . 111 = highest current. Auxiliary ADC reference current. 000 = lowest current. 111 = highest current. Auxiliary ADC internal capacitor value. 0 = 5 pF. 1 = 10 pF. See Register 0x4A. Default 0 0 0 0 0 0 1 0 R Die Temp[15:0] indicates the approximate die temperature. 0xADCC = -39.9°C 0xC422 = 25.1°C . 0xD8A8 = 84.8°C (see Temperature Sensor section for details) 1 = enables the SED circuitry. None of the flags in this register or the values in Register 0x70 through Register 0x73 are significant if the SED is not enabled. 1 = indicates an error is detected. The bit remains set until cleared. Any write to this register clears this bit to 0. 1 = enables autoclear mode. This activates Bit 1 and Bit 0 of this register and causes Register 0x70 through Register 0x73 to be autocleared whenever eight consecutive sample data sets are received error free. 1 = indicates an error has been detected. This bit remains high until it is autocleared by the reception of eight consecutive error free comparisons or is cleared by writing to this register. 1 = indicates that the last sample comparison was error free. Compare Value I0[15:0] is the word that is compared with the I0 input sample captured at the input interface. See Register 0x68. R Compare Value Q0[15:0] is the word that is compared with the Q0 input sample captured at the input interface. 45 Rev. 0 | Page 29 of 56 0 0 0 0 0 B6 7A AD9122 AD9122 Reg Name Compare Q0 MSBs Compare I1 LSBs Compare I1 MSBs Compare Q1 LSBs Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Addr (Hex) 6B Bit 7:0 Name Compare Value Q0[15:8] Description See Register 0x6A Default EA 6C 7:0 Compare Value I1[7:0] 16 6D 7:0 Compare Value I1[15:8] Compare Value I1[15:0] is the word that is compared with the I1 input sample captured at the input interface. See Register 0x6C. 6E 7:0 Compare Value Q1[7:0] C6 6F 7:0 Compare Value Q1[15:8] Compare Value Q1[15:0] is the word that is compared with the Q1 input sample captured at the input interface. See Register 0x6E. 70 7:0 7:0 Errors Detected I_BITS[15:0] indicates which bits were received in error. See Register 0x70. 0 71 72 7:0 7:0 Errors Detected Q_BITS[15:0] indicates which bits were received in error. See Register 0x72. 0 73 Errors Detected I_BITS[7:0] Errors Detected I_BITS[15:8] Errors Detected Q_BITS[7:0] Errors Detected Q_BITS[15:8] Rev. 0 | Page 30 of 56 1A AA 0 0 AD9122 AD9122 LVDS INPUT DATA PORTS The AD9122 AD9122 has one LVDS data port that receives data for both the I and Q transmit paths. The device can accept data in word, byte, and nibble formats. In word, byte, and nibble modes, the data is sent over 16-bit, 8-bit, and 4-bit LVDS data busses, respectively. The pin assignment of the bus in each mode is shown in Table 12. with DCI being high, and the least significant byte of the data should correspond with DCI being low. The FRAME signal indicates to which DAC the data is sent. When FRAME is high, data is sent to the I DAC, and when FRAME is low, data is sent to the Q DAC. The complete timing diagram is shown in Figure 42. Table 12. Data Bit Pair Assignments for Data Input Modes NIBBLE INTERFACE MODE Mode Word Byte1 Nibble1 In nibble mode, the DCI signal is a reference bit used for generating the data sampling clock and should be time aligned with the data. The FRAME signal indicates to which DAC the data is sent. When FRAME is high, data is sent to the I DAC. When FRAME is low, data is sent to the Q DAC. All four nibbles must be written to the device for proper operation. For 12-bit resolution devices, the data in the fourth nibble acts as a place holder for the data framing structure. The complete timing diagram is shown in Figure 43. 1 MSB, ., LSB D15, D14, ., D0 D14, D12, D10, D8, D7, D5, D3, D1 D10, D8, D7, D5 In byte and nibble modes, the unused pins can be left floating. The data is accompanied by a reference bit (DCI) that is used to generate a double data rate (DDR) clock. In byte and nibble modes, a FRAME signal is required for controlling to which DAC the data is sent. All of the interface signals are time aligned. While there is a maximum skew requirement on the bus, there are no setup and hold times to be met. FIFO OPERATION The AD9122 AD9122 contains a 2-channel, 16-bit wide, eight-word deep FIFO designed to relax the timing relationship between the data arriving at the DAC input ports and the internal DAC data rate clock. The FIFO acts as a buffer that absorbs timing variations between the data source and DAC, such as the clock-to-data variation of an FPGA or ASIC, which significantly increases the timing budget of the interface. WORD INTERFACE MODE In word mode, the DCI signal is a reference bit used for generating the data sampling clock. Time align the DCI signal with the data. The I DAC data should correspond with DCI being high and the Q DAC data with DCI being low, as illustrated in Figure 41. Figure 44 shows the block diagram of the datapath through the FIFO. The data is latched into the device, is formatted, and is then written into the FIFO register determined by the FIFO write pointer. The value of the write pointer is incremented every time a new word is loaded into the FIFO. Meanwhile, data is read from the FIFO register determined by the read pointer and fed into the digital datapath. The value of the read pointer is updated every time data is read into the datapath from the FIFO. This happens at the data rate, that is, the DACCLK rate divided by the interpolation ratio. DATA[15:0] Q0 I1 Q1 I2 Q2 I3 Q3 08281-015 DCI Figure 41. Timing Diagram for Word Mode BYTE INTERFACE MODE In byte mode, the DCI signal is a reference bit used for generating the data sampling clock and should be time aligned with the data. The most significant byte of the data should correspond DCI I1MSB I1LSB Q1MSB Q1LSB I2MSB I2LSB Q2MSB Q2LSB 08281-016 DATA[15:0] QLSB FRAME Figure 42. Timing Diagram for Byte Mode DCI I1N3 I1N2 I1N1 I1N0 Q1N3 Q1N2 Q1N1 Q1N0 Q2N3 08281-017 DATA[15:0] Q0N0 FRAME Figure 43. Timing Diagram for Nibble Mode Rev. 0 | Page 31 of 56 AD9122 AD9122 32 BITS REG 0 REG 1 REG 2 INPUT LATCH DATA DATA ASSEMBLER 16 REG 3 DATA PATHS 16 DACS REG 4 REG 5 REG 6 DCI 32 BITS READ POINTER ÷ INT DACCLK 08281-018 REG 7 WRITE POINTER Figure 44. Block Diagram of FIFO Valid data is transmitted through the FIFO as long as the FIFO does not overflow or become empty. Note that an overflow or empty condition of the FIFO is the same as the write pointer and read pointer being equal. When both pointers are equal, an attempt is made to read and write a single FIFO register simultaneously. This simultaneous register access leads to unreliable data transfer through the FIFO and must be avoided. Nominally, data is written to the FIFO at the same rate that data is read from the FIFO, which keeps the data level in the FIFO constant. If data is written to the FIFO faster than data is read, the data level in the FIFO increases. If the data is written to the device slower than data is read, the data level in the FIFO decreases. For optimum timing margin, the FIFO level should be maintained near half full, which is the same as maintaining a difference of four between the write pointer and read pointer values. Resetting the FIFO Data Level To maximize the timing margin between the DCI input and the internal DAC data rate clock, the FIFO data level should be initialized prior to beginning data transmission. The value of the FIFO data level can be initialized in three ways; by resetting the device, by strobing the FRAME input, and via a write sequence to the serial port. The two preferred methods are by using of the FRAME signal and by issuing a command. As discussed in the Byte Interface Mode and Nibble Interface Mode sections, the FRAME input is used as a data select signal that indicates to which DACs the input data is written. The second function of the FRAME input is initializing the FIFO data level value. This is done by asserting the FRAME signal high for at least the time interval needed to load complete data to the I and Q DACs. This corresponds to one DCI period in word mode, two DCI periods in byte mode, and four DCI periods in nibble mode. When FRAME is asserted in this manner, the write pointer is set to 4 (by default or to the FIFO start level) the next time the read pointer becomes 0 (see Figure 45). 0 1 2 3 5 6 7 0 1 2 5 6 7 The FIFO initialization and status can be read from Register 0x18. This register provides information on the FIFO initialization method, and whether the initialization was successful. The MSB of Register 0x18 is a FIFO warning flag that can optionally trigger a device IRQ. This flag is an indication that the FIFO is close to emptying (FIFO level is 1) or overflowing (FIFO level is 7). This is an indication that data may soon be corrupted, and action should be taken. The FIFO data level can be read from Register 0x19 at any time. The serial port reported FIFO data level is denoted as a 7-bit thermometer code of the write counter state relative to the absolute read counter being at 0. The optimum FIFO data level of 4 is therefore reported as a value of 00001111 in the status register. It should be noted that, depending on the timing relationship between DCI and the main DACCLK, the FIFO level value can be off by ±1 count. Therefore, it is important to keep the difference between the read and write pointers to at least 2. 3 4 Monitoring the FIFO Status FIFO WRITE RESETS FRAME WRITE POINTER 4 The recommended procedure for a serial port FIFO data level initialization is as follows: · Request FIFO level reset by setting Register 0x18, Bit 1 to 1. · Verify the part acknowledges the request by ensuring Register 0x18, Bit 2 is 1. · Remove the request by setting Register 0x18, Bit 1 to 0. · Verify the part drops the acknowledge signal by ensuring Register 0x18, Bit 2 is 0. 3 4 5 6 7 0 1 2 08281-019 READ POINTER To initialize the FIFO data level through the serial port, Bit 1 of Register 0x18 should be toggled from 0 to 1 and back. When the write to the register is complete, the FIFO data level is initialized. This method operates similar to the method previously described. When the initialization is triggered, the next time the read pointer becomes 0, the write pointer is set to the value of the FIFO start level (Register 0x17, Bits[2:0]) variable upon initialization. By default, this is 4 but can be programmed to a value of 0 to 7. Figure 45. Timing of the FRAME Input vs. Write Pointer Value Rev. 0 | Page 32 of 56 AD9122 AD9122 INTERFACE TIMING The timing diagram for the digital interface port is shown in Figure 46. The sampling point of the data bus occurs about 350 ps after each edge of the DCI signal and has an uncertainty of ±300 ps, as illustrated by the sampling interval shown in Figure 46. The DATA and FRAME signals must be valid throughout this sampling interval. The DATA and FRAME signals may change at any time between sampling intervals. The setup (tS) and hold (tH) times with respect to the edges are shown in Figure 46. The minimum setup and hold times are shown in Table 13. tDATA In data rate mode, a second timing constraint between DCI and DACCLK must be met in addition to the DCI-to-DATA timing shown in Table 14. In data rate mode, only one FIFO slot is being used. The DCI to DACCLK timing restriction is required to prevent data being written to and read from the FIFO slot at the same time. The required timing between DCI and DACCLK is shown in Figure 47. tDATA DACCLK/ REFCLK tDATA SAMPLING INTERVAL DCI DCI SAMPLING INTERVAL SAMPLING INTERVAL tSDCI DATA 08281-147 tHDCI Figure 47. Timing Diagram for Input Data Port (Data Rate Mode) Table 14. Data Port Setup and Hold Times tS tH 08281-146 tS tH Figure 46. Timing Diagram for Input Data Ports Parameter tSDCI (MIN) tHDCI (MIN) Table 13. Data Port Setup and Hold Times Parameter tS (MIN) tH (MIN) Time (ps) -50 650 The data interface timing can be verified by using the sample error detection (SED) circuitry. See the Interface Timing Validation section for details. Rev. 0 | Page 33 of 56 Time (ps) -120 820 AD9122 AD9122 DIGITAL DATAPATH The block diagram in Figure 48 shows the functionality of the digital datapath. The digital processing includes a premodulation block, three half-band interpolation filters, a quadrature modulator with a fine resolution NCO, phase and offset adjustment blocks, and an inverse sinc filter. HB2 HB3 PHASE AND OFFSET ADJUST MODE 0 SINC­1 Figure 48. Block Diagram of Digital Datapath MODE 3 ­20 ­40 (dB) The digital datapath accepts I and Q data streams and processes them as a quadrature data stream. The signal processing blocks can be used when the input data stream is represented as complex data. ­60 The datapath can be used to process an input data stream representing two independent real data streams as well, but the functionality is somewhat restricted. The premodulation block can be used. As well as, any of the nonshifted interpolation filter modes. See the Premodulation section for more details. ­80 ­100 0 0.2 PREMODULATION 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 (× fIN1) The half-band interpolation filters have selectable pass bands that allow the center frequencies to be moved in increments of ½ of their input data rate. The premodulation block provides a digital upconversion of the incoming waveform by ½ of the incoming data rate, fDATA. This can be used to frequency shift baseband input data to the center of the interpolation filters pass band. INTERPOLATION FILTERS The transmit path contains three interpolation filters. Each of the three interpolation filters provides a 2× increase in output data rate. The half-band (HB) filters can be individually bypassed or cascaded to provide 1×, 2×, 4×, or 8× interpolation ratios. Each of the half-band filter stages offers a different combination of bandwidths and operating modes. The bandwidth of the three half-band filters with respect to the data rate at the filter input is as follows: · · · MODE 2 MODE 1 0 2.0 08281-021 HB1 HB1 has four modes of operation, as shown in Figure 49. The shape of the filter response is identical in each of the four modes. The four modes are distinguished by two factors, the filter center frequency and whether or not the input signal is modulated by the filter. 08281-020 PREMOD Half-Band Filter 1 (HB1) Figure 49. HB1 Filter Modes As is shown in Figure 49, the center frequency in each mode is offset by ½ of the input data rate (fIN1) of the filter. Mode 0 and Mode 1 do not modulate the input signal. Mode 2 and Mode 3 modulate the input signal by fIN1. When operating in Mode 0 and Mode 2, the I and Q paths operate independently and no mixing of the data between channels occurs. When operating in Mode 1 and Mode 3, mixing of the data between the I and Q paths occurs; therefore, the data input into the filter is assumed complex. Table 15 summarizes the HB1 modes. Table 15. HB1 Filter Mode Summary Mode 0 1 2 3 Bandwidth of HB1 = 0.8 × fIN1 Bandwidth of HB2 = 0.5 × fIN2 Bandwidth of HB3 = 0.4 × fIN3 The usable bandwidth is defined as the frequency over which the filters have a pass-band ripple of less than ±0.001 dB and an image rejection of greater than +85 dB. As is discussed in the Half-Band Filter 1 (HB1) section, the image rejection usually sets the usable bandwidth of the filter, not the pass-band flatness. The half-band filters operate in several modes, providing programmable pass-band center frequencies as well as signal modulation. The HB1 filter has four modes of operation and the HB2 and HB3 filters each have eight modes of operation. Rev. 0 | Page 34 of 56 fCENTER DC fIN/2 fIN 3fIN/2 fMOD None None fIN fIN Input Data Real or complex Complex Real or complex Complex AD9122 AD9122 Figure 50 shows the pass-band filter response for HB1. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 16 shows the pass-band flatness and stop-band rejection the HB1 filter supports at different bandwidths. Half-Band Filter 2 (HB2) HB2 has eight modes of operation, as shown in Figure 51 and Figure 52. The shape of the filter response is identical in each of the eight modes. The eight modes are distinguished by two factors, the filter center frequency and whether the input signal is modulated by the filter. 0.02 MODE 0 MODE 4 MODE 2 MODE 6 0 0 ­20 (dB) ­0.04 ­40 ­60 ­0.06 ­80 ­0.08 ­0.10 (× fIN1) 0 0.2 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.8 2.0 Figure 51. HB2, Even Filter Modes MODE 1 Table 16. HB1 Pass-Band and Stop-Band Performance by Bandwidth MODE 3 MODE 5 MODE 7 0 Stop-Band Rejection (dB) 85 80 70 60 50 40 ­20 (dB) Pass-Band Flatness (dB) 0.001 0.0012 0.0033 0.0076 0.0271 0.1096 0.6 (× fIN2) Figure 50. Pass-Band Detail of HB1 Bandwidth (% of fIN1) 80 80.4 81.2 82.0 83.6 85.6 0.4 08281-023 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 08281-022 ­100 0 08281-024 (dB) ­0.02 ­40 ­60 ­80 ­100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 (× fIN2) 1.6 Figure 52. HB2, Odd Filter Modes As shown in Figure 51 and Figure 52, the center frequency in each mode is offset by ¼ of the input data rate (fIN2) of the filter. Mode 0 through Mode 3 do not modulate the input signal. Mode 4 through Mode 7 modulate the input signal by fIN2. When operating in Mode 0 and Mode 4, the I and Q paths operate independently and no mixing of the data between channels occurs. When operating in the other six modes, mixing of the data between the I and Q paths occurs; therefore, the data input to the filter is assumed complex. Rev. 0 | Page 35 of 56 AD9122 AD9122 Half-Band Filter 3 (HB3) Table 17 summarizes the HB2 and HB3 modes. HB3 has eight modes of operation that function the same as HB2. The primary difference between HB2 and HB3 are the filter bandwidths. Table 17. HB2 and HB3 Filter Mode Summary fCENTER DC fIN/8 fIN/4 3fIN/8 fIN/2 5fIN/8 3fIN/4 7fIN/8 fMOD None None None None fIN fIN fIN fIN Input Data Real or complex Complex Complex Complex Real or complex Complex Complex Complex 0.02 0 ­0.02 (dB) Mode 0 1 2 3 4 5 6 7 ­0.04 ­0.06 Figure 53 shows the pass-band filter response for HB2. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 18 shows the pass-band flatness and stop-band rejection the HB2 filter supports at different bandwidths. ­0.08 0 (× fIN3) Figure 54. Pass-Band Detail of HB3 0.02 Figure 54 shows the pass-band filter response for HB3. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 19 shows the pass-band flatness and stop-band rejection the HB3 filter supports at different bandwidths. 0 ­0.02 (dB) 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 08281-026 ­0.10 ­0.04 Table 19. HB3 Pass-Band and Stop-Band Performance by Bandwidth ­0.06 ­0.08 0 0.04 0.08 0.12 0.16 0.20 0.24 (× fIN2) 0.28 0.32 08281-025 ­0.10 Figure 53. Pass-Band Detail of HB2 Table 18. HB2 Pass-Band and Stop-Band Performance by Bandwidth Bandwidth (% of fIN2) 50 50.8 52.8 56.0 60 64.8 Pass-Band Flatness (dB) 0.001 0.0012 0.0028 0.0089 0.0287 0.1877 Bandwidth (% of fIN3) 40 40.8 42.4 45.6 49.8 55.6 Stop-Band Rejection (dB) 85 80 70 60 50 40 Rev. 0 | Page 36 of 56 Pass-Band Flatness (dB) 0.001 0.0014 0.002 0.0093 0.03 0.1 Stop-Band Rejection (dB) 85 80 70 60 50 40 AD9122 AD9122 I DATA INTERPOLATION COSINE FTW[31:0] NCO NCO PHASE OFFSET [15:0] OUT_I SINE OUT_Q ­ + ­1 Q DATA 0 1 08281-027 SPECTRAL INVERSION INTERPOLATION Figure 55. Digital Quadrature Modulator Block Diagram NCO MODULATION The digital quadrature modulator makes use of a numerically controlled oscillator, a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. A block diagram of the digital modulator is shown in Figure 55. The fine modulation provided by the digital modulator, in conjunction with the coarse modulation of the interpolation filters and premodulation block, allows the signal to be placed anywhere in the output spectrum with very fine frequency resolution. The quadrature modulator is used to mix the carrier signal generated by the NCO with the I and Q signal. The NCO produces a quadrature carrier signal to translate the input signal to a new center frequency. A complex carrier signal is a pair of sinusoidal waveforms of the same frequency, offset 90° from each other. The frequency of the complex carrier signal is set via FTW[31:0] in Register 0x30 through Register 0x33. The NCO operating frequency, fNCO, is at either fDATA (HB1 bypassed) or twice fDATA (HB1 enabled). The frequency of the complex carrier signal can be set from dc up to fNCO. The frequency tuning word (FTW) is calculated as Determining Datapath Signal Bandwidth The available signal bandwidth of the datapath is dependent on the center frequency of the output signal in relation to the center frequency of the interpolation filters used. Signal center frequencies offset from the center frequencies of the half-band filters lower the available signal bandwidth. When correctly configured, the available complex signal bandwidth for 2× interpolation is always 80% of the input data rate. The available signal bandwidth for 4× interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in Figure 56. Note that in 4× interpolation mode, fDAC = 4 × fDATA; therefore, the data shown in Figure 56 repeats four times from dc to fDAC. HB1 AND HB2 0.8 f CARRIER × 2 32 f NCO The generated quadrature carrier signal is mixed with the I and Q data. The quadrature products are then summed into the I and Q data paths, as shown in Figure 55. BANDWIDTH/ fDATA FTW = Given these four parameters, the first step in configuring the datapath is to verify that the device supports the bandwidth requirements. The modes of the interpolation filters are then chosen. Finally, any additional frequency offset requirements are determined and applied with premodulation and NCO modulation. 0.5 HB2 AND HB3 0.3 The frequency tuning word registers are not updated immediately upon writing as other configuration registers do. After loading the FTW registers with the desired values, Bit 0 of Register 0x36 must transition from 0 to 1 for the new FTW to take effect. DATAPATH CONFIGURATION Configuring the AD9122 AD9122 datapath starts with the application requirements of the input data rate, the interpolation ratio, the output signal bandwidth, and the output signal center frequency. 0.2 0.4 0.6 fOUT/fDATA 0.8 1.0 08281-028 Updating the Frequency Tuning Word Figure 56. Signal Bandwidth vs. Center Frequency of the Output Signal, 4× Interpolation Configuring 4× interpolation using the HB2 and HB3 filters can lower the power consumption of the device at the expense of bandwidth. The lower curve in Figure 56 shows that the supported bandwidth in this mode varies from 30% to 50% of fDATA. Rev. 0 | Page 37 of 56 AD9122 AD9122 The available signal bandwidth for 8× interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in Figure 57. Note that in 8× interpolation mode, fDAC = 8 × fDATA; therefore, the data shown in Figure 57 repeats eight times from dc to fDAC. HB1, HB2, AND HB3 0.6 Table 20 shows the recommended interpolation filter settings for a variety of filter interpolation factors, filter center frequencies, and signal modulation. The interpolation modes were chosen based on the final center frequency of the signal and by determining the frequency shift of the signal required. When these are known, and put in terms of the input data rate (fDATA), the filter configuration that comes closest to matching is chosen from Table 20. 0.5 0.1 0.25 0.4 0.50 0.6 0.75 fOUT/fDATA 0.9 1.00 08281-029 BANDWIDTH/ fDATA 0.8 DETERMINING INTERPOLATION FILTER MODES Figure 57. Signal Bandwidth vs. Center Frequency of the Output Signal, 8× Interpolation Table 20. Recommended Interpolation Filter Modes (Register 0x1C through Register 0x1E) Interpolation Factor 8 8 82 8 8 8 8 8 8 8 8 8 8 8 8 8 4 43 4 4 4 4 4 4 2 2 2 2 HB1[1:0] 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) Filter Modes HB2[5:0] 000000 001001 010010 011011 100100 101101 110110 111111 000000 001001 010010 011011 100100 101101 110110 111111 000000 001001 010010 011011 100100 101101 110110 111111 Bypass Bypass Bypass Bypass HB3[5:0] 000000 000000 001001 001001 010010 010010 011011 011011 100100 100100 101101 101101 110110 110110 111111 111111 Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass 1 fSIGNAL Modulation DC DC1 fDATA fDATA1 2fDATA 2fDATA1 3fDATA 3 fDATA1 4fDATA 4fDATA1 5fDATA 5fDATA1 6fDATA 6fDATA1 7fDATA 7fDATA1 DC DC1 fDATA fDATA1 2fDATA 2fDATA1 3fDATA 3fDATA1 DC DC1 fDATA fDATA1 fCENTER Shift 0 fDATA/2 fDATA 3fDATA/2 2fDATA 5fDATA/2 3fDATA 7fDATA/2 4fDATA 9fDATA/2 5fDATA 11fDATA/2 6fDATA 13fDATA/2 7fDATA 15fDATA/2 0 fDATA/2 fDATA 3fDATA/2 2fDATA 5fDATA/2 3fDATA 7fDATA/2 0 fDATA/2 fDATA 3fDATA/2 When HB1 Mode 1 or Mode 3 is used, enabling premodulation provides an addition frequency translation of the input signal by fDATA/2, which centers a baseband input signal in the filter pass band. This configuration was used in the 8× interpolation without NCO example. Also, see the 8× Interpolation Without NCO section. 3 This configuration was used in the 4× interpolation with NCO example. Also, see the 4× Interpolation With NCO section. 2 Rev. 0 | Page 38 of 56 AD9122 AD9122 DATAPATH CONFIGURATION EXAMPLE 4× Interpolation With NCO 8× Interpolation Without NCO Given the following: Given the following: fDATA = 250 MSPS 4× interpolation fBW = 140 MHz fCENTER = 175 MHz fDATA = 100 MSPS 8× interpolation fBW = 75 MHz The desired 140 MHz of bandwidth is 56% of fDATA. As shown in Figure 56, the value at 0.7 × fDATA is 0.6. This is calculated as 0.8 - 2(0.7 - 0.6) = 0.6. This verifies that the AD9122 AD9122 supports a bandwidth of 60% of fDATA, which exceeds the required 56%. fCENTER = 100 MHz The desired 75 MHz of bandwidth is 75% of fDATA. In this case, the ratio of fOUT/fDATA = 100/100 = 1.0. From Figure 57, the bandwidth supported at fDATA is 0.8, which verifies that the AD9122 AD9122 supports the bandwidth required in this configuration. The signal center frequency is 0.7 × fDATA, and assuming the input signal is at baseband, the frequency shift required is also 0.7 × fDATA. Choosing the second row in the IF column in the 4× interpolation section in Table 20 selects the filter modes that give a center frequency of fDATA/2 and no frequency translation. The selected modes for the three half-band filters are HB1, Mode 1; HB2, Mode 1; and HB3, bypassed. The signal center frequency is fDATA, and assuming the input signal is at baseband, the frequency shift required is also fDATA. Choosing the third row (highlighted by the superscripted number two) of the IF column from Table 20 selects filter modes that give a center frequency of fDATA and a frequency translation of fDATA. The selected modes for the three half-band filters are: HB1, Mode 2; HB2, Mode 2; and HB3, Mode 1. Figure 58 shows how the signal propagates through the interpolation filters. Because Mode 1 of HB1 was selected, the premodulation block should be enabled. This provides fDATA/2 modulation, which centers the baseband input data at the center frequency of HB1. The digital modulator can be used to provide the final frequency translation of 0.2 × fDATA to place the output signal at 0.7 × fDATA, as desired. Because 2 × fIN1 = fIN2 and 2 × fIN2 = fIN3, the signal appears frequency scaled by ½ into each consecutive stage. The output signal band spans 0.15 to 0.35 of fIN3 (400 MHz). Therefore, the output frequency supported is 60 MHz to 140 MHz, which covers the 75 MHz bandwidth centered at 100 MHz, as desired. The formula for calculating the FTW of the NCO is: f CARRIER FTW = f NCO × 2 32 where: fCARRIER = 0.2 × fDATA. fNCO = 2 × fDATA. Therefore, FTW = 232/10. 0 2 1 0 3 HB1 0.4 0 3 2 0.25 ­0.5 0 3 0.2 0.3 0 1.75 1.5 4 5 2.0 × fIN2 7 6 0.7 0.5 0.15 1.25 1.0 2 ­0.2 ­0.5 7 6 0.7 1 HB3 2.0 × fIN1 1.5 5 4 0.75 0.5 0.3 0 1.0 1 0 HB2 0.6 0.5 1.0 0.35 1.5 2.0 × fIN3 08281-030 0.1 ­0.5 Figure 58. Signal Propagation for 8× Interpolation (fDATA Modulation) Rev. 0 | Page 39 of 56 AD9122 AD9122 DATA RATES vs. INTERPOLATION MODES Table 22 summarizes the maximum bus speed (fBUS), supported input data rates, and signal bandwidths with the various combinations of bus width modes and interpolation rates. The maximum bus speed in any mode is 1200 MHz. The maximum DAC update rate (fDAC) in any mode is 1200 MHz. The real signal bandwidth supported is a fraction of the input data rate, which depends on the interpolation filters (HB1, HB2, or HB3) selected. The complex signal bandwidth supported is twice the real signal bandwidth. In general, 2× interpolation is best supported by enabling HB1, and 4× interpolation is best supported enabling HB1 and HB2. In some cases, power dissipation can be lowered by avoiding HB1. If the bandwidth required is low enough, 2× interpolation can be supported by using HB2, and 4× interpolation can be supported by using HB2 and HB3. COARSE MODULATION MIXING SEQUENCES The coarse digital quadrature modulation occurs within the interpolation filters. The modulation shifts the frequency spectrum of the incoming data by the frequency offset selected. The frequency offsets available are multiples of the input data rate. The modulation is equivalent to multiplying the quadrature input signal by a complex carrier signal, C(t), of the form In practice, this modulation results in mixing functions as shown in Table 21. Table 21. Modulation Mixing Sequences Modulation fS/2 fS/4 3 fS/4 fS/8 Note that r = Mixing Sequence I = I, -I, I, -I, . Q = Q, -Q, Q, -Q, . I = I, Q, -I, -Q, . Q = Q, -I, -Q, I, . I = I, -Q, -I, Q, . Q = Q, I, -Q, -I, . I = I, r(I + Q), Q, r(-I + Q), -I, -r(I + Q), -Q, r(I - Q), . Q = Q, r(Q - I), -I, -r(Q + I), -Q, r(-Q + I),I, r(Q + I), .