AD9878 AD8321/AD8323 AD8322/AD8327 AD8322/AD8327/AD8328 10-BIT REFT10 REFB10 - Datasheet Archive

 

for Broadband Applications AD9878 FEATURES Low cost 3.3 V CMOS MxFETM for broadband applications DOCSIS, EURO-DOCSIS, DVB, DAVIC

 

Mixed-Signal Front End for Broadband Applications AD9878 AD9878 FEATURES Low cost 3.3 V CMOS MxFETM for broadband applications DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant 232 MHz quadrature digital upconverter 12-bit direct IF DAC (TxDAC+TM) Up to 65 MHz carrier frequency DDS Programmable sampling clock rates Analog Tx output level adjust Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input 10-bit, 29 MSPS sampling ADC 8-bit sigma-delta auxiliary DAC Direct interface to AD8321/AD8323 AD8321/AD8323 or AD8322/AD8327 AD8322/AD8327 PGA cable driver FUNCTIONAL BLOCK DIAGRAM I Tx Tx D A TA Q 12 DAC Tx DDS - SPO R T 4 - _ OU T 3 C ON TR O L R EGISTER S C A IN T MC L K PLL IF1 0 [4 :0 ] MU X 10 12 OSC IN Rx10 ADC ADC Rx12B MU X IF1 2 [1 1 :0 ] FL A G[2 :1 ] VID EO ­ C LA MP L EVEL MU X 12 APPLICATIONS SIN C ­ 1 16 MU X Rx12A ADC Cable set-top boxes Cable and wireless modems 03277- 0- 001 Figure 1. Functional Block Diagram GENERAL DESCRIPTION The AD9878 AD9878 is a single-supply cable modem/set-top box mixed-signal front end. The device contains a transmit path interpolation filter, a complete quadrature digital upconverter, and transmit DAC. The receive path contains dual 12-bit ADCs and a 10-bit ADC. All internally required clocks and an output system clock are generated by the PLL from a single crystal oscillator or clock input. The transmit path interpolation filter provides an upsampling factor of 16× with an output signal bandwidth up to 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when reduced output levels are required. The 12-bit ADCs provide excellent undersampling performance, allowing this device to deliver better than 10 ENOBs with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at rates up to 29 MHz, allowing them to process wideband signals. The AD9878 AD9878 includes a programmable sigma-delta DAC, which can be used to control an external component such as a variable gain amplifier (VGA) or a voltage controlled tuner. The AD9878 AD9878 also integrates a CA port that enables a host processor to interface with the AD8321/AD8323 AD8321/AD8323 or AD8322/AD8327/AD8328 AD8322/AD8327/AD8328 programmable gain amplifier (PGA) cable drivers via the MxFE serial port (SPORT). The AD9878 AD9878 is available in a 100-lead LQFP package. The AD9878 AD9878 is specified over the extended industrial (­40°C to +85°C) temperature range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD9878 AD9878 TABLE OF CONTENTS SPECIFICATIONS . 3 INTERPOLATION FILTER . 18 ABSOLUTE MAXIMUM RATINGS. 6 DIGITAL UPCONVERTER . 19 DEFINITIONS OF SPECIFICATIONS. 7 CLOCK AND OSCILLATOR CIRCUITRY. 21 TYPICAL PERFORMANCE CHARACTERISTICS . 8 PROGRAMMABLE CLOCK OUTPUT REFCLK. 22 REGISTER BIT DEFINITIONS . 11 RESET AND TRANSMIT POWER-DOWN . 23 SERIAL INTERFACE FOR REGISTER CONTROL . 15 RECEIVE PATH (Rx) . 24 GENERAL OPERATION OF THE SERIAL INTERFACE. 15 PCB DESIGN CONSIDERATIONS . 25 INSTRUCTION BYTE . 15 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIOINS . 27 SERIAL INTERFACE PORT PIN DESCRIPTION . 15 MSB/LSB TRANSFERS . 16 NOTES ON SERIAL PORT OPERATION . 16 OUTLINE DIMENSIONS . 34 ORDERING GUIDE. 34 THEORY OF OPERATION. 17 TRANSMIT PATH. 18 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 36 AD9878 AD9878 SPECIFICATIONS Table 1. ELECTRICAL CHARACTERISTICS (VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8), ADC Clock Derived from OSCIN, RSET = 4.02 k, Max. Fine Gain, 75 DAC Load.) PARAMETER OSCIN and XTAL CHARACTERISTICS Frequency Range Duty Cycle Input Impedance MCLK Cycle to Cycle Jitter (fMCLK derived from PLL) Tx DAC CHARACTERISTICS Maximum Sample Rate Resolution Full-Scale Output Current Gain Error (Using Internal Reference) Offset Error Reference Voltage (REFIO Level) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Output Capacitance Phase Noise @ 1 kHz Offset, 42 MHz Carrier Output Voltage Compliance Range Wideband SFDR 5 MHz Analog Out, IOUT = 10 mA 65 MHz Analog Out, IOUT = 10 mA Narrow-Band SFDR (±1 MHz Window) 5 MHz Analog Out, IOUT = 10 mA 65 MHz Analog Out, IOUT = 10 mA Tx MODULATOR CHARACTERISTICS I/Q Offset Pass-Band Amplitude Ripple (f < fIQCLK/8) Pass-Band Amplitude Ripple (f < fIQCLK/4) Stop-Band Response (f > fIQCLK × 3/4) Tx GAIN CONTROL Gain Step Size Gain Step Error Settling Time, 1% (Full-Scale Step) 10-BIT 10-BIT ADC CHARACTERISTICS Resolution Maximum Conversion Rate Pipeline Delay Analog Input Input Voltage Range Differential Input Impedance Full Power Bandwidth Dynamic Performance (f = 5 MHz) Signal-to-Noise and Distortion (SINAD) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Reference Voltage Error, REFT10 REFT10­REFB10 REFB10 (1.0 V) Temp Test Level Full 25ºC 25ºC 25ºC II II III III 3 35 Full N/A Full Full 25°C 25°C 25°C 25°C 25°C 25°C Full II N/A II II III III III III III III II 232 Full Full I I 62.4 50.3 68 53.5 dB dB Full Full I I 71 61 74 64 dB dB Full Full Full Full II II II II 50 55 25°C 25°C 25°C III III III Min 4 ­2.5 Typ 50 100||3 6 12 10 ­1 ±1.0 1.23 ±2.5 ±8 5 ­110 Max Unit 29 65 MHz % M||pF ps rms 20 +2.5 +1.5 ­0.5 ±0.1 ±0.5 ­63 MHz Bits mA % FS % FS V LSB LSB pF dBc/Hz V dB dB dB dB 0.5 85 >85 dB dB N/A N/A Full N/A N/A II 5 2.8 Full Full Full Full II II II II 3 3 0 1.0 MHz ns ns ns Full Full II II TOSC/4 ­ 2.0 ­1.0 TOSC/4 + 3.0 +1.0 ns ns Full Full Full Full Full Full Full II II II II II II II 15 MHz ns ns µs ns ns ns 25°C 25°C 25°C 25°C 25°C II II II II III VDRVDD ­ 0.7 25°C 25°C II II VDRVDD ­ 0.6 25°C 25°C 25°C II III III 25°C 25°C 25°C 25°C 25°C 25°C 25°C Min Typ Max 200 4 66 30 30 1 25 0 30 0.4 12 12 3 Unit TMCLK cycles tMCLK cycles ns V V µA µA pF 0.4 V V 184 105 79 204 115 89 mA mA mA II III III III 46 46 124 131 53 52 mA mA mA mA III III III