AD8042 AD8041 AD8044 AD8042A AD8042AN AD8042AR AD8042AR-REEL AD8042S AD9220 - Datasheet Archive

 

Dual 160 MHz Rail-to-Rail Amplifier AD8042 FEATURES Single AD8041 and Quad AD8044 also Available Fully Specified at +3 V, +5 V,

 

a Dual 160 MHz Rail-to-Rail Amplifier AD8042 AD8042 FEATURES Single AD8041 AD8041 and Quad AD8044 AD8044 also Available Fully Specified at +3 V, +5 V, and 5 V Supplies Output Swings to Within 30 mV of Either Rail Input Voltage Range Extends 200 mV Below Ground No Phase Reversal with Inputs 0.5 V Beyond Supplies Low Power of 5.2 mA per Amplifier High Speed and Fast Settling on +5 V: 160 MHz ­3 dB Bandwidth (G = +1) 200 V/s Slew Rate 39 ns Settling Time to 0.1% Good Video Specifications (RL = 150 , G = +2) Gain Flatness of 0.1 dB to 14 MHz 0.02% Differential Gain Error 0.04 Differential Phase Error Low Distortion ­64 dBc Worst Harmonic @ 10 MHz Drives 50 mA 0.5 V from Supply Rails APPLICATIONS Video Switchers Distribution Amplifiers A/D Driver Professional Cameras CCD Imaging Systems Ultrasound Equipment (Multichannel) CONNECTION DIAGRAM 8-Pin Plastic Mini-DIP and SOIC OUT1 1 8 +VS ­IN1 2 7 OUT2 +IN1 3 6 ­IN2 ­VS 4 5 +IN2 AD8042 AD8042 The output voltage swing extends to within 30 mV of each rail, providing the maximum output dynamic range. Additionally, it features gain flatness of 0.1 dB to 14 MHz while offering differential gain and phase error of 0.04% and 0.06° on a single +5 V supply. This makes the AD8042 AD8042 useful for professional video electronics such as cameras, video switchers or any high speed portable equipment. The AD8042 AD8042's low distortion and fast settling make it ideal for buffering single supply, high speed A-to-D converters. The AD8042 AD8042 offers low power supply current of 12 mA max and can run on a single +3.3 V power supply. These features are ideally suited for portable and battery powered applications where size and power are critical. PRODUCT DESCRIPTION The AD8042 AD8042 is a low power voltage feedback, high speed amplifier designed to operate on +3 V, +5 V or ± 5 V supplies. It has true single supply capability with an input voltage range extending 200 mV below the negative rail and within 1 V of the positive rail. The wide bandwidth of 160 MHz along with 200 V/µs of slew rate on a single +5 V supply make the AD8042 AD8042 useful in many general purpose, high speed applications where single supplies from +3.3 V to +12 V and dual power supplies of up to ± 6 V are needed. The AD8042 AD8042 is available in 8-pin plastic DIP and SOIC. 15 VS = +5V G = +1 CL = 5pF RL = 2k TO 2.5V 12 5V 2.5V 0V 1V 1µs 9 CLOSED­LOOP GAIN ­ dB G=1 RL = 2k TO +2.5V 6 3 0 ­3 ­6 ­9 ­12 ­15 1 Figure 1. Output Swing: Gain = ­1, VS = +5 V 10 FREQUENCY ­ MHz 100 500 Figure 2. Frequency Response REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD8042 AD8042­SPECIFICATIONS (@ T = +25C, V = +5 V, R = 2 k to 2.5 V, unless otherwise noted) A S L Parameter Conditions Min DYNAMIC PERFORMANCE ­3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 1% Settling Time to 0.1% G = +1 G = +2, RL = 150 . RF = 200 G = ­1, VO = 2 V Step VO = 2 V p-p G = ­1, VO = 2 V Step AD8042A AD8042A Typ 125 NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC, 100 IRE) Differential Phase Error (NTSC, 100 IRE) Worst Case Crosstalk fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 k f = 10 kHz f = 10 kHz G = +2, RL = 150 to 2.5 V G = +2, RL = 75 to 2.5 V G = +2, RL = 150 to 2.5 V G = +2, RL = 75 to 2.5 V f = 5 MHz, RL = 150 to 2.5 V 160 14 200 30 26 39 MHz MHz V/µs MHz ns ns dB nV/Hz fA/Hz % % Degrees Degrees dB 3 TMIN­TMAX Offset Drift Input Bias Current 12 1.2 TMIN­TMAX INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Swing: Output Voltage Swing: Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Power Supply Rejection Ratio RL = 1 k TMIN ­TMAX 90 VCM = 0 V to 3.5 V RL = 10 k to 2.5 V RL = 1 k to 2.5 V RL = 50 to 2.5 V TMIN to TMAX, VOUT = 0.5 V to 4.5 V Sourcing Sinking G = +1 68 0.10 to 4.9 0.4 to 4.4 0.2 100 90 OPERATING TEMPERATURE RANGE 72 ­40 0.06 0.12 9 12 3.2 4.8 0.5 mV mV µV/°C µA µA µA dB dB 300 1.5 ­0.2 to 4 74 k pF V dB 0.03 to 4.97 0.05 to 4.95 0.36 to 4.45 50 90 100 20 V V V mA mA mA pF 3 VS­ = 0 V to ­1 V, or VS+ = +5 V to +6 V Units ­73 15 700 0.04 0.04 0.06 0.24 ­63 130 DC PERFORMANCE Input Offset Voltage Input Offset Current Open-Loop Gain Max 5.2 80 12 6 V mA dB +85 °C Specifications subject to change without notice. ­2­ REV. 0 AD8042 AD8042 SPECIFICATIONS (@ T = +25C, V = +3 V, R = 2 k to 1.5 V, unless otherwise noted) A S L Parameter Conditions Min DYNAMIC PERFORMANCE ­3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 1% Settling Time to 0.1% G = +1 G = +2, RL = 150 , RF = 200 G = ­1, VO = 2 V Step VO = 2 V p-p G = ­1, VO = 1 V Step AD8042A AD8042A Typ 120 NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC, 100 IRE) Differential Phase Error (NTSC, 100 IRE) Worst Case Crosstalk fC = 5 MHz, VO = 2 V p-p, G = ­1, RL = 100 f = 10 kHz f = 10 kHz G = +2, RL = 150 to 1.5 V, Input VCM = 1 V RL = 75 to 1.5 V, Input VCM = 1 V G = +2, RL = 150 to 1.5 V, Input VCM = 1 V RL = 75 to 1.5 V, Input VCM = 1 V f = 5 MHz, RL = 1 k to 1.5 V 140 11 170 25 30 45 MHz MHz V/µs MHz ns ns dB nV/Hz fA/Hz % % Degrees Degrees dB 3 TMIN ­TMAX Offset Drift Input Bias Current 12 1.2 TMIN ­TMAX INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Swing: Output Voltage Swing: Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Power Supply Rejection Ratio RL = 1 k TMIN ­TMAX 90 VCM = 0 V to 1.5 V RL = 10 k to 1.5 V RL = 1 k to 1.5 V RL = 50 to 1.5 V TMIN to TMAX, VOUT = 0.5 V to 2.5 V Sourcing Sinking G = +1 OPERATING TEMPERATURE RANGE 0.1 to 2.9 0.3 to 2.6 68 0 Specifications subject to change without notice. REV. 0 66 0.2 100 90 ­3­ 9 12 3.2 4.8 0.6 mV mV µV/°C µA µA µA dB dB 300 1.5 ­0.2 to 2 74 k pF V dB 0.03 to 2.97 0.05 to 2.95 0.25 to 2.65 50 50 70 17 V V V mA mA mA pF 3 VS­ = 0 V to ­1 V, or VS+ = +3 V to +4 V Units ­56 16 500 0.10 0.10 0.12 0.27 ­68 120 DC PERFORMANCE Input Offset Voltage Input Offset Current Open-Loop Gain Max 5.0 80 12 6 V mA dB +70 °C AD8042 AD8042­SPECIFICATIONS (@ T = +25C, V = 5 V, R = 2 k to 0 V, unless otherwise noted) A S L Parameter Conditions Min DYNAMIC PERFORMANCE ­3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 1% Settling Time to 0.1% G = +1 G = +2, RL = 150 , RF = 200 G = ­1, VO = 2 V Step VO = 2 V p-p G = ­1, VO = 2 V Step AD8042A AD8042A Typ 125 NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC, 100 IRE) Differential Phase Error (NTSC, 100 IRE) Worst Case Crosstalk fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 k f = 10 kHz f = 10 kHz G = +2, RL = 150 G = +2, RL = 75 G = +2, RL = 150 G = +2, RL = 75 f = 5 MHz, RL = 150 170 18 225 35 22 32 MHz MHz V/µs MHz ns ns dB nV/Hz fA/Hz % % Degrees Degrees dB 3 TMIN ­TMAX Offset Drift Input Bias Current 12 1.2 TMIN ­TMAX INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Swing: Output Voltage Swing: Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Power Supply Rejection Ratio RL = 1 k TMIN ­TMAX 90 VCM = ­5 V to 3.5 V RL = 10 k RL = 1 k RL = 50 TMIN to TMAX, VOUT = ­4.5 V to 4.5 V Sourcing Sinking G = +1 66 ­4.8 to +4.8 ­4 to +3.2 0.2 94 86 68 ­40 OPERATING TEMPERATURE RANGE 0.05 0.10 9.8 14 3.2 4.8 0.6 mV mV µV/°C µA µA µA dB dB 300 1.5 ­5.2 to 4 74 k pF V dB ­4.97 to +4.97 ­4.9 to +4.9 ­4.2 to +3.5 50 100 100 25 V V V mA mA mA pF 12 7 V mA dB +85 °C 3 VS­ = ­5 V to ­6 V, or VS+ = +5 V to +6 V Units ­78 15 700 0.02 0.02 0.04 0.12 ­63 145 DC PERFORMANCE Input Offset Voltage Input Offset Current Open-Loop Gain Max 6 80 Specifications subject to change without notice. ­4­ REV. 0 AD8042 AD8042 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12.6 V Internal Power Dissipation2 Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . 1.3 Watts Small Outline Package (R) . . . . . . . . . . . . . . . . . . 0.9 Watts Input Voltage (Common Mode) . . . . . . . . . . . . . ± VS ± 0.5 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 3.4 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range (N, R) . . . . . . . ­65°C to +125°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C The maximum power that can be safely dissipated by the AD8042 AD8042 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150°C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period can result in device failure. While the AD8042 AD8042 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for the device in free air: 8-Pin Plastic Package: JA = 90°C/Watt 8-Pin SOIC Package: JA = 160°C/Watt. MAXIMUM POWER DISSIPATION ­ Watts 2.0 ORDERING GUIDE Model AD8042AN AD8042AN AD8042AN AD8042AN AD8042AR AD8042AR AD8042AR AD8042AR AD8042AR-REEL AD8042AR-REEL Supply Voltage Temperature Range Package Option +5 V, ± 5 V +3 V +5 V, ± 5 V +3 V ­40°C to +85°C 0°C to +70°C ­40°C to +85°C 0°C to +70°C 8-Pin Plastic DIP 8-Pin Plastic DIP 8-Pin Plastic SOIC 8-Pin Plastic SOIC REEL-SOIC 8-PIN MINI-DIP PACKAGE TJ = +150°C 1.5 1.0 8-PIN SOIC PACKAGE 0.5 0 ­50 ­40 ­30 ­20 ­10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE ­ °C 70 80 90 Figure 3. Maximum Power Dissipation vs. Temperature CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8042 AD8042 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 ­5­ WARNING! ESD SENSITIVE DEVICE AD8042 AD8042­Typical Performance Characteristics 100 100 VS = 5V T = +25°C 140 PARTS, SIDE A & B MEAN = ­1.52mV STD DEVIATION = 1.15 SAMPLE SIZE = 280 (140 AD8042S AD8042S) 80 FREQUENCY 70 60 95 OPEN-LOOP GAIN ­ dB 90 50 40 30 90 85 VS = +5V T = +25°C 80 20 75 10 0 70 ­6 ­5 ­4 ­3 ­2 ­1 0 1 VOS ­ mV 2 3 4 5 6 250 500 750 1000 1250 1500 LOAD RESISTANCE ­ 1750 2000 Figure 7. Open-Loop Gain vs. RL to +2.5 V Figure 4. Typical Distribution of VOS 30 100 VS =+5V MEAN = ­12.6µV/°C STD DEV = 2.02µV/°C SAMPLE SIZE = 60 98 OPEN-LOOP GAIN ­ dB 25 20 FREQUENCY 0 15 10 VS = +5V RL = 1k 96 94 92 90 5 88 0 ­18 ­16 ­14 ­12 ­10 ­8 ­6 VOS DRIFT ­ µV/°C ­4 ­2 86 ­40 0 Figure 5. VOS Drift Over ­40 °C to +85 °C 0 20 40 TEMPERATURE ­ °C 60 80 Figure 8. Open-Loop Gain vs. Temperature 100 0 RL = 500 TO 2.5V VS = +5V VCM= 0V ­0.2 VS = +5V 90 ­0.4 OPEN-LOOP GAIN ­ dB INPUT BIAS CURRENT ­ µA ­20 ­0.6 ­0.8 ­1 ­1.2 80 RL = 50 TO 2.5V 70 60 ­1.4 50 ­1.6 ­1.8 40 0 ­2 ­40 ­30 ­20 ­10 0 10 20 30 40 TEMPERATURE ­ °C 50 60 70 80 0.5 1 1.5 2 2.5 3 3.5 OUTPUT VOLTAGE ­ Volts 4 4.5 5 Figure 9. Open-Loop Gain vs. Output Voltage Figure 6. IB vs. Temperature ­6­ REV. 0 AD8042 AD8042 0.04 DIFFERENTIAL GAIN ERROR ­ % 100 30 10 DIFFERENTIAL PHASE ERROR ­ deg 3 1 10 100 1k 10k 100k 1M 10M 100M 1G 0.00 ­0.01 0.05 0.04 0.03 VS = +5V G = +2 RL = 150 TO 2.5V 0.02 VS = ±5V G = +2 RL = 150 0.01 0 10 20 30 40 50 60 70 80 MODULATING RAMP LEVEL ­ IRE 90 100 0.4 RL = 100 TO 1.5V NORMALIZED GAIN ­ dB VS = +5V, AV = +2, ­50 RL = 100 TO 2.5V VS = +5V, AV = +1, ­60 RL = 100 TO 2.5V ­70 ­80 VS = +5V, AV = +2, RL = 1k TO 2.5V 0.3 0.2 0.1 0 14MHz ­0.1 ­0.2 VS = +5V, AV = +1, ­90 VS = +5V G = +2 RF = 200 RL = 150 TO 2.5V 0.5 VS = +3V, AV = ­1, ­40 ­0.3 RL = 1k TO 2.5V ­0.4 1 3 2 4 5 6 FUNDAMENTAL FREQUENCY ­ MHz 1 7 8 9 10 10 FREQUENCY ­ MHz 100 500 Figure 14. 0.1 dB Gain Flatness Figure 11. Total Harmonic Distortion 120 ­30 VS = +5V G = +2 RF = 200 RL = 150 TO 2.5V 100 ­40 OPEN­LOOP GAIN ­ dB 10 MHz ­50 WORST HARMONIC ­ dBc VS = ±5V G = +2 RL = 150 0.01 0.6 ­30 ­60 5 MHz ­70 ­80 80 GAIN 60 45 40 0 20 ­45 0 ­90 PHASE ­20 ­135 ­40 ­180 ­60 1MHz ­225 ­90 VS = +5V, G = +2, RL = 1k TO 2.5V ­100 ­110 0.0 0.5 1.0 2.0 2.5 3.0 3.5 1.5 OUTPUT VOLTAGE ­ V p-p 4.0 4.5 ­80 0.01 5.0 Figure 12. Worst Harmonic vs. Output Voltage REV. 0 VS = +5V G = +2 RL = 150 TO 2.5V Figure 13. Differential Gain and Phase Errors Figure 10. Input Voltage Noise vs. Frequency TOTAL HARMONIC DISTORTION ­ dBc 0.02 ­0.01 0 FREQUENCY ­ Hz ­100 0.03 0.1 1 10 FREQUENCY ­ MHz 100 Figure 15. Open-Loop Gain and Phase vs. Frequency ­7­ ­270 500 PHASE­ Degrees INPUT VOLTAGE NOISE ­ nV/ Hz NTSC Subcarrier (3.579 MHz) 300 AD8042 AD8042­Typical Performance Characteristics 60 10 VS = +5V G =+1 CL = 5pF RL = 2k TO 2.5V 8 T = +85°C T = +25°C 2 T = ­40°C 0 ­2 ­4 45 VS = +3V, 1% 40 VS = +5V, 0.1% 35 VS = ±5V, 0.1% 30 ­6 VS = +5V, 1% 25 VS = ±5V, 1% ­8 ­10 VS = +3V, 0.1% 50 4 SETTING TIME ­ ns CLOSED­LOOP GAIN ­ dB 6 G = ­1 RL = 2k TO MIDPOINT CL = 5pF 55 1 10 FREQUENCY ­ MHz 100 20 0.5 500 1 1.5 BIPOLAR INPUT STEP ­ V Figure 16. Closed-Loop Frequency Response vs. Temperature 2 Figure 19. Settling Time 12 0 COMMON MODE REJECTION ­ dB 8 CLOSED­LOOP GAIN ­ dB VS = +3V RL & CL TO 1.5V G = +1 CL = 5pF RL = 2k 10 VS = +5V RL & CL TO 2.5V 6 VS = ±5V 4 2 0 ­2 ­4 TEST CIRCUIT: ­10 Vs = +5V 1.02k 1.02k OUT INCM ­20 1.02k ­30 1.02k ­40 ­50 ­60 ­70 ­80 ­6 ­90 10k ­8 1 10 FREQUENCY ­ MHz 100 1M 10M FREQUENCY ­ Hz 100k 500 Figure 17. Closed-Loop Frequency Response vs. Supply 100M 500M Figure 20. CMRR vs. Frequency 0.80 VS = +5V OUTPUT SATURATION VOLTAGE ­ V OUTPUT RESISTANCE ­ 100 RBT = 50 10 VS = +5V G = +1 RBT = 0 RBT 1 VOUT 0.1 0.01 0.70 +5V ­ VOH (+125°C) +5V ­ VOH (+25°C) 0.60 +5V ­ VOH (­55°C) 0.50 0.40 0.30 0.20 +VOL (+125°C) +VOL (+25°C) 0.10 +VOL (­55°C) 0.01 0.1 1 10 FREQUENCY ­ MHz 100 0 500 0 5 10 15 20 25 30 35 LOAD CURRENT ­ mA 40 45 50 Figure 21. Output Saturation Voltage vs. Load Current Figure 18. Output Resistance vs. Frequency ­8­ REV. 0 AD8042 AD8042 12 50 VS = ±5V VS = +5V VOUT = 100mV STEP 11.5 10.5 VS = +5V 10 VS = +3V % OVERSHOOT SUPPLY CURRENT ­ mA 40 11 9.5 G = +2 30 20 G = +3 9 10 8.5 0 8 ­40 ­30 ­20 ­10 0 10 20 30 40 50 TEMPERATURE ­ °C 60 70 80 90 0 Figure 22. Supply Current vs. Temperature 20 40 60 80 100 120 140 LOAD CAPACITANCE ­ pF 160 180 200 Figure 25. % Overshoot vs. Load Capacitance 6 VS = +5V 0 VS = +5V RF = 2k RL = 2k TO +2.5V 5 ­10 4 NORMALIZED GAIN ­ dB PSRR ­ dB ­20 ­30 ­40 ­PSRR ­50 ­60 +PSRR ­70 G = +2 2 1 0 G = +2 RF = 200 ­1 G = +10 ­2 ­80 G = +5 ­3 ­90 10k 100k 1M 10M FREQUENCY ­ Hz 100M 500M ­4 1 Figure 23. PSRR vs. Frequency 10 FREQUENCY ­ MHz 100 500 Figure 26. Frequency Response vs. Closed-Loop Gain 10 ­10 9 ­20 VS = ±5V RL = 2k G = ­1 8 ­30 7 VS = +5V VIN = 0.6V p-p G = +2 RF = 1k VOUT 1 ­40 CROSSTALK ­ dB OUTPUT VOLTAGE ­ V p-p 3 6 5 4 3 VOUT 2 ­50 VOUT 1 ­60 VOUT 2 , RL = 1k TO +2.5V , RL = 150 TO +2.5V ­70 VOUT2 ­80 VOUT1 2 , RL = 150 TO +2.5V ­90 VOUT2 1 ­100 0 0.1 1.0 10.0 FREQUENCY ­ MHz 100.0 ­110 0.1 Figure 24. Output Voltage Swing vs. Frequency REV. 0 VOUT1 1 , RL = 1k TO +2.5V 10 FREQUENCY ­ MHz 100 200 Figure 27. Crosstalk (Output-to-Output) vs. Frequency ­9­ AD8042 AD8042­Typical Performance Characteristics 5V 4.770V 4V VS = +5V G = ­1 RL = 150 TO +2.5V AV = +1 +2.6V VS = +5V VIN = 100mV p-p RL = 1k TO 2.5V CL = 5pF 3V +2.5V 2V 1V +2.4V 0.160V 25mV 200µs 0.5V 10ns 0V Figure 28a. Output Swing with Load Referenced to Supply Midpoint Figure 30. 100 mV Pulse Response, VS = +5 V 5V 4V 4.59V G = ­1 RL = 2k TO +1.5V VS= +5V G = ­1 RL= 150 TO GND 3V 3V 1.5V 2V 1V 0V 0.035V 0.5V 200µs 0.5V 1µs 0V Figure 28b. Output Swing with Load Reference to Negative Supply 4.5V Figure 31. Rail-to-Rail Output Swing, VS = +3 V AV = +2 VS = +5V CL = 5pF RL = 1k TO +2.5V VIN = 1V p-p 3.5V VIN = 100mV p-p +1.6V RL = 1k TO 1.5V VS = +3V CL = 5pF AV = +1V +1.5V 2.5V 1.5V +1.4V 0.5V 10ns 25mV 10ns 0.5V Figure 32. 100 mV Pulse Response, VS = +3 V Figure 29. One Volt Pulse Response, VS = +5 V ­10­ REV. 0 AD8042 AD8042 Overdrive Recovery I5, along with a common-mode feedback loop (not shown). This circuit topology allows the AD8042 AD8042 to drive 40 mA of output current with the outputs within 0.5 V of the supply rails. Overdrive of an amplifier occurs when the output and/or input range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 33, the AD8042 AD8042 recovers within 30 ns from negative overdrive and within 25 ns from positive overdrive. On the input side, the device can handle voltages from 0.2 V below the negative rail to within 1.2 V of the positive rail. Exceeding these values will not cause phase reversal; however, the input ESD devices will begin to conduct if the input voltages exceed the rails by greater than 0.5 V. DRIVING CAPACITIVE LOADS +5V The capacitive load drive of the AD8042 AD8042 can be increased by adding a low valued resistor in series with the load. Figure 35 shows the effects of a series resistor on capacitive drive for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less overshoot. Adding a series resistor with lower closed-loop gains accomplishes this same effect. For large capacitive loads, the frequency response of the amplifier will be dominated by the roll-off of the series resistor and capacitive load. +2.5V VS = +5V VIN= +5V p-p G = +2 RL = 1k TO +2.5V 0V 50ns 1V 1000 Figure 33. Overdrive Recovery VS = +5V 200mV STEP WITH 30% OVERSHOOT The AD8042 AD8042 is fabricated on Analog Devices' proprietary eXtra-Fast Complementary Bipolar (XFCB) process which enables the construction of PNP and NPN transistors with similar fTs in the 2 GHz­4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features allow the construction of high frequency, low distortion amplifiers with low supply currents. This design uses a differential output input stage to maximize bandwidth and headroom (see Figure 34). The smaller signal swings required on the first stage outputs (nodes S1P, S1N) reduce the effect of nonlinear currents due to junction capacitances and improve the distortion performance. With this design harmonic distortion of better than ­77 dB @ 1 MHz into 100 with VOUT = 2 V p-p (Gain = +2) on a single 5 volt supply is achieved. VCC I1 I10 R26 I2 R39 Q4 I 3 Q25 Q36 Q5 Q51 I5 Q39 Q23 Q40 R15 R2 Q22 VEE VINP Q13 C3 Q31 Q21 VINN VOUT Q27 C9 SIN Q2 Q11 Q3 C7 VEE R23 R27 Q7 Q17 SIP I9 Q50 R5 Q8 Q24 R21 R3 I7 Q47 I8 VCC VEE Figure 34. AD8042 AD8042 Simplified Schematic The AD8042 AD8042's rail-to-rail output range is provided by a complementary common-emitter output stage. High output drive capability is provided by injecting all output stage predriver currents directly into the bases of the output devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by I8 and REV. 0 CAPACITIVE LOAD ­ pF Circuit Description RS = 5 RS CL RS = 0 100 RS = 20 10 1 2 3 4 CLOSED-LOOP GAIN ­ V/V 5 Figure 35. Capacitive Load Drive vs. Closed-Loop Gain Single Supply Composite Video Line Driver The two op amps of an AD8042 AD8042 can be configured as a single supply dual line driver for composite video. The wide signal swing of the AD8042 AD8042 enables this function to be performed without using any type of clamping or dc restore circuit which can cause signal distortion. Figure 36 shows a schematic for a circuit that is driven by a single composite video source that is ac coupled, level shifted and applied to both + inputs of the two amplifiers. Each op amp provides a separate 75 composite video output. To obtain single supply operation, ac coupling is used throughout. The large capacitor values are required to ensure that there is minimal tilting of the video signals due to their low frequency (30 Hz) signal content. The circuit shown was measured to have a differential gain of 0.06% and a differential phase of 0.06°. The input is terminated in 75 and ac coupled via CIN to a voltage divider that provides the dc bias point to the input. Setting the optimal bias point requires some understanding of the nature of composite video signals and the video performance of the AD8042 AD8042. ­11­ AD8042 AD8042 +5V To test this, the differential gain and differential phase were measured for the AD8042 AD8042 while the supplies were varied. As the lower supply is raised to approach the video signal, the first effect to be observed is that the sync tips become compressed before the differential gain and differential phase are adversely affected. Thus, there must be adequate swing in the negative direction to pass the sync tips without compression. 4.99k 0.1µF 4.99k 10µF 10µF 3 8 1 COMPOSITE VIDEO IN 75 COAX 1000µF 2 RT 75 RF 1k VOUT RL 75 0.1µF 75 RG 1k 10k As the upper supply is lowered to approach the video, the differential gain and differential phase were not significantly adversely affected until the difference between the peak video output and the supply reached 0.6 V. Thus, the highest video level should be kept at least 0.6 V below the positive supply rail. 220µF 5 1000µF 7 6 RT 75 4 VOUT RL 75 0.1µF RG 1k Taking the above into account, it was found that the optimal point to bias the noninverting input is at 2.2 V dc. Operating at this point, the worst case differential gain is measured at 0.06% and the worst case differential phase is 0.06°. RF 1k 220µF Figure 36. Single Supply Composite Video Line Driver Using AD8042 AD8042 Signals of bounded peak-to-peak amplitude that vary in duty cycle require larger dynamic swing capability than their peak-topeak amplitude after ac coupling. As a worst case, the dynamic signal swing required will approach twice the peak-to-peak value. The two bounding cases are for a duty cycle that is mostly low, but occasionally goes high at a fraction of a percent duty cycle and vice versa. Composite video is not quite this demanding. One bounding extreme is for a signal that is mostly black for an entire frame, but has a white (full intensity), minimum width spike at least once per frame. The other extreme is for a video signal that is full white everywhere. The blanking intervals and sync tips of such a signal will have negative going excursions in compliance with composite video specifications. The combination of horizontal and vertical blanking intervals limit such a signal to being at its highest level (white) for only about 75% of the time. The ac coupling capacitors used in the circuit at first glance appear quite large. A composite video signal has a lower frequency band edge of 30 Hz. The resistances at the various ac coupling points-especially at the output-are quite small. In order to minimize phase shifts and baseline tilt, the large value capacitors are required. For video system performance that is not to be of the highest quality, the value of these capacitors can be reduced by a factor of up to five with only a slightly observable change in the picture quality. Single-Ended to Differential Driver Using a cross-coupled single-ended to differential converter, the AD8042 AD8042 makes a good general purpose differential line driver. This can be used for applications such as driving category 5 twisted pair wire which is becoming common for data communications in buildings. Figure 37 shows a configuration for a circuit that performs this function that can be used for video transmission over a differential pair or various data communication purposes. 0.1µF As a result of the duty cycle variations between the two extremes presented above, a 1 V p-p composite video signal that is multiplied by a gain of two requires about 3.2 V p-p of dynamic voltage swing at the output for an op amp to pass a composite video signal of arbitrary duty cycle without distortion. VIN 49.9 3 2 8 AMP1 1 RF 1k 10µF 60.4 RA 1k Some circuits use a sync tip clamp along with ac coupling to hold the sync tips at a relatively constant level in order to lower the amount of dynamic signal swing required. However, these circuits can have artifacts like sync tip compression unless they are driven by sources with very low output impedance. The AD8042 AD8042 not only has ample signal swing capability to handle the dynamic range required without using a sync tip clamp, but also has good video specifications like differential gain and differential phase when buffering these signals in an ac coupled configuration. RIN 1k AD8042 AD8042 RB 1k 6 5 100 50m RB 1k 121 VOUT RA 1k AMP2 7 60.4 4 0.1µF 10µF ­5V Figure 37. Single-Ended to Differential Twisted Pair Line Driver ­12­ REV. 0 AD8042 AD8042 Each of the AD8042 AD8042's op amps is configured as a unity gain follower by the feedback resistors (RA). Each op amp output also drives the other as a unity gain inverter via the two RBs, creating a totally symmetrical circuit. +5V +5V 0.1µF If the + input to Amp 2 is grounded and a small positive signal is applied to the + input of Amp 1, the output of Amp 1 will be driven to saturation in the positive direction and the input of Amp 2 driven to saturation in the negative direction. This is similar to the way a conventional op amp behaves without any feedback. 0.1µF 1k VIN 3 8 1 2 +5V 1k AD8042 AD8042 0.1µF 1k 0.1µF 26 28 15 DVDD 6 1k AVDD AVDD OTR VINA BIT1 7 2.49k VINB 5 BIT2 4 2.49k BIT3 0.1µF CAPT 0.1µF 10/16 BIT4 AD9220 AD9220 0.1µF BIT5 BIT6 CAPB 18 0.1µF 17 BIT7 VREF BIT8 SENSE BIT9 22 BIT11 BIT11 1 CLOCK BIT10 BIT10 CML 0.1µF The cable has a characteristic impedance of about 120 . Each driver output is back terminated with a pair of 60.4 resistors to make the source look like 120 . The receive end is terminated with 121 , and the signal is measured differentially with a pair of scope probes. One channel on the oscilloscope is inverted and then the signals are added. BIT12 BIT12 CLK 14 13 12 11 10 9 8 7 6 5 4 3 2 REFCOM DVSS AVSS AVSS 19 27 25 16 Figure 39. AD8042 AD8042 Differential Driver for the AD9220 AD9220 12-Bit, 10 MSPS A/D Converter The scope photo in Figure 38 shows a 10 MHz, 2 V p-p input signal driving the circuit with 50 m of category 5 twisted pair wire. The circuit was tested with a 1 MHz input signal and clocked at 10 MHz. An FFT response of the digital output is shown in Figure 40. Pin 5 is biased at 2.5 V by the voltage divider and bypassed. This biases each output at 2.5 V. VIN is ac coupled such that VIN going positive makes VINA go positive and VINB go in the negative direction. The opposite happens for a negative going VIN. 50ns 100 VIN +5V 0.1µF 1k The gain of this circuit from input to either output will be ± RF/ RI. Or the single-ended to differential gain will be 2 × RF/RI. This gives the circuit the advantage of being able to adjust its gain by changing a single resistor. 200mV +5V +5V If a resistor (RF) is connected from the output of Amp 2 to the + input of Amp 1, negative feedback is provided which closes the loop. An input resistor (RI) will make the circuit look like a conventional inverting op amp configuration with differential outputs. 1V 1k 90 VERTICAL SCALE ­ 15dB/DIV 1 VOUT 10 0% 200mV Figure 38. Differential Driver Frequency Response Single Supply Differential A/D Driver The single-ended to differential converter circuit is also useful as a differential driver for video speed, single-ended, differential input A/D converters. Figure 39 is a schematic that shows such a circuit differentially driving an AD9220 AD9220, a 12-bit, 10 MSPS A/D converter. 9 FUND FRQ 1000977 SMPL FRQ 10000000 3 7 2 8 THD SNR SINAD SFDR ­82.00 71.13 70.79 ­86.74 6 5 4 HARMONICS (dBc) 2nd ­88.34 6th ­99.47 3rd ­86.74 7th ­91.16 4th ­99.26 8th ­97.25 5th ­90.67 9th ­91.61 Figure 40. FFT of AD9220 AD9220 Output When Driven by AD8042 AD8042 REV. 0 ­13­ AD8042 AD8042 HDSL Line Driver Layout Considerations HDSL or high-bit-rate digital subscriber line is becoming popular as a means to provide data communication at DS1 rates (1.544 MBPS) over moderate distances via conventional telephone twisted pair wires. In these systems, the transceiver at the customer's end is sometimes powered via the twisted pair from a power source at the central office. It is sometimes required to raise the dc voltage of the power source to compensate for IR drops in long lines or lines with narrow gauge wires. The specified high speed performance of the AD8042 AD8042 requires careful attention to board layout and component selection. Proper RF design techniques and low-pass parasitic component selection are necessary. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the area near the input pins to reduce the stray capacitance. Because of this, it is highly desirable to keep the power consumption of the customer's transceiver as low as possible. One means to realize significant power savings is to run the transceiver from a ± 5 V supply instead of the more conventional ± 12 V. Chip capacitors should be used for the supply bypassing. One end should be connected to the ground plane and the other within 1/8 inch of each power pin. An additional large (0.47 µF­10 µF) tantalum electrolytic capacitor should be connected in parallel, but not necessarily so close, to supply current for fast, large signal changes at the output. The high output swing and current drive capability of the AD8042 AD8042 make it ideally suited to this application. Figure 41 shows a circuit for the analog portion of an HDSL transceiver using the AD8042 AD8042 as the line driver. 2k 3k 6 232 VOUT 5 VIN 1/2 AD8042 AD8042 1 4 10 2k Stripline design techniques should be used for long signal traces (greater than about 1 inch). These should be designed with a characteristic impedance of 50 or 75 and be properly terminated at each end. ATT 2718AF 2718AF 93DJ39 93DJ39 7 5 2 7 9 The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance. 6 3k 2 1 3 0.001µF 1/2 AD8042 AD8042 912 0.0027µF 34 2k 2k 2 2k 2k 1 3 2k 249 VREC 1/4 AD8044 AD8044 0.001µF Figure 41. HDSL Line Driver ­14­ REV. 0 AD8042 AD8042 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 8 5 0.25 (6.35) PIN 1 1 0.31 (7.87) 4 0.30 (7.62) REF 0.39 (9.91) MAX 0.035±0.01 (0.89±0.25) 0.165±0.01 (4.19±0.25) 0.011±0.003 (0.28±0.08) 0.18±0.03 (4.57±0.76) 0.125 (3.18) MIN 0.018±0.003 (0.46±0.08) 0.033 (0.84) NOM 0.10 (2.54) BSC 15° 0° SEATING PLANE 8-Lead Plastic SOIC (SO-8) 8 5 0.1574 (4.00) 0.1497 (3.80) PIN 1 1 0.2440 (6.20) 0.2284 (5.80) 4 0.1968 (5.00) 0.1890 (4.80) 0.0098 (0.25) 0.0040 (0.10) 0.0196 (0.50) x 45° 0.0099 (0.25) 0.0688 (1.75) 0.0532 (1.35) 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC REV. 0 0.0098 (0.25) 0.0075 (0.19) ­15­ 8° 0° 0.0500 (1.27) 0.0160 (0.41) ­16­ PRINTED IN U.S.A. C2082 C2082­10­10/95