AD6623 AD6622 IS136 CDMA2000 128-PIN 196-PIN IS-95-A/B IS-136 AD6623AS - Datasheet Archive

 

4-Channel, 104 MSPS Digital Transmit Signal Processor (TSP) AD6623 FEATURES Pin Compatible to the AD6622 18-Bit Parallel Digital

 

a 4-Channel, 104 MSPS Digital Transmit Signal Processor (TSP) AD6623 AD6623 FEATURES Pin Compatible to the AD6622 AD6622 18-Bit Parallel Digital IF Output Real or Interleaved Complex 18-Bit Bidirectional Parallel Digital IF Input/Output Allows Cascade of Chips for Additional Channels Clipped or Wrapped Over Range Two's Complement or Offset Binary Output Four Independent Digital Transmitters in Single Package RAM Coefficient Filter (RCF) Programmable IF and Modulation for Each Channel Programmable Interpolating RAM Coefficient Filter /4-DQPSK Differential Phase Encoder 3/8-PSK Linear Encoder 8-PSK Linear Encoder Programmable GMSK Look-Up Table Programmable QPSK Look-Up Table All-Pass Phase Equalizer Programmable Fine Scaler Programmable Power Ramp Unit High Speed CIC Interpolating Filter Digital Resampling for Noninteger Interpolation Rates NCO Frequency Translation Carrier Output from DC to 52 MHz Spurious Performance Better than ­100 dBc Separate 3-Wire Serial Data Input for Each Channel Bidirectional Serial Clocks and Frames Microprocessor Control 2.5 V CMOS Core, 3.3 V Outputs, 5 V Inputs JTAG Boundary Scan APPLICATIONS Cellular/PCS Base Stations Micro/Pico Cell Base Stations Wireless Local Loop Base Stations Multicarrier, Multimode Digital Transmit GSM, EDGE, IS136 IS136, PHS, IS95, TDS CDMA, UMTS, CDMA2000 CDMA2000 Phased Array Beam Forming Antennas Software Defined Radio Tuning Resolution Better than 0.025 Hz Real or Complex Outputs FUNCTIONAL BLOCK DIAGRAM NCO = NUMERICALLY CONTROLLED OSCILLATOR/TUNER SDINA DATA SDFIA SPORT SDFOA I RAM COEFFICIENT Q FILTER SCALER I AND Q POWER RAMP CIC5 FILTER Q I I RAM COEFFICIENT Q FILTER SCALER I AND Q POWER RAMP CIC5 FILTER Q I rCIC2 FILTER Q rCIC2 FILTER Q QIN CHAN A NCO IN [17­0] SCLKA SDINB SDFIB DATA SPORT SDFOB I I CHAN B NCO SYNC 4 SCLKB SUMMATION SDINC DATA SDFIC SPORT I I RAM COEFFICIENT Q FILTER SCALER AND Q POWER RAMP I RAM COEFFICIENT Q FILTER SCALER I AND Q POWER RAMP SDFOC I CIC5 FILTER Q I rCIC2 FILTER Q CHAN C NCO SCLKC OEN SDIND SDFID DATA SPORT SDFOD I CIC5 FILTER Q I rCIC2 FILTER Q QOUT CHAN D NCO OUT [17:0] SCLKD MICROPORT JTAG TDL TDO TMS TCK TRST D[7:0] DS DTACK RW MODE A[2:0] CS CLK RESET REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD6623 AD6623 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . 4 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LOGIC INPUTS (5 V TOLERANT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LOGIC OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 IDD SUPPLY CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . 5 MICROPROCESSOR PORT TIMING CHARACTERISTICS . . . . . . . . . . . . 6 MICROPROCESSOR PORT, MODE INM (MODE = 0) . . . . . . . . . . . . . 6 MICROPROCESSOR PORT, MOTOROLA (MODE = 1) . . . . . . . . . . . . 6 TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PIN CONFIGURATION ­ 128-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . 11 128-PIN 128-PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PIN CONFIGURATION ­ 196-Lead CSPBGA . . . . . . . . . . . . . . . . . . . . . . 13 196-PIN 196-PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 JTAG AND BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CONTROL REGISTER ADDRESS NOTATION . . . . . . . . . . . . . . . . . . . . 15 SERIAL DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Master Mode (SCS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Slave Mode (SCS = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Data Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Self-Framing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 External Framing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Port Cascade Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PROGRAMMABLE RAM COEFFICIENT FILTER (RCF) . . . . . . . . . . . . . 16 OVERVIEW OF THE RCF BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 INTERPOLATING FIR FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Channel A RCF Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PSK MODULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 /4-DQSPK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8-PSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3/8-8-PSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 GMSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 QPSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PHASE EQUALIZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FINE SCALE AND RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FINE SCALING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 RCF POWER RAMPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ramp Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Special Handling for SYNC0 Pin-Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CASCADED INTERGRATOR COMB (CIC) INTERPOLATING FILTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CIC Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CIC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 The rCIC2 RESAMPLING INTERPOLATION FILTER . . . . . . . . . . . . . . 25 Permissible Values of L rCIC2 and MrCIC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Frequency Response for rCIC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Programming Guidelines for AD6623 AD6623 CIC Filters . . . . . . . . . . . . . . . . . . . 26 NUMERICALLY CONTROLLED OSCILLATOR/TUNER (NCO) . . . . . 27 Phase Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Amplitude Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 NCO Frequency Update and Phase Offset Update Hold-Off Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 NCO Control Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SUMMATION BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Dual 18-Bit Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Output Clip Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Cascading Multiple AD6623s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Selection of Real and Complex Data Types . . . . . . . . . . . . . . . . . . . . . . . . 29 SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Hold-Off Counters and Shadow Registers . . . . . . . . . . . . . . . . . . . . . . . . . 29 Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Start with No Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Start with SoftSync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Start with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Set Frequency No Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Hop with SoftSync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Hop with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Beam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Set Phase No Beam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Beam with SoftSync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Beam with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Time Slot (Ramp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Set Output Power, No Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Time Slot (Ramp) with SoftSync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Time Slot with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 JTAG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SCALING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Multicarrier Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Single Carrier Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 MICROPORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Microport Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 EXTERNAL MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Intel Nonmultiplexed Mode (INM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Motorola Nonmultiplexed Mode (MNM) . . . . . . . . . . . . . . . . . . . . . . . . . 35 External Address 7 Upper Address Register (UAR) . . . . . . . . . . . . . . . . . . 35 External Address 6 Lower Address Register (LAR) . . . . . . . . . . . . . . . . . . 35 External Address 5 SoftSync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 External Address 4 Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 External Address 3:0 (Data Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INTERNAL CONTROL REGISTERS AND ON-CHIP RAM . . . . . . . . . . . . . 36 AD6623 AD6623 and AD6622 AD6622 Compatibility Common Function Registers (not associated with a particular channel) . . . . . . 36 Channel Function Registers (0x1xx = Ch. A, 0x2xx = Ch. B, 0x3xx = Ch. C, 0x4xx = Ch. D) . . . . . . . . . . . . . . . . . . . . 36 (0x000) Summation Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 (0x001) Sync Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 (0x002) BIST Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 (0x003) BIST Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 (0xn00) Start Update Hold-Off Counter . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn01) NCO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn02) NCO Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn03) NCO Frequency Update Hold-Off Counter . . . . . . . . . . . . . . . . . 39 (0xn04) NCO Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn05) NCO Phase Offset Update Hold-Off Counter . . . . . . . . . . . . . . . 39 (0xn06) CIC Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn07) CIC2 Decimation ­ 1 (M CIC2 ­ 1) . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn08) CIC2 Interpolation ­ 1 (L CIC2 ­ 1) . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn09) CIC5 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn0A) Number of RCF Coefficients ­ 1 . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn0B) RCF Coefficient Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn0C) Channel Mode Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 (0xn0D) Channel Mode Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn0E) Fine Scale Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn0F) RCF Time Slot Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn10­0xn11) RCF Phase Equalizer Coefficients . . . . . . . . . . . . . . . . . . . 40 (0xn12­0xn15) FIR-PSK Magnitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn16) Serial Port Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn17) Power Ramp Length 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn18) Power Ramp Length 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn19) Power Ramp Rest Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn20­0xn1F) Unused . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn20­0xn3F) Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 (0xn40­0xn17F) Power Ramp Coefficient Memory . . . . . . . . . . . . . . . . . . 40 (0xn80­0xnFF) Coefficient Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PSEUDOCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AD6623 AD6623 EVALUATION PCB AND SOFTWARE . . . . . . . . . . . . . . . . . . . . 41 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Using the AD6623 AD6623 to Process UMTS Carriers . . . . . . . . . . . . . . . . . . . . . . 42 Digital-to-Analog Converter (DAC) Selection . . . . . . . . . . . . . . . . . . . . . . 42 Multiple TSP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Determining the Number of TSPs to Use . . . . . . . . . . . . . . . . . . . . . . . . . 42 Programming Multiple TSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Driving Multiple TSP Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 USING THE AD6623 AD6623 TO PROCESS TWO UMTS CARRIERS WITH 24 OUTPUT RATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Configuring the AD6623 AD6623 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 AD6623 AD6623 Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 THERMAL MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ­2­ REV. A AD6623 AD6623 PRODUCT DESCRIPTION The AD6623 AD6623 is a 4-channel Transmit Signal Processor (TSP) that creates high bandwidth data for Transmit Digital-to-Analog Converters (TxDACs) from baseband data provided by a Digital Signal Processor (DSP). Modern TxDACs have achieved sufficiently high sampling rates, analog bandwidth, and dynamic range to create the first Intermediate Frequency (IF) directly. The AD6623 AD6623 synthesizes multicarrier and multistandard digital signals to drive these TxDACs. The RAM-based architecture allows easy reconfiguration for multimode applications. Modulation, pulse-shaping and anti-imaging filters, static equalization, and tuning functions are combined in a single, cost-effective device. Digital IF signal processing provides repeatable manufacturing, higher accuracy, and more flexibility than comparable high dynamic range analog designs. The AD6623 AD6623 has four identical digital TSPs complete with synchronization circuitry and cascadable wideband channel summation. AD6623 AD6623 is pin compatible to AD6622 AD6622 and can operate in AD6622-compatible control register mode. The AD6623 AD6623 utilizes a 3.3 V I/O power supply and a 2.5 V core power supply. All I/O pins are 5 V tolerant. All control registers and coefficient values are programmed through a generic microprocessor interface. Intel and Motorola microprocessor bus modes are supported. All inputs and outputs are LVCMOS compatible. FUNCTIONAL OVERVIEW Each TSP has five cascaded signal processing elements: a programmable interpolating RAM Coefficient Filter (RCF), a programmable Scale and Power Ramp, a programmable fifth order Cascaded Integrator Comb (CIC5) interpolating filter, a flexible second order Resampling Cascaded Integrator Comb filter (rCIC2), and a Numerically Controlled Oscillator/Tuner (NCO). The outputs of the four TSPs are summed and scaled on-chip. In multicarrier wideband transmitters, a bidirectional bus allows the Parallel (wideband) IF Input/Output to drive a second DAC. In this operational mode two AD6623 AD6623 channels drive one DAC and the other two AD6623 AD6623 channels drive a second DAC. Multiple AD6623s may be combined by driving the INOUT[17:0] of the succeeding with the OUT[17:0] of the preceding chip. The REV. A INOUT[17:0] can alternatively be masked off by software to allow preceding AD6623 AD6623's outputs to be ignored. Each channel accepts input data from independent serial ports that may be connected directly to the serial port of Digital Signal Processor (DSP) chips. The RCF implements any one of the following functions: Interpolating Finite Impulse Response (FIR) filter, /4-DQPSK modulator, 8-PSK modulator, or 3/8-8-PSK modulator, GMSK modulator, and QPSK modulator. Each AD6623 AD6623 channel can be dynamically switched between the GMSK modulation mode and the 3/8-8-PSK modulation mode in order to support the GSM/EDGE standard. The RCF also implements an Allpass Phase Equalizer (APE) which meets the requirements of IS-95-A/B IS-95-A/B standard (CDMA transmission). The programmable Scale and Power Ramp block allows power ramping on a time-slot basis as specified for some air-interface standards (e.g., GSM, EDGE). A fine scaling unit at the programmable FIR filter output allows an easy signal amplitude level adjustment on time slot basis. The CIC5 provides integer rate interpolation from 1 to 32 and coarse anti-image filtering. The rCIC2 provides fractional rate interpolation from 1 to 4096 in steps of 1/512. The wide range of interpolation factors in each CIC filter stage and a highly flexible resampler incorporated into rCIC2 makes the AD6623 AD6623 useful for creating both narrowband and wideband carriers in a high-speed sample stream. The high resolution 32-bit NCO allows flexibility in frequency planning and supports both digital and analog air interface standards. The high speed NCO tunes the interpolated complex signal from the rCIC2 to an IF channel. The result may be real or complex. Multicarrier phase synchronization pins and phase offset registers allow intelligent management of the relative phase of independent RF channels. This capability supports the requirements for phased array antenna architectures and management of the wideband peak/power ratio to minimize clipping at the DAC. The wideband Output Ports can deliver real or complex data. Complex words are interleaved into real (I) and imaginary (Q) parts at half the master clock rate. ­3­ AD6623 AD6623 AD6623 AD6623­SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter Test Level Min AD6623 AD6623 Typ Max Unit VDD VDDIO TAMBIENT IV IV IV 2.25 3.0 ­40 2.5 3.3 +25 2.75 3.6 +85 V V °C Max Unit 5.0 +0.8 10 10 V V µA µA pF ELECTRICAL CHARACTERISTICS Parameter (Conditions) Temp Test Level Min LOGIC INPUTS (5 V TOLERANT) Logic Compatibility Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Full Full Full Full Full 25°C IV IV IV IV V 2.0 ­0.3 LOGIC OUTPUTS Logic Compatibility Logic "1" Voltage (IOH = 0.25 mA) Logic "0" Voltage (IOL = 0.25 mA) Full Full Full IV IV 2.0 IDD SUPPLY CURRENT GSM Example: CORE I/O IS-136 IS-136 Example: CORE I/O WBCDMA Example Sleep Mode POWER DISSIPATION GSM Example IS-136 IS-136 Example WBCDMA Example Sleep Mode Typ 3.3 V CMOS 1 0 4 V 3.3 V CMOS/TTL VDD ­ 0.2 0.2 Full V IV 232 56 207 55 TBD TBD Full V V V IV 740 700 TBD TBD V 0.4 V V mA mA mA mA mA mA mW mW mW mW See the Thermal Management section of the data sheet for further details. ­4­ REV. A AD6623 AD6623 GENERAL TIMING CHARACTERISTICS1, 2 Parameter (Conditions) Temp Test Level Min CLK Timing Requirements: tCLK CLK Period CLK Width Low tCLKL tCLKH CLK Width High Full Full Full I IV IV 9.6 3 3 RESET Timing Requirement: tRESL RESET Width Low Full I 30.0 ns Input Data Timing Requirements: tSI INOUT[17:0], QIN to CLK Setup Time tHI INOUT[17:0], QIN to CLK Hold Time Full Full IV IV 1 2 ns ns Output Data Timing Characteristics: CLK to OUT[17:0], INOUT[17:0], tDO QOUT Output Delay Time tDZO OEN HIGH to OUT[17:0] Active Full Full IV IV 2 3 SYNC Timing Requirements: SYNC(0, 1, 2, 3) to CLK Setup Time tSS tHS SYNC(0, 1, 2, 3) to CLK Hold Time Full Full IV IV 1 2 Full Full IV IV 4 5 10.5 13 ns ns Full IV 3.5 9 ns Full IV 4 10 ns Full Full Full IV IV IV 1.7 0 0.5 3.5 ns ns ns Full Full Full Full Full IV IV IV IV IV 2 0 2 0 0.5 3 ns ns ns ns ns Full Full Full IV IV IV 3.5 3.5 ns ns ns Full Full Full IV IV IV 1 2.5 4 ns ns ns Full Full Full Full Full IV IV IV IV IV 2 1 1 2.5 10 Master Mode Serial Port Timing Requirements (SCS = 0): Switching Characteristics3 tDSCLK1 CLK to SCLK Delay (divide by 1) tDSCLKH CLK to SCLK Delay (for any other divisor) CLK to SCLK Delay tDSCLKL (divide by 2 or even number) CLK to SCLK Delay tDSCLKLL (divide by 3 or odd number) Channel is Self-Framing SDIN to SCLK Setup Time tSSDI0 SDIN to SCLK Hold Time tHSDI0 SCLK to SDFO Delay tDSFO0A Channel is External-Framing SDFI to SCLK Setup Time tSSFI0 SDFI to SCLK Hold Time tHSFI0 tSSDI0 SDIN to SCLK Setup Time SDIN to SCLK Hold Time tHSDI0 tDSFO0B SCLK to SDFO Delay Slave Mode Serial Port Timing Requirements (SCS = 1): Switching Characteristics3 tSCLK SCLK Period tSCLKL SCLK Low Time SCLK High Time tSCLKH Channel is Self-Framing SDIN to SCLK Setup Time tSSDH SDIN to SCLK Hold Time tHSDH SCLK to SDFO Delay tDSFO1 Channel is External-Framing SDFI to SCLK Setup Time tSSFI1 SDFI to SCLK Hold Time tHSFI1 tSSDI1 SDIN to SCLK Setup Time SDIN to SCLK Hold Time tHSDI1 tDSFO1 SCLK to SDFO Delay NOTES 1 All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V. 2 CLOAD = 40 pF on all outputs (unless otherwise specified). 3 The timing parameters for SCLK, SDIN, SDFI, SDFO, and SYNC apply to all four channels (A, B, C, and D). Specifications subject to change without notice. REV. A ­5­ AD6623AS AD6623AS Typ Max 0.5 × tCLK 6 7.5 Unit ns ns ns ns ns ns ns 2 tCLK 10 ns ns ns ns ns AD6623 AD6623 MICROPROCESSOR PORT TIMING CHARACTERISTICS1, 2 Temp Test Level Min MODE INM Write Timing: Control3 to CLK Setup Time tSC tHC Control3 to CLK Hold Time WR(RW) to RDY(DTACK) Hold Time tHWR Address/Data to WR(RW) Setup Time tSAM tHAM Address/Data to RDY(DTACK) Hold Time WR(RW) to RDY(DTACK) Delay tDRDY tACC WR(RW) to RDY(DTACK) High Delay Full Full Full Full Full Full Full IV IV IV IV IV IV IV 4.5 2.0 8.0 3.0 2.0 4.0 4 × tCLK MODE INM Read Timing: tSC Control3 to CLK Setup Time Control3 to CLK Hold Time tHC tSAM Address to RD(DS) Setup Time Address to Data Hold Time tHAM Data Three-State Delay tZOZ tDD RDY(DTACK) to Data Delay RD(DS) to RDY(DTACK) Delay tDRDY tACC RD(DS) to RDY(DTACK) High Delay Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV 4.5 2.0 3.0 2.0 4.0 8 × tCLK Parameter (Conditions) AD6623AS AD6623AS Typ Max Unit MICROPROCESSOR PORT, MODE INM (MODE = 0) 5 × tCLK 9 × tCLK ns ns ns ns ns ns ns 10 × tCLK 13 × tCLK ns ns ns ns ns ns ns ns 5 × tCLK ns ns ns ns ns ns ns ns MICROPROCESSOR PORT, MOTOROLA (MODE = 1) MODE MNM Write Timing: Control3 to CLK Setup Time tSC Control3 to CLK Hold Time tHC DS(RD) to DTACK(RDY) Hold Time tHDS RW(WR) to DTACK(RDY) Hold Time tHRW tSAM Address/Data to RW(WR) Setup Time Address/Data to RW(WR) Hold Time tHAM DS(RD) to DTACK(RDY) Delay tDDTACK tACC RW(WR) to DTACK(RDY) Low Delay Full Full Full Full Full Full IV IV IV IV IV IV 4.5 2.0 8.0 8.0 3.0 2.0 Full IV 4 × tCLK MODE MNM Read Timing: tSC Control3 to CLK Setup Time Control3 to CLK Hold Time tHC DS(RD) to DTACK(RDY) Hold Time tHDS tSAM Address to DS(RD) Setup Time Address to Data Hold Time tHAM Data Three-State Delay tZD tDD DTACK(RDY) to Data Delay DS(RD) to DTACK(RDY) Delay tDDTACK tACC DS(RD) to DTACK(RDY) Low Delay Full Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV IV 4.0 2.0 8.0 3.0 2.0 8 × tCLK 9 × tCLK 10 × tCLK 13 × tCLK ns ns ns ns ns ns ns ns ns NOTES 1 All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V. 2 CLOAD = 40 pF on all outputs (unless otherwise specified). 3 Specification pertains to control signals: RW, (WR), DS, (RD), CS. Specifications subject to change without notice. ­6­ REV. A AD6623 AD6623 TIMING DIAGRAMS tCLK tCLKL CLK tCLKH RESET INOUT[17:0] OUT[17:0] QOUT tRESL tDO tZO tZO OEN Figure 4. RESET Timing Requirements Figure 1. Parallel Output Switching Characteristics CLK CLK tDSCLKH tSI t HI tSCLKH INOUT[17:0] SCLK QIN tSCLKL Figure 2. Wideband Input Timing Figure 5. SCLK Switching Characteristics (Divide by 1) CLK CLK tDSCLKH tSS tHS tDSCLKL SCLK SYNC Figure 6. SCLK Switching Characteristic (Divide by 2 or EVEN Integer) Figure 3. SYNC Timing Inputs CLK tDSCLKH tDSCLKLL SCLK Figure 7. SCLK Switching Characteristic (Divide by 3 or ODD Integer) REV. A ­7­ AD6623 AD6623 SCLK tDSFO0A SDFO tSSDI0 SDIN tHSDI0 DATAn Figure 8. Serial Port Timing, Master Mode (SCS = 0), Channel is Self-Framing SCLK tDSFO1 SDFO tSSDI1 SDIN tHSDI1 DATAn Figure 9. Serial Port Timing, Slave Mode (SCS = 1), Channel is Self-Framing nCLKs SCLK tDSFO0B SDFO tHSFI0 tSSFI0 SDFI tSSDI0 SDIN tHSDI0 DATAn Figure 10. Serial Port Timing, Master Mode (SCS = 0), Channel is External-Framing nCLKs SCLK tDSFO1 SDFO tSSFI1 tHSFI1 SDFI tSSDI1 SDIN tHSDI1 DATAn Figure 11. Serial Port Timing, Slave Mode (SCS = 1), Channel is External-Framing ­8­ REV. A AD6623 AD6623 TIMING DIAGRAMS-INM MICROPORT MODE TIMING DIAGRAMS-MNM MICROPORT MODE CLK CLK tHC tSC RD (DS) tHC tHDS DS (RD) tHWR tSC tHRW WR (RW) RW (WR) CS CS tHAM tSAM A[2:0] A[2:0] VALID ADDRESS tHAM tSAM D[7:0] tHAM tSAM VALID ADDRESS tHAM tSAM VALID DATA D[7:0] VALID DATA tDRDY RDY (DTACK) tDDTACK DTACK (RDY) tACC tACC NOTES 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM FE OF WR TO THE RE OF RDY. 2. tACC REQUIRES A MAXIMUM 9 CLK PERIODS. NOTES 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM FE OF DS TO THE FE OF DTACK. 2. tACC REQUIRES A MAXIMUM 9 CLK PERIODS. Figure 12. INM Microport Write Timing Requirements Figure 14. MNM Microport Write Timing Requirements CLK CLK tHC tHC tSC tSC RD (DS) DS (RD) WR (RW) tHDS RW (WR) CS CS tSAM tSAM A[2:0] VALID ADDRESS tDD tZD D[7:0] tHAM VALID ADDRESS A[2:0] tDD tZD tZD VALID DATA D[7:0] tDRDY RDY (DTACK) tZD tDDTACK DTACK (RDY) tACC tACC NOTES 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM FE OF DS TO THE FE OF DTACK. 2. tACC REQUIRES A MAXIMUM 13 CLK PERIODS. NOTES 1. tACC ACCESS TIME DEPENDS ON THE ADDRESS ACCESSED. ACCESS TIME IS MEASURED FROM FE OF WR TO THE RE OF RDY. 2. tACC REQUIRES A MAXIMUM OF 13 CLK PERIODS AND APPLIES TO A[2:0] = 7, 6, 5, 3, 2, 1 Figure 13. INM Microport Read Timing Requirements REV. A tHAM VALID DATA Figure 15. MNM Microport Read Timing Requirements ­9­ AD6623 AD6623 ABSOLUTE MAXIMUM RATINGS* THERMAL CHARACTERISTICS VDDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V to +3.6 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ­0.3 V to +2.75 V Input Voltage . . . . . . . . . . . . . . ­0.3 V to +5 V (5 V Tolerant) Output Voltage Swing . . . . . . . . . . ­0.3 V to VDDIO + 0.3 V Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 125°C Operating Temperature . . . . . . . . . ­40°C to +85°C (Ambient) Storage Temperature Range . . . . . . . . . . . . ­65°C to +150°C Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280°C 128-Lead MQFP with Internal Heat Spreader: JA = 28.1°C/W, no airflow JA = 22.6°C/W, 200 lfpm airflow JA = 20.5°C/W, 400 lfpm airflow *Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the devices at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 196-Lead BGA: JA = 26.3°C/W, no airflow JA = 22°C/W, 200 lfpm airflow Thermal measurements made in the horizontal position on a 4-layer board. EXPLANATION OF TEST LEVELS I. 100% Production Tested II. 100% Production Tested at 25°C, and Sample Tested at Specified Temperatures III. Sample Tested Only IV. Parameter Guaranteed by Design and Analysis V. Parameter is Typical Value Only ORDERING GUIDE Model Temperature Range Package Description AD6623AS AD6623AS AD6623ABC AD6623ABC AD6623S/PCB AD6623S/PCB AD6623BC/PCB AD6623BC/PCB ­40°C to +85°C (Ambient) ­40°C to +85°C (Ambient) 128-Lead MQFP (Plastic Quad Flatpack) S-128 S-128 196-Lead CSPBGA (Chip Scale Package Ball Grid Array) BC-196 BC-196 MQFP Evaluation Board with AD6623 AD6623 and Software CSPBGA Evaluation Board with AD6623 AD6623 and Software CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6623 AD6623 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ­10­ Package Option WARNING! ESD SENSITIVE DEVICE REV. A REV. A GND 21 ­11­ D6 37 GND 38 GND 35 GND 36 D7 33 GND 34 GND 32 GND 31 QOUT 30 OUT17 OUT17 29 OUT16 OUT16 28 OUT15 OUT15 27 VDDIO 26 OUT14 OUT14 25 OUT13 OUT13 24 OUT12 OUT12 23 SDFIC 117 OUT11 OUT11 22 GND 116 GND 20 SDFIB 115 GND 19 SDFOB 114 OUT10 OUT10 18 OUT9 17 OUT8 16 OUT7 15 VDDIO 14 OUT6 13 OUT5 12 OUT4 11 OUT3 10 GND 9 OUT2 8 OUT1 7 OUT0 6 GND 5 GND 4 GND 3 OEN 2 GND 1 65 GND 67 CLK 66 VDD 69 SYNC2 68 GND 71 INOUT17 INOUT17 70 QIN 73 SYNC3 72 GND 75 INOUT15 INOUT15 74 INOUT16 INOUT16 78 VDDIO 77 INOUT13 INOUT13 76 INOUT14 INOUT14 80 INOUT11 INOUT11 79 INOUT12 INOUT12 82 INOUT9 81 INOUT10 INOUT10 84 GND 83 GND 86 INOUT8 85 GND 88 INOUT6 87 INOUT7 90 VDDIO 89 INOUT5 92 INOUT3 91 INOUT4 94 INOUT1 93 INOUT2 97 INOUT0 96 GND 95 GND 100 TRST 99 GND 98 GND 102 GND 101 TCK AD6623 AD6623 PIN CONFIGURATION 128-Lead MQFP GND 103 64 GND VDD 104 63 SYNC1 SDFIA 105 62 SYNC0 TMS 106 61 RESET TDO 107 TDI 108 60 CS SCLKA 109 59 VDD 58 A0 VDDIO 110 57 A1 SDFOA 111 SDINA 112 56 A2 SCLKB 113 55 MODE 54 GND AD6623 AD6623 53 GND TOP VIEW (Not to Scale) 52 GND 51 RW(WR) SDINB 118 50 DTACK(RDY) SCLKC 119 49 DS(RD) 48 D0 SDFOC 120 SDINC 121 47 VDD 46 D1 VDDIO 122 45 D2 SCLKD 123 44 D3 SDFOD 124 SDIND 125 43 D4 42 GND SDFID 126 VDD 127 41 VDDIO 40 D5 GND 128 39 GND AD6623 AD6623 128-LEAD 128-LEAD FUNCTION DESCRIPTIONS Pin Number Mnemonic Type Description 1, 3­5, 9, 19­21, 31, 32, 34­36, 38, 39, 42, 52­54, 64­65, 68, 72, 83­85, 95, 96, 98, 99, 102, 103, 116, 128 2 29, 28, 27, 25, 24, 23, 22, 18, 17, 16, 15, 13, 12, 11, 10, 8, 7, 6 47, 59, 66, 104, 127 14, 26, 41, 78, 90, 110, 122 30 33, 37, 40, 43, 44, 45, 46, 48 49 50 GND P Ground Connection OEN1 OUT[17:0] I O/T Active High Output Enable Pin Parallel Output Data VDD VDDIO QOUT D[7:0] DS (RD) DTACK (RDY) P P O/T I/O/T I O 51 55 RW (WR) MODE I I 56, 57, 58 60 61 62 63 67 69 70 71, 74­77, 79­82, 86­89, 91­94, 97 A[2:0] CS RESET2 SYNC01 SYNC01 SYNC11 SYNC11 CLK1 SYNC21 SYNC21 QIN1 INOUT[17:0]1 I I I I I I I I I/O 73 100 101 105 106 107 108 109 111 112 113 114 115 117 118 119 120 121 123 124 125 126 SYNC31 SYNC31 TRST2 TCK1 SDFIA TMS2 TDO TDI1 SCLKA SDFOA SDINA1 SCLKB SDFOB SDFIB SDFIC SDINB1 SCLKC SDFOC SDINC1 SCLKD SDFOD SDIND1 SDFID I I I I I O I I/O O I I/O O I I I I/O O I I/O O I I 2.5 V Supply 3.3 V Supply When HIGH indicates Q Output Data (Complex Output Mode) Bidirectional Microport Data INM Mode: Read Signal, MNM Mode: Data Strobe Signal Acknowledgment of a Completed Transaction (Signals when µP Port Is Ready for an Access) Open Drain, Must Be Pulled Up Externally Active HIGH Read, Active Low Write Sets Microport Mode: MODE = 1, MNM Mode; MODE = 0, INM Mode Microport Address Bus Chip Select, Active low enable for µP Access Active Low Reset Pin SYNC Signal for Synchronizing Multiple AD6623s SYNC Signal for Synchronizing Multiple AD6623s Input Clock SYNC Signal for Synchronizing Multiple AD6623s When HIGH indicates Q input data (Complex Input Mode) Wideband Input/Output Data (Allows Cascade of Multiple AD6623 AD6623 Chips In a System) SYNC Signal for Synchronizing Multiple AD6623s Test Reset Pin Test Clock Input Serial Data Frame Input-Channel A Test Mode Select Test Data Output Test Data Input Bidirectional Serial Clock-Channel A Serial Data Frame Sync Output-Channel A Serial Data Input-Channel A Bidirectional Serial Clock-Channel B Serial Data Frame Sync Output-Channel B Serial Data Frame Input -Channel B Serial Data Frame Input-Channel C Serial Data Input-Channel B Bidirectional Serial Clock-Channel C Serial Data Frame Sync Output-Channel C Serial Data Input-Channel C Bidirectional Serial Clock-Channel D Serial Data Frame Sync Output-Channel D Serial Data Input-Channel D Serial Data Frame Input-Channel D NOTES 1 Pins with a Pull-Down resistor of nominal 70 k. 2 Pins with a Pull-Up resistor of nominal 70 k. ­12­ REV. A AD6623 AD6623 PIN CONFIGURATION 196-Lead CSPBGA TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G 15mm sq. H J K L BALL LEGEND M I/O GROUND N CORE POWER RING POWER P 1.0mm 4 5 6 7 8 9 10 11 12 SDFID SDINC SDINB SDFOB SCLKB SCLKA TDO SDFIA B OEN SDIND SDFOC SDFIC SDINA TDI C SDFOD SCLKD SCLKC SDFIB SDFOA A D 2 3 NC IN0 TMS IN1 IN2 IN4 OUT3 VDDIO VDD VDDIO VDD VDDIO VDD OUT6 VDD GND GND GND GND VDDIO IN3 IN5 IN7 VDDIO GND GND GND GND VDD IN6 IN8 IN9 VDD GND GND GND GND VDDIO IN11 IN10 VDDIO GND GND GND GND VDD IN12 IN14 IN13 VDD VDDIO VDD VDDIO VDD VDDIO IN16 IN17 IN15 D4 D1 DTACK (RDY) MODE (ALE) D5 D3 D0 RW(WR) OUT5 OUT4 G OUT8 OUT7 H OUT9 OUT10 OUT10 J OUT11 OUT11 OUT13 OUT13 K OUT14 OUT14 OUT17 OUT17 L OUT16 OUT16 OUT15 OUT15 NC OUT12 OUT12 D7 QOUT N P NC OUT1 F M 14 TRST OUT0 OUT2 E D6 SYNC3 QIN D2 A1 RESET SYNC2 ­13­ A0 SYNC0 A2 DS(RD) NC = NO CONNECT REV. A 13 TCK 1 CS SYNC1 CLK NC AD6623 AD6623 196-LEAD 196-LEAD FUNCTION DESCRIPTIONS Mnemonic Type Function P P G 2.5 V Supply 3.3 V IO Supply Ground I/O I I I I I I I I I I I I A Input Data (Mantissa) When HIGH Indicates Q Input Data (Complex Input Mode) Active LOW Reset Pin Input Clock All Sync Pins Go to All Four Output Channels All Sync Pins Go to All Four Output Channels All Sync Pins Go to All Four Output Channels All Sync Pins Go to All Four Output Channels Serial Data Input-Channel A Serial Data Input-Channel B Serial Data Input-Channel C Serial Data Input-Channel D Active LOW Chip Select I/O I/O I/O I/O O O O O I I I I I Bidirectional Serial Clock-Channel A Bidirectional Serial Clock-Channel B Bidirectional Serial Clock-Channel C Bidirectional Serial Clock-Channel D Serial Data Frame Sync Output-Channel A Serial Data Frame Sync Output-Channel B Serial Data Frame Sync Output-Channel C Serial Data Frame Sync Output-Channel D Serial Data Frame Input-Channel A Serial Data Frame Input-Channel B Serial Data Frame Input-Channel C Serial Data Frame Input-Channel D Active High Output Enable Pin I/O/T I I O/T I I Bidirectional Microport Data Microport Address Bus Active Low Data Strobe (Active Low Read) Active Low Data Acknowledge (Microport Status Bit) Read Write (Active Low Write) Intel or Motorola Mode Select O O Wideband Output Data When HIGH Indicates Q Output Data (Complex Output Mode) I I I O/T I Test Reset Pin (Active Low) Test Clock Input Test Mode Select Input Test Data Output Test Data Input POWER SUPPLY VDD VDDIO GND INPUTS INOUT[17:0]1 QIN1 RESET2 CLK1 SYNC01 SYNC01 SYNC11 SYNC11 SYNC21 SYNC21 SYNC31 SYNC31 SDINA1 SDINB1 SDINC1 SDIND1 CS CONTROL SCLKA SCLKB SCLKC SCLKD SDFOA SDFOB SDFOC SDFOD SDFIA SDFIB SDFIC SDFID OEN1 MICROPORT CONTROL D[7:0] A[2:0] DS (RD) DTACK (RDY)2 RW (WR) MODE OUTPUTS OUT[17:0] QOUT JTAG AND BIST TRST2 TCK1 TMS2 TDO TDI1 NOTES 1 Pins with a Pull-Down resistor of nominal 70 k. 2 Pins with a Pull-Up resistors of nominal 70 k. ­14­ REV. A AD6623 AD6623 CONTROL REGISTER ADDRESS NOTATION Serial Slave Mode (SCS = 1) Register address notation and bit assignment referred to throughout this data sheet are as follows: There are eight, one-digit "External" register addresses in decimal format. "Internal" address notation (read from left to right) begins with "0x", meaning the address that follows is hexadecimal. The next three characters represent the address. The first number or character is the MSB of the address. If an "n" is present, its value can be 1, 2, 3, or 4 and it depends upon the channel that is being addressed (A, B, C, or D). The remaining two digits preceding the colon (if present) are the LSBs of the address. If a colon follows the address, then the succeeding digits tell the user what bit number(s) is/are involved in decimal format. For example, 0xn24:7-0. Any of the AD6623 AD6623 serial ports may be operated in the serial slave mode. In this mode, the selected AD6623 AD6623 channel requires that an external device such as a DSP to supply the SCLK. This is done to synchronize the serial port to meet an external timing requirement. SDIN is captured on negative edge of SCLK when in slave mode. Serial Data Framing The SDIN input pin of each transmit channel of the AD6623 AD6623 receives data from an external DSP to be digitally filtered, interpolated, and then modulated by the NCO-generated carrier. Serial data from the DSP to the AD6623 AD6623 is sent as a series of blocks or frames. The length of each block is a function of the desired output format that is supported by the AD6623 AD6623. Block length may range from 1 bit (MSK) to 32 bits of I and Q data. SERIAL DATA PORT The AD6623 AD6623 has four independent Serial Ports (A, B, C, and D), and each accepts data to its own channel (A, B, C, or D) of the device. Each Serial Port has four pins: SCLK (Serial CLocK), SDFO (Serial Data Frame Out), SDFI (Serial Data Frame In), and SDIN (Serial Data INput). SDFI and SDIN are inputs, SDFO is an output, and SCLK is either input or output depending on the state of SCS (Serial Clock Slave: 0xn16, Bit 4). Each channel can be operated either as a Master or Slave channel depending upon SCS. The Serial Port can be self-framing or accept external framing from the SFDI pin or from the previous adjacent channel (0xn16, Bits 7 and 6). The flow of data to the SDIN input is regulated either by the AD6623 AD6623 (in Self-Framing Mode) or by the external DSP (using AD6623 AD6623 External Framing Mode). This is accomplished by generating a pulse, SDFO or SDFI, to indicate that the next frame or serial data block is ready to be input or sent to the AD6623 AD6623. Functions of the two pins, SDFO and SDFI, are fully described in the framing modes that follow. Self-Framing Mode In this mode Bit 7 of register 0xn16 is set low. The serial data frame output, SDFO, generates a self-framing data request and is pulsed high for one SCLK cycle at the input sample rate. In this mode, the SDFI pin is not used, and the SDFO signal would be programmed to be a serial data frame request (0xn16, Bit 5 = 0). SDFO is used to provide a sync signal to the host. The input sample rate is determined by the CLK divided by channel interpolation factor. If the SCLK rate is not an integer multiple of the input sample rate, then the SDFO will continually adjust the period by one SCLK cycle to keep the average SDFO rate equal to the input sample rate. When the channel is in sleep mode, SDFO is held low. The first SDFO is delayed by the channel reset latency after the Channel Reset is removed. The channel reset latency varies dependent on channel configuration. Serial Master Mode (SCS = 0) In master mode, SCLK is created by a programmable internal counter that divides CLK. When the channel is "sleeping," SCLK is held low. SCLK becomes active on the first rising edge of CLK after Channel sleep is removed (D0 through D3 of external address 4). Once active, the SCLK frequency is determined by the CLK frequency and the SCLK divider, according to the equations below. AD6623 AD6623 mode: fSCLK = fCLK SCLKdivider + 1 (1) External Framing Mode AD6622 AD6622 mode: fSCLK = fCLK 2 × (SCLKdivider + 1) (2) The SCLK divider is a 5-bit unsigned value located at Internal Channel Address 0xn0D (Bits 4­0), where "n" is 1, 2, 3, or 4 for the chosen channel A, B, C, or D, respectively. The user must select the SCLK divider to insure that SCLK is fast enough to accept full input sample words at the input sample rate. See the design example at the end of this section. The maximum SCLK frequency is equal to the CLK when operating in AD6623 AD6623 mode serial clock master. When operating in AD6622 AD6622 compatible mode, the maximum SCLK frequency is one-half the CLK. The minimum SCLK frequency is 1/32 of the CLK frequency in AD6623 AD6623 mode or 1/64 of the CLK frequency when in AD6622 AD6622 mode. SDFO changes on the positive edge of SCLK when in master mode. SDIN is captured on positive edge when SCLK is in master mode. REV. A In this mode Bit 7 of register 0xn16 is set high. The external framing can come from either the SDFI pin (0xn16, Bit 6 = 0) or the previous adjacent channel (0xn16, Bit 6 = 1). In the case of external framing from a previous channel, it uses the internal frame end signal for serial data frame synchronizing. When in master mode, SDFO and SDFI transition on the positive edge of SCLK, and SDIN is captured on the positive edge of SCLK. When in slave mode, SDFO and SDFI transition on the negative edge of SCLK, and SDIN is captured on the negative edge of SCLK. Serial Port Cascade Configuration In this case the SDFO signal from the last channel of the first chip would be programmed to be a serial data frame end (SFE:0xn16, Bit 5 = 1). This SDFO signal would then be fed as an input for the second cascaded chip's SDFI pin input. The second chip would be programmed to accept external framing from the SDFI pin (0xn16, Bit 7 = 1, Bit 6 = 0). ­15­ AD6623 AD6623 Serial Data Format The format of data applied to the serial port is determined by the RCF mode selected in Control Register 0xn0C. Below is a table showing the RCF modes and input data format that it sets. Table I. Serial Data Format 0xn0C 0xn0C Bit 6 Bit 5 0xn0C Bit 4 Serial Data Word Length RCF Mode 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 32 1 1 1 0 1 1 1 0 1 FIR /4-DQPSK GMSK MSK FIR, compact 8-PSK 3/8-8-PSK QPSK 24 (Bit 9 is high) 16 (Bit 9 is low) See Table II for usable SCLK divider values and the corresponding SCLK and fSCLK/fSDFO ratio for the example of L = 2560. In conclusion, SDFO rate is determined by the AD6623 AD6623 CLK rate and the interpolation rate of the channel. The SDFO rate is equal to the channel input rate. The channel interpolation is equal to RCF interpolation times CIC5 interpolation, times CIC2 interpolation: LCRIC 2 L = LRCF × LCIC 5 × MCRIC 2 The SCLK divide ratio is determined by SCLKdivider as shown in equation 3. The SCLK must be fast enough to input 32 bits of data prior to the next SDFO. Extra SCLKs are ignored by the serial port. Table II. Example of Usable SCLK Divider Values and fSCLK/fSDFO Ratios for L = 2560 SCLKdivider fSCLK/fSDFO The serial data input, SDIN, accepts 32-bit words as channel input data. The 32-bit word is interpreted as two 16-bit two's complement quadrature words, I followed by Q, MSB first. This results in linear I and Q data being provided to the RCF. The first bit is shifted into the serial port starting on the next rising edge of SCLK after the SDFO pulse. Figure 16 shows a timing diagram for SCLK master (SCS = 0) and SDFO set for frame request (SFE = 0). 0 1 3 4 7 9 15 19 31 CLK tSSDI0 2560 1280 640 512 320 256 160 128 80 PROGRAMMABLE RAM COEFFICIENT FILTER (RCF) SCLK Each channel has a fully independent RAM Coefficient Filter (RCF). The RCF accepts data from the Serial Port, processes it, and passes the resultant I and Q data to the CIC filter. A variety of processing options may be selected individually or in combination, including PSK and MSK modulation, FIR filtering, all-pass phase equalization, and scaling with arbitrary ramping. See Table III. CLKn tDSDFO0A SDFO tSSDI0 SDI (4) tHSDI0 DATAn Figure 16. Serial Port Switching Characteristics Table III. Data Format Processing Options As an example of the Serial Port operation, consider a CLK frequency of 62.208 MHz and a channel interpolation of 2560. In that case, the input sample rate is 24.3 kSPS (62.208 MHz/2560), which is also the SDFO rate. Substituting, fSCLK 32 3 fSDFO into the equation and solving for SCLKdivider, we find the minimum value for SCLKdivider according to the equation below. fCLK (3) 32 × f SDFO Evaluating this equation for our example, SCLKdivider must be less than or equal to 79. Since the SCLKdivider channel register is a 5-bit unsigned number it can only range from 0 to 31. Any value in that range will be valid for this example, but if it is important that the SDFO period is constant, then there is another restriction. For regular frames, the ratio fSCLK/fSDFO must be equal to an integer of 32 or larger. For this example, constant SDFO periods can only be achieved with an SCLK divider of 31 or less. Processing Block Input Data Output Data Interpolating FIR Filter PSK Modulator I and Q 2 or 3 bits per symbol I and Q SCLKdivider MSK Modulator 1 bit per symbol QPSK 2 bits per symbol All-pass Phase Equalizer Scale and Ramp I and Q I and Q ­16­ Unfiltered I and Q: /4-QPSK, 8-PSK, or 3/8-8-PSK Filtered MSK or GSM I and Q Filtered QPSK I and Q I and Q I and Q REV. A AD6623 AD6623 OVERVIEW OF THE RCF BLOCKS throughput and decreased power consumption compared to Interpolating FIR Filter. In addition, the Interpolating MSK Modulator can realize filters with nonlinear inter-symbol interference, achieving excellent accuracy for GMSK applications. The Serial Port passes data to the RCF with the appropriate format and bit precision for each RCF configuration, see Figure 17. The data may be modulated vectors or unmodulated bits. I and Q vectors are sent directly to the Interpolating Fir Filter. Unmodulated bits may be sent to the PSK Modulator, the Interpolating MSK Modulator, or the Interpolating QPSK Modulator. The PSK Modulator produces unfiltered I and Q vectors at the symbol rate which are then passed through the Interpolating FIR Filter. The Interpolating MSK Modulator and the Interpolating QPSK Modulator produce oversampled, pulse-shaped vectors directly without employing the Interpolating FIR Filter. When possible, the MSK and QPSK modulators are recommended for increased 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 After interpolation, an optional Allpass Phase Equalizer (APE) can be inserted into the signal path. The APE can realize any real, stable, two-pole, two-zero all-pass filter at the RCF's interpolated rate. This is especially useful to precompensate for nonlinear phase responses of receive filters in terminals, as specified by IS-95 IS-95. When active, the APE utilizes shared hardware with the interpolating modulators and filter, which may reduce the allowed RCF throughput, inter-symbol interference, or both. See Figure 18. 14 13 12 11 10 < MSB, I, LSB > 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 < MSB, I, LSB > 15 14 13 12 11 10 9 8 < MSB, I, LSB > 7 6 5 4 < MSB, Q, LSB > 7 6 9 8 7 6 5 4 < MSB, Q, LSB > 5 4 3 2 < MSB, Q, LSB > 4 3 2 1 0 S D1 D2 D0 3 2 1 0 BIT SERIAL SYNC M S X D1 D0 QPSK RAMP 1 0 1 0 BIT FIR BIT COMPACT FIR BIT COMPACT FIR 8PSK 4 0 2 2 BIT M 1 3 3 4 3 2 1 0 BIT M S X X D0 These three formats are available only when SERIAL TIME SLOT SYNC ENABLE cont. reg. 0xn16:2 = 1 and ignored in FIR Mode MSK/GSM 2 1 0 BIT 0 D1 D0 8PSK 1 0 D1 D0 BIT QPSK 0 BIT D0 These three formats are available only when SERIAL TIME SLOT SYNC ENABLE cont. reg. 0xn16:2 = 0 and ignored in FIR Mode MSK/GSM M = mode bit. If M = 0, then the MSB of 3-bit mode select word at 0xn0C:6 is set to 0 (this is also called MODE 0). If M = 1, then the MSB is set to 1 and this is MODE 1. Mode allows quick format changes via the serial port, for example, 010 = GMSK and 110 = 3pi/8PSK. The value m should be held for the duration of the time slot since the value of m will only be updated after the RCF Scale Holdoff Counter reaches a value of 1 (see below). S = serial time slot sync bit. If S = 0, then no sync is generated. If S = 1, a "Serial Time Slot Sync" occurs that loads the RCF Scale Hold-off Counter with a user programmed value and commences a backwards count of CLK cycles. When the counter reaches one, an automatic sequence occurs as follows: Power Ramp Down occurs, m (above) is updated, serial input is suspended for a REST or QUIET time and any control register with a 2 superscript is updated. After REST, the serial input becomes active and the power level is ramped up to the Fine Scale multiplier value or any lesser power level. Ramp enable bit, 0xn16:0, must be set to logic 1 for the ramp functions to occur. See the RCF Power Ramping and Time Slot Synchronization sections for more detail. X = don't care D = payload data bit Important notes: The sync pulse, s, should be held at Logic 1 for only one serial frame since every frame with Logic 1 in the s position will cause the RCF Scale Hold-off Counter to reload its beginning count and begin counting again. The RCF Scale Hold-off Counter counts master CLK cycles. The REST time period is a programmable 5-bit value that counts interpolated RCF output samples before resuming serial input to the channel. The succeeding actions of any hold-off counter in the AD6623 AD6623 can be defeated by setting its count value to 0. Figure 17. Data Formats Supported by the AD6623 AD6623 when SCLK Master (SCS = 0), and SFDO Set for Frame Request (SFE = 0) REV. A ­17­ AD6623 AD6623 INTERPOLATING FIR FILTER PSK MODULATOR INTERPOLATING MSK MODULATOR SCALE AND RAMP ALLPASS PHASE EQUALIZER DATA FROM SERIAL PORT DATA TO CIC FILTERS INTERPOLATING QPSK MODULATOR Figure 18. RCF Block Diagram Table IV. FIR Filter Internal Precision Signal x y Notation Decimal I and Q Inputs Coefficients Product Sum FIR Output 1.15 1.15 2.18 4.18 1.17 ­1.00000 ­1.00000 ­0.99969 ­7.00000 ­1.00000 Minimum Hexadecimal (h) Decimal 0.999969 0.999969 1.000000 7.999996 0.999992 +1.00000 +1.00000 +3.00020 +8.00000 +1.00000 The Scale and Ramp block adjusts the final magnitude of the modulated RCF output. A synchronization pulse from the SYNC0­3 pins or serial words can be used to command this block to ramp down, pause, and ramp up to a new scale factor. The shape of the ramp is stored in RAM, allowing complete sample by sample control at the RCF interpolated rate. This is particularly useful for time division multiplexed standards such as GSM/EDGE. Modulator configurations can be updated while the ramp is quiet, allowing for GSM and EDGE timeslots to be multiplexed together without resetting or reconfiguring the channel. Each of the RCF processing blocks is discussed in greater detail in the following sections. DMEM 3216 Maximum Hexadecimal (h) 0.FFFE 0.FFFE 1.00000 7.FFFFC 0.FFFF8 INPUT 1.15 ACCUMULATOR 4.18 INPUT 1.15 CMEM 25616 COEF 1.15 PRODUCT 2.18 OUTPUT 1.17 20, 2­1, 2­2, OR 2­3 Figure 19. Interpolating FIR Filter Block Diagram INTERPOLATING FIR FILTER The Interpolating FIR Filter realizes a real, sum-of-products filter on I and Q inputs using a single interleaved Multiply-Accumulator (MAC) running at the CLK rate. The input signal is interpolated by integer factors to produce arbitrary impulse responses up to 256 output samples long. Each bus in the data path carries bipolar two's complement values. For the purpose of discussion, we will arbitrarily consider the radix point positioned so that the input data ranges from ­1 to just below 1. In Figure 19, the data buses are marked x × y to denote finite precision limitations. A bus marked x × y has x bits above the radix and y bits below the radix, which implies a range from ­2x­1 to 2x­1 ­ 2­y in 2­y steps. The range limits are tabulated in Table IV for each bus. The hexadecimal values are bit-exact and each MSB has negative weight. Note that the Product bus range is limited by result of the multiplication and the two most significant bits are the same except in one case. The RCF realizes a FIR filter with optional interpolation. The FIR filter can produce impulse responses up to 256 output samples long. The FIR response may be interpolated up to a factor of 256, although the best filter performance is usually achieved when the RCF interpolation factor (LRCF) is confined to eight or below. The 256 × 16 coefficient memory (CMEM) can be divided among an arbitrary number of filters, one of which is selected by the Coefficient Offset Pointer (channel address 0x0B). The polyphase implementation is an efficient equivalent to an integer up-sampler followed FIR filter running at the interpolated rate. The AD6623 AD6623 RCF realizes a sum-of-products filter using a polyphase implementation. This mode is equivalent to an interpolator followed by a FIR filter running at the interpolated rate. In the functional diagram below, the interpolating block increases the rate by the RCF interpolation factor (LRCF) by inserting LRCF­1 zero valued samples between every input sample. The next block is a filter with a finite impulse response length (NRCF) and an impulse response of h[n], where n is an integer from 0 to NRCF­1. The difference equation for Figure 20 is written below, where h[n] is the RCF impulse response, b[n] is the interpolated input sample sequence at point `b' in the diagram above, and c[n] is the output sample sequence at point `c' in Figure 20. ­18­ REV. A AD6623 AD6623 fIN fIN LRCF LRCF a b NRCFTAP FIR FILTER h[n] The Coef-Mem stores up to 256 16-bit filter coefficients. The CoefMem can be accessed through the Microport from 0x800 to 0x8FF above the processing channel's base internal address, while the channel's Prog bit is set (external address 4). For AD6622 AD6622 compatibility, the lower 128 words are also mirrored from 0x080 to 0x0FF above the processing channel's base internal address, while the Prog bit is set. fIN LRCF c Figure 20. RCF Interpolation [] c n = N RCF ­ 1 k=0 [] [ ] h n ×b n­k (5) This difference equation can be described by the transfer function from point `b' to `c' as: H bc ( z ) = N RCF ­ 1 k=0 [] h n × z ­1 (6) The actual implementation of this filter uses a polyphase decomposition to skip the multiply-accumulates when b[n­k] is zero. Compared to the diagram above, this implementation has the benefits of reducing by a factor of LRCF both the time needed to calculate an output and the required data memory (DMEM). The price of these benefits is that the user must place the coefficients into the coefficient memory (CMEM) indexed by the interpolation phase. The process of selecting the coefficients and placing them into the CMEM is broken into three steps shown below. The FIR accepts two's complement I and Q samples from the serial port with a fixed-point resolution of 16 bits each. When the serial port provides data with less precision, the LSBs are padded with zeroes. The Data-Mem stores the most recent 16 I and Q pairs for a total of 32 words. The size of the Data-Mem limits the RCF impulse response to 16 LRCF output samples. When the data words from the Serial Port have fewer than 16 bits, the LSBs are padded with zeroes. The Data-Mem can be accessed through the Microport from 0x20 to 0x5F above the processing channel's base internal address, while the channel's Prog bit is set (external address 4). In order to avoid start-up transients, the Data-Mem should be cleared before operation. The Prog bit must then be reset to enable normal operation. REV. A There is a single Multiply-Accumulator (MAC) on which both the I and Q operations must be interleaved. Two CLK cycles are required for the MAC to multiply each coefficient by an I and Q pair. The MAC is also used for four additional CLK cycles if the All-pass Phase Equalizer is active. The size of the Data-Mem and Coef-Mem combined with the speed of the MAC determine the total number of the taps per phase (TRCF) that may be calculated. TRCF is the number of RCF input samples that influence each RCF output sample. The maximum available TRCF is calculated by the equation below. 256 fCLK TRCF least of 16 , floor ­ 2 × APE (7) , floor 2 × f LRCF SDFO Where APE = 1 (allpass phase equalizer enabled) or 0 (allpass phase equalizer disabled) and fSDFO = [Output Data Rate/Total Interpolation Rate] in Hz. "floor()" indicates that the value within the parenthesis should be reduced to the lowest integer, e.g., floor(9.9999) = 9. The impulse response length at the output of the RCF is determined by the product of the number of interfering input samples (TRCF) and the RCF interpolation factor (LRCF), as shown by equation (8) below. The values of NRCF and TRCF are programmed into control registers. LRCF is not a control register, but NRCF and TRCF must be set so that LRCF is an integer. If the integer interpolation by the RCF results in an inconvenient sample rate at the output of the RCF, the desired output rate can usually be achieved by selecting non-integer interpolation in the resampling CIC2 filter. N RCF = TRCF × LRCF ­19­ (8) AD6623 AD6623 Table V. Channel A RCF Control Registers Channel Address Bit Width 0x10A 0x10B 0x10C 16 8 10 0x10D 8 0x10E 16 0x10F 18 0x110 0x111 0x112 0x113 0x114 0x115 0x116 16 16 16 16 16 16 8 Channel Address Description 15­8: NRCF ­1 B; 7­0: NRCF ­1 A 7­0: ORCF 9: Ch. A Compact FIR Input Word Length 0: 16 bits­8 I followed by 8 Q 1: 24 bits­12 I followed by 12 Q 8: Ch. A RCF PRBS Enable 7: Ch A RCF PRBS Length 0: 15 1: 8,388,607 6­4: Ch. A RCF Mode Select 000 = FIR 001 = /4-DQPSK Modulator 010 = GMSK Look-Up Table 011 = MSK Look-Up Table 100 = FIR compact mode 101 = 8-PSK 110 = 3/8-8PSK Modulator 111 = QPSK Look-Up Table 3­0: Ch. A RCF Taps per Phase 7­6: RCF Coarse Scale (g): 00 = 0 dB 01 = ­6 dB 10 = ­12 dB 11 = ­18 dB 5: Ch. A Allpass Ph. Eq. Enable 4­0: Serial Clock Divider (1, ., 32) 15­2: Ch. A Unsigned Scale Factor 1­0: Reserved 17­16: Ch. A Time Slot Sync Select 00: Sync0 (See 0x001 Time Slot) 01: Sync1 10: Sync2 11: Sync3 15­0: Ch. A RCF Scale Hold-Off Counter 1) Ramp Down (if Ramp is enabled) 2) Update Scale and Mode 3) Ramp Up (if Ramp is enabled) 15­0: Ch. A RCF Phase EQ Coef1 15­0: Ch. A RCF Phase EQ Coef2 15­0: Ch. A RCF MPSK Magnitude 0 15­0: Ch. A RCF MPSK Magnitude 1 15­0: Ch. A RCF MPSK Magnitude 2 15­0: Ch. A RCF MPSK Magnitude 3 7: Reserved 6: Ch. A Serial Data Frame Select 0: Serial Data Frame Request 1: Serial Data Frame End 0x117 0x118 0x119 0x11A­0x11F 0x120­0x13F 0x140­0x17F Bit Width Description 6 6 5 16 16 0x180­0x1FF 16 5: Ch. A External SDFI Select 0: Internal SDFI 1: External SDFI 4: Ch. A SCLK Slave Select 0: Master 1: Slave 3: Ch. A Serial Fine Scale Enable 2: Ch. A Serial Time Slot Sync Enable (ignored in FIR mode) 1: Ch. A Ramp Interpolation Enable 0: Ch. A Ramp Enable 5­0: Ch. A Mode 0 Ramp Length, R0­1 5­0: Ch. A Mode 1 Ramp Length, R1­1 4­0: Ch. A Ramp Rest Time, Q Reserved 15­0: Ch. A Data Memory 15­14: Reserved 13­0: Ch. A Power Ramp Memory 15­0: Ch. A Coefficient Memory This address is mirrored at 0x900­0x97F and contiguously extended at 0x980­0x9FF PSK MODULATOR The PSK Modulator is an AD6623 AD6623 extension feature that is only available when the control register bit 0x000:7 is high. The PSK Modulator creates 32-bit complex inputs to the Interpolating FIR Filter from two or three data bits captured by the serial port. The FIR Filter operates exactly as if the 32bit word came directly from the serial port. There are three PSK modulation options to choose from: /4-DQPSK, 8-PSK, and 3/8-8-PSK. Every symbol of any of these modulations can be represented by one of the 16 phases shown in Figure 21. ­20­ 0 Figure 21. 16-Phase Modulations REV. A AD6623 AD6623 All of these phase locations are represented in rectangular coordinates by only four unique magnitudes in the positive and negative directions. These four values are read from four channel registers that are programmed according to the following table, which gives the generic formulas and a specific example. The example is notable because it is only 0.046 dB below full-scale and the 16-bit quantization is so benign at that magnitude, that the rms error is better than ­122 dBc. It is also worth noting that because none of the phases are aligned with the axes, magnitudes slightly beyond 0.16 dB above full-scale are achievable. SERIAL QPSK MAPPER [1:0] SPH PHASE [3:0] [3:0] RPH [3:0] 2 Figure 22. QPSK Mapper The Sph word is calculated by the QPSK Mapper according to the following truth table. Table VI. Program Registers Table VIII. QPSK Mapper Truth Table Channel Register Magnitude M Magnitude E 0x7F53 Serial [1:0] Sph [3:0] 0x12 0x13 0x14 0x15 M 3 cos(/16) M 3 cos(3/16) M 3 cos(5/16) M 3 cos(7/16) 0x7CE1 0x69DE 0x46BD 0x18D7 00b 01b 11b 10b 0 4 8 12 Using the four channel registers from the preceding table, the PSK Modulator assembles the 16 phases according to Table VII. Table VII. PSK Modulator Phase Phase I Value Q Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x12 0x13 0x14 0x15 ­0x15 ­0x14 ­0x13 ­0x12 ­0x12 ­0x13 ­0x14 ­0x15 +0x15 +0x14 +0x13 +0x12 0x15 0x14 0x13 0x12 +0x12 +0x13 +0x14 +0x15 ­0x15 ­0x14 ­0x13 ­0x12 ­0x12 ­0x13 ­0x14 ­0x15 8-PSK Modulation IS-136 IS-136+ compliant 8-PSK modulation is selected by setting the channel register 0xn0C: 6­4 to 101b. The Phase word is calculated according to the following diagram. The three LSBs of the serial input word update the payload bits once per symbol. SERIAL [2:0] IS-136 IS-136 compliant /4-DQPSK modulation is selected by setting the channel register 0xn0C: 6­4 to 001b. The phase word is calculated according to the following diagram. The two LSBs of the serial input word update the payload bits once per symbol. The QPSK Mapper creates a data dependent static phase word (Sph) which is added to a time dependent rotating phase word (Rph). The Rph starts at zero when the RCF is reset or switches modes via a sync pulse. Otherwise, the Rph increments by two on every symbol. REV. A PHASE [3:0] Figure 23. 8-PSK Mapper The Phase word is calculated by the 8-PSK Mapper according to the following truth table: Table IX. 8-PSK Mapper Truth Table Serial [2:0] Sph [3:0] 111b 011b 010b 000b 001b 101b 100b 110b The following three sections show how the phase values are created for each PSK modulation mode. /4-DQPSK Modulation 8-PSK MAPPER 0 2 4 6 8 10 12 14 3/8-8-PSK Modulation EDGE compliant 3/8-8-PSK modulation is selected by setting the channel register 0xn0C: 6­4 to 110b. The phase word is calculated according to the following diagram. The three LSBs of the serial input word update the payload bits once per symbol. The 8-PSK Mapper creates a data-dependent static phase word (Sph) which is added to a time-dependent rotating phase word (Rph). The 8-PSK Mapper operates exactly as described in the preceding 8-PSK Modulation section. The Rph starts at zero when the RCF is reset or switches modes via a sync pulse. Otherwise, the Rph increments by three on every symbol. ­21­ AD6623 AD6623 SERIAL 8-PSK MAPPER [2:0] SPH [3:0] Table X. Coefficient Weights PHASE [3:0] Register Value 3 Figure 24. 3 /8-8-PSK Mapper MSK Look-Up Table The MSK Look-Up Table mode for the RCF is selected in Control Register 0xn0C. In the MSK Mode, the RCF performs arbitrary pulse-shaping based on four symbols of impulse response. For the MSK Mode, the serial input format is 1 bit of data. Coefficient Weight 0x7FFF . 0x0001 0x0000 0xFFFF . 0x8001 0x8000 RPH [3:0] +1.999938964844 QPSK Look-Up Table The QPSK Filter mode for the RCF is selected in Control Register 0xn0C. In the QPSK Mode, the RCF performs baseband linear pulse-shaping based on filter impulse response up to 12 symbols. For the QPSK Mode, the serial input format is 1 Bit I followed by 1 Bit Q. PHASE EQUALIZER The IS-95 IS-95 Standard includes a phase equalizer after matched filtering at the baseband transmit side of a base station. This filter pre-distorts the transmitted signal at the base station in order to compensate for the distortion introduced to the received signal by the analog baseband filtering in a handset. The AD6623 AD6623 includes this functionality in the form of an Infinite Impulse Response (IIR) all-pass filter in the RCF. This Phase Equalizer pre-distort filter has the following transfer function: H( z ) = X(z) Y ( z ) 1 + b1z + b2z 2 = X ( z ) z 2 + b1z + b2 Z­1 (9) b2 Z­1 Table XI. b1 and b2 Coefficients Oversampling b0 1 2 3 4 5 6 7 8 1 1 1 1 1 1 1 1 b1 ­0.25421 ­0.96075 ­1.28210 ­1.45514 ­1.56195 ­1.63409 ­1.68604 ­1.72516 (0.efbbh) (0.c283h) (0.adf2h) (0.a2dfh) (0.9c09h) (0.976bh) (0.9418h) (0.9197h) b2 +0.11188 +0.33447 +0.48181 +0.57831 +0.64526 +0.69415 +0.73132 +0.76050 (0.0729h) (0.1568h) (0.1ed6h) (0.2503h) (0.294ch) (0.2c6dh) (0.2eceh) (0.30ach) FINE SCALE AND POWER RAMP Fine Scale multiplier factors in the range [0, 2) with a step resolution of 2­16. Power Ramp multiplier factors in the range [0, 1) with a step resolution of 2­14. FINE SCALING Fine Scale multiplier factors range from [0, 2) with a step resolution of 2­15 in the AD6622 AD6622 emulation mode and 2­16 in the AD6623 AD6623 emulation mode. Scaling values for each channel are programmed at register 0xn0E in the AD6623 AD6623 internal memory using the Microport interface. RCF POWER RAMPING Z­1 b1 Z­1 ­1.999938964844 ­2 Table XI shows the recommended b1 and b2 coefficients for the respective oversampling rate. GMSK Look-Up Table The GMSK Look-Up Table mode for the RCF is selected in Control Register 0xn0C. In the GMSK Mode, the RCF performs arbitrary pulse-shaping based on four symbols of impulse response. For the GMSK Mode, the serial input format is 1 Bit of data. +0.00006103515625 0 ­0.00006103515625 Y(z) Figure 25. Second Order All-Pass IIR Filter The Allpass Phase Equalizer (APE) is enabled (logic 1) or disabled (logic 0) in Control Register 0xn0D:5. The value of Bit 5 then becomes the value of the APE term in Equation 7. The coefficients b1 and b2 are located in Control Registers 0xn10 and 0xn11 respectively. The format for b1 and b2 is two's complement fractional binary with a range of [­2, 2). With one bit for sign at most significant bit position there are 15 bits for magnitude. The value of one bit is (2 ­15) × 2, or 0.00006103515625. The register values, in hexadecimal, and the corresponding coefficient weight from positive full-scale through zero to negative full-scale is illustrated in Table X. When the output of the AD6623 AD6623 is programmed to be a rapid series of on/off bursts of data, the DAC used to produce an analog output signal will produce undesirable spectral components that should (or must) be suppressed. Shaping or "ramping" the transition from no power to full power, and vice versa, reduces the amplitude of these spurious signals. To program the ramp function a user must provide, through the Microport, the ramp memory (RMEM) coefficient values (up to 64), number of RMEM coefficients to "construct" the ramp (1 to 64) and selection of a synchronizing signal source as discussed below. The programmable power ramp up/down unit allows power ramping on time-slot basis as specified for some wireless transmission technologies (e.g. TDMA). The shape of the ramp is stored in RAM. The RAM coefficients (RMEM) allow complete sample-by-sample control at the RCF interpolated rate. This is particularly useful for time division multiplexed standards such as GSM/EDGE. A time slot or "burst" is ramped-up and down by multiplying the Fine Scaled output of the RCF by a series of up to 64 ramp coefficients. If more ramp resolution is required, up to 64 interpolated coefficients can be added if the Ramp Interpolation bit, 0xn16:1, is set to ­22­ REV. A AD6623 AD6623 Logic 1. This extends the maximum ramp length to 128 coefficients. Although the ramp is limited in length, its time duration is a function of the output sample rate of the RCF multiplied by the ramp length. Ramp duration is twice as long with Ramp Interpolation enabled than when it is not enabled. The channel's Ramp Enable bit at control register address 0xn16: bit 0, must be set to Logic 1 or else the ramp function will be bypassed and the RCF output data is passed unaltered to the CIC interpolation stages. When in use, the maximum signal gain is dependent on what value is stored in the last valid RMEM (ramp memory) location. RMEM words are 14-bits with a range of [0-1). When the ramp is triggered, the following sequence occurs (see Figures 26 and 27): RAMP-DOWN beginning at the last coefficient of the specified ramp length and proceeding, sample-by-sample, to the first coefficient. Next, a REST or quiet period (from 0 to 32 RCF output samples duration) occurs. During this time, the Mode bit (as shown in Figure 17, AD6623 AD6623 Data Format and Bit Definition chart) is updated, input sampling is halted and any control register with a superscript 2 is updated. Modulator configurations can be updated while the ramp is "quiet" allowing for GSM and EDGE timeslots to be multiplexed without resetting or reconfiguring the channel. Lastly, RAMP-UP occurs beginning at the first coefficient and ending at the last coefficient of the specified length. The final output level from the ramp stage is equal to the RCF Fine Scale output level multiplied by the last ramp coefficient. Figure 26. View of an unmodulated carrier with linear ramp-down and ramp-up and rest time between ramps set to 0. Ramp Triggering The ramp sequence is triggered by the Fine Scale Hold-Off counter. The counter is loaded with a 16-bit user-specified value (>1 and