AD6600 20MSPS AD6620 AD6630 IS-136 AD6600AST 13MSPS AD6600ST/PCB ST-44 AN501 - Datasheet Archive

 

ADC with RSSI a PRELIMINARY TECHNICAL DATA FEATURES Dual "IF" Inputs, 70-250 MHz Diversity or two independent IF

 

Dual Channel, Gain-Ranging ADC with RSSI a PRELIMINARY TECHNICAL DATA FEATURES Dual "IF" Inputs, 70-250 MHz Diversity or two independent IF signals Separate Attenuation Paths Oversample RF Channels 20 MSPS on a Single Carrier 10 MSPS/channel in Diversity Mode Total Signal Range 90+ dB 30 dB from Automatic Gain-Ranging (AGC) 60 dB from A/D Converter Range >100 dB after Processing Gain Digital Outputs 11-Bit ADC Word 3-Bit RSSI Word 2X Clock, A/B Indicator Single +5V Power Supply Output DVCC +3.3V or +5V 775mW Power Dissipation AD6600 AD6600 by an 11-bit, 20MSPS 20MSPS analog-to-digital converter. Digital RSSI outputs, an A/B channel indicator, a 2X Clock output, references, and control circuitry are all on-chip. Digital output signals are twos complement, CMOS-compatible and interface directly to +3.3V or +5V digital processing chips. The primary use for the dual analog input structure is sampling both antennas in a two-antenna diversity receiver. However channels A and B may also be used to sample two, independent IF signals. Diversity, or dual-channel mode, is limited to 10 MSPS per channel. In single channel mode, the full clock rate of 20 MSPS may be applied to a single carrier. The AD6600 AD6600 may be used as a stand-alone sampling chip, or it may be combined with the AD6620 AD6620 Digital Receive Signal Processor. The AD6620 AD6620 provides 10-25dB of additional processing gain before passing data to a fixed or floating point DSP. APPLICATIONS Communications Receivers PCS/Cellular Base Stations GSM, CDMA, TDMA Wireless Local Loop, Fixed Access Driving the AD6600 AD6600 is simplified by using the AD6630 AD6630, differential IF amplifier. The AD6630 AD6630 is easily matched to inexpensive SAW filters from 70 to 250 MHz. Designed specifically for cellular/PCS receivers, the AD6600 AD6600 supports GSM, IS-136 IS-136, CDMA, Wireless LANs, as well as proprietary air interfaces used in WLL/fixed access systems. PRODUCT DESCRIPTION The AD6600 AD6600 mixed-signal receiver chip directly samples signals at analog input frequencies up to 250 MHz. The device includes two input channels, each with 1GHz input amplifiers and 30dB of automatic gain-ranging circuitry. Both channels are sampled with a 450MHz track-and-hold followed Units are available in plastic, surface-mount packages (44-pin TQFP) and specified over the industrial temperature range (-40°C to +85°C). NOISE FILTER FLT FLT 0, -12, -24 dB 630 RESONANT PORT AIN ATTEN AIN AB_OUT DETECT PEAK 3 SET RSSI RSSI GAIN ANALOG MUX GAIN +12, +18 dB Encode A/D CONVERTER GAIN TWOS 11 COMPLEMENT 3 SELECT GAIN Encode RSSI D10 - D0 RSSI [2:0] BIN ATTEN BIN TIM ING CLK2X 0, -12, -24 dB A_SEL B_SEL AVCC GND ENC ENC DVCC FUNCTIONAL BLOCK DIAGRAM REV. PrA Analog Devices Specification Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringement of patents or other rights of third parities which may result from its use. No license is granted by implication or otherwise under any patent or rights of Analog Devices. Revcode:010699; AD6600 AD6600 Marketing Administrator: (781) 937-1480 AD6600 AD6600 ­ SPECIFICATIONS DC SPECIFICATIONS (AVCC = +5V, DVCC = +3.3V; TMIN = -40°C, TMAX = +85°C unless otherwise specified) ° ° Test AD6600AST AD6600AST Parameter Temp Level Min Typ Max Units ANALOG INPUTS (AIN, AIN / BIN, BIN ) Full V 2.0 VPP Differential Analog Input Voltage Range1 Full IV 160 200 240 Differential Analog Input Resistance2 +25°C V 1.5 pF Differential Analog Input Capacitance PEAK DETECTOR (internal), RSSI Resolution 3 Bits RSSI Gain Step Full V 6 dB RSSI Hysterisis3 Full V 6 dB RESONANT PORT (FLT, FLT ) Full V 630 Differential Port Resistance Full V 1.75 pF Differential Port Capacitance A/D CONVERTER Resolution Full IV 11 Bits ENCODE INPUTS (ENC, ENC ) Full IV 0.4 VPP Differential Input Voltage (ac-coupled)4 +25°C V 11 k Differential Input Resistance +25°C V 2.5 pF Differential Input Capacitance A/B MODE INPUTS (A_SEL, B_SEL)5 Input High Voltage Range Full IV 4.75 5.25 V Input Low Voltage Range Full IV 0.0 0.5 V POWER SUPPLY Supply Voltages Full II 4.75 5.0 5.25 V AVCC Full IV 3.0 3.3 5.25 V DVCC Supply Current I AVCC (AVCC = 5.0V) Full II 145 182 mA I DVCC (DVCC = 3.3V) Full II 15 20 mA POWER CONSUMPTION6 Full II 775 976 mW NOTES 1 Analog Input Range is a function of input frequency. See AC specifications for 70-250 MHz inputs. 2 Analog Input Impedance is a function of input frequency. See AC specifications for 70-450 MHz inputs. 3 Six dB of digital hysterisis is used to eliminate level uncertainty at the RSSI threshold points due to noise and amplitude variations. 4 Encode inputs should be ac-coupled and driven differentially. See "Encoding the AD6600 AD6600" for details. 5 A_SEL and B_SEL should be tied directly to ground or AVCC. 6 Maximum power consumption is computed as maximum current at nominal supplies. DIGITAL SPECIFICATIONS (AVCC = +5V, DVCC = +3.3V; TMIN = -40°C, TMAX = +85°C unless otherwise specified) Test AD6600AST AD6600AST Parameter (Conditions) Temp Level Min Typ Max LOGIC OUTPUTS (D10 - D0, AB_OUT, RSSI2-0)1 Logic Compatibility CMOS Logic "1" Voltage (DVCC = +3.3V) Full II 2.8 DVCC-0.2 Logic "0" Voltage (DVCC = +3.3V) Full II 0.2 0.5 Logic "1" Voltage (DVCC = +5.0V) Full IV 4.0 DVCC-0.35 Logic "0" Voltage (DVCC = +5.0V) Full IV 0.35 0.5 Output Coding (D10 - D0) Twos Complement CLK2X OUTPUT1,2 Logic "1" Voltage (DVCC = +3.3V) Full II 2.8 DVCC-0.2 Logic "0" Voltage (DVCC = +3.3V) Full II 0.2 0.5 Logic "1" Voltage (DVCC = +5.0V) Full IV 4.0 DVCC-0.3 Logic "0" Voltage (DVCC = +5.0V) Full IV 0.35 0.5 NOTES 1 Digital output load is one LCX gate. 2 CLK2X output voltage levels, high and low, tested at switching rate of 10MHz. REV. PrA -2- Units V V V V V V V V AD6600 AD6600 ­ SPECIFICATIONS TIMING REQUIREMENTS & SWITCHING SPECIFICATIONS1 (AVCC = +5V, DVCC = +3.3V; ENC & ENC = 20 MSPS; TMIN = -40°C, TMAX = +85°C unless otherwise specified) Test AD6600AST AD6600AST Parameter Name Temp Level Min Typ Max Units A/D CONVERTER fENC 1/(tENC) MSPS Conversion Rate 20 MSPS Maximum Conversion Rate Full II 6 MSPS Minimum Conversion Rate Full IV 0.3 psRMS Aperture Uncertainty tj V +25°C 2 ENCODE INPUTS (ENC, ENC ) tENC Full II 50 ns Period tENCH Full IV 20 ns Pulsewidth High3 tENCL Full IV 20 ns Pulsewidth Low4 2X CLOCK OUTPUT (CLK2X)5 Output Frequency 2*fENC V Full MSPS Output Period6 tCLK2X_1 V tENCL Full ns tCLK2X_2 V Full tENCH ns CLK2X Pulsewidth Low6 V tCLK2XL Full ns tENCH/2 Output Risetime8 V Full ns 3 Output Falltime8 V Full ns 2.6 OUTPUT RISE/FALL TIMES9 ns 8 V Full Output Risetime (D10:D0, RSSI2:0) ns 8.4 V Full Output Falltime (D10:D0, RSSI2:0) ns 6 V Full Output Risetime (AB_OUT) ns 6.2 V Full Output Falltime (AB_OUT) NOTES 1 See AD6600 AD6600 Timing Diagrams. 2 All switching specifications tested by driving ENC and ENC differentially. 3 Several timing specifications are a function of Encode high time, tENCH ; these specifications are shown in the data tables and timing diagrams. Encode duty cycle should kept as close to 50% as possible. 4 Encode pulse low directly affects the amount of settling time available at FLT resonant port. See "External Analog (Resonant) Filter" section for details. 5 The 2X Clock is generated internally, therefore some specifications are functions of encode period and duty cycle. All timing measurements to or from CLK2X are referenced to 2.0Vcrossing. 6 This specification IS a function of Encode period and duty cycle; reference timing diagrams Figure 8. 7 This specification IS NOT a function of Encode period and duty cycle. 8 Output rise time is measured from 20% point to 80% point of total CLK2X voltage swing; output fall time is measured from 80% point to 20% point of total CLK2X voltage swing. 9 Output rise time is measured from 20% point to 80% point of total data voltage swing; output fall time is measured from 80% point to 20% point of total data voltage swing. All outputs specified with 10pF load. REV. PrA -3- AD6600 AD6600 ­ SPECIFICATIONS TIMING REQUIREMENTS & SWITCHING SPECIFICATIONS cont.1 (AVCC = +5V, DVCC = +3.3V; ENC & ENC = 20 MSPS, Duty Cycle = 50%; TMIN = -40°C, TMAX = +85°C unless otherwise specified) Test AD6600AST AD6600AST Parameter Name Temp Level Min Typ Max Units ENCODE/CLK2X Encode Rising to CLK2X Falling6 tCF IV 6.5 8.0 9.5 ns Full Encode Rising to CLK2X Rising5 IV tCF + (tENCH)/2 ns tCR Full IV 25.7 27.2 28.7 ns @ Encode = 13MSPS 13MSPS, 50% Duty Cycle Full IV 19.0 20.5 22.0 ns @ Encode = 20MSPS 20MSPS, 50% Duty Cycle Full CLK2X/DATA (D10:0, RSSI2:0) CLK2X to DATA Rising Low Delay6 t2X_DRL 3.0 6.5 ns IV Full CLK2X to DATA Hold Time6 tH_D2X 3.0 6.5 ns IV Full 25°C CLK2X to DATA Falling Low6,8 10.0 15.0 20.0 ns t2X_DFL IV Full 11.0 15.5 22.0 ns IV Full CLK2X to DATA Setup Time5 tENCH - t2X_DFL ns IV tS_D2X Full @ Encode = 13MSPS 13MSPS, 50% Duty Cycle ns IV 16.5 23.0 25°C @ Encode = 20MSPS 20MSPS, 50% Duty Cycle8 ns IV 5.0 10.0 Full ns IV 3.0 9.5 CLK2X/AB_OUT ns 7.0 11.0 IV t2X_ARL Full CLK2X to AB_OUT Rising Low Delay6 ns 7.0 11.0 IV tH_A2X Full CLK2X to AB_OUT Hold Time6 25°C ns 12.0 18.0 23.0 IV t2X_AFL CLK2X to AB_OUT Falling Low Delay6,8 Full ns 10.7 19.0 26.0 IV Full ns tENCH - t2X_AFL IV tS_A2X CLK2X to AB_OUT Setup Time5 Full ns 12.5 19.5 IV @ Encode = 13MSPS 13MSPS, 50% Duty Cycle 25°C ns 2.0 7.0 IV @ Encode = 20MSPS 20MSPS, 50% Duty Cycle8 Full ns -1.0 6.0 IV ENCODE/DATA (D10:0, RSSI2:0) ns tCR + t2X_DRL IV Full tEN_DRL ENCODE to DATA Rising Low Delay5 ns tEN_DRL IV Full tH_DEN ENCODE to DATA Hold Time5 ns 28.7 33.7 IV Full @ Encode = 13MSPS 13MSPS, 50% Duty Cycle ns 22.0 27.0 IV Full @ Encode = 20MSPS 20MSPS, 50% Duty Cycle ns tCR + t2X_DFL IV Full tEN_DFL ENCODE to DATA Falling Low Delay5 Full ns tENC - tEN_DFL IV tS_DEN ENCODE to DATA Delay (Setup)5 Full ns 26.2 34.2 IV @ Encode = 13MSPS 13MSPS, 50% Duty Cycle 25°C ns 8.0 14.5 IV @ Encode = 20MSPS 20MSPS, 50% Duty Cycle8 Full ns 6.0 14.0 IV ENCODE/AB_OUT ENCODE to AB_OUT Rising Low Delay5 tEN_ARL Full IV tCR + t2X_ARL ns ENCODE to AB_OUT Delay (Hold)5 tH_AEN Full IV tEN_ARL ns @ Encode = 13MSPS 13MSPS, 50% Duty Cycle Full IV 32.7 38.2 ns @ Encode = 20MSPS 20MSPS, 50% Duty Cycle Full IV 26.0 31.5 ns ENCODE to AB_OUT Falling Low Delay5 tEN_AFL Full IV tCR + t2X_AFL ns ENCODE to AB_OUT Delay (Setup)5 tS_AEN Full IV tENC - tEN_AFL ns @ Encode = 13MSPS 13MSPS, 50% Duty Cycle Full IV 22.2 30.7 ns 25°C @ Encode = 20MSPS 20MSPS, 50% Duty Cycle8 IV 5.0 11.5 ns Full IV 2 10.5 ns NOTES 1 See AD6600 AD6600 Timing Diagrams. 2 All switching specifications tested by driving ENC and ENC differentially. 3 Several timing specifications are a function of Encode high time, tENCH ; these specifications are shown in the data tables and timing diagrams. Encode duty cycle should kept as close to 50% as possible. Reference AD6600 AD6600 Timing Diagrams 4 The 2X Clock is generated internally, therefore some specifications are functions of encode period and duty cycle. 5 This specification IS a function of Encode period and duty cycle. 6 This specification IS NOT a function of Encode period and duty cycle. 7 CLK2X referenced to 2.0Vcrossing; digital output levels referenced to 0.8 and 2.0V crossings; all outputs with 10pF load. 8 For these particular specifications, the "+25°C" specification is valid from +25°C to +85°C. The "Full" temperature specification includes cold temperature extreme and covers the entire range, -40°C to +85°C. REV. PrA -4- AD6600 AD6600 ­ SPECIFICATIONS AC SPECIFICATIONS (AVCC = +5V, DVCC = +3.3V; ENC & ENC = 20 MSPS, Duty Cycle = 50%; TMIN = -40°C, TMAX = +85°C unless otherwise specified) Test AD6600AST AD6600AST Parameter Temp Level Min Typ Max Units ANALOG INPUTS1 Analog Input 3dB Bandwidth2 Full V 450 MHz Differential Analog Input Voltage Range Full V 2.45 VPP 70 MHz Full V 2.57 150 MHz VPP Full V 2.62 200 MHz VPP Full V 2.86 250 MHz VPP Differential Analog Input Impedance3 197 - j24 V 70 MHz +25°C 188 - j48 V 150 MHz +25°C 175 - j57 V 200 MHz +25°C 161 - j67 V 250 MHz +25°C 151 - j73 V 300 MHz +25°C 140 - j80 V +25°C 350 MHz +25°C 141 - j75 V 400 MHz +25°C 173 - j107 V 450 MHz Full-scale Input Power dBm 5.8 V Full 70 MHz dBm 6.3 V Full 150 MHz dBm 6.7 V Full 200 MHz dBm 7.7 V Full 250 MHz Full-scale Gain Tolerance4 Full V ±0.5 dB 70-250 MHz 5 +25°C I -1.0 ±0.1 +1.0 dB 200 MHz Gain Matching (Input A:B) Full V ±0.1 dB 70-250 MHz Full II -0.5 ±0.05 +0.5 dB 200 MHz Range-to-Range Gain Tolerance Full 70-250 MHz V ±0.1 dB Range-to-Range Phase Tolerance Full 70 MHz V 0.2 degree Full 250 MHz V 0.5 degree Channel Isolation6 70­ 250 MHz Full IV 45 50 dB Noise7 Full µVrms Minimum Attenuation Level V 34 Full µVrms Maximum Attenuation Level V 869 Attenuator 3OIP8 Full V +33 dBm NOTES 1 AIN, AIN / BIN, BIN : The AD6600 AD6600 analog inputs are unconditionally stable and guarantee proper operation over the 70-250MHz specified operating range. Circuit board layout is critical on this device, and proper PCB layout must be employed to achieve specified results. 2 Analog Input 3dB Bandwidth is determined by internal track-and-hold. The front-end attenuators have a bandwidth of 1GHz 3 Measured real and imaginary values using Network Analyzer. 4 Full-scale gain tolerance is the typical variation in gain at a given IF input frequency. The nominal value for fullscale input power is a function of frequency as shown in previous specification. 5 Fullscale gain tolerance measured at 200MHz analog input referenced to 6.7dBm nominal fullscale input power. For the gain measurement test, the input signal level is set to ­6dBFS. Tuning port bandwidth is set to 50 MHz. 6 Main channel set to fullscale input power. Diversity channel swept from ­20dBFS to ­90dBFS. 7 Measurement includes thermal and quantization noise at 70MHz analog input. Tuning port bandwidth is set to 50MHz. 8 Test tones at 160.05MHz and 170.05MHz. REV. PrA -5- AD6600 AD6600 ­ SPECIFICATIONS AC SPECIFICATIONS cont. (AVCC = +5V, DVCC = +3.3V; ENC & ENC = 20 MSPS, Duty Cycle = 50%; TMIN = -40°C, TMAX = +85°C unless otherwise specified) Test AD6600AST AD6600AST Parameter Temp Level Min Typ Max Units Signal-to-Noise Ratio (SNR)1,2,3 AIN = 70 MHz +25°C dB 55 59 IV @ -1dBFS +25°C dB 54.5 V @ -6dBFS +25°C dB 45 49 IV @ -10dBFS +25°C dB 41 48±6 IV @ -12dBFS to -42dBFS +25°C dB 31 34 IV @ -54dBFS AIN = 150 MHz +25°C dB 55 58 IV @ -1dBFS +25°C dB 54 V @ -6dBFS +25°C dB 45 49 IV @ -10dBFS +25°C dB 41 48±6 IV @ -12dBFS to -42dBFS +25°C dB 31 34 IV @ -54dBFS AIN = 200 MHz +25°C dB 55 57.5 I @ -1dBFS1 1 +25°C dB 53.5 V @ -6dBFS +25°C dB 45 49 I @ -10dBFS1 +25°C dB 41 48±6 I @ -12dBFS to -42dBFS2 +25°C dB 31 34 I @ -54dBFS3 AIN = 250 MHz +25°C dB 52 56 @ -1dBFS IV +25°C dB 53.5 @ -6dBFS V +25°C dB 43 49 @ -10dBFS IV +25°C dB 40 48±6 @ -12dBFS to -42dBFS IV +25°C dB 30 34 @ -54dBFS IV 2nd HARMONIC AIN = 70 MHz dBc 69 V Full @ -1dBFS dBc 68 V Full @ -6dBFS dBc 68±6 V Full @ -12dBFS to -42dBFS AIN = 150 MHz dBc 60 V Full @ -1dBFS dBc 59 V Full @ -6dBFS dBc 67±6 V Full @ -12dBFS to -42dBFS AIN = 200 MHz1,2,3 +25°C @ -1dBFS I 50 60 dBc Full @ -6dBFS V 56 dBc +25°C @ -10dBFS I 48 55 dBc Full @ -12dBFS to -42dBFS V 65±6 dBc Full @ -54dBFS V 50 dBc AIN = 250 MHz Full @ -1dBFS V 54 dBc Full @ -6dBFS V 52 dBc Full @ -12dBFS to -42dBFS V 65±6 dBc NOTES 1 Measurements at -1dFBS, -6dBFS, and -10dBFS are in highest attenuation mode, RSSI = 101 2 Each gain-range is checked at ~3dB from RSSI trip point (not in hysterisis); nominally -16dBFS (RSSI = 100), -22dBFS (RSSI = 011), -28dBFS (RSSI = 010), -35dBFS (RSSI = 001). 3 Measurement at -54 dBFS is in the lowest attenuation mode, RSSI = 000. REV. PrA -6- AD6600 AD6600 ­ SPECIFICATIONS AC SPECIFICATIONS cont. (AVCC = +5V, DVCC = +3.3V; ENC & ENC = 20 MSPS, Duty Cycle = 50%; TMIN = -40°C, TMAX = +85°C unless otherwise specified) Test AD6600AST AD6600AST Parameter Temp Level Min Typ Max Units 3rd HARMONIC AIN = 70 MHz @ -1dBFS Full V 77 dBc @ -6dBFS Full V 76 dBc @ -12dBFS to -42dBFS Full V 67±6 dBc AIN = 150 MHz @ -1dBFS Full V 65 dBc @ -6dBFS Full V 70 dBc @ -12dBFS to -42dBFS Full V 66±6 dBc AIN = 200 MHz1,2,3 +25°C dBc 50 55 I @ -1dBFS Full dBc 58 V @ -6dBFS +25°C dBc 55 66 I @ -10dBFS Full dBc 65±6 V @ -12dBFS to -42dBFS Full dBc 62 V @ -54dBFS AIN = 250 MHz dBc 50 V Full @ -1dBFS dBc 56 V Full @ -6dBFS dBc 65±6 V Full @ -12dBFS to -42dBFS WORST OTHER SPUR (4th or higher) AIN = 70 MHz dBc 74.5 V Full @ -1dBFS dBc 71 V Full @ -6dBFS dBc 68±6 V Full @ -12dBFS to -42dBFS AIN = 150 MHz dBc 67 V Full @ -1dBFS dBc 65 V Full @ -6dBFS dBc 67±6 V Full @ -12dBFS to -42dBFS AIN = 200 MHz +25°C dBc 60 67 I @ -1dBFS Full dBc 66 V @ -6dBFS +25°C dBc 55 66 I @ -10dBFS Full dBc 65±6 V @ -12dBFS to -42dBFS AIN = 250 MHz @ -1dBFS Full V 66.5 dBc @ -6dBFS Full V 65 dBc @ -12dBFS to -42dBFS Full V dBc 65±6 NOTES 1 Measurements at -1dFBS, -6dBFS, and -10dBFS are in highest attenuation mode, RSSI = 101 2 Each gain-range is checked at ~3dB from RSSI trip point (not in hysterisis); nominally -16dBFS (RSSI = 100), -22dBFS (RSSI = 011), -28dBFS (RSSI = 010), -35dBFS (RSSI = 001). 3 Measurement at -54 dBFS is in the lowest attenuation mode, RSSI = 000. REV. PrA -7- AD6600 AD6600 ­ SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS1 Parameter Min Max Units ELECTRICAL AVCC Voltage V 7 0 DVCC Voltage V 7 0 Analog Input Voltage2 V AVCC 0 Analog Input Current2 mA 25 Digital Input Voltage3 V AVCC 0 mA Output Current4 4 V AVCC Resonant Port Voltage5 0 ENVIRONMENTAL6 Operating Temperature Range (Ambient) -40 +85 °C Maximum Junction Temperature +150 °C Lead Temperature (Soldering, 10 sec) +300 °C Storage Temperature Range (Ambient) -65 +150 °C NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Pins AIN, AIN , BIN, BIN 3 Pins ENC, ENC , A_SEL, B_SEL 4 Pins D10:0, RSSI2:0, AB_OUT, CLK2X 5 Pins FLT, FLT 6 Typical thermal impedance (44-pin TQFP); JC = 16°C/W, JA = 55°C/W EXPLANATION OF TEST LEVELS Test Level I 100% production tested. II 100% production tested at +25°C and guaranteed by design and characterization at temperature extremes. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. ORDERING GUIDE Model AD6600AST AD6600AST AD6600ST/PCB AD6600ST/PCB Temperature Range -40°C to +85°C (Ambient) Package Description 44-Terminal TQFP (Thin Quad Plastic Flatpack) Evaluation Board with AD6600AST AD6600AST Package Option ST-44 ST-44 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6600 AD6600 features proprietary protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. PrA -8- AD6600 AD6600 ­ SPECIFICATIONS PIN FUNCTION DESCRIPTIONS Pin No. Name Function 1, 33 DVCC Digital VCC for Digital outputs. Can be +3.3V. 2, 5, 13, 19, 21, 24, 30, 32 GND Ground. 3 C1 Internal bias point. Bypass by .01 µF to GND. 4, 14, 15, 18, 20, 25, 31 AVCC +5 V power supply. 6-8 RSSI[2:0] RSSI digital output bits. 9, 10 B_SEL, A_SEL Mode Select pins for analog input channel A and B sampling. 11 AIN True analog input channel A. 12 Complementary analog input channel A. AIN Resonant Filters pins for external LC noise filter. 16, 17 FLT , FLT 22 Complementary analog input channel B. BIN 23 BIN True analog input channel B. 26 Complementary Encode input. ENC 27 ENC True Encode input. 28 CLK2X 2 x clock output used for clocking digital filter chips. 29 AB_OUT Digital output flag indicating whether output is input A (high) or B (low). 34 D0 Digital data output bit (Least significant bit)1 35 - 43 D1-D9 Digital data output bits1 44 D10 Digital data output bit (Most significant bit)1 NOTES 1 Digital Outputs (D10:D0) in Twos Complement Format D4 D3 D2 D1 D0 (LSB) 41 D6 42 D5 43 D8 D9 44 D7 D1 0(MSB) PIN CONFIGURATION 40 39 38 37 36 35 34 DVCC DVCC 1 33 GND 2 32 GND C1 3 31 AVCC AVCC 4 30 GND GND 5 29 AB_OUT 28 CLK2X 27 ENC AD6600 AD6600 TOP VIEW (Not to Scale) 24 GND AIN 11 23 BIN 12 REV. PrA 13 14 15 16 17 18 19 20 21 22 BIN 10 GND A_SEL AVCC AVCC GND 25 AVCC 9 FLT ENC B_SEL FLT 26 AVCC RSSI0 8 AVCC 7 AIN 6 RSSI1 GND RSSI2 -9- AD6600 AD6600 ­ SPECIFICATIONS DEFINITIONS OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. The bandwidth is determined by the internal track-and-hold when the filter node is resonated. Aperture Delay The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Fullscale Gain Tolerance Unit to unit variation in fullscale input power. Fullscale Input Power Expressed in dBm. Computed using the following equation: Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Attenuator 3OIP The third order intercept point of the front end of the AD6600 AD6600. It is the point where the third order products would theoretically intercept the input signal level if the input level could increase without bounds. This is measured using the ADC within the AD6600 AD6600 while the input is stimulated with dual tones in the minimum attenuation (i.e. maximum gain) range. Channel Isolation The amount of signal leakage from one channel to the next when one channel is driven with a fullscale input, and the other channel is swept from ­20 dBFS to ­90dBFS with a frequency offset. The leakage is measured on the side with the smaller signal. PowerFullscale 2 VFullscalerms Z Input = 10 log .001 Gain Matching (Input A:B) Variation in fullscale power between A and B inputs. Harmonic Distortion, 2nd The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, 3rd The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Differential Analog Input Resistance, Differential Analog Input Capacitance and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit. Differential Analog Input Voltage Range The peak to peak differential voltage that must be applied to the converter to generate a fullscale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. Then the difference is computed between both peak measurements. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Noise (for any range within the ADC) Vnoise = Z * .001*10 Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. FS dBm - SNRdBc - SignaldBFS 10 Where Z is the input impedance, FS is the fullscale of the device for the frequency in question, SNR is the value for the particular input level and Signal is the signal level within the ADC reported in dB below fullscale. This value includes both thermal and quantization noise. Differential Resonant Port Resistance The resistance shunted across the resonant port (nominally 630 ohms). Used to determine the filter bandwidth and gain of that stage. REV. PrA Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic "1" state to achieve rated performance; pulse width low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a give clock rate, these specs define an acceptable Encode duty cycle. - 10 - AD6600 AD6600 ­ SPECIFICATIONS DEFINITIONS OF SPECIFICATIONS cont. Range-Range Gain Tolerance The gain error in the RSSI attenuator ladder from one range to the next. RSSI Hysterisis The amount of movement in the RSSI switch points depending on the direction of approach. Hysterisis prevents unnecessary RSSI toggling when input signal power is near a threshold. Range-Range Phase Tolerance The phase error in the RSSI attenuator ladder from one range to the next. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Differential Resonant Port Capacitance The capacitance between the two resonant pins. Used to determine filter bandwidth and resonant frequency. Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the 2nd and 3rd harmonic) reported in dBc. RSSI Gain Step The input amplitude span between taps of the RSSI (received signal strength) attenuator ladder. Ideally each stage should span 6 dB of input power. AD6600 AD6600 TRANSFER FUNCTION 60 54 48 SNR (dB) 42 36 30 24 18 12 6 0 -100 -90 -80 -70 -60 -50 -40 -30 AIN Level (dBFS) Figure 1. AD6600 AD6600 SNR versus Input Power REV. PrA - 11 - -20 -10 0 AD6600 AD6600 ­ SPECIFICATIONS EQUIVALENT CIRCUITS AVCC ATTENUATOR STAGE EQUIVALENT INPUT R SHOWN ONLY AIN 4X/8X GAIN STAGE GND 100 VREF BUF BUF AVCC GAIN 100 AIN GND Figure 2. Analog Input Stage (Channel A shown; Channel B is equivalent) External LC Filter AVCC AVCC FLT FLT AVCC GND GND 315 315 To T/H From Gain Stage GND Figure 3. Resonant (LC Noise Filter) Port REV. PrA - 12 - AD6600 AD6600 ­ SPECIFICATIONS EQUIVALENT CIRCUITS cont. AVCC AVCC AVCC ISEL ISEL_B A_SEL B_SEL BIAS GND GND GND Figure 4. A_SEL, B_SEL Input Mode Pins AVCC AVCC AVCC R1 17k½ R1 17k½ ENCODE ENCODE R2 8k½ TIMING CIRCUITS R2 8k½ Figure 5. Encode Inputs DVCC DVCC CURRENT MIRROR CURRENT MIRROR DVCC DVCC VREF 500 VREF D10 - D0 RSSI[2:0] AB_OUT CURRENT MIRROR CURRENT MIRROR Figure 7. CLK2X, AB_OUT Outputs Figure 6. Digital Outputs REV. PrA CLK2X - 13 - AD6600 AD6600 ­ SPECIFICATIONS AD6600 AD6600 TIMING DIAGRAMS tENCH tENCL tENC ENCODE tCR1 tCF1 CLK2X tCR2 tCF2 tCLK2XL CLK2X2 tCLK2X2 tCLK2XL tCLK2XH2 tCLK2XH1 CLK2X2 CLK2X1 tCLK2X1 CLK2X2 CLK2X1 t2X1_DFL t2X1_DRL D[10:0], RSSI[2:0] t2X1_AFL t2X1_ARL AB_OUT Figure 8. Encode to CLK2X Delays and CLK2X Propagation Delays tENCH tENCL tENC ENCODE tCR1 tCF1 CLK2X CLK2X2 tCR2 tCF2 tCLK2XL tCLK2X2 tCLK2XL CLK2X2 CLK2X1 tH_D2X tCLK2XH2 tS_D2X tCLK2X1 tCLK2XH1 CLK2X2 CLK2X1 tH_D2X tS_D2X D[10:0], RSSI[2:0] tH_A2X tS_A2X AB_OUT Figure 9. CLK2X Setup and Hold Time Characteristics REV. PrA - 14 - tH_A2X tS_A2X AD6600 AD6600 ­ SPECIFICATIONS AD6600 AD6600 TIMING DIAGRAMS cont. tENCH ENCODE tENCL ENCODE ENCODE ENCODE tCR1 tCR2 tCF1 CLK2X tENC tCF2 tCLK2XL CLK2X2 tCLK2X2 tCLK2XL CLK2X1 tCLK2X1 tCLK2XH2 tCLK2XH1 CLK2X2 CLK2X2 CLK2X1 tEN_DFL tEN_AFL tEN_DRL D[10:0], RSSI[2:0] tEN_ARL AB_OUT Figure 10. Encode to CLK2X Delays and Encode Propagation Delays tENCH ENCODE tENCL ENCODE ENCODE tCR1 tCF1 CLK2X tENC tCR2 tCF2 tCLK2XL CLK2X2 tCLK2X2 tCLK2XL CLK2X1 tH_DEN ENCODE tCLK2X1 tCLK2XH2 tCLK2XH1 CLK2X2 tS_DEN CLK2X1 tH_DEN CLK2X2 tS_DEN D[10:0], RSSI[2:0] tH_AEN tS_AEN tH_AEN AB_OUT Figure 11. Encode Setup and Hold Time Characteristics REV. PrA - 15 - tS_AEN AD6600 AD6600 ­ SPECIFICATIONS AD6600 AD6600 TIMING DIAGRAMS cont. 3 2.6 CLK2X 8.4 8 D[10:0], RSSI[2:0] 6 6.2 AB_OUT Figure 12. Typical Output Rise and Fall Times 20 30 50 40% ENCODE 18 18 8 30 20 8 CLK2X Figure 13. Encode = 20 MSPS, Duty Cycle = 40% 30 ENCODE 20 50 60% 23 8 23 20 8 CLK2X Figure 14. Encode = 20 MSPS, Duty Cycle = 60% REV. PrA - 16 - 30 AD6600 AD6600 ­ SPECIFICATIONS THEORY OF OPERATION The AD6600 AD6600, dual-channel, gain-ranging ADC integrates analog IF circuitry with high-speed data conversion. Each analog input stage is a 1GHz, 0 to -24dB, phase-compensated step attenuator; the step size in each attenuator is 12dB. Both input stages drive an analog multiplex function followed by a +12/+18 dB gain amplifier. A simple LC noise filter at the output of the gain amplifier is required to resonate at the desired IF. This resonant filter port precedes a wide input bandwidth (450MHz) track-and-hold followed by an 11-bit analog-to-digital converter (ADC). A high-speed synchronous peak detector monitors signal strength at both input channels. The peak detector drives RSSI circuitry that automatically adjusts attenuation and gain on a clock by clock basis. Both the three RSSI indicator bits and the eleven ADC bits are available at the output providing an exponent and mantissa data format. Together these integrated components form an IF sampling, high dynamic range ADC system. NOISE FILTER FLT FLT 0, -12, -24 dB RESONANT PORT 630 AIN ATTEN AIN AB_OUT DETECT PEAK 3 SET RSSI RSSI Encode +12, +18 dB ANALOG MUX GAIN A/D CONVERTER GAIN GAIN TWOS 11 COMPLEMENT SELECT GAIN 3 RSSI Encode D10 - D0 RSSI [2:0] BIN ATTEN BIN TIMING CLK2X 0, -12, -24 dB A_SEL AVCC B_SEL GND DVCC ENC ENC It is helpful to view this device as a stand-alone ADC using automatic gain control. The gain-control referred to in this data sheet as gain-ranging, works to maintain a constant SNR over as wide a range as possible. 0 101 -12 100 100 011 011 010 010 001 001 000 -18 -24 -30 -36 -42 000 -48 -54 Ain (dBFS) 101 maximum gain. However when the input signal level gets into the gain-ranging section (approx. -42dBFS), the SNR is contained between about 50 and 56 dB or between 44 and 56 including the effects of hysterisis. Although the graph above does not indicate so, there are slight differences between the SNR from one gain range to the next as the gain amp switches between 12dB and 18dB. Once the final RSSI range has been exceeded (approx. -12dBFS), SNR again increases 1 dB per 1 dB input power increase until converter fullscale is reached. Again, this performance is very much like the effects of a typical analog AGC loop. AD6600 AD6600 SUBCIRCUITS Input Step Attenuator and Gain Stage The AD6600 AD6600 has two identical input attenuators, channel A and channel B. These dual inputs are typically used as diversity channels but may also process two independent IF signals. For maximum oversampling the device is used in single channel mode; in this case only one input channel is required. The attenuator steps are 0, -12 and -24 dB. The attenuator settings are based on the decisions of the RSSI stage (ref. Peak Detector/RSSI section). The outputs of the attenuators connect to an analog multiplexer that selects either channel A or B for subsequent processing (ref. Input Mode). The selected signal drives a dual-gain amplifier set to either +12 or +18 dB; the selected gain is also determined by the RSSI stage. Therefore, based on all possible combinations of attenuation and gain, the input signal receives -12 to +18 dB of voltage gain in 6 dB steps (Table 1). Overall gain-matching is typically within 0.1dB. And with a bandwidth of 1 GHz, the phase delay through the front-end ranges from 0.2 to 0.5 degrees depending on input frequency. Additionally, the input impedance does not change with attenuator settings so there is no AM to PM distortion. Attenuator 0 dB 0 dB -12 dB -12 dB -24 dB -24 dB Gain Amp +18 dB +12 dB +18 dB +12 dB +18 dB +12 dB Total +18 dB +12 dB +6 dB 0 dB -6 dB -12 dB RSSI Word 000 001 010 011 100 101 Table 1. Attenuator and Gain Settings -60 -66 -72 -78 High Speed Peak Detector and RSSI Circuitry The peak detector along with the attenuator and dual gain amplifier form the control loop within the AD6600 AD6600. -84 -90 -90 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 -96 SNR (dB) 12dB SNR WINDOW Figure 15. SNR for Gain-Ranging ADC As stated previously, the AD6600 AD6600 has a floating-point output: eleven mantissa bits and three exponent bits. As shown in Figure 15, at the lowest input levels SNR increases 1dB for a 1dB increase in input power. In this range, the AD6600 AD6600 is set for REV. PrA - 17 - The peak detector is designed to follow the analog input one clock cycle before the conversion is actually made. Therefore, while the converter section of the AD6600 AD6600 is converting sample `n', the peak detector is already looking at sample `n+1'. While looking at the `n+1' sample (the calibration period), the peak detector examines the envelope of the input signal. The more of an envelope that is tracked, the more accurate the gain setting. At the very least, the peak detector must be presented either a positive or negative sinusoidal peak, which represents about ½ of a cycle of a sine wave. AD6600 AD6600 ­ SPECIFICATIONS Since the peak detector works for a complete cycle prior to conversion, the absolute minimum IF frequency that can be determined is twice the sample rate per channel. Therefore at 15 MSPS, the minimum IF frequency that can be sampled would be 30 MHz. Note that the more cycles of the input that are monitored by the peak detector, the more accurate the gain setting will be. Therefore, the actual minimum IF frequency recommended is higher than this. The minimum specified frequency is 70 MHz. Since the RSSI control loop is performed on a sample by sample basis, the AD6600 AD6600 follows the signals into and out of a deep fade very accurately. Hysterisis The AD6600 AD6600 employs hysterisis to prevent the gain-ranging from unnecessarily changing when the signal envelope is near an RSSI threshold. The hysterisis is digital and will account for exactly 6 dB of shift depending on whether the signal is increasing or decreasing. This effect is shown in the dashed lines of the overall transfer function, Figure 15. External LC Noise Filter, Resonant Port The output of the attenuator/gain stage drives the wide bandwidth track-and-hold (T/H), followed by the ADC encoder. Because the attenuator/gain stage has a very wide bandwidth (~1 GHz), an LC filter or "resonant port" is provided to limit the amount of wideband noise delivered to the ADC. The simple LC filter does not provide signal selectivity and should typically be 35 to 50 MHz wide. However, because the ADC's track-and-hold itself has a wide bandwidth (~450MHz), this noise-limiting filter is critical to meeting overall sensitivity. Specific details on selecting components for the resonant port are provided later in the text (Understanding the External Analog Filter). ADC Encoder After the calibration period is complete (one clock cycle), the appropriate gain and attenuator settings are determined and set. Once settled, the internal track-and-hold freezes the input signal so that the ADC encoder may digitize the signal. During digitization, the peak detector/RSSI circuitry is already looking at the next sample. When the AD6600 AD6600 is in dual channel mode, the process is interleaved: while channel B is monitored for signal strength, channel A is digitized. This allows the RSSI to update on a clock by clock basis. Digitize Old Data T&H Hold Encode T&H Track ADC Digitize T&H Hold IF Input Internal 2x Clock RSSI Cal. RSSI Calibration RSSI Set Noise Filter Discharge Amplifier Control Noise Filter Settling 4/8 Amp Clamped T/H Input Noise Filter Settling Figure 16. AD6600 AD6600 Internal Timing Figure 16 shows internal timing of how the chip works. The encode applied to the device initiates several actions. The first and most important is that the track-and-hold is placed in hold thus sampling the analog input at that instant. The second action is that the peak detector of the RSSI circuitry is initialized. During this period, the analog input envelope is monitored to determine signal power. The AD6600 AD6600 is in calibration mode for about one quarter of the encode period. While the AD6600 AD6600 is in calibration, the external noise filter is discharged and the amplifier driving the filter disabled. Since this filter is shared between the two input channels in dual channel mode, this greatly reduces the feed-though between the channels that would otherwise exist. One quarter of an encode period after the calibration is complete, the amplifier is re-enabled and allowed to settle to its new signal conditions for sampling by the wideband T/H on the next encode signal. The final action is that the signal on the resonant port is sampled by the track-and-hold. This happens on the next rising edge of the encode. Input Mode Select The AD6600 AD6600 has two operating modes: single channel and dual channel. In single channel mode, the ADC always samples channel A or always samples channel B. In dual channel mode, the ADC converter is sampling channel A and channel B on alternating Encode cycles. Two control pins are provided to select the desired mode of operation. A_SEL and B_SEL arbitrate the selection of how these input channels are connected to the output. Table 2 shows the truth table for selection of the input. Mode Dual: A/B Single: A Single: B Not Valid A_SEL B_SEL 1 1 0 0 1 0 1 0 Output vs. Encode Clock n n+1 n+2 n+3 A B A B A A A A B B B B - Table 2. Selecting AD6600 AD6600 Operating Mode A_SEL and B_SEL are not logic inputs and should be tied directly to ground or analog VCC (+5 volts analog). REV. PrA - 18 - AD6600 AD6600 ­ SPECIFICATIONS In dual channel mode, the AB_OUT signal indicates which input is currently available on the digital output. When the AB_OUT is 1, the digital output is the digitized version of channel A. Likewise, when AB_OUT is 0, the channel B is available on the digital output (Table 3). A_SEL & B_SEL = 1 D[10:0], RSSI[2:0] ABOUT Outputs Data vs. Encode Clock n n+1 n+2 n+3 A B A B 1 0 1 0 RSSI 11-Bit Word 101 100 011 010 001 000 DATA DATA DATA DATA DATA DATA 16-bit Data Format DATA x 32 DATA x 16 DATA x 8 DATA x 4 DATA x 2 DATA x 1 Corresponds to a shift right of 5 4 3 2 1 0 Table 5. 16-Bit, Fixed-Point Data Format Table 3. ABOUT for Dual Channel Operation Data Output Stage The output stage provides data in the form of mantissa, D[10:0], and exponent, RSSI[2:0] where D[10:0] represents the output of the 11-bit ADC coded as twos complement, and RSSI[2:0] represents the gain-range setting coded in offset binary. Table 4 shows the nominal gain-ranges for a nominal, 2Vpp differential fullscale input. Keep in mind that the actual fullscale input voltage and power will vary with input frequency. Differential Analog Input Voltage (VPP) 0.5 < Vin 0.25 < Vin < 0.5 0.125 < Vin < 0.25 0.0625 < Vin < 0.125 0.03125 < Vin < 0.0625 Vin < 0.03125 RSSI [2:0] Binary Decimal Equiv. 101 5 100 4 011 3 010 2 001 1 000 0 Attenuation or Gain (dB) -12 -6 0 +6 +12 +18 When mated with the AD6620 AD6620, Digital Receive Processor chip, the AD6600 AD6600 floating point data (mantissa + exponent) is automatically converted to 16-bit twos complement format by the AD6620 AD6620. APPLYING THE AD6600 AD6600 Encoding the AD6600 AD6600 The AD6600 AD6600 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Digitizing high frequency signals (IF range 70-250MHz) places a premium on encode clock phase noise. SNR performance can easily degrade by 3-4dB with 70MHz input signals when using a questionable clock source. At higher IFs (up to 250MHz) and with questionable clock sources the higher slew rates of the input signals reduce performance even further. See AN501 AN501, "Aperture Uncertainty and ADC System Performance" for complete details. For optimum performance the AD6600 AD6600 must be clocked differentially. The encode signal is usually ac-coupled into the ENC and ENC pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Table 4. Interpreting the RSSI Bits The digital processing chip which follows the AD6600 AD6600 can combine the 11 bits of twos complement data, with the 3 RSSI bits to form a 16-bit equivalent output word. Table 5 explains how the RSSI data can be interpreted when using a PLD or ASIC. Basically, the circuit performs right shifts of the data depending on the RSSI word. This can also be performed in software using the following pseudo code fragment. r0=dm(rssi); r2=5; r0=r2-r0; r1=dm(adc);(11 bits, MSB justified into DSP word) rshift r1, r0;(arithmetic shift to extend the sign bit) The result of the shifted data is a 16 bit fixed-point word that can be used as any normal 16-bit word. Figure 17 shows one preferred method for clocking the AD6600 AD6600. The sine source (low jitter) is converted from single-ended to differential using a RF transformer. The backto-back Schottky diodes across the transformer secondary limit clock excursions into the AD6600 AD6600 to approximately 0.8Vp-p differential. This helps prevent the sharp edges of the clock from feeding to other portions of the AD6600 AD6600, and limit the noise presented to the encode inputs. A crystal clock oscillator can also be used to drive the RF transformer if an appropriate limiting resistor (typically 100) is placed in the series with the primary. SINE SOURCE T1-1T ENCODE AD6600 AD6600 ENCODE 5082-2810 DIODES Figure 17. Transformer-Coupled Sine Source REV. PrA - 19 - AD6600 AD6600 ­ SPECIFICATIONS If a low jitter ECL/PECL clock is available, another option is to ac-couple a differential ECL/PECL signal to the encode input pins as shown in Figure 18. When general purpose gain blocks are used, matching can easily be achieved using a transformer. Most gain blocks are available with 50ohm input and output ports. Thus matching to the 200ohm impedance of the AD6600 AD6600 requires only a 1:4(impedance ratio) transformer as shown in Figure 20. VT 0.1uF ENCODE ECL/ PECL AD6600 AD6600 0.1uF suited to many application of the AD6600 AD6600. For more information on the AD6630 AD6630, reference the AD6630 AD6630 datasheet. from mixer output ENCODE 50 Ohm Gain Block Figure 20. Transformer-Coupled Gain Block VT Figure 18. AC-Coupled ECL/PECL Encode Driving the Analog Inputs As with most new high-speed, high dynamic range analog-todigital converters, the analog input to the AD6600 AD6600 is differential. Differential inputs allow much improvement in performance on-chip as IF signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even order harmonics. There are also benefits at the PCB level. First, differential inputs have high common mode rejection to stray signals such as ground and power noise. Also, they provide good rejection to common mode signals such as local oscillator feed-through. Driving a differential analog input introduces some new challenges. Most RF/IF amplifiers are single-ended and may not obviously interface to the AD6600 AD6600. However, using simple techniques, a clean interface is possible. The recommended method to drive the analog input port is shown below. The AD6600 AD6600 input is actually designed to match easily to a SAW filter such as SAWTEK 855297. This allows the SAW filter to be used in a differential mode, which often improves the operations of a SAW filter. Using network analyzer data for both the SAW filter output and the AD6600 AD6600 input ports (see data tables for AD6600 AD6600 S11 data), a conjugate match can be used for maximum power transfer. Often an adequate match can be achieved simply by using a shunt inductor to make the port look real (Figure 19). For more details on how to exactly match networks, see RF Circuit Design by Chris Bowick, ISBN: 0-672-21868-2. from mixer output SAW #2 SAW #1 AD6600 AD6600 ADC AD6630 AD6630 Figure 19. Cascaded SAW Filters with AD6630 AD6630 Where gain is required, the AD6630 AD6630 differential, low noise, IF gain block is recommended. This amplifier provides 24 dB of gain and provides limiting to prevent damage to the SAW filter and AD6600 AD6600. The AD6630 AD6630 is designed to reside between two SAW filters. This low noise device is ideally REV. PrA AD6600 AD6600 ADC - 20 - In the rare case that better matching is required, a conjugate match between the amplifier selected and the transformercoupled analog input can be achieved by placing the matching network between the amplifier and the transformer (Figure 21). For more details on matching, see the reference mentioned above for more details. from mixer output Matching Network 50 Ohm Gain Block AD6600 AD6600 ADC Figure 21. Gain Block and Matching Network Understanding the External Analog Filter Two primary tradeoffs must be made when designing the external resonant filter. The obvious one is the bandwidth of the filter. The second not so obvious tradeoff is settling time of the filter nodes. Resonant Filter Bandwidth determines the amount of noise that is limited at the center frequency chosen. If the resonant filter is too wide, little noise improvement is seen. If the resonant filter is too narrow, amplitude variation can be seen due to the tolerance of filter components. If the narrow filter is off center due to these tolerances (or drift), the 4x/8x signal will fall on the transition band of the filter. An optimum starting point for this filter is approximately 50MHz. Resonant Filter Settling limits the amount of capacitance of this filter. The output of the 4x/8x amplifier is clamped when the ADC is processing its input (encode high time). This prevents the amp output from feeding through to the ADC (T/H) and corrupting the ADC results. But, upon the falling edge of encode, the amp must now come out of clamp and present an accurate signal to the ADC T/H. The RC of the external filter determines the settling of the amp. If the amp output does not settle, the ADC sees an attenuated signal. So obviously a narrow bandwidth is desired to improve noise performance, but if the filter is too narrow, the amp will not settle and the ADC will see an attenuated signal. AD6600 AD6600 ­ SPECIFICATIONS T = RC; t = time; n = number of bits AVCC 315 Vo = A(1 - e t / T ) ) RESONANT FILTER PORT 315 A - A / 2 n = A(1 - e t / T ) 1 1 - n = 1 - et /T 2 1 = et /T n 2 1 t = ln( n ) T 2 t T = ln( 2 n ) FLT FLT From Gain Stage CLAMP ENCODE GND Figure 22. 4x/8x Amplifier Clamp Circuitry Figure 22 shows a simplified model of the 4x/8x amplifier. A key point to note is the resistor values in the collector legs are 315 ohms nominal with tolerance of +/-20%. The filter performance is determined by these values in conjunction with the internal parasitic capacitance, board parasitics, and the external filter components. ENCODE Hold RESONANT FILTER Clamped Track Ctotal = (Tencode * 0.5) 38.5ns = = 13.6 pF R * ln( 8192) 315 * ln(8192) In this case, Ctotal includes all parasitics and external capacitance. R is nominally the 315 ohms. The 8192 is (4*2048), which is ¼ lsb of the converter (11 bits, 2048). So for settling purposes, with 13MSPS 13MSPS encode and 50% duty cycle, the maximum allowable capacitance for proper settling is Ctotal = 13.6pF. Hold Settling Figure 23. 4x/8x Amplifier Settling Figure 23 shows why settling is important for this circuit. If the 4x/8x amp doesn't settle (come out of clamp) then the amplitude presented to the ADC will be decreased. This results in decreased gain when the filter capacitance is too high. This explains why the total capacitance that is allowed for the external filter varies depending on the clock rate (actually encode clock high time). If the encode is 13MSPS 13MSPS and the duty cycle is 50% then the allowable settling time is 38.5ns (1/2 of the encode time). Our assumption is that the amp should be allowed to settle to ¼ lsb in this time period. This has been proven with both simulation and empirical analysis. If the settling is assumed to be an RC circuit, then: As stated above this Ctotal includes the external capacitors, the board parasitics, and the AD6600 AD6600 parasitics. The parasitics of the AD6600 AD6600 (lead, internal bond pad, and internal connections) at FLT and FLT are 1.75pF +/- 0.35pF (differential). If the resistors are at maximum value (315 +20%), the maximum allowable capacitance is Ctotal = 11.3pF. If the duty cycle is less than 50% then the maximum allowable capacitance is decreased further, to allow for settling. Power Supplies Care should be taken when selecting a power source. Linear supplies are strongly recommended. Switching supplies tend to have radiated components that may be "received" by the AD6600 AD6600. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1uF chip capacitors. The AD6600 AD6600 has separate digital and analog power supply pins. The analog supplies are denoted AVCC and the digital supply pins are denoted DVCC. Although analog and digital supplies may be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching back into the analog supplies. Note that AVCC must be held within 5% of 5 Volts; however the DVCC supply may be varied according to output digital logic family. The AD6600 AD6600 is specified for DVCC = 3.3V as this is a common supply for digital ASICS. REV. PrA - 21 - AD6600 AD6600 ­ SPECIFICATIONS Output Loading Care must be taken when designing the data receivers for the AD6600 AD6600. Note from the equivalent circuits shown earlier (ref. Equivalent Circuits) that D[10:0] and RSSI[2:0] contain a 500-ohm output series resistor. To minimize capacitive loading, there should only be one gate on each output pin. Extra capacitive loading will increase output timing and invalidate timing specifications. CLK2X and AB_OUT do not contain the output series resistors. Testing for digital output timing is performed with 10pF loads. Layout Information The schematic of the evaluation board (Figures 24, 25) represents a typical implementation of the AD6600 AD6600. A multilayer board is recommended to achieve best results. It is highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. The pinout of the AD6600 AD6600 facilitates ease of use in the implementation of high frequency, high resolution design practices. All of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes. Care should be taken when routing the digital output traces. To prevent coupling through the digital outputs into the analog portion of the AD6600 AD6600, minimal capacitive loading should be placed on these outputs. It is recommended that a fan-out of only one be used for all AD6600 AD6600 digital outputs. The layout of the analog inputs and the external resonant filter are critical. No digital traces must be routed near, under, or above these portions of the circuit. The transformers used for coupling into the analog inputs must be located as close as possible to the analog inputs of the AD6600 AD6600. The external resonant filter components must be physically close to the filter-input pins, yet separated from the analog inputs. The layout of the Encode circuit is equally critical. Any noise received on this circuitry will result in corruption in the digitization process and lower overall performance. The Encode clock must be isolated from the digital outputs and the analog inputs. Evaluation Board The evaluation board for the AD6600 AD6600 is straightforward, containing all required circuitry for evaluating the device. The only external connections required are power supplies, clock, and the analog inputs. The evaluation board includes the option for an onboard, clock oscillator for encode. Power to the analog supply pins of the AD6600 AD6600 is connected via the power terminal block (TB1). Power for the digital interface is supplied via pin 1 of J201, or the VDD e-hole located adjacent to J201. The VDD supply can vary between +3.3V to 5.0V and sets the level for the output digital data (J201). The J201 connector mates directly with the AD6620 AD6620 (Receive Signal Processor) evaluation board, part# AD6620S/PCB AD6620S/PCB, allowing complete evaluation of system performance. REV. PrA - 22 - The two analog inputs are connected via SMA connectors AIN and BIN, which are transformer-coupled to the AD6600 AD6600 inputs. The transformers have a turns-ratio of 1:4 to match the input resistance of the AD6600 AD6600 (200 ohms) to 50 ohms at the SMA connectors. The Encode signal may be generated using an onboard crystal oscillator, U100. If an onboard crystal is used, R104 must be removed from the board to prevent loading of the oscillator's output. The on-board oscillator may be replaced by an external encode source via the SMA connector labeled ENCODE. If an external source is used, it must be a high quality and very low phase noise source. The high-IF range of the AD6600 AD6600 (70-250MHz) demands that the Encode clock be sufficiently pure to maintain performance. The AD6600 AD6600 output data is latched using 74LCX574 74LCX574 (U201, U202) latches. The clock for these latches is determined by jumper selection on header J1. The clock can be a delayed version of the encode clock (CLKA, CLKB), or the CLK2X generated by the AD6600 AD6600. A clock is also distributed with the output data (J201) that is labeled CLKX (pin 11, J201). The CLKX is selected with jumpers on header J1 and can be CLKA, CLKB, or CLK2X. The resonant LC filter components (SEL2, C2 and C3) are omitted. The user must install proper values based on the IF chosen. See "Understanding the External Analog Filter" section of the data sheet for guidelines on selecting these components. AD6600 AD6600 ­ SPECIFICATIONS Item 1 2 Quantity 3 15 3 4 5 6 7 8 9 10 11 12 13 14 4 2 1 1 1 2 2 1 1 1 1 3 Reference AIN, BIN, ENCODE C1, C102-108 C102-108, C111, C114, C117-118 C117-118, C120-121 C120-121, C299 C112-113 C112-113, C115-116 C115-116 CR2-3 DUT J1 J201 R1-2 R100-101 R100-101 R103 R104 R298 R299 T1-2, T4 Description SMA Connector 0.1uF Chip Cap Low Inductance 0.1uF Chip Cap 1N2810 1N2810 Schottky Diode AD6600AST AD6600AST 20-Pin Double Row Male Header 50-Pin Double Row Male Header, Right Angle Omitted Surface Mount Resistor 1206, 10k Surface Mount Resistor 1206, 100 Surface Mount Resistor 1206, 50 Surface Mount Resistor 1206, 3.9k Surface Mount Resistor 1206, 2k Surface Mount Transformer Mini-Circuits T4-1T Table 6. AD6600ST/PCB AD6600ST/PCB Bill of Material Figure 24. AD6600ST/PCB AD6600ST/PCB Schematic Diagram, Page 1 REV. PrA - 23 - AD6600 AD6600 ­ SPECIFICATIONS Figure 25. AD6600ST/PCB AD6600ST/PCB Schematic Diagram, Page 2 Figure 27. AD6600ST/PCB AD6600ST/PCB Top Side Copper Figure 26. AD6600ST/PCB AD6600ST/PCB Top Side Silk Screen REV. PrA - 24 - AD6600 AD6600 ­ SPECIFICATIONS Connecting the AD6600 AD6600 with the AD6620 AD6620 The AD6600 AD6600 interfaces directly to the AD6620 AD6620 Digital Receive Signal Processor as shown in the Figure 31. No addition external components are required. Note that the layout requirements discussed previously do apply and deviations can result in degraded performance. The digital outputs of the AD6600 AD6600 must connect directly to the AD6620 AD6620 inputs with no additional fan-out. Additional loading on the outputs will compromise timing performance. D10 (MSB) AD6600 AD6600 D0 (LSB) Figure 28. AD6600ST/PCB AD6600ST/PCB Bottom Side Copper ENC ENC RSSI2 RSSI1 RSSI0 AB_OUT CLK2X IN15 AD6620 AD6620 IN5 IN4 IN3 IN2 IN1 IN0 EXP2 EXP1 EXP0 A/B CLK Figure 31. AD6600/AD6620 AD6600/AD6620 Connections Figure 32 shows the timing details between the AD6600 AD6600 and the AD6620 AD6620. On Clock 1, D[10:0], RSSI[2:0], and AB_OUT are captured by the AD6620 AD6620. Since AB_OUT has changed state from the previous clock, the D[10:0] and RSSI[2:0] are processed by the AD6620 AD6620. This clock allows adequate setup and hold time for AB_OUT, D[10:0], and RSSI[2:0] to be captured by the AD6620 AD6620. On Clock2, D[10:0], RSSI[2:0], and AB_OUT are captured by the AD6620 AD6620. Since AB_OUT has not changed from the previous clock, the D[10:0] and RSSI[2:0] are ignored by the AD6620 AD6620. This clock is concerned only with the AB_OUT setup and hold time. Figure 29. AD6600ST/PCB AD6600ST/PCB Power Supply Layer (Negative) Figure 30. AD6600ST/PCB AD6600ST/PCB Ground Layer (Negative) REV. PrA - 25 - AD6600 AD6600 ­ SPECIFICATIONS Timing w.r.t. CLKK2X (Encode = 13MSPS 13MSPS, Duty Cycle = 50%) 38.5 38.5 Clock2 Clock1 CLK2X 3.0 3.0 16.5 16.5 D[10:0], RSSI[2:0] 12.5 7.0 AB_OUT Figure 32. AD6600 AD6600 to AD6620 AD6620 Timing at 13MSPS 13MSPS AD6600AST AD6600AST OUTLINE DIMENSIONS 0.063 (1.60) MAX 0.472 (12.00) SQ 0.030 (0.75) 0.018 (0.45) 33 23 34 22 SEATING PLANE 0.394 (10.0) SQ TOP VIEW (PINS DOWN) 44 12 1 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35) REV. PrA 0.031 (0.80) BSC - 26 - 11 0.018 (0.45) 0.012 (0.30)