AD5532-4/AD5532-5 AD5532 AD5532-4 AD5532-5 IN-30 AD780 AD5532ABC-4 AD5532ABC-5 - Datasheet Archive

 

32-Channel Infinite Sample-and-Hold AD5532-4/AD5532-5 Preliminary Technical Data GENERAL DESCRIPTION The AD5532 combines a 32

 

a 32-Channel Infinite Sample-and-Hold AD5532-4/AD5532-5 AD5532-4/AD5532-5 Preliminary Technical Data GENERAL DESCRIPTION The AD5532 AD5532 combines a 32 channel voltage translation function with an infinite output hold capability. An analog input voltage on the common input pin, VIN, is sampled and its digital representation transferred to a chosen DAC register. VOUT for this DAC is then updated to reflect the new contents of the DAC register. Channel selection is accomplished via the parallel address inputs A0-A4 or via the serial input port. The device is operated with AVcc = +5V±5%, DVcc= 2.7V to 5.25V, Vss = -4.75V to -16.5V and VDD= 8V to 16.5V and requires a stable +3V reference on REF_IN pins as well as an offset voltage on OFFS_IN. The output voltage range is determined by the headroom of the output amplifier and is restricted to a range from Vss+2.2V to VDD-2V. FEATURES Infinite Sample & Hold Capability to ±0.012% accuracy High Integration: 32-channel SHA in 12x12 mm2 LFBGA Per channel acquisition time of 16µs max µ Adjustable Voltage Output Range Output Voltage Span: 10V Output impedance 0.5 (AD5532-4 AD5532-4) 1k (AD5532-5 AD5532-5) Readback capability Serial (SPI) and Parallel interfaces APPLICATIONS Level Setting Instrumentation Automatic Test Equipment Industrial Control Systems Data Acquisition Low Cost I/O PRODUCT HIGHLIGHTS 1. Infinite Droopless Sample & Hold Capability. 2. The AD5532 AD5532 is available in a 74-lead LFBGA package with a body size of 12mm by 12mm. FUNCTIONAL BLOCK DIAGRAM DVCC AVCC R E F _IN VDD R E F _O U T O F F S _IN VSS A D 5532 - V IN D AC ADC V O UT 0 + TR A C K /R E S E T BUSY - D AC V O UT 31 + DAC_GND AG N D O FFS_O UT D AC DGND IN T E R F A C E C O N TR O L L O G IC SER /PAR SC LK D IN DOUT A D D R E S S IN P U T R E G IS TE R S Y N C /C S A4-A0 C AL WR O F F S E T_S E L Patents Applied For REV. PrF 8/99 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999 AD5532-4/AD5532-5 AD5532-4/AD5532-5 SPECIFICATIONS VDD = +8V to +16.5V, VSS = -4.75V to -16.5V; AVCC = +4.75V to +5.25V; DVCC = +2.7V to +5.25V; AGND = DGND = DAC_GND = 0V; REF_IN = 3V; Output Range from Vss+2.2V to VDD -2V. All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted. Parameter1 ANALOG CHANNEL VIN to VOUT Nonlinearity Gain Offset Error Gain Error ANALOG INPUT (V IN) Input Voltage Range Input Current Input Capacitance Input Lower Deadband Input Upper Deadband ANALOG INPUT (OFFS_IN) Input Current VOLTAGE REFERENCE REF_IN Nominal Input Voltage Input Voltage Range Input Current REF_OUT Output Voltage Output Impedance Reference Drift ANALOG OUTPUTS (VOUT 0-31) Output Temp Coeff4 DC Output Impedance Output Range Resistive Load5 Capacitive Load Short-Circuit Current Output PSRR DC Crosstalk ANALOG OUTPUT (OFFS_OUT) Output Temp Coeff4 DC Output Impedance Output Range Output Current Capacitive Load DIGITAL INPUTS Input Current Input Low Voltage Input High Voltage Input Hysteresis (SCLK and CS only) Input Capacitance A Version2 Units ± 0.012 ± 0.006 +3.5 ± 50 ± 60 % max % typ typ mV max mV max 0 to +3 100 3.2 V nA max µA max 50 60 30 pF typ mV max mV max 100 Conditions/Comments nA max +3.0 +2.85/+3.15 50 ppm/°C typ typ k typ V min/max k max pF max nF max mA typ dB dB µV max 10 1 60 /+REF_IN-30 IN-30 10 100 ppm/°C typ k typ mV typ µA max pF typ See Figure 5 See Figure 5 V typ k typ ppm/°C typ 10 0.5 1 VSS +2.2 /VDD - 2 5 500 15 10 -70 -70 250 Nominal Input Range VIN being acquired on one channel VIN being acquired on all 32channels simultaneously - Cal Mode V V min/max nA max 3 TBD 60 After gain and offset adjustment µA max V max V max V min mV typ pF max ±1 0.8 0.4 2.0 200 10 NOTES: 1 See Terminology 2 A Version: Industrial temperature range -20°C to +85°C. 3 Guaranteed by design and characterisation, not production tested 4 AD780 AD780 as reference for the AD5532 AD5532 5 Ensure that you do not exceed Tj(max). See max. ratings. Specifications subject to change without notice ­2­ AD5532-4 AD5532-4 AD5532-5 AD5532-5 100µA output load AD5532-4 AD5532-4 AD5532-5 AD5532-5 VDD varied ±5% VSS varied ±5% Source Current DVCC = 5V±5% DVCC = 3V±10% REV. PrF AD5532-4/AD5532-5 AD5532-4/AD5532-5 SPECIFICATIONS= +2.7V to +5.25V; AGND = DGND = DAC_GND = 0V; REF_IN = V = +8V to +16.5V, V = -4.75V to -16.5V; AV = +4.75V to +5.25V; DV DD SS CC CC 3V; Output Range from Vss+2.2V to VDD -2V. All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted. Parameter1 DIGITAL OUTPUTS (BUSY, DOUT) Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage High Impedance Leakage Current4 High Impedance Output Capacitance4 A Version2 Units Conditions/Comments 3 POWER REQUIREMENTS Power-Supply Voltages VDD VSS AVCC DVCC Power-Supply Currents5 IDD ISS AICC DICC Power Dissipation5 0.4 4.0 0.4 2.4 ±10 15 V max V min V max V min µA max pF typ +8/+16.5 -4.75/-16.5 +4.75/+5.25 +2.7/+5.25 V V V V TBD TBD TBD < 1 250 mA mA mA mA mW DVCC DVCC DVCC DVCC = = = = 5V. 5V. 3V. 3V. Sinking 200 µA Sourcing 200 µA Sinking 200 µA Sourcing 200 µA min/max min/max min/max min/max max max max max typ 8 mA typ 8 mA typ 27 mA typ VDD=10V, VSS=-5V NOTES: 1 See Terminology 2 A version: Industrial temperature range -20°C to +85°C. 3 Guaranteed by design and characterisation, not production tested 4 DOUT only 5 Outputs Unloaded. Specifications subject to change without notice AC Characteristics (VDD = +8V to +16.5V, VSS = -4.75V to -16.5V; AVCC = +4.75V to +5.25V; DVCC = +2.7V to +5.25V; AGND = DGND = DAC_GND = 0V; REF_IN = 3V; Output Range from Vss+2.2V to VDD -2V. All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted). Parameter1 Output Settling Time Acquisition Time OFFS_IN Settling Time Digital-to-Analog Glitch Impulse Digital Crosstalk Analog Crosstalk Digital Feedthrough Output Noise Spectral Density AC Crosstalk A Version2 Units µs max µs max µs typ nV-s typ nV-s typ nV-s typ nV-s typ nV/(Hz)1/2 typ nV-s typ 3 16 TBD TBD TBD TBD TBD TBD 20 Conditions/Comments 100pF load Acquire VIN to ± 0.012% accuracy NOTES: 1 Guaranteed by design and characterisation, not production tested 2 A version: Industrial temperature range -20°C to +85°C. ­3­ REV. PrF Preliminary Technical Data AD5532-4/AD5532-5 AD5532-4/AD5532-5 Timing Characteristics Parallel Interface Parameter1,2 Limit at TMIN, TMAX (A Version) t1 t2 t3 t4 t5 t6 Units 0 0 50 50 20 0 ns ns ns ns ns ns Conditions/Comments CS to WR Setup Time CS to WR Hold Time CS Pulse Width Low WR Pulse Width Low A4-A0, CAL, OFFS_SEL to WR Setup Time A4-A0, CAL, OFFS_SEL to WR Hold Time min min min min min min NOTES: 1 See Interface Timing Diagram below 2 Guaranteed by design and characterization, not production tested. Serial Interface Parameter1,2 Limit at TMIN, TMAX (A Version) Units Conditions/Comments SCLK frequency SCLK High Pulse Width SCLK Low Pulse Width SYNC Falling Edge to SCLK Falling Edge Setup Time SYNC Low Time DIN Setup Time DIN Hold Time SYNC Falling Edge to SCLK Rising Edge Setup Time SCLK Rising Edge to DOUT Valid SCLK Falling Edge to DOUT High Impedance fCLKIN t1 t2 t3 20 23 23 5 MHz max ns min ns min ns min t4 t5 t6 t7 t83 t93 TBD 10 5 5 10 20 ns ns ns ns ns ns min min min min max max NOTES: 1 See Interface Timing Diagrams on following page 2 Guaranteed by design and characterization, not production tested. 3 These numbers are measured with the load circuit of Figure 2 Parallel Interface Timing Diagram CS 2m A t2 t1 IO L t3 TO OU TP UT P IN t4 WR t5 + 1.6V CL 5 0p F t6 A4 -A0 , C AL , O FF S_SE L 2m A Figure 1. Parallel Write (SHA Mode only) ­4­ IO H Figure 2. Load Circuit for DOUT Timing Specifications REV. PrF AD5532-4/AD5532-5 AD5532-4/AD5532-5 Preliminary Technical Data Serial Interface Timing Diagrams t1 2 1 SCLK 4 3 6 5 7 9 8 10 t2 t3 SYNC t4 t5 t6 D IN LSB MS B Figure 3. 10-Bit Write (SHA Mode and Both Readback Modes) t1 1 SCLK 2 4 3 5 6 7 8 9 10 11 12 13 14 t2 t7 SYNC t4 t9 t8 D OUT MS B LSB Figure 4. 14-Bit Read (Both Readback Modes) ­5­ REV. PrF Preliminary Technical Data AD5532-4/AD5532-5 AD5532-4/AD5532-5 ORDERING GUIDE Model Function Output Impedance Output Voltage Span Package Option AD5532ABC-4 AD5532ABC-4 AD5532ABC-5 AD5532ABC-5 32-channel SHA only 32-channel SHA only 0.5 typ 1k typ 10V 10V 74-lead LFBGA 74-lead LFBGA AD5532ABC-1 AD5532ABC-1* AD5532ABC-2 AD5532ABC-2* AD5532ABC-3 AD5532ABC-3* 32 DACs, 32-channel SHA 32 DACs, 32-channel SHA 32 DACs, 32-channel SHA 0.5 typ 0.5 typ 500 typ 10V 20V 10V 74-lead LFBGA 74-lead LFBGA 74-lead LFBGA * Separate datasheet ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) V DD to AGND.-0.3V to +17V V SS to AGND.+0.3V to -17V AVCC to AGND, DAC_GND.-0.3V to +7V DV CC to DGND.-0.3V to +7V Digital Inputs to DGND.-0.3V to DV CC+0.3V Digital Outputs to DGND.-0.3V to DV CC+0.3V REF_IN to AGND, DAC_GND.-0.3V to +7V V IN to AGND, DAC_GND.-0.3V to +7V VOUT0-31 VOUT0-31 to AGND.V SS-0.3V to VDD+0.3V OFFS_IN to AGND.VSS-0.3V to VDD+0.3V OFFS_OUT to AGND.AGND-0.3V to AVCC+0.3V AGND to DGND.TBD Operating Temperature Range Industrial .-20°C to +85°C Storage Temperature Range.-65°C to +150°C Junction Temperature (T J max).+150°C 74-lead LFBGA Package, Power Dissipation.(TJ max - TA)/JA mW JA Thermal Impedance.75°C /W Solder Ball Temperature, Soldering.TBD °C. NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100mA will not cause SCR latch-up CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5532 AD5532 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ­6­ REV. PrF AD5532-4/AD5532-5 AD5532-4/AD5532-5 Preliminary Technical Data TERMINOLOGY Output Settling Time V IN to VOUT Nonlinearity This is a measure of the maximum deviation from a straight line passing through the endpoints of the VIN vs. VOUT transfer function. It is expressed as a percentage of the full-scale span. Offset Error This is the time taken from when BUSY goes high to when the output has settled to ± 0.012% (± 0.5 LSB at 12 bits). Acquisition Time This is the time taken for the VIN input to be acquired. It is the length of time that BUSY stays low. This is a measure of the output error when VIN = 60mV. Ideally, with VIN=60mV: VOUT = (Gain * 60) - (Gain - 1) * VOFFS_IN) mV Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal). It is expressed in mV. OFFS_IN Settling Time Gain Error This is the area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-secs when the digital code is changed by 1 LSB at the major carry transition (011.11 to 100.00). This is a measure of the span error of the analog channel. It is the deviation in slope of the transfer function expressed in mV. It is calculated as: Gain Error = Ideal Fullscale Output - Actual Fullscale Output - Offset Error where Ideal Fullscale Output = Gain*2.97 - (Gain-1)*VOFFS_IN) Output Temp Coefficient This is a measure of the change in analog output with changes in temperature. It is expressed in ppm/°C. Output PSRR Power-Supply Rejection Ratio (PSRR) is a measure of the change in analog output for a change in supply voltage (VDD and VSS). It is expressed in dBs. VDD and VSS are varied ± 5%. DC Crosstalk This the DC change in the output level of one channel in response to a full-scale change in the output of all other channels. It is expressed in mV. This is the time taken from a step change in input voltage on OFFS_IN until the output has settled to within ± 0.2% (± 0.5 LSB at 9 bits). Digital-to-Analog Glitch Impulse Analog Crosstalk This the area of the glitch transferred to the output of one DAC due to a full-scale change in the output of another DAC. The area of the glitch is expressed in nV-secs. Digital Feeedthrough This is a measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to, i.e. CS/SYNC is high. The digital inputs are toggled between all 0s and all 1s. The area of the glitch is expressed in nV-secs. Output Noise Spectral Density This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured in nV/(Hz)1/2. AC Crosstalk This is the area of the glitch that occurs on the output of one channel while another channel is acquiring. It is expressed in nV-secs. VOUT Gain Error + Offset Error Ideal Transfer Function Actual Transfer Function O ffs e t E rro r 0V 60m V 2.970 3V Low er deadband VIN U pper deadband Figure 5. SHA Transfer Function ­7­ REV. PrF Preliminary Technical Data AD5532-4/AD5532-5 AD5532-4/AD5532-5 PIN FUNCTION DESCRIPTION AD5532 AD5532 Function AGND(1-2) AVCC (1-2) VDD (1-4) VSS (1-4) DGND DVCC DAC_GND(1-2) REF_IN REF_OUT VOUT (0-31) VIN A4-A11 A4-A11, A02 CAL 1 Analog GND pins. Analog supply pins. Voltage range from +4.75V to +5.25V. VDD supply pins. Voltage range from +8V to +16.5V. VSS supply pins. Voltage range from -4.75V to -16.5V. Digital GND pins Digital supply pins. Voltage range from +2.7V to +5.25V. Reference GND supply for all the DACs. Reference voltage for channels 0-31 Reference output voltage Analog output voltages from the 32 channels. Analog input voltage Parallel Interface: 5 address pins for 32 channels. A4=MSB of channel address. A0=LSB Parallel Interface: Control input which allows all 32 channels to acquire VIN simulta neously This pin is both the active low Chip Select pin for the parallel interface and the Frame Synchronisation pin for the serial interface. Parallel Interface. Write pin. Active low. This is used in conjunction with the CS pin to address the device using the parallel interface. Offset Select pin. This is activated when writing to the DAC which provides its output at the OFFS_OUT pin. Serial Clock input for serial interface. This operates at clock speeds up to 20MHz Data input for serial interface. Data must be valid on the falling edge of SCLK Output from the DAC registers for readback. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low, the parallel interface will be used. If it is tied high, the serial interface will be used. Offset input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the user wants to drive this pin with the Offset Channel. Offset output. This is the acquired offset voltage which can be tied to OFFS_IN to offset the span. This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when the acquisition operation is complete. If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the gain/offset stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge of TRACK. See TRACK Input section for further information. This input can also be used as a means of resetting the complete device to its power-on-reset conditions. This is achieved by applying a low going pulse of between 50ns and 150ns to this pin. See section on RESET Function for further details. CS / SYNC WR 1 OFFSET_SEL 1 SCLK 2 DIN2 DOUT SER/PAR 1 OFFS_IN OFFS_OUT BUSY TRACK/RESET 2 NOTES: 1 Internal Pull-down devices on these logic inputs. Therfore, they can be left floating and will default to a logic low condition. 2 Internal Pull-up devices on these logic inputs. Therfore, they can be left floating and will default to a logic high condition. ­8­ REV. PrF AD5532-4/AD5532-5 AD5532-4/AD5532-5 Preliminary Technical Data Circuit Description Offset Voltage Channel The AD5532 AD5532 can be thought of as consisting of an ADC and 32 DACs in a single package. The input voltage VIN is sampled and converted into a digital word. The digital result is loaded into one of the DAC registers and is converted (with gain and offset) into an analog output voltage (VOUT0 - VOUT 31). Since the channel output voltage is effectively the output of a DAC there is no droop associated with it. As long as power is maintained to the device the output voltage will remain constant until this channel is addressed again. The offset voltage can be supplied externally by the user at OFFS_IN or it can be supplied by an additional offset voltage channel on the device itself. The required offset voltage is set up on VIN and acquired by the offset DAC. This offset channel's DAC output is connected directly to OFFS_OUT. By connecting OFFS_OUT to OFFS_IN this offset voltage can be used as the offset voltage for the 32 output amplifiers. It is important to choose the offset so that VOUT is within maximum ratings. To update a single channel's output voltage the required new voltage level is set up on the common input pin, VIN. The desired channel is then addressed via the parallel port or the serial port. When the channel address has been loaded, provided TRACK is high, the circuit begins to acquire the correct code to load to the DAC in order that the DAC output matches the voltage on VIN. The BUSY pin goes low and remains so until the acquistion is complete. The non-inverting input to the output buffer is tied to VIN during the acquisition period to avoid spurious outputs while the DAC acquires the correct code. The acquistion is completed in 16 µs max. Then BUSY pin goes high and the updated DAC output assumes control of the output voltage. The output voltage of the DAC is connected to the non-inverting input of the output buffer. The held voltage will remain on the output pin indefinitely, without drooping, as long as power is maintained to the device. On power-on, all the DACs, including the offset channel, are loaded with zeros. The outputs of the DACs are at 60mV and the outputs of the output buffers are at negative full-scale. If the OFFS_IN pin is driven by the onboard offset channel, the outputs VOUT0 to VOUT31 VOUT31 are also at 60mV on power-on since OFFS_IN = 60mV (VOUT=3.5*VDAC-2.5*VOFFS_IN=210mV-150mV=60mV). Output Buffer Stage - Gain and Offset The function of the output buffer stage is to translate the 0-3V output of the DAC to a wider range. This is done by gaining up the DAC output by 3.5 and offsetting the voltage by the voltage on OFFS_IN pin. VOUT = 3.5*VDAC - 2.5*VOFFS_IN VDAC is the output of the DAC VOFFS_IN is the voltage at the OFFS_IN pin The following table shows how the output range on VOUT relates to the Offset voltage supplied by the user: SAMPLE OUTPUT VOLTAGE RANGES VOFFS_IN (V) VDAC (V) VOUT(V) 0.5 1 0 to 3 0 to 3 Reset Function The reset function on the AD5532 AD5532 can be used to reset all nodes on this device to their power-on-reset condition. This is implemented by applying a low going pulse of between 50ns and 150ns to the TRACK/RESET pin on the device. If the applied pulse is less than 50ns it is taken as being a glitch and no operation takes place. If the applied pulse is wider than 150ns this pin adopts its track function on the selected channel, VIN is switched to the output buffer and an acquisition on the channel will not occur until a rising edge of TRACK. TRACK Function Normally in SHA mode of operation, TRACK is held high and the channel begins to acquire when it is addressed. However, if TRACK is low when the channel is addressed, VIN is switched to the output buffer and an acquisition on the channel will not occur until a rising edge of TRACK. At this stage the BUSY pin will go low until the acquisition is complete at which point the DAC assumes control of the voltage to the output buffer and VIN is free to change again without affecting this output value. This is useful in an application where the user wants to ramp up VIN until VOUT reaches a particular level (Figure 6). VIN doesn't need to be acquired continuously while it is ramping up. TRACK can be kept low and only when VOUT has reached its desired voltage is TRACK brought high. At this stage, the acquisition of VIN begins. In the example shown, a desired voltage is required on the output of the pin driver. This voltage is represented by one input to a comparator. The microcontroller/ microprocessor ramps up the input voltage on VIN through a DAC. TRACK is kept low while the voltage on VIN ramps up so that VIN is not continually acquired. When the desired voltage is reached on the output of the pin driver, the comparator output switches. The µC/µP then knows what code is required to be input in order to get the desired voltage at the DUT. The TRACK input is now brought high and the part begins to acquire VIN. BUSY goes low until VIN has been acquired. When BUSY goes high the output buffer is switched from VIN to the output of the DAC. -1.25 to 9.25 -2.5 to 8 VOUT is limited only by the headroom of the output amplifiers. VOUT must be within maximum ratings. ­9­ REV. PrF Preliminary Technical Data AD5532-4/AD5532-5 AD5532-4/AD5532-5 INTERFACE Serial Interface 2) Acquire and Readback Mode: This mode allows the user to acquire VIN and read back the data in a particular DAC register. The relevant DAC is addressed (10-bit write) and VIN is acquired in 16µs (max). Following the acquisition the next falling edge of SYNC clocks the data in the relevant DAC register out onto the DOUT line in a 14-bit serial format. The full acquisition time must elapse before the DAC register data can be clocked out. The serial interface is controlled by 4 pins. SYNC, DIN, SCLK: Standard 3-wire SPI interface pins. The SYNC pin is shared with the CS function of the parallel interface. DOUT: Data Out pin for reading back the contents of the DAC registers. The data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. The SER/PAR pin must also be tied high to enable the serial interface and to disable the parallel interface. Cal bit: This is used as a calibration instruction. When this is high all 32 channels acquire VIN simultaneously. Offset_Sel bit: Used to address the offset voltage control channel. Normally low. A4-A0: Used to address any one of the 32 channels (A4 = MSB of address, A0=LSB). DB13-DB0 DB13-DB0: These are used in both Readback modes to read a 14-bit word from the addressed DAC register. Parallel Interface Mode bits: The AD5532 AD5532 series can be used in 4 different modes. These modes are set by two Mode bits, the first 2 bits in the serial word. However DAC mode is not available for AD5532-4 AD5532-4 and AD5532-5 AD5532-5. To avail of DAC mode refer to the separate datasheet for AD5532-1 AD5532-1, AD5532-2 AD5532-2 and AD5532-3 AD5532-3. If you attempt to set up this mode the part will enter a test-mode and a 24 clock write is necessary to clear this. The parallel interface is controlled by 10 pins. CS: Active low package select pin. This pin is shared with the SYNC function for the serial interface. WR: Active low Write pin. The values on the address pins are latched on a rising edge of WR. A4-A0: 5 Address pins (A4=MSB of address, A0=LSB). These are used to address the relevant channel (out of a possible 32). Offset_Sel: Offset select pin. This has the same function as the Offset_Sel bit in the serial interface. When it is activated, the offset voltage control channel is addressed. The address on A4-A0 is ignored in this case. Cal: Same functionality as the Cal bit in the serial interface (calibration instruction). When this pin is active, all 32 channels acquire VIN simultaneously. MODES OF OPERATION Mode Bit 1 Mode Bit 2 0 0 1 1 0 1 0 1 Operating Mode SHA Mode DAC Mode (not available) Acquire and Readback Readback 1) SHA Mode: In this standard mode a channel is addressed and that channel acquires the voltage on VIN. This mode requires a 10-bit write to address the relevant channel (VOUT0-VOUT31 VOUT0-VOUT31, Offset Channel or all channels). C ON TRO LLER DAC V in AC Q U ISITIO N C IRC U IT 3) Readback Mode Again, this is a readback mode but no acquisition is performed. The relevant DAC is addressed (10-bit write) and on the next falling edge of SYNC, the data in the relevant DAC register is clocked out onto the DOUT line in a 14-bit serial format. The serial write and read words can be seen in Figure 7. This feature allows the user to readback the DAC register code of any of the DACs. Readback is useful if the system has been calibrated and the user wants to know what code in the DAC corresponds to a desired voltage on VOUT. The SER/PAR bit must be tied low to enable the parallel interface and disable the serial interface. O U TPU T STAG E V out 1 PIN D R IV ER + - BUSY D E VIC E U ND ER TE ST TRAC K Threshold Voltage *O nly one channel shown for simplicity Figure 6. Typical ATE circuit using TRACK Input ­10­ REV. PrF AD5532-4/AD5532-5 AD5532-4/AD5532-5 Preliminary Technical Data MSB LSB 0 0 Cal 0 O ffs et_ S e l A 4 -A 0 T est B it M ode B it1 M ode B it2 M o d e B its 10-Bit Input Serial Write Word (SHA Mode) MSB LSB 1 0 Cal O ffs e t_ S e l 0 MSB + A 4 -A 0 LSB D B 1 3 -D B 0 T e s t B it M o d e B its 1 0 -B it S eria l w o rd w ritte n to p a rt 1 4 -B it D a ta rea d fro m p a rt a fte r n e x t fa llin g e d g e o f S Y N C (D B 1 3 = M S B o f D A C W o rd ) Input Serial Interface (Acquire and Readback Mode) MSB 1 LSB 1 0 O ffs et _ S e l 0 A4 -A 0 MSB + LSB D B 1 3 -D B 0 T e s t B it M o d e B its 1 0-B it S e ria l w o rd w ritten to p a rt 1 4-B it D a ta re a d fro m p a rt a fte r n e x t fa llin g e d g e o f S Y N C (D B 1 3 = M S B o f D A C W o rd ) Input Serial Interface (Readback Mode) Figure 7. Serial Interface Formats ­11­ REV. PrF Preliminary Technical Data AD5532-4/AD5532-5 AD5532-4/AD5532-5 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J A B C D E F G H J K L K L 1 2 3 4 5 6 7 8 9 10 11 AD5532 AD5532 74-LEAD 74-LEAD LFBGA BALL CONFIGURATION LFBGA Number Ball Name LFBGA Number Ball Name LFBGA Number Ball Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C6 N/C A4 A2 A0 CS/SYNC DVCC SCLK OFFSET_SEL BUSY TRACK/RESET N/C VO16 N/C A3 A1 WR DGND DIN CAL SER/PAR DOUT REF_IN VO18 DAC_GND1 N/C C10 C11 D1 D2 D10 D11 E1 E2 E10 E11 F1 F2 F10 F11 G1 G2 G10 G11 H1 H2 H10 H11 J1 J2 J6 AVCC1 REF_OUT VO20 DAC_GND2 AVCC2 OFFS_OUT VO26 VO14 AGND1 OFFS_IN VO25 VO21 AGND2 VO6 VO24 VO8 VO5 VO3 VO23 VIN VO4 VO7 VO22 VO19 VSS2 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 VO9 VO11 VO17 VO15 VO27 VSS3 VSS1 VSS4 VDD2 VO2 VO10 VO13 VO12 N/C VO28 VO29 VO30 VDD3 VDD1 VDD4 VO31 VO0 VO1 N/C ­12­ REV. PrF AD5532-4/AD5532-5 AD5532-4/AD5532-5 Preliminary Technical Data OUTLINE DIMENSIONS Dimensions shown in mm. 74-lead LFBGA 10.00BSC 00BSC BOT T OM 11 10 9 8 7 6 5 4 3 2 1 VIEW 12.00 A B A1 TO P VIEW 12.00 C D E F G 1.00 BSC 10.00B H J K L 1.00 BS C D ETA IL A 0.85m in 1.70max 0.25m in SEAT ING PLAN E ­13­ 0.60BSC 60BSC BALL DIA M ET ER REV. PrF