AD2S82A AD2S81A AD2S81A/AD2S82A 16-BIT DB9-DB16 2N3904 IN4148 AD2S81A/ OSC1758 - Datasheet Archive

 

Monolithic (BiMOS ll) Tracking R/D Converter Ratiometric Conversion Low Power Consumption: 300 mW typ Dynamic Performance Set by

 

FEATURES Monolithic (BiMOS ll) Tracking R/D Converter Ratiometric Conversion Low Power Consumption: 300 mW typ Dynamic Performance Set by User Velocity Output ESD Class 2 Protection (2,000 V min) AD2S82A AD2S82A FUNCTIONAL BLOCK DIAGRAM AC ERROR DEMOD DEMOD O/P I/P O/P AD2S82A AD2S82A SIN I/P AD2S82A AD2S82A 44-Pin PLCC Package 10-, 12-, 14- and 16-Bit Resolution Set by User High Max Tracking Rate 1040 RPS (10 Bits) VCO Output (Inter LSB Output) Data Complement Facility APPLICATIONS DC Brushless and AC Motor Control Process Control Numerical Control of Machine Tools Robotics Axis Control GENERAL DESCRIPTION The AD2S82A AD2S82A is a monolithic 10-, 12-, 14- or 16-bit tracking resolver-to-digital converter contained in a 44-pin J leaded PLCC package. Two extra functions are provided in the new surface mount package­COMPLEMENT and VCO output. The AD2S81A AD2S81A is a monolithic 12-bit fixed resolution tracking resolver-to-digital converter packaged in a 28-pin DIP. The converters allow users to select their own dynamic performance with external components. This allows the users great flexibility in defining the converter that best suits their system requirements. The AD2S82A AD2S82A allows users to select the resolution to be 10, 12, 14 or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution. The AD2S81A AD2S81A and AD2S82A AD2S82A convert resolver format input signals into a parallel natural binary digital word using a ratiometric tracking conversion method. This ensures high-noise immunity and tolerance of lead length when the converter is remote from the resolver. The output word is in a three-state digital logic form available in 2 bytes on the 16 output data lines for the AD2S82A AD2S82A and on 8 output data lines for the AD2S81A AD2S81A. BYTE SELECT, ENABLE and INHIBIT pins ensure easy data transfer to 8- and 16-bit data buses, and outputs are provided to allow for cycle or pitch counting in external counters. A1 SEGMENT SWITCHING SIG GND COS I/P AD2S81A AD2S81A 28-Pin DIP Package Low Cost INTEGRATOR I/P A3 a Variable Resolution, Monolithic Resolver-to-Digital Converters AD2S81A/AD2S82A AD2S81A/AD2S82A R-2R DAC A2 PHASE SENSITIVE DETECTOR INTEGRATOR O/P ANALOG GND RIPPLE CLK +12V 16-BIT 16-BIT UP /DOWN COUNTER ­12V VCO DATA TRANSFER LOGIC VCO I/P INHIBIT VCO O/P OUTPUT DATA LATCH COMP DATA SC1 SC2 LOAD ENABLE 16 DATA BITS +5V DIG BUSY DIR BYTE GND SELECT An analog signal proportional to velocity is also available and can be used to replace a tachogenerator. PRODUCT HIGHLIGHTS Monolithic. A one-chip solution reduces the package size required and increases the reliability. Resolution Set by User. Two control pins are used to select the resolution of the AD2S82A AD2S82A to be 10, 12, 14 or 16 bits allowing the user to use the AD2S82A AD2S82A with the optimum resolution for each application. Ratiometric Tracking Conversion. Conversion technique provides continuous output position data without conversion delay and is insensitive to absolute signal levels. It also provides good noise immunity and tolerance to harmonic distortion on the reference and input signals. Dynamic Performance Set by the User. By selecting external resistor and capacitor values the user can determine bandwidth, maximum tracking rate and velocity scaling of the converter to match the system requirements. The external components required are all low cost, preferred value resistors and capacitors, and the component values are easy to select using the simple instructions given. Velocity Output. An analog signal proportional to velocity is available and is linear to typically one percent. This can be used in place of a velocity transducer in many applications to provide loop stabilization in servo controls and velocity feedback data. Low Power Consumption. Typically only 300 mW. MODELS AVAILABLE Information on the models available is given in the section "Ordering Information." REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD2S81A/AD2S82A AD2S81A/AD2S82A­SPECIFICATIONS (@ T = +25C, unless otherwise noted) A Parameter Conditions SIGNAL INPUTS Frequency Voltage Level Input Bias Current Input Impedance Maximum Voltage Min AD2S81A AD2S81A Typ Max 400 1.8 1.0 REFERENCE INPUT Frequency Voltage Level Input Bias Current Input Impedance 60 20,000 8.0 150 1.0 (Signals to Reference) 10 Bits 12 Bits 14 Bits 16 Bits User Selectable Bandwidth1 1 +10 ­10 Units 20,000 H J K L Monotonicity Guaranteed Monotonic Missing Codes (16-Bit Resolution) J, K L 20,000 ±1 3 ±2 6 Hz V pk nA M 1 1040 260 65 16.25 LSB Degrees rps rps rps rps 22 + 1 LSB 8 + 1 LSB 4 + 1 LSB 2 + 1 LSB 50 arc min arc min arc min arc min Codes Code * * * * 30 + 1 LSB 10 ± 10.5 1.5 1.0 * * * * * * * * % FSD % FSD mV µV/°C % FSD V % rms O/P k ± 10.4 * * V mA 3 * LSTTL 600 * ns 35 110 * ns 60 INPUT/OUTPUT PROTECTION Analog Inputs Analog Outputs Over Full Range Hz V rms nA M V pk * * * * 260 ACCURACY Angular Accuracy VELOCITY SIGNAL Linearity Reversion Error DC Zero Offset2 DC Zero Offset Tempco Gain Scaling Accuracy Output Voltage Dynamic Ripple Output Load 50 ±8 400 1.0 CONTROL DYNAMICS Repeatability Allowable Phase Shift Tracking Rate AD2S82A AD2S82A Typ Max 4 1 2.0 60 20,000 2.2 150 Min 140 * ns ­22 1 mA Load Mean Value Overvoltage Protection Short Circuit O/P Protection DIGITAL POSITION Resolution Output Format Load ±9 ± 5.6 ±8 ±8 10, 12, 14 and 16 Bidirectional Natural Binary INHIBIT3 Sense Time to Stable Data ±8 Logic LO to Inhibit ENABLE 3 Logic LO Enables Position Output. Logic HI Outputs in High Impedance State ENABLE/Disable Time BYTE SELECT3 Sense Logic HI MS Byte DB1-DB8, (LS Byte DB9-DB16 DB9-DB16)4 LS Byte DB1-DB8, (LS Byte DB9-DB16 DB9-DB16)4 Logic LO Time to Data Available 4 SHORT CYCLE INPUTS SC1 0 0 1 1 SC2 0 1 0 1 DATA LOAD4 Sense Internally Pulled High (100 k) to +VS 10 Bit 12 Bit 14 Bit 16 Bit Internally Pulled High (100 k) to +VS; Logic LO Allows Data to Be Loaded into the Counters from the Data Lines 150 ­2­ 300 ns REV. A AD2S81A/AD2S82A AD2S81A/AD2S82A Parameter Conditions COMPLEMENT4 AD2S81A AD2S81A Typ Max Min AD2S82A AD2S82A Typ Max Internally Pulled High (100 k) to +VS; Logic LO to Activate; No Connect for Normal Operation BUSY3 Sense Width Load Min Units Logic HI When Position O/P Changing 600 1 DIRECTION3 Sense * * ns LSTTL 3 200 Use Additional Pull-Up * LSTTL Logic HI Counting Up Logic LO Counting Down Max Load 3 RIPPLE CLOCK Sense Width Reset Load DIGITAL INPUTS High Voltage, VIH Low Voltage, VIL DIGITAL INPUTS High Current, IIH Low Current, IIL DIGITAL INPUTS Low Voltage, VIL Low Current, IIL DIGITAL OUTPUTS High Voltage, VOH Low Voltage, VOL THREE-STATE LEAKAGE Current IL POWER SUPPLIES Voltage Levels +VS ­VS +VL` Current +IS +IS +IL Logic HI, All 1s to All 0s All 0s to All 1s Dependent On Input Velocity Before Next Busy * 300 3 * LSTTL * V 0.8 * V INHIBIT, ENABLE DB1­DB16 ± VS = ± 13.2 V, VL = 5.5 V INHIBIT, ENABLE DB1­DB16, Byte Select ± VS = ± 13.2 V, VL = 5.5 V 100 * µA 100 * µA ENABLE = HI SC1, SC2, Data Load ± VS = ± 12.0 V, VL = 5.0 V ENABLE = HI SC1, SC2, Data Load ± VS = ± 12.0 V, VL = 5.0 V 1.0 * V ­400 * µA * V 0.4 * V ± 100 * µA ± 100 * µA +13.2 ­13.2 +13.2 * * * V V V 23 30 1.5 * * * mA mA mA INHIBIT, ENABLE DB1­DB16, Byte Select ± VS = ± 10.8 V, VL = 5.0 V INHIBIT, ENABLE DB1­DB16, Byte Select ± VS = ± 13.2 V, VL = 5.0 V 2.0 DB1­DB16; RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 4.5 V IOH = 100 µA DB1­DB16, RIPPLE CLK, DIR ± VS = ± 12.0 V, VL = 5.5 V IOL = 1.2 mA 2.4 DB1­DB16 Only +VS = ± 12.0 V, VL = 5.5 V VOL = 0 V +VS = ± 12.0 V, VL = 5.5 V VOH = 5.0 V +10.8 ­10.8 +5 ± VS @ ± 12 V ± VS @ ± 13.2 V ± VL @ ± 5.0 V 12 19 0.5 NOTES 1 Refers to small signal bandwidth. 2 Output offset dependent on value for R6. 3 Refer to timing diagram. 4 AD2S82A AD2S82A only. *Specifications same as AD2S81A AD2S81A. Specifications subject to change without notice. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. REV. A ­3­ AD2S81A/AD2S82A AD2S81A/AD2S82A­SPECIFICATIONS (typical @ +25C unless otherwise noted) Parameter RATIO MULTIPLIER AC Error Output Scaling PHASE SENSITIVE DETECTOR Output Offset Voltage Gain In Phase In Quadrature Input Bias Current Input Impedance Input Voltage INTEGRATOR Open-Loop Gain Dead Zone Current (Hysteresis) Input Offset Voltage Input Bias Current Output Voltage Range VCO Maximum Rate VCO Rate VCO Power Supply Sensitivity Increase Decrease Min AD2S81A AD2S81A Typ Max 10 Bit 12 Bit 14 Bit 16 Bit w.r.t. REF w.r.t. REF ­0.882 ­0.9 60 ± VS = ± 10.8 V dc 177.6 44.4 11.1 2.775 mV/Bit mV/Bit mV/Bit mV/Bit * mV ­0.918 0.04 150 * * * * * V rms/V dc V rms/V dc nA M V dB nA/LSB mV nA V ±8 57 63 ±7 100 1 60 5 150 * * * * 1.1 7.9 7.9 8.7 8.7 * * * MHz kHz/µA kHz/µA * * * * * * * * %/V %/V %/V %/V mV nA nA/°C V * * * * % FSD % FSD % FSD %/V of Asymmetry V/LSB ± VS = ± 12 V dc Positive DIR Negative DIR 1.0 7.1 7.1 +0.5 ­8.0 ­8.0 +2.0 1 70 ­1.22 +VS ­VS +VS ­VS Input Offset Voltage Input Bias Current Input Bias Current Tempco Input Voltage Range Linearity of Absolute Rate Full Range Over 0% to 50% of Full Range Reversion Error Sensitivity of Reversion Error to Symmetry of Power Supplies VCO Output1, 2 POWER SUPPLIES Voltage Levels +VS ­VS +VL Current +IS +IS +IL Units Min * 1 At 10 kHz AD2S82A AD2S82A Typ Max 12 Conditions ±8 5 380 ±8