AD1815 MPU-401 16-BIT 12/FS 18/FS AD1815JS S-100 AD1843 MPU401 PNPB006 PNPB02F - Datasheet Archive

 

SoundComm Controller AD1815 1 Hz Resolution Programmable Sample Rates from 4 kHz to 55.2 kHz Bidirectional DSP Serial Port Power

 

a SoundComm Controller AD1815 AD1815 1 Hz Resolution Programmable Sample Rates from 4 kHz to 55.2 kHz Bidirectional DSP Serial Port Power Management Modes Operation from +5 V Supply Built-In 24 mA Bus Drivers 100-Pin PQFP Package FEATURES Supports Applications Written for SoundBlaster* Pro, AdLib/OPL3 Win 3.1, Win 95 Stereo Audio 16-Bit Codec MPC Level-2/3 Mixer ISA Plug and Play Compatible Dual Type F FIFO DMA Support MPU-401 MPU-401 Compatible MIDI Port Integrated V.34, Modem Analog Front End Integrated Enhanced Digital Game Port Supports Wavetable Synthesizers Two I 2S Digital Audio Serial Port Inputs Software & Hardware Volume Control Integrated FM Compatible Music Synthesizer Full-Duplex Capture and Playback Operation at Different Sample Rates Supports Up to Six Different Sample Rates Simultaneously Supports Voice Over Data PRODUCT OVERVIEW The AD1815 AD1815 SoundCommTM Controller is a single chip Plug and Play audio subsystem for adding 16-bit stereo audio and communications support to personal computers. The AD1815 AD1815 is compatible with applications written for SoundBlaster Pro and AdLib/OPL3. The AD1815 AD1815 provides an integrated audio solution for Windows 95, Windows 3.1, DirectSound and multimedia applications. The AD1815 AD1815 supports telephony and advanced audio applications by providing a V.34 compatible modem analog front end and a serial port linking a companion media pump or DSP to the subsystem. The AD1815 AD1815 on-chip Plug and Play hardware provides configuration services for all integrated logical devices. OSCILLATORS VOLUME CONTROL MUTE MDM_IN 0dB/ 20dB MIC AGC WSS SB PRO REGISTER B_Y A_Y A_2 B_2 A_X B_X A_1 MPU-401 MPU-401 B_1 MIDI_OUT MIDI_IN VOL_UP XTALO XTALI AD1815 AD1815 VOL_DN FUNCTIONAL BLOCK DIAGRAM GAME PORT CD VID PGA 16-BIT 16-BIT A/D CONVERTER FIFO FORMAT MUSIC SYNTHESIZER M G A M G A M G A M R_OUT M MV MDMP_OUT G = GAIN A = ATTENUATE A M = MUTE M MV = MASTER VOLUME MONO_IN MDMN_OUT DIF. M M G A M A A FORMAT 16-BIT 16-BIT D/A CONVERTER M A M PC_D (7:0) PC_A (11:0) AEN DACK (X) IOR IOW I2S SERIAL PORT (0) BCLK (0) LRCLK (0) DATA (0) BCLK (1) LRCLK (1) DATA (1) A DIGITAL PLL 16-BIT 16-BIT D/A CONVERTER SoundComm is a trademark of Analog Devices, Inc. *SoundBlaster is a registered trademark of Creative Labs. AdLib is a trademark of AdLib Multimedia and OPL is a registered trademark of Yamaha Corporation. DirectSound is a trademark of Microsoft Corp. FIFO IRQ (X) I2S SERIAL PORT (1) A M DSP SERIAL PORT DRQ (X) PCLKO SDFFS SCLK MV L_OUT G A M SDI SDO G A M PLUG AND PLAY ISA BUS PARALLEL INTERFACE SELECTOR LINE SYNTH REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD1815 AD1815 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SERIAL INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ISA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 APPENDIX A Additional Plug and Play Programming Information . . . . 41 Plug and Play Key & "Alternate Key" Sequences . . . . . . . 42 Reference Designs and Device Drivers . . . . . . . . . . . . . . . 43 FIGURES Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. PIO Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. PIO Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. DMA Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. DMA Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. Codec Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. DSP Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. I2S Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Reset Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. Serial Interface Right-Justified Mode . . . . . . . . . . 18 Figure 10. Serial Interface I2S-Justified Mode . . . . . . . . . . . 18 Figure 11. Serial Interface Left-Justified Mode . . . . . . . . . . 18 Figure 12. DSP Serial Interface (Default Frame Rate) . . . . 21 Figure 13. DSP Serial Interface (User Programmed Frame Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14. DSP Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15. Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 16. AD1815 AD1815 Frequency Response Plots . . . . . . . . . . . 43 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 TABLES Table I. Modem Disabled Timeslot Map . . . . . . . . . . . . . . Table II. Chip Register Diagram . . . . . . . . . . . . . . . . . . . . . Table III. Logical Devices and Compatible Plug and Play Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . Table IV. Logical Device Configuration . . . . . . . . . . . . . . . Table V. Sound System Direct Registers . . . . . . . . . . . . . . . Table VI. Codec Transfers . . . . . . . . . . . . . . . . . . . . . . . . . Table VII. Indirect Register Map and Reset/Default States Table VIII. Sound System Indirect Registers . . . . . . . . . . . Table IX. Sound Blaster Pro ISA Bus Register . . . . . . . . . . Table X. Adlib ISA Bus Register . . . . . . . . . . . . . . . . . . . . . Table XI. MIDI ISA Bus Register . . . . . . . . . . . . . . . . . . . . Table XII. Game Port ISA Bus Registers . . . . . . . . . . . . . . 19 22 23 24 24 28 31 32 39 39 40 40 ­2­ REV. 0 AD1815 AD1815 SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (FS) Audio Modem Input Signal Audio Output Passband Modem Output Passband VIH VIL 25 5.0 5.0 °C V V 48 kHz 12.8 kHz 1008 Hz 20 Hz to 20 kHz 400 Hz to 4.2 kHz 5.0 V 0 V DAC Test Conditions Calibrated 0 dB Attenuation Input Full Scale 16-Bit Linear Mode 100 k Output Load Mute Off Measured at Line Output ADC Test Conditions Calibrated 0 dB Gain Input ­1.0 dB Relative to Full Scale Line Input Selected 16-Bit Linear Mode ANALOG INPUT Parameter Min Full-Scale Input Voltage (RMS Values Assume Sine Wave Input) MONO_IN, LINE, SYNTH, CD, VID Typ Max 1 2.83 3.156 0.1 0.283 1 2.83 17 15 MDM_IN MIC with +20 dB Gain (MGE = 1) MIC with 0 dB Gain (MGE = 0) Input Impedance* Input Capacitance* Units V rms V p-p V p-p V rms V p-p V rms V p-p k pF PROGRAMMABLE GAIN AMPLIFIER-ADC Parameter Min Typ Max Units Step Size (0 dB to 22.5 dB) (All Steps Tested) PGA Gain Range Span 1.3 21.5 1.5 22.5 1.7 23.5 dB dB CD, LINE, MICROPHONE, MODEM, SYNTHESIZER, AND VIDEO INPUT ANALOG GAIN/ AMPLIFIERS/ATTENUATORS Parameter Min REV. 0 Units 1.5 1.5 46.5 1.7 2.0 47.5 dB dB dB 2.6 43 ­3­ Max 1.3 1.0 45.5 CD, LINE, MIC, SYNTH, VID, MDM_IN Step Size: (All Steps Tested) +12 dB to ­31.5 dB ­33 dB to ­34.5 dB Input Gain/Attenuation Range MONO_IN Step Size 0 dB to ­45 dB: (All Steps Tested) Input Gain/Attenuation Range Typ 3.0 45 3.4 46 dB dB AD1815 AD1815 DIGITAL DECIMATION AND INTERPOLATION FILTERS* Parameter Min Audio Passband Audio Passband Ripple Audio Transition Band Audio Stopband Audio Stopband Rejection Modem Passband Modem Passband Ripple Modem Transition Band Modem Stopband Modem Stopband Rejection (3 dB Roll Off After Stop Band Edge) Audio Group Delay Modem Group Delay Group Delay Variation Over Passband Typ 0 Units 0.4 × FS ± 0.09 0.6 × FS 12/FS 12/FS 18/FS 18/FS 0.0 0.4 × FS 0.6 × FS 82 0 Max Hz dB Hz Hz dB Hz dB Hz Hz dB sec sec µs Max Units 0.4 × FS ± 0.2 0.542 × FS 0.442 × FS 0.542 × FS 78 ANALOG-TO-DIGITAL CONVERTERS Parameter Min Resolution Audio Dynamic Range (­60 dB Input THD+N Referenced to Full-Scale, A-Weighted) Audio THD+N (Referenced to Full Scale) Typ 16 80 82 ­74 Modem Dynamic Range (­60 dB Input THD+N Referenced to Full Scale, FS = 12.8 kHz) Modem THD+N (Referenced to Full Scale, FS = 12.8 kHz) Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L Read L) Line to MIC (Input LINE, Ground and Select MIC, Read ADC) Line to SYNTH Line to CD Line to VID Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error ­4­ 85 Bits 0.036 ­70 89 ­75 85 ­90 ­90 ­90 ­90 ­90 dB % dB 0.025 ­72 dB % dB dB ­80 ­80 ­80 ­80 ­80 ± 10 ±1 ±5 dB dB dB dB dB % dB mV REV. 0 AD1815 AD1815 DIGITAL-TO-ANALOG CONVERTERS Parameter Min Resolution Audio Dynamic Range (­60 dB Input THD+N Referenced to Full Scale, A-Weighted) Audio THD+N (Referenced to Full Scale) Typ 16 80 82 Units Bits 82 ­78 Modem Dynamic Range (­60 dB Input THD+N Referenced to Full Scale, 4.2 kHz Analog Output Passband, Differential Output FS = 12.8 kHz) Modem THD+N (Referenced to Full Scale, FS = 12.8 kHz, Differential Output 4.2 kHz Analog Passband) Max 0.020 ­74 88 dB % dB dB ± 10 ± 0.5 dB ­45 dB ­75 Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) Total Out-of-Band Energy (Measured from 0.6 × FS to 100 kHz at L-OUT and R_OUT)* Audible Out-of-Band Energy (Measured from 0.6 × FS to 20 kHz at L-OUT and R_OUT)* % dB dB % dB ­80 ­88 90 0.008 ­82 dB MASTER VOLUME & MODEM ATTENUATOR Parameter Min Typ Max Units Master Volume Step Size (0 dB to ­22.5 dB) Master Volume Step Size (­22.5 dB to ­46.5 dB) Master Volume Output Attenuation Range Span Modem Volume Step Size (0 dB to ­31 dB) Modem Attenuation Range Mute Attenuation of 0 dB Fundamental* 1.3 1.0 45.5 0.8 30 80 1.5 1.5 46.5 1.0 31 1.7 2.0 47.5 1.2 32 dB dB dB dB dB dB Min Typ Max Units DIGITAL MIX ATTENUATORS Parameter 2 2 Step Size: I S (0), I S (1), Music, ISA* Digital Mix Attenuation Range Span* 1.505 94.8 dB dB ANALOG OUTPUT Parameter Min Full-Scale Output Voltage (at L_OUT and R_OUT ) Full-Scale Output Voltage MDMN_OUT (at MDMN_OUT, MDMP_OUT; Differential) Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance VREFX* VREFX Current Drive* VREFX Output Impedance* Mute Click (Muted Analog Mixers), Muted Output Minus Unmuted Output at 0 dB* REV. 0 ­5­ Typ Max 2.8 V p-p 6.312 800 10 15 2.10 2.25 100 6.5 ±5 Units 100 2.40 V p-p k pF pF V µA k mV AD1815 AD1815 SYSTEM SPECIFICATIONS* Parameter Min Typ Units 1.0 ±1 5 System Frequency Response Ripple (Line In to Line Out) Differential Nonlinearity Phase Linearity Deviation Max dB LSB Degrees Max Units STATIC DIGITAL SPECIFICATIONS Parameter Min High Level Input Voltage (VIH) XTALI Low Level Input Voltage (VIL) High Level Output Voltage (VOH), IOH = 8 mA Low Level Output Voltage (VOL), IOL = 8 mA Input Leakage Current Output Leakage Current Typ 2 2.4 +10 +10 V V V V V µA µA Max Units 5.25 5.25 193 965 35 158 2 23 0.2 10 V V mA mW mA mA mA mA mA mA 0.8 2.4 0.4 ­10 ­10 POWER SUPPLY Parameter Min Power Supply Range-Analog Power Supply Range-Digital Power Supply Current Power Dissipation Analog Supply Current Digital Supply Current Analog Power Supply Current-Powerdown Digital Power Supply Current-Powerdown Analog Power Supply Current-RESET Digital Power Supply Current-RESET Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs) Typ 4.75 4.75 40 dB CLOCK SPECIFICATIONS* Parameter Min Typ Input Clock Frequency Recommended Clock Duty Cycle Power Up Initialization Time 25 33 50 ­6­ Max Units 75 500 MHz % ms REV. 0 AD1815 AD1815 TIMING PARAMETERS (Guaranteed Over Operating Temperature Range) Parameter Symbol Min IOW/IOR Strobe Width IOW/IOR Rising to IOW/IOR Falling Write Data Setup to IOW Rising IOW Falling to Valid Read Data AEN Setup to IOW/IOR Falling AEN Hold from IOW/IOR Rising Adr Setup to IOW/IOR Falling Adr Hold from IOW/IOR Rising DACK Rising to IOW/IOR Falling Data Hold from IOR Rising Data Hold from IOW Rising DRQ Hold from IOW/IOR Falling DACK Hold from IOW/IOR Rising Data [SDI] Input Setup Time to SCLK* Data [SDI] Input Hold Time from SCLK* Frame Sync [SDFS] HI Pulse Width* Clock [SCLK] to Frame Sync [SDFS] Propagation Delay* Clock [SCLK] to Output Data [SDO] Valid* RESET Pulse Width BCLK HI Pulse Width BCLK LO Pulse Width BCLK Period LRCLK Setup SDATA Setup SDATA Hold tSTW tBWDN tWDSU tRDDV tAESU tAEHD tADSU tADHD tDKSU tDHD1 tDHD2 tDRHD tDKHD tS tH tFSW Typ Max Units 100 80 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40 10 0 10 0 20 20 15 25 10 10 10 80 tPD tDV tRPWL tDBH tDBL tDBP tDLS tDDS tDDH 15 15 ns ns ns ns ns ns ns ns ns 100 25 25 50 5 2 5 NOTES *Guaranteed, not tested. (All ISA pins MIDI_OUT IOL = 24 mA. Refer to pin description for individual output drive levels. Specifications subject to change without notice. DRQ (0, 1, 3) DRQ (0, 1, 3) tDKHD tDKSU tDKHD tDKSU DACK (0, 1, 3) DACK (0, 1, 3) tAESU tAEHD tAESU AEN tAEHD AEN tSTW tSTW IOW IOR tRDDV tWDSU tDHD1 tDHD2 PC_D [7:0] PC_D [7:0] tADSU tADSU tADHD tADHD PC_A [11:0] PC_A [11:0] Figure 1. PIO Read Cycle REV. 0 Figure 2. PIO Write Cycle ­7­ AD1815 AD1815 DRQ (0, 1, 3) tDRHD tDKSU SCLK tDKHD tFSW DACK (0, 1, 3) SDFS tAESU tAEHD tPD tH tS AEN BIT 0 BIT 14 BIT 15 SDI tSTW tDV IOR BIT 0 BIT 14 BIT 15 SDO tRDDV tDHD1 PC_D [7:0] Figure 6. DSP Port Timing Figure 3. DMA Read Cycle tDBH tDBP BCLK DRQ (0, 1, 3) tDBL tDLS tDRHD tDKSU tDKHD LRCLK DACK (0, 1, 3) tDDS SDATA LEFT-JUSTIFIED MODE tAEHD tAESU AEN MSB MSB-1 tDDH tDDS SDATA I 2 S-JUSTIFIED MODE tSTW MSB tWDSU tDDH SDATA RIGHT-JUSTIFIED MODE tDHD2 MSB PC_D [7:0] tDDH LSB tDDH Figure 7. I2S Serial Port Timing Figure 4. DMA Write Cycle tRPWL tBWDN RESET IOR/IOW DATA [7:0] tDDS tDDS IOW BYTE N N+1 N+2 N+3 Figure 8. Reset Pulse Width Figure 5. Codec Transfers ­8­ REV. 0 AD1815 AD1815 ENVIRONMENTAL CONDITIONS ABSOLUTE MAXIMUM RATINGS* Parameter Power Supplies Digital (VDD) Analog (VCC) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature Min Max Units ­0.3 ­0.3 6.0 6.0 ± 10.0 VCC + 0.3 VDD + 0.3 +70 +150 V V mA V V °C °C ­0.3 ­0.3 0 ­65 Ambient Temperature Rating: TAMB = TCASE ­ (PD × CA) TCASE = Case Temperature in °C PD = Power Dissipation in W CA = Thermal Resistance (Case-to-Ambient) JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) Package JA JC CA PQFP 77°C 7°C 70°C *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Option AD1815JS AD1815JS 0°C to +70°C 100-Lead PQFP S-100 S-100 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1815 AD1815 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 ­9­ WARNING! ESD SENSITIVE DEVICE AD1815 AD1815 IRQ (5) IRQ (7) PC_D (7) GNDD PC_D (6) PC_D (4) PC_D (5) VDD GNDD PC_D (2) PC_D (3) PC_D (0) PC_D (1) VDD SPORT_SCLK GNDD SPORT_SDFS SPORT_SDO I2S1_DATA SPORT_SDI PIN CONFIGURATIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I2S1_LRCLK 1 I2S1_BCLK 2 80 IRQ (9) PIN 1 IDENTIFIER 79 IRQ (11) I2S0_DATA 3 78 IRQ (12) I2S0_LRCLK 4 77 IRQ (15) I2S0_BCLK 5 76 DRQ (0) PC_A (11) 6 75 DRQ (1) PC_A (10) 7 74 DRQ (3) PC_A (9) 8 73 VDD PC_A (8) 9 72 GNDD PC_A (7) 10 71 XCTL1/RING PC_A (6) 11 70 XCTL0/PCLKO PC_A (5) 12 69 MIDI_OUT PC_A (4) 13 68 MIDI_IN PC_A (3) 14 67 GNDD AD1815 AD1815 PC_A (2) 15 66 XTALO TOP VIEW (Not to Scale) PC_A (1) 16 65 XTALI PC_A (0) 17 64 VDD AEN 18 63 DACK (0) IOW 19 62 DACK (1) IOR 20 61 DACK (3) VDD 21 60 VOL_UP GNDD 22 59 VOL_DWN A_1 23 58 RESET A_2 24 57 MDMN_OUT B_1 25 56 MDMP_OUT B_2 26 55 L_OUT GNDG 27 54 R_OUT A_X 28 53 MONO_IN A_Y 29 52 VCC B_X 30 51 GNDA ­10­ VREF VREF_X L_VID R_VID L_SYNTH R_SYNTH L_CD R_CD MDM_IN MIC L_LINE R_LINE L_AAFILT R_AAFILT L_FILT R_FILT VCC GNDA B_Y VDDG 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 REV. 0 AD1815 AD1815 PIN DESCRIPTIONS Analog Signals Pin Name PQFP I/O Description MDM_IN 42 I MIC 41 I L_LINE 40 I R_LINE 39 I L_SYNTH 46 I R_SYNTH 45 I L_CD 44 I R_CD 43 I L_VID 48 I R_VID 47 I L_OUT 55 O R_OUT 54 O MDMN_OUT MDMP_OUT MONO_IN 57 56 53 O O I Modem Input mono telephony signal from DAA. The input may be sent to the right channel of the ADC if the AD1815 AD1815 is in modem mode; gained or attenuated from +12 dB to ­34.5 dB in 1.5 dB steps and then summed with left and right line out (L_OUT and R_OUT). Microphone Input. The MIC input may be either line-level or ­20 dB from line-level (the difference being made up through a software controlled 20 dB gain block). The mono MIC input may be sent to the left and right channel of the ADC for conversion, or gained/ attenuated from +12 dB to ­34.5 dB in 1.5 dB steps and then summed with left and right line out (L_OUT and R_OUT), before the Master Volume stage. Left Line-Level Input. The left line-level input may be: sent to the left channel of the ADC; gained/attenuated from +12 dB to ­34.5 dB in 1.5 dB steps and then summed with left line out (L_OUT). Right Line-Level Input. The right line-level input may be: sent to the right channel of the ADC; gained/attenuated from +12 dB to ­34.5 dB in 1.5 dB steps and then summed with right line out (R_OUT). Left Synthesizer Input. The left MIDI upgrade line-level input may be: sent to the left channel of the ADC; gained/attenuated from +12 dB to ­34.5 dB in 1.5 dB steps and then summed with left line out (L_OUT). Right Synthesizer Input. The right MIDI upgrade line-level input may be: sent to the right channel of the ADC; gained/attenuated from +12 dB to ­34.5 dB in 1.5 dB steps and then summed with right line out (R_OUT). Left CD Line-Level Input. The left CD line-level input may be: sent to the left channel of the ADC; gained/attenuated from +12 dB to ­34.5 dB in 1.5 dB steps and then summed with left line out (L_OUT). Right CD Line-Level Input. The right CD line-level input may be: sent to the right channel of the ADC; gained/attenuated from +12 dB to ­34.5 dB in 1.5 dB steps and then summed with right line out (R_OUT). Left Video Input. The left audio track for a video line-level input may be: sent to the left channel of the ADC; gained/attenuated from +12 dB to ­34.5 dB in 1.5 dB steps and then summed with left line out (L_OUT). Right Video Input. The right audio track for a video line-level input may be: sent to the right channel of the ADC; gained/attenuated from +12 dB to ­34.5 dB in 1.5 dB steps and then summed with right line out (R_OUT). Left Output. Left channel line-level post-mixed output. The final stage passes through the Master Volume block and may be attenuated 0 dB to ­45 dB in 1.5 dB steps. Right Output. Right channel line-level post-mixed output. The final stage passes through the Master Volume block and may be attenuated 0 dB to ­45 dB in 1.5 dB steps. Differential Modem Output Negative. Differential Modem Output Positive. Mono Line-Level Input. REV. 0 ­11­ AD1815 AD1815 Parallel Interface (All Outputs are 24 mA Drivers) Pin Name PQFP I/O Description PC_D[7:0] 84­87, 90­93 I/O IRQ(x) 77­82 O DRQ(x) 74­76 O PC_A[11:0] AEN DACK (x) 6­17 18 61­63 I I I IOR IOW RESET 20 19 58 I I I Bidirectional ISA Bus PC Data, 24 mA drive. Connects the AD1815 AD1815 to the low byte data on the bus. Host Interrupt Request, 24 mA drive. IRQ(5), IRQ(7), IRQ(9), IRQ(11), IRQ(12), IRQ(15). Active HI signals indicating a pending interrupt. These signals are always edge triggered, not level triggered. DMA Request, 24 mA drive. DRQ(0), DRQ(1), DRQ(3). Active HI signals indicating a request for DMA bus operation. ISA Bus PC Address. Connects the AD1815 AD1815 to the ISA bus address lines. Address Enable. Low signal indicates a PIO transfer. DMA Acknowledge. DACK(0), DACK(1), DACK(3). Active LO signal indicating that a DMA operation can begin. I/O Read. Active LO signal indicates a read operation. I/O Write. Active HI signal indicates a write operation. Reset. Active HI. Pin Name PQFP I/O Description A_1 A_2 A_X A_Y B_1 B_2 B_X B_Y 23 24 28 29 25 26 30 31 I I I I I I I I Game Port A, Button #1. Game Port A, Button #2. Game Port A, X-Axis. Game Port A, Y-Axis. Game Port B, Button #1. Game Port B, Button #2. Game Port B, X-Axis. Game Port B, Y-Axis. Game Port MIDI Interface Signal (24 mA Drivers) Pin Name PQFP I/O Description MIDI_IN 68 I MIDI_OUT 69 O RXD MIDI Input. This pin is typically connected to Pin 15 of the game port connector via an optoisolator. TXD MIDI Output. This pin is typically connected to Pin 12 of the game port connector to form a 5 mA current loop. ­12­ REV. 0 AD1815 AD1815 Serial Ports (8 mA Drivers) Pin Name PQFP I/O Description I2S0_BCLK I2S0_LRCLK I2S0_DATA I2S1_BCLK I2S1_LRCLK I2S1_DATA SPORT_SDI SPORT_SCLK SPORT_SDFS SPORT_SDO 5 4 3 2 1 100 99 96 97 98 I I I I I I I O O O I2S (0) Bit Clock. I2S (0) Left/Right Clock. I2S (0) Serial Data Input. I2S (1) Bit Clock. I2S (1) Left/Right Clock. I2S (1) Serial Data Input. Serial Port Digital Serial Input. Serial Port Serial Clock. Serial Port Serial Data Frame Synchronization. Serial Port Serial Data Output. Miscellaneous Analog Pins Pin Name PQFP I/O Description VREF_X 49 O VREF 50 I L_FILT R_FILT L_AAFILT 36 35 38 I I I R_AAFILT 37 I Voltage Reference. Nominal 2.25 volt reference available for dc-coupling and level-shifting. VREF_X should not be used to sink or source signal current. Voltage Reference Filter. Voltage reference filter point for external bypassing only. Left Channel Filter. Requires a 1.0 µF to analog ground for proper operation. Right Channel Filter. Requires a 1.0 µF to analog ground for proper operation. Left Channel Antialias Filter. This pin requires a 270 pF NPO capacitor to analog ground for proper operation. Right Channel Antialias Filter. This pin requires a 270 pF NPO capacitor to analog ground for proper operation. Pin Name PQFP I/O Description XTALO XTALI 66 65 O I 33 MHz Crystal Output. If no Crystal is present leave XTALO unconnected. 33 MHz Clock. When using a crystal as a clock source, the crystal should be connected between the XTALI and XTALO pins. Clock input may be driven into XTALI in place of a crystal. When using an external clock, VIH must be 2.4 V rather than the VIH of 2.0 V specified for all other digital inputs. Crystal Pin REV. 0 ­13­ AD1815 AD1815 Hardware Volume Pins Pin Name PQFP I/O Description VOL_DWN 59 I VOL_UP 60 I Master Volume Down. Modifies output level on pins L_OUT and R_OUT. Contains a 10 k internal pull-up resistor. When asserted LO, decreases Master Volume by 1.5 dB/sec. Must be asserted at least 25 ms to be recognized. When asserted simultaneously with VOL_UP, output is muted. Output level modification reflected in indirect register 0 × 29. Master Volume Up. Modifies output level on pins L_OUT and R_OUT. Contains a 10 k internal pull-up resistor. When asserted LO, increases Master Volume by 1.5 dB/sec. Must be asserted at least 25 ms to be recognized. When asserted simultaneously with VOL_UP, output is muted. Output level modification reflected in indirect register 0 × 29. Muxed Control Pins Pin Name PQFP I/O Description XCTL0 70 O PCLKO 70 O XCTL1 71 O RING 71 I External Control 0. The state of this pin (TTL HI or LO) is reflected in codec indexed register. This pin is an open drain driver. Programmable Clock Output. This pin can be programmed to generate an output clock equal to FS, 8 × FS, 16 × FS, 32 × FS, 64 × FS, 128 × FS or 256 × FS. MPEG decoders typically require a master clock of 256 × F S for audio synchronization. External Control 1. The state of this pin (TTL HI or LO) is reflected in codec indexed register. Open drain, 8 mA active 0.5 mA internal pull-up resistor. Ring Indicator. Used to accept the ring indicator flag from the DAA. Pin Name PQFP I/O Description VCC GNDA VDD 33, 52 34, 51 21, 64, 73, 88, 94 22, 67, 72, 83, 89, 95 32 27 I I Analog Supply Voltage (+5 V). Analog Ground. I Digital Supply Voltage (+5 V). I I I Digital Ground. Game Port Digital Supply Voltage (+5 V). Game Port Digital Ground. Power Supplies GNDD VDDG GNDG ­14­ REV. 0 AD1815 AD1815 HOST INTERFACE For supporting time correlated I/O echo cancellation, the ADC is capable of sampling microphone data on the left channel and the mono summation of left and right OUT on the right channel. The AD1815 AD1815 contains all necessary ISA bus interface logic on chip. This logic includes address decoding for all onboard resources, control and signal interpretation, DMA selection and control logic, IRQ selection and control logic, and all interface configuration logic. The codec can operate either in global stereo mode or in a global mono mode with left channel inputs appearing at both channels of the 16-bit converters. Data can be sampled at the programmed sampling frequency (from 4 kHz to 55.2 kHz with 1 Hz resolution). The AD1815 AD1815 supports a Type "F" DMA request/grant architecture for transferring data with the ISA bus through the 8-bit interface. The AD1815 AD1815 also supports DACK preemption. Programmed I/O (PIO) mode is also supported for control register accesses and for applications lacking DMA control. The AD1815 AD1815 includes dual DMA count registers for full-duplex operation enabling simultaneous capture and playback on separate DMA channels. Codec Functional Description The AD1815 AD1815's full-duplex stereo codec supports business audio and multimedia applications. The codec includes stereo audio converters, complete on-chip filtering, MPC Level-2 and Level3 compliant analog mixing, programmable gain and attenuation, a variable sample rate converter, extensive digital mixing, and FIFOs buffering the Plug and Play ISA bus interface. Analog Inputs The codec contains a stereo pair of analog-to-digital converters (ADC). Inputs to the ADC can be selected from the following analog signals: mono modem or telephony (MDM_IN), mono microphone (MIC), stereo line (LINE), external stereo synthesizer (SYNTH), stereo CD ROM (CD), stereo audio from a video source (VID), and post-mixed stereo or mono line output (OUT). Analog Mixing MDM_IN, MIC, MONO_IN, LINE, SYNTH, CD, and VID can be mixed in the analog domain with the stereo line OUT from the digital-to-analog converters (DAC). Each channel of the stereo analog inputs can be independently gained or attenuated from +12 dB to ­34.5 dB in 1.5 dB steps. The summing path for the mono inputs (MDM_IN, MIC, and MONO_IN to line OUT) duplicates mono channel data on both the left and right line OUT which can also be gained or attenuated from +12 dB to ­34.5 dB in 1.5 dB steps for MDM_IN and MIC, and +0 dB to ­45.5 dB in 3 dB steps for MONO_IN. The left and right mono summing signals are always identical being gained or attenuated equally. Analog-to-Digital Datapath The selector sends left and right channel information to the programmable gain amplifier (PGA). The PGA following the selector allows independent gain for each channel entering the ADC from 0 dB to 22.5 dB in 1.5 dB steps. When the modem converters are enabled, each channel of the ADC is independent and can process left and right channel data at different sample rates. The right channel of the ADC samples modem information received from the DAA in the programmable range between 4 kHz and 13.8 kHz. All programmed sample rates have a resolution of 1 Hz. The AD1815 AD1815 also supports the following irrational V.34 sample rates: 8/7 × 7,200 Hz, 8/7 × 9,000 Hz, and 8/7 × 12,000 Hz. REV. 0 Digital Mixing & Sample Rates The audio ADC sample rate and the audio DAC sample rates are completely independent. The AD1815 AD1815 includes a variable sample rate converter that lets the codec instantaneously change and process sample rates from 4 kHz to 55.2 kHz with a resolution of 1 Hz. The in-band integrated noise and distortion artifacts introduced by rate conversions are below ­90 dB. When the modem converters are enabled, the right channel of the ADC and the modem DAC convert modem data at the same sample rate. Up to four channels of digital data can be summed together and presented to the stereo DAC for conversion. Each digital channel pair can contain information encoded at a different sample rate. For example, 8 kHz .wav data received from the ISA interface, 48 kHz MPEG audio data received from I2S(0), digital 44.1 kHz CD data received from I2S(1), and internally generated 22.05 kHz music data may be summed together and then converted by the DACs. Digital-to-Analog Datapath The internally generated music synthesizer data, PCM data received from the ISA interface, data received from the I2S(0) port, and data received from the I2S(1) port, and the DSP serial port passes through an attenuation mute stage. The attenuator allows independent control over each digital channel which can be attenuated from 0 dB to ­94.5 dB in 1.5 dB steps before being summed together and passed to the DAC or the channel may be muted entirely. Analog Outputs The analog output of the DAC can be summed with any of the analog input signals. The summed analog signal enters the Master Volume stage where each channel of the line OUT can be attenuated from 0 dB to ­46.5 dB in 1.5 dB steps or muted. Digital Data Types The codec can process 16-bit twos-complement PCM linear digital data, 8-bit unsigned magnitude PCM linear data, and 8-bit µ-law or A-law companded digital data as specified in the control registers. The AD1815 AD1815 also supports ADPCM encoded in the Creative SoundBlaster ADPCM formats. Host-Based Echo Cancellation Support The AD1815 AD1815 supports time correlated I/O data format by presenting MIC data on the left channel of the ADC and the mono summation of left and right OUT on the right channel. The ADC sample rates are independent of the DAC sample rate allowing the AD1815 AD1815 to support ADC time correlated I/O data at 8 kHz and DAC data at any other sample rate in the range of 4 kHz to 55.2 kHz simultaneously. ­15­ AD1815 AD1815 IMA Digital Audio Doc-Pac (IMA-ADPCM), © 1992, Interactive Multimedia Association, 48 Maryland Avenue, Suite 202, Annapolis, MD 21401-8011 Telephony Modem Support AD1815 AD1815 contains a V.34 capable analog front end for supporting host-based and data pump modems. The modem DAC typical dynamic range is 90 dB over a 4.2 kHz analog output passband. In modem mode, the right channel of the ADC and a dedicated DAC convert modem data at the same sample rate in the range between 4 kHz and 13.8 kHz. All programmed sample rates have a 1 Hz resolution. The AD1815 AD1815 also supports the following irrational V.34 sample rates: The following reference texts can serve as additional sources of information on developing applications that run on the AD1815 AD1815. S. De Furia & J. Scacciaferro, The MIDI Implementation Book, (© 1986, Third Earth, Pompton Lake) C. Petzold, Programming Windows: the Microsoft guide to writing applications for Windows 3.1, 3rd. ed., (© 1992, Microsoft Press, Redmond) 8/7 × 7,200 Hz, 8/7 × 9,000 Hz, and 8/7 × 12,000 Hz For native modem applications, all modem processing is handled by the host and all data is transferred by PIO over the ISA interface through a 4 deep FIFO. K. Pohlmann, Principles of Digital Audio, (© 1989, Sams, Indianapolis) For modem applications using a dedicated data pump, a bidirectional DSP serial port interfaces directly to the data pump. A. Stolz, The SoundBlaster Book, (© 1993, Abacaus, Grand Rapids) WSS & SoundBlaster Compatibility Windows Sound System software audio compatibility is built into the AD1815 AD1815. J. Strawn, Digital Audio Engineering, An Anthology, (©1985, Kaufmann, Los Altos) SoundBlaster emulation is provided through the SoundBlaster register set and the internal music synthesizer. SoundBlaster Pro version 2.01 functions are supported including record and Creative SoundBlaster ADPCM. Yamamoto, MIDI Guidebook, 4th. ed., (© 1987, 1989, Roland Corp.) Virtually all applications developed for SoundBlaster, Windows Sound System, AdLib, and MIDI MPU-401 MPU-401 platforms run on the AD1815 AD1815 SoundComm Controller. Follow the same development process for the controller as you would use for these other devices. This section provides information on related development kits, hardware/software specifications, and reference texts. As the AD1815 AD1815 contains SoundBlaster (compatible) and Windows Sound System logical devices. You may find the following related development kits useful when developing AD1815 AD1815 applications. Multimedia PC Capabilities The AD1815 AD1815 is MPC-2 and MPC-3 compliant. This compliance is achieved through the AD1815 AD1815's flexible mixer and the embedded chip resources. Music Synthesis The AD1815 AD1815 includes an embedded music synthesizer that emulates industry standard OPL3 FM synthesizer chips and deliver 20 voice polyphony. The internal synthesizer generates digital music data at 22.05 kHz and is summed into the DACs digital data stream prior to conversion. To sum synthesizer data with the ADC output, the ADC must be programmed for a 22.05 kHz sample rate. The synthesizer is a hardware implementation of Eusyhth-1 + code that was developed by Euphonics, a research and development company that specializes in audio processing and electronic music synthesis. Developer Kit for SoundBlaster Series, 2nd ed. © 1993, Creative Labs, Inc., 1901 McCarthy Blvd., Milpitas, CA 95035 Microsoft Windows Sound System Driver Development Kit (CD), Version 2.0, © 1993, Microsoft Corp., One Microsoft Way, Redmond, WA 98052 Because the AD1815 AD1815 complies with the following related specifications, you can use them as an additional reference to AD1815 AD1815 operations beyond the material in this data sheet. EuSynth-1+ Plug & Play ISA Specification, Version 1.0a, © 1993, 1994, Intel Corp. & Microsoft Corp., One Microsoft Way, Redmond, WA 98052 Wavetable MIDI Inputs The AD1815 AD1815 has a dedicated analog input for receiving an analog wavetable synthesizer output. Alternatively, a wavetable synthesizer's I2S formatted digital output can be directly connected to one of the AD1815 AD1815's I2S serial ports. Digital wavetable data from the AD1815 AD1815's I2S port can be summed with other digital data streams being handled by the AD1815 AD1815 and then sent to the 16-bit DAC. Multimedia PC Level 2 Specification, © 1993, Multimedia PC Marketing Council, 1730 M St. NW, Suite 707, Washington, DC 20036 MIDI 1.0 Detailed Specification & Standard MIDI Files 1.0, © 1994, MIDI Manufacturers Association, PO Box 3173 La Habra, CA 90632-3173 Recommendation G.711-Pulse Code Modulation (PCM) Of Voice Frequencies (µ-Law & A-Law Companding), The International Telegraph and Telephone Consultative Committee IX Plenary Assembly Blue Book, Volume III - Fascicle III.4, General Aspects Of Digital Transmission Systems; Terminal Equipment's, Recommendations G.700 - G.795, (Geneva, 1988), ISBN 92-61-03341-5 MIDI The primary interface for communicating MIDI data to and from the host PC is the compatible MPU-401 MPU-401 interface that operates in UART mode. The MPU-401 MPU-401 interface has two built-in FIFOs: a 64 byte receive FIFO and a 16 byte transmit FIFO. ­16­ REV. 0 AD1815 AD1815 Game Port An IBM-compatible game port interface is provided on chip. The game port supports up to two joysticks via a 15-pin D-sub connector. Joystick registers supporting the Microsoft Direct Input standard are included as part of the register map. The AD1815 AD1815 may be programmed to automatically sample the game port and save the value in the Joystick Position Data Register. When enabled, this feature saves up to 10% CPU MIPS by offloading the host from constantly polling the joystick port. Plug & Play The AD1815 AD1815 is fully Plug and Play configurable. For motherboard applications, the built-in Plug and Play protocol can be disabled with a software key providing a back door for the BIOS to configure the AD1815 AD1815's logical devices. For information on the Plug & Play mode configuration process, see the Plug & Play ISA Specification Version 1.0a (May 5, 1994). All the AD1815 AD1815's logical devices comply with Plug & Play resource definitions described in the specification. Volume Control The registers that control the Master Volume output stage are accessible through the parallel port. Master Volume output can also be controlled through a 2-pin hardware interface. One pin is used to increase the gain, the other pin attenuates the output, and both pins together mute the output entirely. Once muted, any further activity of these pins will unmute the AD1815 AD1815's output. REV. 0 ­17­ AD1815 AD1815 SERIAL INTERFACES I2S Serial Ports The two I2S serial ports on the AD1815 AD1815 accept serial data in the following formats: Right-Justified, I2S-Justified, and Left-Justified. The following figure shows the right-justified mode. LRCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of the BCLK. The MSB is delayed 16-bit clock periods from an LRCLK transition, so that when there are 64 BCLK periods per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition. LRCLK RIGHT CHANNEL LEFT CHANNEL BCLK SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 9. Serial Interface Right-Justified Mode The following figure shows the I2S-justified mode. LRCLK is LO for the left channel, and HI for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition, but with a single BCLK period delay. LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 10. Serial Interface I2S-Justified Mode The following figure shows the left-justified mode. LRCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay. LRCLK RIGHT CHANNEL LEFT CHANNEL BCLK SDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 11. Serial Interface Left-Justified Mode Bidirectional DSP Serial Interface The AD1815 AD1815 SoundComm Controller transmits and receives both data and control/status information through its DSP serial interface port (SPORT). The AD1815 AD1815 is always the bus master and supplies the frame sync and the serial clock. The AD1815 AD1815 has four pins assigned to the SPORT: SDI, SDO, SDFS, and SCLK. The SPORT has two operating modes: monitor and intercept. The SPORT always monitors the various data streams being processed by the AD1815 AD1815. In intercept mode, any of the digital data streams can be manipulated by the DSP before reaching the final ADC or DAC stages. The SDI and SDO pins handle the serial data input and output of the AD1815 AD1815. Communication in and out of the AD1815 AD1815 requires that bits of data are transmitted after a rising edge of SCLK, and sampled on the falling edge of SCLK. The SCLK frequency is always 11 MHz (or 1/3 or XTALI). When the modem channel is not enabled, these time slots are mapped as shown in Table I. ­18­ REV. 0 AD1815 AD1815 Table I. Modem Disabled Time Slot Map Time Slot SDI Pin SDO Pin 0 1 2 3 4 5 6 7 8 9 10 11 Control Word Input Control Register Data Input * SS/SB ADC Right Input (to ISA) * SS/SB ADC Left Input (to ISA) * SS/SB DAC Right Input (to Codec) * SS/SB DAC Left Input (to Codec) * FM DAC Right Input (to Codec) * FM DAC Left Input (to Codec) * I2S 1 DAC Right Input (to Codec) * I2S 1 DAC Left Input (to Codec) * I2S 0 DAC Right Input (to Codec) * I2S 0 DAC Left Input (to Codec) Status Word Output Control Register Data Output SS/SB ADC Right Output (from Codec) SS/SB ADC Left Output (from Codec) SS/SB DAC Right Output (from ISA) SS/SB DAC Left Output (from ISA) FM DAC Right Output (from FM Synth Block) FM DAC Left Output (from FM Synth Block) I2S 1 DAC Right Output (from I2S Port 1) I2S 1 DAC Left Output (from I2S Port 1) I2S 0 DAC Right Output (from I2S Port 0) I2S 0 DAC Left Output (from I2S Port 0) *This data is ignored by the AD1815 AD1815 unless the channel pair is in intercept mode (see below). SS - Sound System Mode SB = Sound Blaster Mode When the modem channel is enabled (DSP modem mode), time slots are mapped as above except for time Slot 2, which is as follows: 2 Modem DAC Input (to Codec) Modem ADC Output (from Codec) When the modem channel is enabled, stereo SB or SS capture is not possible and SB and SS fall back to mono capture. The right capture channel then gets the left channel capture data. At startup (after pin reset), there are exactly 12 time slots per frame. The frame rate will be 57,291 and 2/3 Hz (11 MHz sclk/ (16 bits × 12 slots). Interfacing with an Analog Devices 21xx family DSP can be achieved by putting the ADSP-21xx in 24 slot per frame mode, where the first 12 and second 12 slots in the ADSP-21xx frame are identical. The frame rate can be changed from its default by a write to the DFS(2:0) bits in register 33. Rate choices are: Maximum (57,291 and 2/3 Hz default), Modem rate, SS capture rate, SS playback rate, FM rate, I2S Port (1) rate, or I2S Port (0) rate. When the frame rate is less than 57,261 and 2/3 Hz, extra SCLK periods are added to fill up the time. The number of SCLK periods added will vary somewhat from frame to frame. Similar to the AD1843 AD1843, Valid out, Request in, and Valid in bits located in the control and status words are used to control sample data flow. If a channel's sample rate is equal to the frame rate, these bits can be ignored since they will predictably always be 1s. By default, the DSP serial port only allows codec sample data I/O to be monitored. Intercept modes must be enabled to make substitutions in sample data flow to and from the codec. There are five bits in SS register 33 which enable intercept mode for SS capture, SS playback, FM playback, I2S Port (1) playback, and I2S Port (0) playback. Control Word Input (Slot 0 SDI) 15 FCLR 7 ALIVE 14 RES 6 R/W 13 MODVI 5 12 SSCVI 4 11 SSPVI 3 IA[5:0] 10 FMVI 2 9 IS1VI 1 8 IS0VI 0 IA [5:0] Indirect Register Address. Sound System Indirect Register Address defines the address of indirect registers shown in Table VI. R/W Read/Write request. Either a read from or a write to a SS indirect register occurs every frame. Setting this bit initiates a SS indirect register read while clearing this bit initiates a SS indirect register write. ALIVE DSP port alive bit. When set, this bit indicates to the powerdown timer that the DSP port is active. When cleared, this bit indicates that the DSP port is inactive. IS0VI I2S Port 0 Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for the I2S port 0 channel pair, or (2) The AD1815 AD1815 did not request data from the I2S port 0 channel pair in the previous frame. Otherwise, setting this bit indicates that slots 10 and 11 contain valid right and left I2S Port 0 substitution data. When this bit is cleared, data in slots 10 and 11 is ignored. IS1VI I2S Port 1 Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for I2S port 1 channel pair, or (2) The AD1815 AD1815 did not request data from the I2S port channel pair in the previous frame. Otherwise, setting this bit indicates that Slots 8 and 9 contain valid right and left I2S Port 1 substitution data. When this bit is cleared, data in slots 8 and 9 is ignored. REV. 0 ­19­ AD1815 AD1815 FMVI FM Synthesis Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for the FM synthesis channel pair, or (2) The AD1815 AD1815 did not request data from the FM synthesis channel pair in the previous frame (see the FMRQ Bit 9 in the status word output). Otherwise, setting this bit to 1 indicates that slots 6 and 7 contain valid right and left FM synthesis channel substitution data. When this bit is reset to 0, data in slots 6 and 7 is ignored. SSPVI SS/SB Playback Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for SS/SB playback, or (2) The AD1815 AD1815 did not request data for SS/SB playback in the previous frame (see the SSPRQ bit in the Status Word Output). Otherwise, setting this bit indicates that Slots 4 and 5 contain valid right and left SS/SB playback substitution data. If in "capture rate equal to playback rate" mode, setting this bit also indicates that valid capture substitution data is being sent to the AD1815 AD1815. If not in modem mode, right and left channel capture substitution data is accepted in Slots 2 and 3 respectively. If in modem mode, only mono capture substitution data is accepted in slots 2 and 3. When this bit is cleared, data in all slots controlled by this bit, as defined above, is ignored. SSCVI SS/SB Capture Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for SS/ SB capture, or (2) The AD1815 AD1815 did not request data for SS/SB capture in the previous frame (see the SSCRQ bit in the Status Word Output). Otherwise, setting this bit indicates that valid SS/SB capture substitution data is being sent to the AD1815 AD1815. If not in modem mode, or DSP port or ISA bus based, right and left channel capture data is accepted in Slots 2 and 3 respectively. If in modem mode, only mono capture substitution data is accepted in Slot 3, because Slot 2, which is mapped to the right capture channel, is being used for modem. This mono data will, however, be sent to both left and right ISA SS/SB capture channels. When this bit is cleared, data in Slots 3 and 2 is ignored. MODVI Modem Input Valid flag. This bit is ignored if: (1) The AD1815 AD1815 is in DSP modem mode, or (2) If the AD1815 AD1815 did not request data for the modem in the previous frame (see the MODRQ bit in the Status Word Output). When in DSP modem mode, setting this bit indicates that Slot 2 contains valid modem data to be transmitted. When this bit is cleared, data in Slot 2 is ignored. RES Reserved: To insure future compatibility write "0" to all reserved bits. FCLR DSP Port Clear Status Flag. When you set this bit, (write 1), the PNPR and PDN flag bits in the status word (Bits 15 and 14 of slots 0 SDO) are cleared. When you clear this bit, (writing a 0), it has no effect on PNPR and PDN and preserves them in the previous states. Status Word Output (Slot 0 SDO) 15 PDN 7 MB1 14 PNPR 6 MB0 13 MODVO 5 MODRQ 12 SSCVO 4 SSCRQ 11 SSPVO 3 SSPRQ 10 FMVO 2 FMRQ 9 IS1VO 1 IS1RQ 8 IS0VO 0 IS0RQ IS0RQ I2S Port (0) Input Request Flag. This bit is set if intercept mode is enabled for I2S Port (0) and its four-word stereo input buffer is not full. IS1RQ I2S Port (1) Input Request Flag. This bit is set if intercept mode is enabled for I2S Port (1) and its four-word stereo input buffer is not full. FMRQ FM Synthesis Input Request Flag. This bit is set if intercept mode is enabled for FM synthesis and its four-word stereo input buffer is not full. SSPRQ SS/SB Capture Input Request Flag. This bit is set if intercept mode is enabled for SS/SB playback and its fourword stereo input buffer is not full. SSCRQ SS/SB Capture Input Request Flag. This bit is set if intercept mode is enabled for SS/SB capture and its four-word stereo input buffer is not full. MODRQ Modem Input Request Flag. This bit is set if the modem is enabled and its four-word stereo input buffer is not full. MB0 Mailbox 0 Status Flag. This bit is set if the most recent action to SS indirect register 42 (DSP port Mail Box 1) was a write, and is cleared if the most recent action was a read. The status of this bit is also reflected in SS indirect register 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and a host CPU on the ISA bus. MB1 Mailbox 1 Status Flag. This bit is set if the most recent action to SS indirect register 43 (DSP port Mail Box 1) was a write and is cleared if the most recent action was a read. The status of this bit is also reflected in SS indirect register 33. It may be used as a handshake bit to facilitate communication between a DSP on the DSP port and a host CPU on the ISA bus. IS0VO I2S Port 0 Valid Out. This bit is set if Slots 10 and 11 contain valid right and left I2S Port 0 data. IS1V1 I2S Port 1 Valid Out. This bit is set if Slots 8 and 9 contain valid right and left I2S Port 1 data. ­20­ REV. 0 AD1815 AD1815 FMVO FM Synthesis Valid Out. This bit is set if Slots 6 and 7 contain valid left and right FM synthesis data. SSPVO SS/SB Playback Valid Out. This bit is set if Slots 4 and 5 contain valid right and left SS/SB playback data. SSCVO SS/SB Capture Valid Out. This bit is set if valid SS/SB capture data is being transmitted. If not in a modem mode, Slots 2 and 3 will contain valid right and left SS/SB capture data. If in modem mode, only Slot 3 will contain valid left SS/SB capture data as Slot 2 and the ADC right channel are used by the modem. MODVO Modem Valid Out. This bit is set if Slot 2 contains valid modem capture data. PNPR Plug and Play Reset flag. This bit is set by an AD1815 AD1815 reset (RESETB pin asserted LOW), or by a Plug and Play reset command. This bit is cleared by the assertion of the FCLR bit in the control word. While this bit is set, all attempts to write a SS indirect register via the DSP port will be ignored and fail. This is to insure that Plug and Play resets are immediately applied to the application running on the DSP, without requiring them to continuously poll the Plug and Play reset status bit. During the frame that this bit is cleared (by asserting FCLR), an attempt to write a SS indirect register will succeed. If the FCLR bit is asserted continuously, writes to indirect registers via the DSP port will always be enabled. A Plug and Play reset command will set this PNPR bit HIGH during at least one frame. PDN Powerdown flag. This bit is set by an AD1815 AD1815 reset (RESETB pin asserted LOW), or by an AD1815 AD1815 powerdown. Before an AD1815 AD1815 powerdown sequence shuts down the DSP port, at least one frame will be sent with this bit set. This bit can be cleared by the assertion of the FCLR (DSP port status clear) bit in the control word, providing the AD1815 AD1815 is no longer in powerdown. The SDFS pin is used for the serial interface frame synchronization. New frames are marked by a one SCLK duration HI pulse driven out on SDFS one serial clock period before the frame begins. Upon initializing, there are exactly 12 time slots per frame, and 16 bits per time slot. The frame rate is 57,291 and 2/3 Hz (11 MHz SCLK / (16 bits * 12 slots). The frame rate can also be changed from the default value by reprogramming the rate in registers. The frame rate can run at the default rate or programmed to match the modem sample rate, ADC capture rate, DAC playback rate, music sample rate, I2S(1) sample rate, or I2S(0) sample rate. When the frame rate is not equivalent to the sample rate, Valid Out, Request In, and Valid In bits are used to control the sample data flow. When the frame rate is equivalent to the sample rate, Valid and Request bits can be ignored. SAMPLE PERIOD N SLOT 0 SAMPLE PERIOD N + 1 SLOT 15 SLOT 0 SAMPLE PERIOD N + 2 SLOT 15 SLOT 0 SLOT 15 SCLK SDI OR SDO 15 14 13 3 2 1 0 15 14 13 3 2 1 0 15 14 13 3 2 1 0 SDFS Figure 12. DSP Serial Interface (Default Frame Rate) SAMPLE PERIOD N SLOT 0 SAMPLE PERIOD N + 1 SLOT 15 SLOT 0 SAMPLE PERIOD N + 2 SLOT 15 SLOT 0 SLOT 15 SCLK SDI OR SDO 15 14 13 3 2 1 0 15 14 13 3 2 1 0 15 14 13 SDFS Figure 13. DSP Serial Interface (User Programmed Frame Rate) REV. 0 ­21­ 3 2 1 0 AD1815 AD1815 SELECTOR The following figure illustrates the flexibility of the DSP Serial Port interface. This port can monitor or intercept any of the digital streams managed by the AD1815 AD1815. Any ADC or DAC data stream can be intercepted by the port, shipped to an external DSP or ASIC, manipulated, and returned to any DAC summing path or the ADC. AUDIO/ MODEM ADC PGA 2 2 FORMAT 2 M 2 G FIFO MUSIC SYNTHESIZER PLUG AND PLAY ISA BUS PARALLEL INTERFACE 2 FORMAT 2 M M AUDIO DAC FIFO G G 2 I2S SERIAL PORT (0) 2 I2S SERIAL PORT (1) 2 2 M G 2 MODEM DAC 2 SERIAL PORT INTERFACE SDI SDO SDFS SCLK Figure 14. DSP Serial Port ISA INTERFACE AD1815 AD1815 Chip Registers Table II, Chip Register Diagram, details the AD1815 AD1815 direct register set available from the ISA Bus. The PC I/O addressable ports must be configured using the Plug and Play Resources prior to any accesses by the host. Table II. Chip Register Diagram Register Type-Register Name Register PC I/O Address Plug and Play ADDRESS WRITE_DATA READ_DATA 0x279 0xA79 Relocatable in Range 0x203 ­ 0x3FF Sound System Codec CODEC REGISTERS Sound Blaster Pro Music0: Address (w), Status (r) Music0: Data (w) Music1: Address (w) Music1: Data (w) Mixer Address (w) Mixer Data (w) Reset (w) Music0: Address (w) Music0: Data (w) Input Data (r) Status (r), Output Data (w) Status (r) 0x(SS Base+0 ­ SS Base+15) Relocatable in Range 0x100 ­ 0x3FF See Table V 0x(SB Base) Relocatable in Range 0x010 ­ 0x3F0 0x(SB Base+1) 0x(SB Base+2) 0x(SB Base+3) 0x(SB Base+4) 0x(SB Base+5) 0x(SB Base+6 or 7) 0x(SB Base+8) 0x(SB Base+9) 0x(SB Base+A or +B) 0x(SB Base+C or +D) 0x(SB Base+E or +F) ­22­ REV. 0 AD1815 AD1815 Register Type-Register Name Register PC I/O Address AdLib Music0: Address (w), Status (r) Music0: Data (w) Music1: Address (w) Music1: Data (w) 0x(Adlib Base) Relocatable in Range 0x100 ­ 0x3F8 0x(Adlib Base+1) 0x(Adlib Base+2) 0x(Adlib Base+3) MIDI MPU-401 MPU-401 MIDI Data (r/w) MIDI Status (r), Command (w) 0x(MIDI Base) Relocatable in Range 0x100 ­ 0x3F8 0x(MIDI Base+1) Game Port Game Port I/O 0x(Game Base +0 to Game Base +7) Relocatable in Range 0x100 ­ 0x3F8 AD1815 AD1815 Plug and Play Device Configuration Registers The AD1815 AD1815 may be configured according to the Intel/Microsoft Plug and Play Specification using the internal ROM. Alternatively, the PnP configuration sequence may be bypassed using the "Alternate Key Sequence" described in Appendix A. The operating system configures/reconfigures AD1815 AD1815 Plug and Play Logical Devices after system boot. There are no "boot-devices" among the Plug and Play Logical Devices in the AD1815 AD1815. Non-Plug and Play BIOS systems configure the AD1815 AD1815's Logical Devices after boot using drivers. Depending on BIOS implementations, Plug and Play BIOS systems may configure the AD1815 AD1815's Logical Devices before POST or after Boot. See the Plug and Play ISA Specification Version 1.0a for more information on configuration control. To complete this configuration, the system reads resource data from the AD1815 AD1815's on-chip resource ROM and from any other Plug and Play cards in the system, then arbitrates the configuration of system resources with a heuristic algorithm. The algorithm maximizes the number of active devices and the acceptability of their configurations. The system considers all Plug and Play logical device resource data at the same time and makes a conflict-free assignment of resources to the devices. If the system cannot assign a conflict-free resource to a device, the system does not configure or activate the device. All configured devices are activated. The system's Plug and Play support selects all necessary drivers, starts them, and maintains a list of system resources allocated to each logical device. Optionally, you can reassign system resources at runtime with a Plug and Play Resource Manager. The custom setup created using the manager can be saved and used automatically on subsequent system boots. Plug and Play Device IDs (embedded in the logical device's resource data) provide the system with the information required to find and load the correct device drivers. One custom driver, the AD1815 AD1815 Sound System driver from Analog Devices, is required for correct operation. In the other cases (MIDI, Game Port), the system can use generic drivers. Table III lists the AD1815 AD1815's logical devices and compatible Plug and Play device drivers. Table III. Logical Devices and Compatible Plug and Play Device Drivers Logical Device Number Emulated Device Compatible (Device ID) Device ID 0 1 2 Sound System MIDI MPU401 MPU401 compatible Game/Joystick port - PNPB006 PNPB006 PNPB02F PNPB02F ADS7150 ADS7150 ADS7151 ADS7151 ADS7152 ADS7152 The configuration process for the logical devices on the AD1815 AD1815 is described in the Plug and Play ISA Specification Version 1.0a (May 5, 1994). The specification describes how to transfer the logical devices from their start-up Wait For Key state to the Config state and how to assign I/O ranges, interrupt channels, and DMA channels. See Appendix A for an example setup program and specific Plug and Play resource data. Table IV describes in detail the I/O Port Address Descriptors, DMA Channels, Interrupts for the functions required for the AD1815 AD1815 Logical Device groups. REV. 0 ­23­ AD1815 AD1815 Table IV. Logical Device Configuration LDN PnP Function Description 0 I/O Port Address Descriptor (0x60-0x61) The Sound Blaster Pro address range is from 0x100 to 0x3F0. The typical address is 0x220. The range is 16 bytes long and must be aligned to a 16 byte memory boundary. 0 I/O Port Address Descriptor (0x62-0x63) The Adlib address range is from 0x100 to 0x3F8. The typical address is 0x388. The range is 4 bytes long and must be aligned to a 8 byte memory boundary. 0 I/O Port Address Descriptor (0x64-0x65) The Codec address range is from 0x100 to 0x3F8. The range is 16 bytes long and must be aligned to a 16 byte memory boundary. 0 Interrupt Request Level Select (0x70-0x71) This IRQ is shared between the SB Pro device and the Codec. These devices require one of the following IRQ channels: 5, 7, 9, 11, 12, or 15. Typically, the IRQ is set to 5 or 7 for this device. 0 DMA Playback Channel Select (0x74) This 8-bit channel is shared between the SB Pro device and the Codec for playback. These devices require one of the following DMA channels; 0, 1, 3. Typically, DMA channel 1 is set. 0 DMA Capture Channel Select (0x75) This the DMA channel used for capturing Codec data. The Codec operates in single channel mode if a separate DMA channel for capture and playback is not assigned. The following DMA channels may be programmed; 0, 1, 3. DMA Channel 4 indicates single channel mode. 1 I/O Port Address Descriptor (0x60-0x61) The MPU-401 MPU-401 compatible device address range is 0x100 to 0x3FE. Typical configurations use 0x330. The range is 2 bytes long and must be aligned to a 2 byte memory boundary. 1 Interrupt Request Level Select (0x70-0x71) The MIDI device requires one of the following IRQ channels: 5, 7, 9, 11, 12, or 15. 2 I/O Port Address Descriptor (0x60-0x61) The Game Port address range is from 0x100 to 0x3F8. The typical address is 0x200. The range is 8 bytes long and must be aligned to a 8 byte memory boundary. NOTE DMA channel 4 indicates single-channel mode. Sound System Direct Registers The AD1815 AD1815 has a set of 16 programmable Sound System Direct Registers and 36 Indirect Registers. This section describes all the AD1815 AD1815 registers and gives their address, name, and initialization state/reset value. Following each register table is a list (in ascending order) of the full register name, its usage, and its type: (RO) Read Only, (WO) Write Only, (STKY) Sticky, (RW) Read Write, and Reserved (res). Table V is a map of the AD1815 AD1815 direct registers. Table V. Sound System Direct Registers Direct Address BASE + 0 BASE + 1 BASE + 2 BASE + 3 BASE + 4 BASE + 5 BASE + 6 BASE + 7 BASE + 8 BASE + 9 BASE + 10 BASE + 11 BASE + 12 BASE + 13 BASE + 14 BASE + 15 Bit 7 CRDY PI Bit 6 IMRDY CI RES PFH MOF PDR TRD DAZ RES JRDY JWRP Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 INADR[5:0] TI VI DI RI GI Indirect SS Data [7:0] Indirect SS Data [15:8] PUR COR ORR [1:0] PLR PUL CFH CDR CLR PIO Playback/Capture [7:0] RESERVED PFMT [1:0] PC/L PST PIO CFMT [1:0] PC/L CST CIO PIO MODEM OUT / IN [7:0] PIO MODEM OUT / IN [15:8] JOYSTICK DATA [7:0] JSEL [1:0] JMSK [3:0] JAXIS [7:0] JAXIS [15:8] ­24­ Bit 0 SI ORL [1:0] CUL PEN CEN REV. 0 AD1815 AD1815 [Base+0] Chip/Modem Status/Indirect Address 7 CRDY 6 IMRDY 5 4 3 INADR[5:0] 2 1 0 RESET = [0x00] INADR [5:0] (RW) Indirect Address for Sound System (SS). These bits are used to access the Indirect Registers shown in Table VIII. All registers data must be written in pairs, low byte followed by high byte, by loading the Indirect SS Data Registers, (Base +2) and (Base +3). IMRDY (RO) ISA Modem Ready. The AD1815 AD1815 asserts this bit when the modem can accept data. 0 Modem not ready. 1 Modem ready. CRDY (RO) AD1815 AD1815 Ready. The AD1815 AD1815 asserts this bit when AD1815 AD1815 can accept data. 0 AD1815 AD1815 not ready. 1 AD1815 AD1815 ready. [Base+1] Interrupt Status 7 PI 6 CI 5 TI 4 VI 3 DI 2 RI 1 GI 0 SI RESET = [0x00] SI (RO) SoundBlaster generated Interrupt. 0 No interrupt. 1 SoundBlaster interrupt pending. GI (RW) Game Interrupt (Sticky, Write "0" to Clear). 0 No interrupt. 1 An interrupt is pending due to Digital Game Port data ready. RI (RW) Ring Interrupt (Sticky, Write "0" to Clear). 0 No interrupt. 1 An interrupt is pending due to a Hardware Ring pin being asserted. DI (RW) DSP Interrupt (Sticky, Write "0" to Clear). 0 No interrupt. 1 An interrupt is pending due to a write to the DIT bit in indirect register [33] bit . VI (RW) Volume Interrupt (Sticky, Write "0" to Clear). 0 No interrupt. 1 An interrupt is pending due to Hardware Volume Button being pressed. TI (RW) Timer Interrupt. This bit indicates there is an interrupt pending from the timer count registers. (Sticky, Write "0" to Clear). 0 No interrupt. 1 Interrupt is pending from the timer count register. CI (RW) Capture Interrupt. This bit indicates that there is an interrupt pending from the capture DMA count register. (Sticky, Write "0" to Clear). 0 No interrupt. 1 Interrupt is pending from the capture DMA count register. PI (RW) Playback Interrupt. This bit indicates that there is an interrupt pending from the playback DMA count register. (Sticky, Write "0" to Clear). 0 No interrupt. 1 Interrupt is pending from the playback DMA count register. [Base+2] Indirect SS Data Low Byte 7 [Base+3] REV. 0 5 4 3 Indirect SS Data [7:0] 2 1 0 RESET = [0xXX] Indirect SS Data High Byte 7 Indirect SS Data [15:0] 6 6 5 4 3 Indirect SS Data [15:8] 2 1 0 RESET = [0xXX] Indirect Sound System Data. Data in this register is written to the Sound System Indirect Register specified by the address contained in INDAR [5:0], Sound System Direct Register [Base +0]. Data is written when the Indirect SS Data High Byte value is loaded. ­25­ AD1815 AD1815 [Base+4] PIO Debug 7 RES 6 MOF 5 PUR 4 COR 3 2 ORR[1:0] 1 0 ORL[1:0] RESET = [0x00] All bits in this register are sticky until any write which clears all bits to 0. ORL/ORR (RO) [1:0] Overrange Left/Right detect. These bits record the largest output magnitude on the ADC right and left chan nels and are cleared to 00 after any write to this register. The peak amplitude as recorded by these bits is "sticky," i.e., the largest output magnitude recorded by these bits will persist until these bits are explicitly cleared. They are also cleared by powering down the ADC right channel. ORL/ORR Over/Under Range Detection 00 Less than ­1 dB Underrange 01 Between ­1 dB and 0 dB Underrange 10 Between 0 dB and 1 dB Overrange 11 Greater than 1 dB Overrange COR (RO) Capture Over Run. The codec sets (1) this bit when capture data is not read within one sample period after the capture FIFO fills. When COR is set, the FIFO is full and the codec discards any new data generated. The codec clears this bit immediately after a four byte capture sample is read. PUR (RO) Playback Under Run. The codec sets (1) this bit when playback data is not written within one sample period after the playback FIFO empties. The codec clears (0) this bit immediately after a four byte playback sample is written. When PUR is set the playback channel has "run out" of data and either plays back a mid-scale value or repeats the last sample. MOF (RO) Modem Fail ("Sticky "). The modem sets (1) this bit if in ISA modem mode (see Sound System Indirect Register 32, bit IME) and the four deep transmit/receive FIFO underruns. [Base+5] PIO Status 7 PFH 6 PDR 5 PLR 4 PUL 3 CFH 2 CDR 1 CLR 0 CUL RESET = [0x00] CUL (RO) Capture Upper/Lower Sample. This bit indicates whether the PIO capture data ready is for the upper or lower byte of the channel. 0 Lower byte ready. 1 Upper byte ready or any 8-bit mode. CLR (RO) Capture Left/Right Sample. This bit indicates whether the PIO capture data waiting is for the left channel ADC or the right channel ADC. 0 Right channel. 1 Left channel or mono. CDR (RO) Capture Data Ready. The PIO Capture Data register contains data ready for reading by the host. This bit should be used only when direct programmed I/O data transfers are desired (FIFO has at least 4 bytes before full). 0 ADC is stale. Do not reread the information. 1 ADC data is fresh. Ready for next host data read. CFH (RO) Capture FIFO Half Full. (FIFO has at least 32 bytes before full.) PUL (RO) Playback Upper/Lower Sample. This bit indicates whether the PIO playback data needed is for the upper or lower byte of the channel. 0 Lower byte needed. 1 Upper byte needed or any 8-bit mode. PLR (RO) Playback Left/Right Sample. This bit indicates whether the PIO playback data needed is or the left channel DAC or the right channel DAC. 0 Right channel needed. 1 Left channel or mono. PDR (RO) Playback Data Ready. The PIO Playback data register is ready for more data. This bit should only be used when direct programmed I/O data transfers are desired (FIFO can take at least 4 bytes). 0 DAC data is still valid. Do not overwrite. 1 DAC data is stale. Ready for next host data write value. PFH (RO) Playback FIFO Half Empty. FIFO can take at least 32-bytes, 8 groups of 4-bytes. ­26­ REV. 0 AD1815 AD1815 [Base+6] PIO Data 7 PIO Playback/ Capture [7:0] 6 5 4 3 PIO Playback/Capture [7:0] 2 1 0 RESET = [0x00] The Programmed I/O (PIO) Data Registers for capture and playback are mapped to the same address. Writes send data to the Playback Register and reads will receive data from the Capture Register. Reading this register will increment the capture byte state machine so that the following read will be from the next appropriate byte in the sample. The exact byte may be determined by reading the PIO Status Register. Once all relevant bytes have been read, the state machine will stay pointed to the last byte of the sample until a new sample is received. Writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the sample. Once all bytes have been written, subsequent byte writes will be ignored. The state machine is reset when the current sample is transferred. Note: All writes to the FIFO "MUST" contain 4 bytes of data. * 1 sample of 16-bit stereo * 2 samples of 16-bit mono * 2 samples of 8-bit stereo (Linear PCM, U-law PCM, A-Law PCM) * 4 samples of 8-bit mono (Linear PCM, U-law PCM, A-Law PCM) [Base+7] Reserved 7 6 5 4 3 2 1 0 Reserved [7:0] [Base+8] RESET = [0xXX] Playback Config 7 TRD 6 DAZ 5 4 PFMT [1:0] 3 PC/L 2 PST 1 PIO 0 PEN RESET = [0x00] PEN (RW) Playback Enable. This bit enables or disables programmed I/O data playback. 0 Disable 1 Enable PIO (RW) Programmed Input/Output. This bit determines whether the playback data is transferred via DMA or PIO. 0 DMA transfers only. 1 PIO transfers only. PST (RW) Playback Stereo/Mono select. These bits select stereo or mono formatting for the input audio data streams. In stereo, the Codec alternates samples between channels to provide left and right channel input. For mono, the Codec captures samples on the left channel stereo. 0 Mono 1 Stereo PC/L (RW) Playback Companded/Linear Select. This bit selects between a linear digital representation of the audio signal or a nonlinear, companded format for all output data. The type of linear PCM or the type of companded format is defined by PFMT [1:0]. 0 Linear PCM 1 Companded PFMT [1:0] (RW) Playback Format. Use these bits to select the playback data format for output data according to Table VI and Figure 15. DAZ (RW) DAC zero. This bit forces the DAC to zero. 0 Repeat last sample. 1 Force DAC to ZERO. TRD (RW) Transfer Request Disable. This bit enables or disables Codec DMA transfers during a Codec interrupt (indicated by the SS Codec Status register's INT bit being set (1). This assumes Codec DMA transfers were enabled and the SS Codec Indexed (0x09) Interface Configuration register's PEN or CEN bits are set. 0 Transfer Request Enable. 1 Transfer Request Disable. After setting format bits, sample data into the AD1815 AD1815 must be ordered according to Figure 15, Table VI. REV. 0 ­27­ AD1815 AD1815 tBWDN IOR/IOW PC_D [7:0] BYTE N N+1 N+2 N+3 Figure 15. Codec Transfers Table VI. Codec Transfers ST FMT1 FMT0 C/L Format Byte 3 MSB LSB Byte 2 MSB LSB Byte 1 MSB LSB Byte 0 MSB LSB 0 000 Mono Linear, 8-Bit Unsigned Sample 3 8-Bits Left Channel Sample 2 8-Bits Left Channel Sample 1 8-Bits Left Channel Sample 0 8-Bits Left Channel 1 000 Stereo Linear, 8-Bit Unsigned Sample 1 8-Bits Right Channel Sample 1 8-Bits Left Channel Sample 0 8-Bits Right Channel Sample 0 8-Bits Left Channel 0 001 Mono µ-Law, 8-Bit Companded Sample 3 8-Bits Left Channel Sample 2 8-Bits Left Channel Sample 1 8-Bits Left Channel Sample 0 8 Bits Left Channel 1 001 Stereo µ-Law, 8-Bit Companded Sample 1 8-Bits Right Channel Sample 1 8-Bits Left Channel Sample 0 8-Bits Right Channel Sample 0 8 Bits Left Channel 0 010 Mono Linear 16-Bit Little Endian Sample 1 Upper 8-Bits Left Channel Sample 1 Lower 8-Bits Left Channel Sample 0 Upper 8-Bits Left Channel Sample 0 Lower 8-Bits Left Channel 1 010 Stero Linear 16-Bit Little Endian Sample 0 Upper 8-Bits Right Channel Sample 0 Lower 8-Bits Right Channel Sample 0 Upper 8-Bits Left Channel Sample 0 Lower 8-Bits Left Channel 0 011 Mono A-Law, 8-Bit Companded Sample 3 8-Bits Left Channel Sample 2 8-Bits Left Channel Sample 1 8-Bits Left Channel Sample 0 8-Bits Left Channel 1 011 Stereo A-Law, 8-Bit Companded Sample 1 8-Bits Right Channel Sample 1 8-Bits Left Channel Sample 0 8-Bits Right Channel Sample 0 8-Bits Left Channel 0 100 Reserved 1 100 Reserved 0 101 Reserved 1 101 Reserved 0 110 Mono Linear, 16-Bit Big Endian Sample 1 Lower 8-Bits Left Channel Sample 1 Upper 8-Bits Left Channel Sample 0 Lower 8-Bits Left Channel Sample 0 Upper 8-Bits Left Channel 0 110 Stereo Linear, 16-Bit Big Endian Sample 0 Lower 8-Bits Right+ Channel Sample 0 Upper 8-Bits Left Channel Sample 0 Lower 8-Bits Left Channel Sample 0 Upper 8-Bits Left Channel 0 111 Reserved 1 111 Reserved [Base+9] (Capture Config) 7 6 RES 5 4 CFMT [1:0] 3 CC/L 2 CST ­28­ 1 CIO 0 CEN RESET = [0x00] REV. 0 AD1815 AD1815 CEN (RW) Capture Enable. This bit enables or disables data capture. 0 Disable 1 Enable CIO (RW) Capture Programmed I/O. This bit determines whether the capture data is transferred via DMA or PIO. 0 DMA 1 PIO CST (RW) Capture Stereo/Mono Select. This bit selects stereo or mono formatting for the input audio data streams. In stereo, the Codec alternates samples between channels to provide left and right channel input. For mono, the Codec captures samples on the left channel. 0 Mono 1 Stereo CC/L (RW) Capture Companded/Linear Select. This bit selects between a linear digital representation of the audio signal or a nonlinear, companded format for all output data. The type of linear PCM or the type of companded format is defined by CFMT [1:0]. 0 Linear PCM 1 Companded (RW) Capture Format. Use these bits to select the format for capture data according to the following Table VI and Figure 15. CFMT [1:0] [Base+10] PIO Modem Data Low Byte 7 [Base+11] 5 4 3 2 PIO Modem Out/Modem In [7:0] 1 0 RESET = [0xXX] PIO Modem Data High Byte 7 [Base+12] 6 6 5 4 3 2 PIO Modem Out/Modem In [15:8] 1 0 RESET = [0xXX] Joystick RAW DATA 7 6 DATA (RO) [Base+13] 5 4 3 Joystick Data [7:0] 2 1 0 RESET = [0xF0] Joystick Control 7 JRDY JMSK [3:0] (RW) Joystick Data. Joystick Data (identical to 0x201): Writes to this register are ignored. 6 JWRP 5 4 JSEL [1:0] 3 2 1 JMSK [3:0] Enable AX xx1x Enable AY x1xx Enable BX 1xxx (RW) Enable BY Joystick Select. Selects one of four joystick axis register sets according to the following table: 00 Read AY (16 Bits) from [Base+14] & [Base+15] 10 Read BX (16 Bits) from [Base+14] & [Base+15] 11 (RW) Read AX (16 Bits) from [Base+14] & [Base+15] 01 JWRP RESET = [0x8F] Joystick Axis Mask. JRDY bit calculated based on axes selected by JMSK only. xxx1 JSEL [1:0] 0 Read BY (16 Bits) from [Base+14] & [Base+15] Joystick Wrapmode. Continuous Joystick sampling mode-sampling automatically restarted every ~16 ms. JRDY (RO) Joystick Ready. Sampling complete, joystick data ready for reading. Note: Sampling must be started manually if JWRP is set before any sampling cycles are run. To start sampling AFTER setting the WRP bit, write to the joystick port [Base+14]. REV. 0 ­29­ AD1815 AD1815 [Base+14] Joystick Position Data Low Byte 7 6 5 4 3 JAXIS [7:0] 2 1 0 RESET = [0xFF] JAXIS [7:0] (RO) Joystick Axis Low Byte. Note: Axis to be read through this register is selected by the JSEL bits in the control register. A write to this register starts a sampling cycle. [Base+15] Joystick Position Data High Byte 7 JAXIS [15:8] (RO) 6 5 4 3 JAXIS [15:8] 2 1 0 RESET = [0xFF] Joystick Axis High Byte. Note: Axis to be read through this register is selected by the JSEL bits in the control register. A write to this register starts a sampling cycle. Sound System Indirect Registers Writing Indirect Registers All Indirect Registers "MUST" be written in pairs: low byte followed by high byte. The Indirect Address Register [SSBASE+0] holds the address for a register pair, the Indirect Low Data Byte [SSBASE+2] is used to write low data byte and Indirect High Data Byte [SSBASE+3] is used to write the High data byte. The Low data byte is held in in the temporary register until the upper byte is written. Programming Example "Write Sample Rate for Playback to 11,000 (2AF8hex)" 1) Write [SSBASE+0] with 0x08; indirect register for playback sample rate 2) Write [SSBASE+2] with 0xF8; low byte of 16-bit sample rate register 3) Write [SSBASE+3] with 0x2A; high byte of 16-bit sample rate register Reading Indirect Registers All indirect registers can be read individually. The Sound System Indirect Address Register [SSBASE+0] holds the address for a register pair, the Indirect Low Data Byte [SSBASE+2] is used to read low data byte and Indirect High Data Byte[SSBASE+3] is used to read the High data byte. Programming Example "Read Sample Rate for Playback to 11,000 (2AF8hex)" 1) Write [SSBASE+0] with 0x08 ; Indirect register for Playback Sample Rate 2) Read [SSBASE+2] ; Low byte of 16-bit sample rate register 3) Read [SSBASE+3] ; High byte of 16-bit sample rate register ISR Saves and Restores For Interrupt Service Routines, ISRs, it is necessary to save and restore the Indirect Address and the Low Byte Temp Data registers inside the ISR. Programming Example "Save/Restore during an ISR" Beginning of ISR: 1) Read [SSBASE+0] 2) Write [SSBASE+0] with 0x00; 3) Read [SSBASE+2] 4) ISR Code 5) Write [SSBASE+2] with TMP_LBT 6) Write [SSBASE+0] with TMP_IA 7) Return from Interrupt ; Save Indirect Address register to TMP_IA ; Indirect Register for Low Byte Temp Data ; Save Low Byte Temp data to TMP_LBT ; ISR routine ; Restore Low Byte Temp data TMP_LBT ; Restore Indirect Address TMP_IA ; Return from ISR ­30­ REV. 0 AD1815 AD1815 Table VII. Indirect Register Map and Reset/Default States Index Reset/ Default State 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 REV. 0 Register Name Low Byte TMP Interrupt Enable and External Control Voice Playback Sample Rate Voice Capture Sample Rate Voice Attenuation FM Attenuation I2S(1) Attenuation I2S(0) Attenuation Playback Base Count Playback Current Count Capture Base Count Capture Current Count Timer Base Count Timer Current Count Master Volume Attenuation CD Gain/Attenuation Synth Gain/Attenuation Video Gain/Attenuation Line Gain/Attenuation Mic/Mono-In Gain Attenuation ADC Source Select and ADC PGA Chip Configuration DSP Configuration FM Sample Rate I2S(1) Sample Rate I2S(0) Sample Rate Modem Sample Rate Programmable Clock Rate Modem DAC and ADC Attenuation Modem Mix Attenuation Hardware Volume Button Modifier and Status DSP Mailbox 0 DSP Mailbox 1 Powerdown and Timer Control Version ID Reserved 0xXX 0x0102 0x1F40 0x1F40 0x8080 0x8080 0x8080 0x8080 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x8888 0x8888 0x8888 0x8888 0x8888 0x0000 0x00F0 0x0000 0x5622 0xAC44 0xAC44 0x1C20 0xAC44 0x8000 0x80XX 0xXX1B 0x0000 0x0000 0x0000 0x0000 0x0000 ­31­ AD1815 AD1815 Table VIII. Sound System Indirect Registers ADDRESS 7 00 (0x00) 01 (0x01) PIE 02 (0x02) 03 (0x03) 04 (0x04) LVM 05 (0x05) LFMM 06 (0x06) LS1M 07 (0x07) LS0M 08 (0x08) 09 (0x09) 10 (0x0A) 11 (0x0B) 12 (0x0C) 13 (0x0D) 14 (0x0E) LMVM 15 (0x0F) LCDM 16 (0x10) LSYM 17 (0x11) LVDM 18 (0x12) LLM 19 (0x13) MCM 20 (0x14) LAGC 32 (0x20) WSE 33 (0x21) DS1 34 (0x22) 35 (0x23) 36 (0x24) 37 (0x25) 38 (0x26) 39 (0x27) MDM 40 (0x28) MMM 41 (0x29 ) 42 (0x2A) 43 (0x2B) 44 (0x2C) CPD 45 (0x2D) 46 (0x2E) 6 (High Byte) 5 4 3 2 1 0 7 6 (Low Byte) 4 3 LBTD [7:0] 5 RES CIE TIE VIE DIE RIE JIE VPSR [15.8] VCSR [15:8] RES LVA [5:0] RES LFMA [5:0] RES LS1A [5:0] RES LS0A [5:0] PBC [15:8] PCC [15:8] CBC [15:8] CCC [15:8] TBC [15:8] TCC [15:8] RES LMVA [4:0] RES LCDA [4:0] RES LSYA [4:0] RES LVDA [4:0] RES LLA [4:0] M20 RES MCA [4:0] LAS [2:0] LAG [3:0] CDE RES CNP RES IME DS0 DIT DME DMR ADR I1T FSMR [15:8] S1SR [15:8] S0SR [15:8] MSR [15:8] PCR [15:8] RES MDA [4:0] RES MMA [4:0] RES MB0R [15:8] MB1R [15:8] RES PIW PIR PAA PDA PDP VER [15:8] RES [00] INDIRECT LOW BYTE TMP 7 6 5 4 3 RES 2 1 0 SIE RES RVM LFMM RS1M RS0M RMVM RCDM RSYM RVDM RLM MM RAGC IMR I0T RES RES RES RES RES RES RES RES RES RES RAS [2:0] COF [3:0] PBI FMI CPI RES VMU VUP VDN PTB 7 6 5 2 1 0 XC1 XC0 VPSR [7:0] VCSR [7:0] RVA [5:0] RFMA [5:0] RS1A [5:0] RS0A [5:0] PBC [7:0] PCC [7:0] CBC [7:0] CCC [7:0] TBC [7:0] TCC [7:0] RMVA [4:0] RCDA [4:0] RSYA [4:0] RVDA [4:0] RLA [4:0] MA [4:0] RAG [3:0] I2SF1 [1:0] I2SF0 [1:0] I1I I01 DFS [2:0] FMSR [7:0] S1SR [7:0] S0SR [7:0] MSR [7:0] PCR [7:0] MAG [3:0] RES BM [4:0] MB0R [7:0] MB1R [7:0] RES VER [7:0] RES 4 3 LBTD [7:0] DEFAULT = [0xXX] 2 1 0 LBTD [7:0] Low Byte Temporary Data holding latch for register pair writes Written on any write to [SSBase + 2] Read from [SSBase + 2] when the indirect address is 0x00 [01] INTERRUPT ENABLE AND EXTERNAL CONTROL 7 6 5 4 3 2 1 0 7 PIE CIE TIE VIE DIE RIE JIE SIE 6 5 4 RES 3 DEFAULT = [0x0102] 2 1 0 XC1 XC0 XC0 (R/W) External Control 0. The state of this bit is reflected on the XCTLO pin. This pin is also muxed with PCLKO. COF must be greater than 11 for PCLKO to be disabled, SS [32]. XC1 (R/W) SIE (R/W) JIE (R/W) External Control 1. The state of this bit is reflected on the XCTL1 pin. XCTL1 may also be used for Ring-In Interrupt. Sound Blaster Interrupt Enable; 0 Sound Blaster Interrupt disabled 1 Sound Blaster Interrupt enabled Joystick Interrupt Enable; 0 Joystick Interrupt disabled 1 Joystick Interrupt enabled ­32­ REV. 0 AD1815 AD1815 RIE (R/W) DIE (R/W) VIE (R/W) TIE (R/W) CIE (R/W) PIE (R/W) Ring Interrupt Enable; 0 Ring Interrupt disabled 1 Ring Interrupt enabled DSP Interrupt Enable; 0 DSP Interrupt disabled 1 DSP Interrupt enabled Volume Interrupt Enable. If enabled, software increments/decrements BUTTON MODIFIER via interrupt routine and pushing buttons only sets VUP, VDN, VMU bits. It does not change the volume. 0 Volume Interrupt disabled 1 Volume Interrupt enabled Timer Interrupt Enable; 0 Timer Interrupt disabled 1 Timer Interrupt enabled Capture Interrupt Enable; 0 Capture Interrupt disabled 1 Capture Interrupt enabled Playback Interrupt Enable; 0 Playback Interrupt disabled 1 Playback Interrupt enabled [02] VOICE PLAYBACK SAMPLE RATE 7 6 5 4 3 2 VPSR [15:8] 1 0 7 6 5 4 3 VPSR [7:0] DEFAULT = [0x1F40] 2 1 VPSR [15:0] Voice Playback Sample Rate. The sample rate can be programmed from 4 kHz to 55.2 kHz in 1 hertz increments. The default playback sample rate is 8 kHz. [03] VOICE CAPTURE SAMPLE RATE 7 6 5 4 3 2 VCSR [15:8] 1 0 7 6 5 DEFAULT = [0x1F40] 4 3 2 1 0 VCSR [7:0] VCSR [15:0] Voice Capture Sample Rate. The sample rate can be programmed from 4 kHz to 55.2 kHz in 1 hertz increments. Ignored if CNP bit in SS [32] = 0 in which case VPSR [15:0] controls capture rate. The default capture sample rate is 8 kHz. [04] VOICE ATTENUATION 7 6 5 4 3 2 LVM RES LVA [5:0] RVA [5:0] RVM LVA [5:0] LVM RES 0 7 RVM 6 RES 5 4 3 DEFAULT = [0x8080] 2 1 0 RVA [5:0] Right Voice Attenuation for Playback channel. The LSB represents ­1.5 dB, 000000 = 0 dB and the range is 0 dB to ­94.5 dB. Right Voice Mute. 0 = Unmuted, 1 = Muted. Left Voice Attenuation for Playback channel. The LSB represents ­1.5 dB, 000000 = 0 dB and the range is 0 dB to ­94.5 dB Left Voice Mute. 0 = Unmuted, 1 = Muted. [05] FM ATTENUATION 7 6 5 4 LFMM 1 3 2 1 0 7 6 RFMM LFMA [5:0] RES 5 4 3 DEFAULT = [0x8080] 2 1 0 RFMA [5:0] RFMA [5:0] Right F Music Attenuation for the internal Music Synthesizer. The LSB represents ­1.5 dB, 000000 = 0 dB and the range is 0 dB to ­94.5 dB. RFMM Right F Music Mute. 0 = Unmuted, 1 = Muted. LFMA [5:0] Left F Music Attenuation for the internal Music Synthesizer. The LSB represents ­1.5 dB, 000000 = 0 dB and the range is 0 dB to ­94.5 dB. LFMM Left F Music Mute. 0 = Unmuted, 1 = Muted. [06] I2S(1) ATTENUATION 7 6 5 4 3 2 LS1M RES LS1A [5:0] RS1A [5:0] REV. 0 1 0 7 RS1M 6 RES 5 4 3 DEFAULT = [0x8080] 2 1 0 RS1A [5:0] Right I2S(1) Attenuation register. The LSB represents ­1.5 dB, 000000 = 0 dB and the range is 0 dB to ­94.5 dB. ­33­ AD1815 AD1815 RS1M LS1A [5:0] LS1M Right I2S(1) Mute. 0 = Unmuted, 1 = Muted. Left I2S(1) Attenuation register. The LSB represents ­1.5 dB, 000000 = 0 dB and the range is 0 dB to ­94.5 dB. Left I2S(1) Mute. 0 = Unmuted, 1 = Muted. [07] I2S(0) ATTENUATION 7 6 5 4 3 2 LS0M RES LS0A [5:0] RS0A [5:0] RS0M LS0A [5:0] LS0M 2 2 4 3 DEFAULT = [0x8080] 2 1 0 RS0A [5:0] 1 0 7 6 5 4 3 PBC [7:0] DEFAULT = [0x0000] 2 1 0 1 0 7 6 5 4 3 PCC [7:0] DEFAULT = [0x0000] 2 1 0 1 0 7 6 5 4 3 CBC [7:0] DEFAULT = [0x0000] 2 1 0 1 0 7 6 5 4 3 CCC [7:0] DEFAULT = [0x0000] 2 1 0 Capture Current Count register. Contains the current Capture DMA Count. Reading and Writing must be done when CEN is de-asserted. [12] TIMER BASE COUNT 7 6 5 4 3 TBC [15:8] TBC [15:0] 5 Capture Base Count. This register is for loading the Capture DMA Count. Writing a value to this register also loads the same data into the Capture Current Count register. Loading must be done when Capture Enable (CEN) is de-asserted. When CEN is asserted, the Capture Current Count decrements once for every four-bytes which are transferred via a DMA cycle. The next transfer, after zero is reached in the Capture Current Count, will generate an interrupt and will reload the Capture Current Count with the value in the Capture Base Count. The Capture Base Count should always be programmed to Number-Bytes divided by four, minus one (NumberBytes/4) ­1). The circular software DMA buffer must be divisible by four to ensure proper operation. [11] CAPTURE CURRENT COUNT 7 6 5 4 3 2 CCC [15:8] CCC [15:0] 6 RES Playback Current Count register. Contains the current Playback DMA Count. Reads and Writes must be done when PEN is de-asserted. [10] CAPTURE BASE COUNT 7 6 5 4 3 CBC [15:8] CBC [15:0] 7 RS0M Playback Base Count.This register is for loading the Playback DMA Count. Writing a value to this register also loads the same data into the Playback Current Count register. You must load this register when Playback Enable (PEN) is de-asserted. When PEN is asserted, the Playback Current Count decrements once for every four-bytes which are transferred via a DMA cycle. The next transfer, after zero is reached in the Playback Current Count. will generate an interrupt and will reload the Playback Current Count with the value in the Playback Base Count. The Playback Base Count should always be programmed to Number-Bytes divided by four, minus one (Number-Bytes/4) ­1). The circular software DMA buffer must be divisible by four to ensure proper operation. [09] PLAYBACK CURRENT COUNT 7 6 5 4 3 2 PCC [15:8] PCC [15:0] 0 Right I2S(0) Attenuation register. The LSB represents ­1.5 dB, 000000 = 0 dB and the range is 0 dB to ­94.5 dB. Right I2S(0) Mute. 0 = Unmuted, 1 = Muted. Left I2S(0) Attenuation register. The LSB represents ­1.5 dB, 000000 = 0 dB and the range is 0 dB to ­94.5 dB. Left I2S(0) Mute. 0 = Unmuted, 1 = Muted. [08] PLAYBACK BASE COUNT 7 6 5 4 3 PBC [15:8] PBC [15:0] 1 2 1 0 7 6 5 4 3 TBC [7:0] DEFAULT = [0x0000] 2 1 0 Timer Base Count. Register for loading the Timer Count. Writing a value to this register also loads the same data into the Timer Current Count register. Loading must be done when Timer Enable (TE) is de-asserted. When TE is asserted, the Timer Current Count register decrements once for every specified time period. The time period ­34­ REV. 0 AD1815 AD1815 (10 µs or 100 ms) is programmed via the PTB bit in WS[44]. When TE is asserted, the Timer Current Count decrements once every time period. The next count, after zero is reached in the Timer Current Count register, will generate an interrupt and will reload the Timer Current Count register with the value in the Timer Current Count register. [13] TIMER CURRENT COUNT 7 6 5 4 3 TCC [15:8] TCC [15:0] 2 1 7 6 5 4 3 TCC [7:0] DEFAULT = [0x0000] 2 1 0 Timer DMA Current Count register. Contains the current timer count. Reading and Writing must be done when TE is de-asserted. [14] MASTER VOLUME ATTENUATION 7 6 5 4 3 2 1 LMVM 0 RES 0 LMVA [4:0] 7 6 RMVM 5 4 3 RES DEFAULT = [0x0000] 2 1 0 RMVA [4:0] RMVA [4:0] Right Master Volume Attenuation. The LSB represents ­1.5 dB, 00000 = 0 dB and the range is 0 dB to ­46.5 dB. This register is added with the HARDWARE VOLUME BUTTON MODIFIER to produce the final DAC Master Volume attenuation level. See HARDWARE VOLUME BUTTON MODIFIER description for more details. RMVM Right Master Volume Mute. 0 = Unmuted, 1 = Muted. LMVA [4:0] Left Master Volume Attenuation. The LSB represents ­1.5 dB, 00000 = 0 dB and the range is 0 dB to ­46.5 dB. This register is added with the HARDWARE VOLUME BUTTON MODIFIER to produce the final DAC Master Volume attenuation level. See HARDWARE VOLUME BUTTON MODIFIER description for more details. LMVM Left Master Volume. Mute 0 = Unmuted, 1 = Muted. [15] CD GAIN/ATTENUATION 7 6 5 4 3 LCDM RCDA [4:0] RCDM LCDA [4:0] LCDM RES 2 RSYA [4:0] RSYM LSYA [4:0] LSYM RVDA [4:0] RVDM LVDA [4:0] LVDM RES RLA [4:0] RLM LLA [4:0] LLM REV. 0 6 RCDM 1 0 LSYA [4:0] 5 4 3 RES DEFAULT = [0x8888] 2 1 0 RCDA [4:0] 7 6 RSYM 5 4 3 RES DEFAULT = [0x8888] 2 1 0 RSYA [4:0] Right SYNTH Attenuation.The LSB represents ­1.5 dB, 00000 = +12 dB and the range is +12 dB to ­34.5 dB. Right SYNTH Mute. 0 = Unmuted, 1 = Muted. Left SYNTH Attenuation. The LSB represents ­1.5 dB, 00000 = +12 dB and the range is +12 dB to ­34.5 dB. Left SYNTH Mute. 0 = Unmuted, 1 = Muted. RES 2 1 0 LVDA [4:0] 7 6 RVDM 5 4 3 RES DEFAULT = [0x8888] 2 1 0 RVDA [4:0] Right VID Attenuation. The LSB represents ­1.5 dB, 00000 = +12 dB and the range is +12 dB to ­34.5 dB. Right VID Mute. 0 = Unmute, 1 = Muted. Left VID Attenuation. The LSB represents ­1.5 dB, 00000 = +12 dB and the range is +12 dB to ­34.5 dB. Left VID Mute. 0 = Unmuted, 1 = Muted. [18] LINE GAIN/ATTENUATION 7 6 5 4 3 LLM 7 Right CD Attenuation. The LSB represents ­1.5 dB, 00000 = +12 dB and the range is +12 dB to ­34.5 dB. Right CD Mute. 0 = Unmuted, 1 = Muted. Left CD Attenuation. The LSB represents ­1.5 dB, 00000 = +12 dB and the range is +12 dB to ­34.5 dB. Left CD Mute. 0 = Unmuted, 1 = Muted. [17] VID GAIN/ATTENUATION 7 6 5 4 3 LVDM 0 LCDA [4:0] [16] SYNTH GAIN/ATTENUATION 7 6 5 4 3 2 LSYM 1 RES 2 LLA [4:0] 1 0 7 RLM 6 5 RES 4 3 DEFAULT = [0x8888] 2 1 0 RLA [4:0] Right LINE Attenuation. The LSB represents ­1.5 dB, 00000 = +12 dB and the range is +12 dB to ­34.5 dB. Right Line Mute. 0 = Unmuted, 1 = Muted. Left LINE Attenuation. The LSB represents ­1.5 dB, 00000 = +12 dB and the range is +12 dB to ­34.5 dB. Left Line Mute. 0 = Unmuted, 1 = Muted. ­35­ AD1815 AD1815 [19] MIC/MONO_IN GAIN/ATTENUATION 7 6 5 4 3 2 1 MCM M20 MA [4:0] MM MCA [4:0] M20 MCM RES 7 MCA [4:0] 6 MM 5 4 3 RES DEFAULT = [0x8888] 2 1 0 MA [4:0] MONO IN Attenuation. The LSB represents ­1.5 dB, 00000 = +12 dB and the range is +12 dB to ­34.5 dB. MONO IN Mute. Microphone Attenuation. The LSB represents ­1.5 dB, 0000 = +12 dB and the range is ± 12 dB to ­34.5 dB. Microphone 20 dB Gain. The M20-bit enables the Microphone +20 dB gain stage. Microphone Mute. [20] ADC SOURCE Select and ADC PGA 7 6 5 4 3 2 1 LAGC LAS [2:0] LAG [3:0] RAG [3:0] 0 0 7 RAGC 6 5 RAS [2:0] 4 3 DEFAULT = [0x0000] 2 1 0 RAG [3:0] LAGC Right ADC Gain Control ADC source select and GAIN. For GAIN, LSB represents +1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. Right Automatic Gain Control (AGC) Enable, 0 = Enabled, 1 = Disabled. Left ADC Gain Control ADC source select and GAIN. For GAIN, LSB represents +1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. Left Automatic Gain Control (AGC) Enable, 0 = Enabled, 1 = Disabled. RAS [2:0] 000 001 010 011 100 101 110 111 ADC Right Input Source R_LINE R_OUT R_CD R_SYNTH R_VID Mono Mix Reserved Reserved RAGC LAG [3:0] [32] CHIP CONFIGURATION 7 6 5 4 3 2 WSE CDE RES CNP RES I2SF0 [1:0] I2SF1 [1:0] COF [3:0] IMR IME CNP CDE WSE LAS [2:0] 000 001 010 011 100 101 110 111 1 IME 0 IMR 7 ADC Left Input Source L_LINE L_OUT L_CD L_SYNTH L_VID MIC MDM_IN Reserved 6 5 COF [3:0] 4 3 DEFAULT = [0x00F0] 2 1 0 I2SF1 [1:0] I2SF0 [1:0] I2S Port Configuration for serial data type. 00 Disabled 01 Right Justified 10 I2S Justified 11 Left Justified Clock Output Frequency. Programmable clock output on PCLKO pin is determined using the following formula PCLKO = 256 × SS[38]/2COF where COF = 0:11. If COF > 11, then PCLKO is disabled. ISA Modem Enable. Set to "1" for host based modem. ISA Moden Resync. Write "1" to resynchronize modem. Capture not equal to Playback. 0 Capture = Playback. The capture sample rate is determined by the playback sample rate in SS Indirect Register [02]. 1 Capture not equal to Playback CD Enable, Set to "1" when a CD player is connected to I2S (0). Sound System Enable. 0 = Sound Blaster Mode. 1 = Sound System Mode under Windows. Note: When in Sound Blaster Mode, the Codec ADC and DAC channels will be used solely for converting Sound Blaster data. ­36­ REV. 0 AD1815 AD1815 [33] DSP CONFIGURATION 7 6 5 4 3 DS1 DS0 DIT DME DMR DFS [2:0] I0I I1I FMI PBI CPI I0T I1T ADR DMR DME DIT DS0 DS1 2 ADR 1 I1T 0 I0T 7 CPI 6 PBI 5 FMI 4 I1I DEFAULT = [0x0000] 2 1 0 DFS [2:0] 3 I0I DSP Frame Sync Source. Sets the DSP Port Frame Sync according to the following source. 000-Maximum Frame Rate 001-I2S 001-I2S(0) Sample Rate 010-I2S 010-I2S(1) Sample Rate 011-Music Synthesizer Sample Rate 100-Sound System Playback Sample Rate 101-Sound System Capture Sample Rate 111-Reserved I2S(0) Data Intercept. 0 = Disable, 1 = Intercept I2S(0) Data Enabled. I2S(1) Data Intercept. 0 = Disable, 1 = Intercept I2S(1) Data Enabled. FM Music Synthesizer Data Intercept. 0 = Disable, 1 = Intercept FM Music Data Enabled. Playback Data Intercept. 0 = Disable, 1 = Intercept Playback Data Enabled. Capture Data Intercept. 0