ACS401 ACS406 ACS406CS ACS406EVBL ACS406EVB-P ACS4060 ACS405A ACS406EVB 8B10B - Datasheet Archive

 

ACS406 EVB Evaluation Board Users Manual Optical driver/receiver IC chip set for long haul T1/E1 and T2/E2 transmission for

 

ACS401 ACS401 - Evaluation Board ACS406 ACS406 EVB Evaluation Board Users Manual Optical driver/receiver IC chip set for long haul T1/E1 and T2/E2 transmission for single fiber applications. Main Features General Description * This ACS406 ACS406 EVB Users Manual should be read in conjunction with the ACS406CS ACS406CS data sheet describing the detailed specification for the chip set. User configuration options with the PCB The ACS406 ACS406 EVB has the provision for external signal input via industrial standard BNC connectors and a 26 way ribbon connector. Internal or external transmission clock generation. Synchronous input data coding types. Data input/output via BNC or Ribbon cable. Data rate (determined by XTAL). 1,2,4,8 multi-channel operation. Support channels. Diagnostic and locking modes. BARLED The ACS406 ACS406 EVB is supplied PRE-SETUP with either Laser Duplex Devices (Part no. ACS406EVBL ACS406EVBL) or Ping Pong LED (Part no. ACS406EVB-P ACS406EVB-P) depending on the particular requirement as ordered. IC3 Equivalent schematic of the ACS406 ACS406 Evaluation Board VDD ON SW3 LED drivers DCD HB2 PPLED HB1 Laser Duplex Device (LDD) VA+ 680 LOSS CM2 DM2C4 POL2 DM1C1 TRSEL DM1C3 DR4 DR2 FHOLD DM2C2 CM3 CM1 DM1C4 RPOS4 TCLK2 TCLK4 TmD2 TmD4 TPOS2 TPOS4 TNEG2 TNEG4 o o o o o o o o o o 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 o o o o o o o o o o DM2C2 DM1C2 FHOLD RESEL CKM CKC M4B POL1 DM2C1 DM2C3 DR5 RxdatTxdat ENTX ENRXB Rxdata+ pin36 pin37 pin69 pin70 SCEXT pin72 DR1 J6 TM1 TM2 TM3 TM4 PNN J2 LASER Txdat ENTX ENRXB Rxdata+ DM2C1 DM1C1 DM1C1 DM2C1 DR3 RIBB1 - 34 way ribbon RmCLK o1 2o RCLK4 RCLK2 RCLK3 o3 4o RmD1 RCLK1 o5 6o RmD3 RmD2 o7 8o RmD4 RNEG1 o 9 10 o RNEG2 RNEG3 o 11 12 o RNEG4 RPOS1 o 13 14 o RPOS2 TRSEL DM2C3 DM1C3 DR5 DR4 DR3 DR2 DR1 PNP M4B CKM VDD LAN o o o o o o o o o o o o o ACS4060 ACS4060 DM1C2 FRAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 TxFLG J8 J1 RxFLG J5 VDD J3 LASERX VDD J4 PINRX SW2 SW4 XTO RESEL o o o o o o o o o o o o o XTI CKC SW1 ERRC ERRL LOSS DCD POL1 POL2 DM1C4 DM2C4 CM1 CM2 CM3 FRAME RIBB2 - 26 way ribbon 1 uF 680 680 ERRC LAP ERRL TPOS1 RPOS1 TCLK1 RCLK1 * * * * * * * ACS405A ACS405A * DVDD * The ACS406 ACS406 EVB supports all operational modes using the switches CM(3:1), diagnostic mode using the switches DM1Cx and DM2Cx and all data rates and distance modes using switches DR(5:1). The ACS406 ACS406 EVB supports NRZ, AMI, B8ZS and HDB3 data coding formats. RSET2 * * * Offers full duplex serial transmission through a single fiber-optic cable. Supports E1/T1 and E2/T2 data rates. Incorporates maintenance channel at 64kbps. Link lengths up to 25km with a 50km mode at reduced bandwidth. Support for bi-directional Laser Duplex Devices or PPLEDs. Support for HDB3/AMI/NRZ/B8ZS data formats. VB L = 47 µH R < 1 PORB PCBSW VDD XTAL1 Cpad 100nF GND Cpad TERM1 (VDD) +5V RPOS3 TCLK1 VA+ L = 47 µH R < 1 TCLK3 + TmD1 TmD3 TPOS1 RPOS1 TCLK1 RCLK1 TPOS1 TPOS3 TNEG1 Zener diode 100nF 100 µ F 100 nF GND BNC1 BNC2 BNC3 BNC4 TERM2 (GND) 0V TNEG3 TmCLK 1 ACS406CS ACS406CS Chip Set Evaluation Board Issue 1.0 May 1999 5 HIGH (Logic1) then PINN and PINP are connected to the receiver. For PPLED applications, PINRX = LOW (Logic0). Data Coding The main synchronous channels may use NRZ, AMI, HDB3, B8ZS coding methods. The desired mode is selected by POL1 and POL2 input pins, as shown in the ACS406CS ACS406CS data sheet, Table 2. Jumper J5 Jumper J5 allows the monitoring of RXFLG from the ACS405A ACS405A (Pin 14). For Non-Return-to-Zero (NRZ) coding, data is applied directly to TPOS inputs, and output data appears only on the RPOS output pins . When using NRZ code, unconnected TNEG input pins will automatically pull-up to VD+. In addition, the ACS4060 ACS4060 will assert a continuous Low on redundant RNEG output pins. Jumper J6 Jumper J6 defines the input of ACS4060 ACS4060 Pin 36. This should always be set to LOW (Logic0) for normal operation. AMI, B8ZS and HDB3 coding is normally bipolar. However, it is possible to interface with the ACS4060 ACS4060 using two inputs and outputs rather than a single bipolar interface. Data equivalent to positive excursions of the bipolar AMI/B8ZS/HDB3 signal are applied as a HIGH (Logic1) to TPOS, while data equivalent to negative excursions are applied as a HIGH (Logic1) to TNEG. Similarly, AMI/B8ZS/HDB3 positive excursions will appear as a HIGH (Logic1) on RPOS and negative excursions will appear as a HIGH (Logic1) on RNEG. Jumper J8 Jumper J8 defines the input of ACS4060 ACS4060 Pin 37. This should always be set to LOW (Logic0) for normal operation. Switch Bank SW1 Switch SW1 defines the logic levels of signals DR(5:1), DM1C3, DM2C3, TRSEL. Switch settings HIGH, Logic1 = switch up; LOW, Logic0 = switch down. (Uses resistor block R6 for pull up). Fiber Interface The optical fiber interface supports all operational modes of the ACS406CS ACS406CS chip set. The interface contains all of the necessary components including a variable resistor R16 to adjust the transmit current. The ACS406 ACS406 EVB can be equipped with Laser Duplex Devices or PPLEDs. This will be PRE-SET and should not be changed. DR(5:1) Switches The DR(5:1) switches on SW1 set the configuration for the data rates and the number of channels. DM1C3, DM2C3 Switches Configuration of the Board using Jumpers The DM2C3/DM1C3 switches on SW1 set the diagnostic modes for data channel 3 with the associated TCLK3/RCLK3. Jumper J1 TRSEL Switch Jumper J1 allows the monitoring of TXFLG from the ACS405A ACS405A (pin 37). The TRSEL switch on SW1 sets the Tx clock edge on which the data is valid. Jumper J2 Switch Bank SW2 Jumper J2 defines the input of the ACS405A ACS405A LASER (Pin 6) to select the type optical component between a Laser Duplex Device or a PPLED. Set LASER = HIGH (Logic 1) for interfacing to Lasers. For PPLED, set LASER = LOW (Logic 0). Switch SW2 defines the logic levels of signals DM2C1, DM1C1 and ACS4060 ACS4060 Pins 69-73. Switch settings HIGH, Logic1 = switch up; LOW, Logic 0 = switch down. (Uses resistor block R7 for pull up). Jumper J3 5 DM2C1, DM1C1 Switches Jumper J3 defines the input of the ACS405A ACS405A LASRX (Pin 8) to select the type of optical component between a Laser Duplex Device or a PPLED. When LASRX = HIGH (Logic1) then LAN and LAP are connected to the receiver, required for PPLED applications. For all other combinations, LASRX = LOW (Logic0). The DM2C1/DM1C1 switches on SW2 set the diagnostic modes for data channel 1 with the associated TCLK1/RCLK1. Pins 69, 70 and 72 The switch on SW2 to ACS4060 ACS4060 Pins 69, 70 and 72 should be set LOW (Logic 0) at all times for normal operation. Jumper J4 Jumper J4 defines the input of the ACS405A ACS405A PINRX (Pin 13) to select the type optical component between a Laser Duplex Device or a PPLED. When PINX = ACS406CS ACS406CS Chip Set Evaluation Board Issue 1.0 May 1999 2 SCEXT Switch FHOLD Switch SCEXT (ACS4060 ACS4060 Pin 71) switch on SW2 controls the selection of the system clock between an external or internal clock. When SCEXT = HIGH, (Logic 1) then the external clock applied to input ECLK (ACS4060 ACS4060 Pin 37). When SCEXT = LOW (Logic 0) the system clock will be generated from the XTI/XTO (ACS4060 ACS4060 Pins 60, 59). The FHOLD switch on SW4 sets the device for symmetrical (HIGH, Logic 1) or asymmetrical (LOW, Logic 0) data communication. The most common setting is FHOLD = HIGH (Logic 1) DM2C2, DM1C2 Switches The DM2C2/DM1C2 switches on SW4 set the diagnostic modes for data channel 2 with the associated TCLK2/RCLK2. Switch Bank SW3 Switch SW3 defines the logic levels of signals FRAME, CM(3:1), DM2C4, DM1C4, POL(2:1). Ribbon connector RIBB2 Switch settings HIGH, Logic1 = switch up; LOW, Logic 0 = switch down. (Uses resistor block R8 for pull up). A 26 way ribbon connector interface is provided on the PCB. FRAME Switch 2 - M4B Four Channel Maintenance Mode. The switch on SW3 to pins 55, 56 and 58 should be set LOW (Logic 0) at all times for normal operation. 3 - CKC Main Channel Clock select. 1 - N/A 4 - CKM Maintenance Channel Clock select. CM(3:1) Switches 5 - RESEL Receive Edge select. The CM(3:1) switches on SW3 set the configuration and locking modes such as Full duplex, slave and master. 6 - FHOLD Format Hold. 7 - DM1C2 Diagnostic Mode for Channel 2. 8 - DM2C2 Diagnostic Mode for Channel 2. DM2C4, DM1C4 Switches 9 - FRAME FRAME Mode select. The DM2C4/DM1C4 switches on SW3 set the diagnostic modes for data channel 4 with the associated TCLK4/RCLK4. 10 - CM3 Configuration Mode select. 11 - CM2 Configuration Mode select. POL(2:1) Switches 12 - CM1 Configuration Mode select. The POL(2:1) switches on SW1 sets the configuration for the specific data input signal coding type. 13 - DM2C4 Diagnostic Mode for Channel 4. 14 - DM1C4 Diagnostic Mode for Channel 4. 15 - POL2 Input Data Polarity select. Switch Bank SW4 16 - POL1 Input Data Polarity select. Switch SW4 defines the logic levels of signals M4B, CKC, CKM, RESEL, FHOLD, DM2C2, DM1C2. 17 - DM1C1 Diagnostic Mode for Channel 1. 18 - DM2C1 Diagnostic Mode for Channel 1. Switch settings HIGH, Logic1 = switch up; LOW, Logic 0 = switch down. (Uses resistor block R9 for pull up). 19 - TRSEL Transmit Edge select. 20 - DM2C3 Diagnostic Mode for Channel 3. M4B Switch 21 - DM1C3 Diagnostic Mode for Channel 3. The M4B switch on SW4 sets the number of maintenance channels available, either 1 or 4. 22 - DR5 Data Rate select. CKC Switch 24 - DR3 Data Rate select. The CKC switch on SW4 sets TCLK1/2 clock as an output (LOW, Logic 0) or as an input (HIGH, Logic 1). 25 - DR2 Data Rate select. 23 - DR4 Data Rate select. 26 - DR1 Data Rate select. CKM Switch The CKM switch on SW4 sets TmCLK1/2 clock as an output (LOW, Logic 0) or as an input (HIGH, Logic 1). RESEL Switch The RESEL switch on SW4 sets the Rx clock edge on which the data is valid. 3 ACS406CS ACS406CS Chip Set Evaluation Board Issue 1.0 May 1999 5 Ribbon connector RIBB1 BNC connectors A 34 way ribbon connector interface is provided on the PCB. In addition to the 26 and 34 way ribbon connector interfaces, there are 4 BNC connector interfaces provided on the PCB. 1 - RmCLK Support Channel Receive Clock. TPOS1 - TPOS1 Transmit Data Positive channel 1. 2 - RCLK4 Receive Clock. RPOS1 - RPOS1 Receive Data Positive channel 1. 3 - RCLK3 Receive Clock. TCLK1 - Transmit clock. 4 - RCLK2 Receive Clock. RCLK1 - Receive clock. 5 - RCLK1 Receive Clock. NOTE: provision has been made on the ACS406EVB ACS406EVB for 100 Ohm termination resistor to be inserted if the BNC interface is to be used with 100 Ohm equipment. The standard configuration will leave R1 and R2 unpopulated. If the ACS4060 ACS4060 is configured to generate the transmit clock internally (CKC=0, Logic 0) to be driven out on the TCLK pin and accesssible via the BNC connector TCLK1, the R2 resistor must be removed. 6 - RmD1 Receive Data Negative channel 1. 7 - RmD2 Receive Data Negative channel 2. 8 - RmD3 Receive Data Negative channel 3. 9 - RmD4 Receive Data Negative channel 4. 10 - RNEG1 Receive Data Negative channel 1. 11 - RNEG2 Receive Data Negative channel 2. 12 - RNEG3 Receive Data Negative channel 3. Power on Reset 13 - RNEG4 Receive Data Negative channel 4. The PORB switch will reset the device by forcing the PORB input Low. 14 - RPOS1 Receive Data Positive channel 1. 15 - RPOS2 Receive Data Positive channel 2. Indicator BARLED 16 - RPOS3 Receive Data Positive channel 3. The LEDs are provided to show the status of various signals. The LED block is driven by IC3. 17 - RPOS4 Receive Data Positive channel 4. 18 - TCLK1 Transmit Clock. ERRC ERRL LOSS DCD ON 19 - TCLK2 Transmit Clock. 20 - TCLK3 Transmit Clock. 21 - TCLK4 Transmit Clock. Coding error detected. Coding error detected. Loss of signal. Data Carrier Detect. Power supply connected. ERRC gives an indication of the error count in the 8B10B 8B10B coding rules. The ERRC LED is normally 'off' and will be forced 'on' on detection of an error. 22 - TmD1 Transmit Maintenance data. 23 - TmD2 Transmit Maintenance data. 24 - TmD3 Transmit Maintenance data. ERRL latches an error in the 8B10B 8B10B coding rules. The indicator LED, initially 'off', goes 'on' and remains 'on' on detection of an error. The LED may be reset to 'off', by applying a Power On Reset via PORB or by temporarily removing the fiber optic cable. 25 - TmD4 Transmit Maintenance data. 26 - TPOS1 Transmit Data Positive channel 1. 27 - TPOS2 Transmit Data Positive channel 2. LOSS gives an indication of reliable data. The indicator LED will go 'on' when the receive data is unreliable. For normal operation, the LED is 'off' indicating good and reliable receive data. 28 - TPOS3 Transmit Data Positive channel 3. 29 - TPOS4 Transmit Data Positive channel 4. 30 - TNEG1 Transmit Data Negative channel 1. 32 - TNEG3 Transmit Data Negative channel 3. DCD indicates Data Carrier Detection. The indicator LED will go 'on' when the modems have synchronised and are communicating. 33 - TNEG4 Transmit Data Negative channel 4. ON indicates power is applied to the PCB. 31 - TNEG2 Transmit Data Negative channel 2. 5 - 34 - TmCLK - Support Channel Transmit Clock. Optical component footprints Ribbon Connector SK1 The ACS406EVB ACS406EVB has the provision for a number of optical components that can be used in a single wavelength Ping Pong Time Division Duplex system. The pin configurations are defined in detail in the ACS406CS ACS406CS data sheet. Acapella can supply the data sheets for the approved optical components on request. HB1 is the footprint for Laser Duplex Ribbon connector SK1 is used to test and commission the ACS406 ACS406 EVB. It serves no function on the board itself. ACS406CS ACS406CS Chip Set Evaluation Board Issue 1.0 May 1999 4 Devices from various suppliers or the Bookham Laser Transceiver. HB2 is the footprint for the PPLED from MITEL (1A-212). Modes of Operation The ACS406 ACS406 EVB may be configured in any of the modes described in the ACS406CS ACS406CS data sheet by selecting the appropriate logic levels on the switches in banks SW1-4. Each of the inputs connected to the switches has a pull-up resistor to VDD. The switch, when closed, will force the chosen input Low, and when open will allow the input to pull-up High via the external resistor. Optical Operational Modes The ACS4060 ACS4060 has four optical operational modes controlled by the pins LASER, LASRX and PINRX on the ACS405A ACS405A. Mode Switches DR(5:1) on SW1 select the operational mode as detailed in the ACS406CS ACS406CS data sheet. This in combination with the value of XTAL1 and the Divide Constant will define the communication frequency. All modes are supported provided the correct XTAL is inserted. See section headed Data Rate Selection in the ACS406CS ACS406CS data sheet for more details. Optical Device 1 Laser Duplex using 4-pin Laser. 2 Laser Duplex using 3-pin Laser. 3 LED Duplex. 4 LED (ping-pong). Switches CM(3:1) on SW3 select the locking/ diagnostic mode as detailed in the ACS406CS ACS406CS data sheet. All modes are supported. See section headed Configuration Modes in the ACS406CS ACS406CS data sheet for more details. System Clock The system clock on the ACS406CS ACS406CS chip set may be derived from an external source or generated locally using the on-chip crystal oscillator. Switches DM2Cx and DM1Cx offer independent diagnostics control of the data channels associated with each clock domain TCLK/RCLK. See section headed Diagnostic Modes in the ACS406CS ACS406CS data sheet for more details. The external oscillator XTAL1 is a fundamental parallel resonance crystal with appropriate padding capacitors. For an internally generated clock, the input SCEXT (Pin 71) should be connected to GND. Switch SETB is used to set up the LASER 'on' current. See section headed LASER Adjustment Procedure in the ACS406CS ACS406CS data sheet for more details. If it is required to drive the device with an externally generated system clock source, then the clock source should be connected to input pin ECLK with SCEXT connected to VD+. It is often more convenient to drive boards containing multi ACS406CS ACS406CS chip sets from a single system clock source. LED Current The LED current should be set up in accordance with the section headed Control of LED current in the ACS406CS ACS406CS data sheet. This will be pre-set on the ACS406 ACS406 EVB if the LED option is incorporated. The system clock frequency is determined by the choice of data rates and is tabulated in the section Data Rate Selection in the ACS406CS ACS406CS data sheet. LASER Current The system clock must have a maximum tolerance of +/- 50 ppm. The LASER current should be set in accordance with the section headed Control of Laser current in the ACS406CS ACS406CS data sheet. This will be pre-set on the ACS406 ACS406 EVB if the LASER option is incorporated. Power Supply The ACS406 ACS406 EVB operates from a single +5 Volt power supply. Connect a 5 Volt power supply between TERM1 (VDD) and TERM2 (GND). 5 ACS406CS ACS406CS Chip Set Evaluation Board Issue 1.0 May 1999 5 Optical configurations The ACS406 ACS406 EVB can be delivered with either the PPLED for multi mode applications or Laser Duplex Devices for single mode applications. The ACS406 ACS406 EVB will be pre-setup for the option ordered. For the PPLED option, please order ACS406 ACS406 EVB-P. For the Laser option, please order ACS406 ACS406 EVB-L. Pricing is available on request. Getting Started In order to get started and demonstrate full-duplex communication over a single fibre take the following sequence of events. 5 16) Press the PORB once on each board to poweron-reset each device. 17) Propagate transmit data through the BNC socket TPOS1, the received data will appear at the BNC socket RPOS1 on the far-end board. 18) If it is not convenient to test the system with synchronous data, then simply apply low frequency asynchronous data to the TPOS1 socket and allow the system to over-sample the input and transmit the data over the link to the far-end RPOS1. See the ACS406CS ACS406CS data sheet section Asynchronous Data Rates and Asynchronous Communication for more details on Over-Sampling factors and Sampling Jitter. 1) Place a length of the appropriate fiber between the ACS406 ACS406 EVBs. 2) Connect a +5V Power supply between the TERM1 (VDD) and TERM2 (GND) terminals provided on the board . 3) Make sure that the switch bank SW1, SW2 and SW3 are set in accordance with section headed, Switch Banks SW1, SW2 and SW3. 4) Set the CM(3:1) switches on board 1 to be all LOW Logic 0 (the down position), this will select "full-duplex" with "drift" lock. Set the CM(3:1) switches on board 2 so to be all HIGH Logic 1 (the up position), this will select "fullduplex" with "active" lock. 5) Set the DR switches DR(5:1) on both boards to select a transmission frequency in combination with the XTAL value chosen for the required E1, T1, E2 or T2 frequency of operation. NOTE: The ACS406 ACS406 EVB kit will be supplied with an XTAL that is appropriate for the required application. 6) Set the DM2C(4:1) and the DM1C(4:1) switches on both boards to all Logic 0 (the down position). 7) Set the switch POL2 and POL1 on both boards HIGH Logic 1 (the up position), this will select NRZ code. 8) Set the switch RSL (RESEL) on both boards to HIGH Logic 1 (the up position). 9) Set the switch TRSL (TRESEL) on both boards to HIGH Logic 1 (the up position). 10) Set the switch SETB on both boards to HIGH Logic 1 (the up position). 11) Set the switch M4B on both boards to HIGH Logic 1 (the up position). 12) Set the switch Frame on both boards to LOW Logic 0 (the down position). 13) Set the switch Fhold on both boards to HIGH Logic 1 (the up position). 14) Set the switch CKC on both boards to LOW Logic 0 (the down position). 15) Set the switch CKM on both boards to LOW Logic 0 (the down position). ACS406CS ACS406CS Chip Set Evaluation Board Issue 1.0 May 1999 6 PCB Component overlay of the ACS406CS ACS406CS Chip Set Evaluation Board (not drawn to scale). 5 PCB Layout Recommendations The performance of a fiber optic modem using the ACS406CS ACS406CS chip set is partially dependent on the layout of the printed circuit board containing the recommended components. The most critical layout issues apply to the ACS405A ACS405A and the associated external components. We have provided a separate document entitled ACS405CS ACS405CS Chip Set Reference Design and Gerber plots of the critical routing layers represented by Layer1 and Layer4 for a reference to assist in the development of a custom PCB design. Please refer to the ACS405CS ACS405CS section of the web site. 7 ACS406CS ACS406CS Chip Set Evaluation Board Issue 1.0 May 1999 ACS406 ACS406 Evaluation Board Component Listing This BOM refers to the component layout of the ACS406CS ACS406CS Evaluation kit, as shown on ACS406CS ACS406CS_EVB_Schematic.pdf which can be found in the ACS406CS ACS406CS section of the web site. Instance Value Type Additional information C14, C17, C12 C13, C11 C16 C15 100nF 10nF 1nF 100pF CAP CAP CAP CAP 63V, tantalum de-coupling, SM type 63/50V 63/50V, multilayer ceramic, SM type 63/50V 63/50V, multilayer ceramic, SM type 50V, multilayer ceramic, SM type C C5 C6, C7 C1, C3 C4, CA, CB 100uF 100nF 22pF 100nF 100nF CAP CAP CAP CAP CAP 25V, tantalum, lead type 16V, ceramic disc, lead type 100V, low K, ceramic, lead type 16V, ceramic disc, lead type 16V, ceramic disc, lead type R18 R15 R17 R11, R12, R13 R16 27 1K 3.3K 680 50K RES RES RES RES POT 0.125W, 1%, thin flim, SM type 0.125W, 1%, thin flim, SM type 0.1W, 1%, thin flim, SM type 0.1W, 1%, thin flim, SM type 250mW, multi turn, SM type R6, R7, R8, R9 R5 R20 R4 4.7K 330 51K 100K RES RES RES RES Single-In Line Single-In Line 0.25W, 5%, carbon flim, lead type 0.25W, 5%, carbon flim, lead type L2, L5 47µH R