ACEX1K datasheet and application note, data sheet, circuit, pdf, cross reference, pinout

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ACEX1K Datasheet, Circuit, PDF, Cross Reference, & Application Note Results

		1 - 11 of about 11 for ACEX1K
ACEX 1K	Altera Corporation	ACEX 1K Programmable Logic Device Family Data Sheet	628.32 Kb, 86 Pages.

ACEX 1K	Altera Corporation	AN 116: Configuring SRAM-Based LUT Devices	667.8 Kb, 102 Pages.

ACEX 1K	Altera Corporation	Figure 43 Design File for Configuring APEX 20K (43 KB)	42.61 Kb, 4 Pages.

ACEX 1K	Altera Corporation	ACEX Devices Brochure: Low-Cost Solutions for High Volume Applications	172.25 Kb, 4 Pages.

ACEX 1K	Altera Corporation	Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB)	36.58 Kb, 4 Pages.

ACEX 1K	Altera Corporation	Ordering Information	386.32 Kb, 6 Pages.

ACEX 1K	Altera Corporation	Configuring PLDs with FLASH Memory	42.62 Kb, 5 Pages.

ACEX 1K	Altera Corporation	EPC16 Configuration Device Data Sheet	750.55 Kb, 32 Pages.

ACEX1K	Altera Corporation	ACEX1K Programmable Logic Device Family Data Sheet	628.32 Kb, 86 Pages.

ACEX1K	Altera Corporation	Programmable Logic	1015.48 Kb, 88 Pages.

ACEX1K	N/A	Programmable Logic Device Family	362.86 Kb, 86 Pages.

	1 - 38 of about 38 for ACEX1K
First line: Bosch DPRAM Configurable Controller 1.01 stand-alone controller Controller Area Network (CAN) widely used automotive industrial applications. conforms Bosch 2.0B specification (2.0B Active). Core simple interface (8/16/32 configurable data width) with little endian adressing scheme. Hardware message Abstract: .. ACEX1K -1 1956 + 2 ESB 66 MHz. FLEX10KE FLEX10KE -1 1956 + 2 ESB 66 MHz. 8-bit CPU Core performance in ALTERA � devices. Device. Speed grade Logic Cells Fmax. CYCLONE -6 1967 + 2 ESB 124 MHz. CYCLONE2 -6 1890 + 2 ESB 135 .. Tags: DPRAM Bosch FLEX10KE APEX20KE A1600 datasheet abstract..	109.38 Kb	3 Pages	Original

First line: EP2C20F484C7 led sign diagram LED Sign Board Diagram Smart Station Sign Third Prize Smart Station Sign Institution: Participants: Instructor: Oriental Institute Technology Jian Jinrong, Zhan Yilin, Taida Xiao Ruxuan Abstract: .. ● Create an nRF2401 nRF2401 RF module on the Taurus ACEX1K development board. ● Compile nRF2401 nRF2401 RF module sub-drivers using the C language. ● Compile the main program control settings of the bus sub-module .. Tags: LED Sign Board Diagram led sign diagram EP2C20F484C7 datasheet abstract..	250.82 Kb	10 Pages	Original

First line: ACEX1K 10/100/1000Mbps Ethernet Core Reference Guide Version July 2002 Ethernet available different speeds (10/100/1000 10000Mbps) provides connectivity meet wide range needs from desktop switches. MorethanIP solutions provides solution each Ethernet application with library configurable (Medium Acc Abstract: .. Source code option for Altera CPLDs ACEX1K, APEX20KE APEX20KE , APEX-II or STRATIX or ASIC implementations. ALTR. Encrypted netlist for Altera CPLDs ACEX1K, APEX20KE APEX20KE , APEX-II or STRATIX . 5. 10/100 .. Tags: ACEX1K Ethernet-MAC ethernet phy altera rgmii specification 1gbps serdes datasheet abstract..	147.54 Kb	6 Pages	Original

First line: DFPSQRT Floating Point Pipelined Square Root Unit 2.90 DFPSQRT uses pipelined mathematics algorithm compute square root function. input number format according IEEE-754 standard. DFPSQRT supports single precision real numbers. SQRT operation pipelined levels. Input data every clock cycle. first resu Abstract: .. ACEX1K -1 1000 48 MHz. APEX20K APEX20K -1 970 50 MHz. APEX20KE APEX20KE -1 970 53 MHz. APEX20KC APEX20KC -7 970 62 MHz. APEX-II -7 970 83 MHz. MERCURY -5 975 99 MHz. STRATIX -5 725 96 MHz. CYCLONE -6 725 94 MHz. STRATIX-II -3 890 131 MHz. CYCLONE .. Tags: A1600 datasheet abstract..	106.8 Kb	3 Pages	Original

First line: DFP2INT Floating Point Integer Pipelined Converter 2.20 DFP2INT pipelined floating point integer converter. input output numbers format according IEEE-754 standard. DFP2INT supports single precision real numbers double word integers Bytes). Convert operation pipelined levels. Input data every clock Abstract: .. ACEX1K -1 335 71 MHz. APEX20K APEX20K -1 295 69 MHz. APEX20KE APEX20KE -1 295 67 MHz. APEX20KC APEX20KC -7 295 88 MHz. APEX-II -7 295 114 MHz. MERCURY -5 270 208 MHz. STRATIX -5 245 184 MHz. CYCLONE -6 245 165 MHz. STRATIX-II -3 185 214 MHz .. Tags: datasheet abstract..	98.81 Kb	3 Pages	Original

First line: DFPDIV Floating Point Pipelined Divider Unit 2.15 DFPDIV uses pipelined mathematics algorithm divide arguments. input numbers format according IEEE754 standard. DFPDIV supports single precision real number. Divide operation pipelined levels. Input data every clock cycle. first result appears after c Abstract: .. ACEX1K -1 3100 30 MHz. APEX20K APEX20K -1 2720 40 MHz. APEX20KE APEX20KE -1 2720 40 MHz. APEX20KC APEX20KC -7 2720 42 MHz. APEX-II -7 2720 50 MHz. MERCURY -5 2780 65 MHz. STRATIX -5 2270 88 MHz. CYCLONE -6 2270 86 MHz. STRATIX-II -3 2040 .. Tags: ieee floating point vhdl IEEE754	98.69 Kb	3 Pages	Original

First line: DFPMUL Floating Point Pipelined Multiplier Unit 2.70 DFPMUL uses pipelined mathematics algorithm multiply arguments. input numbers format according IEEE754 standard. DFPMUL supports single precision real number. Multiply operation pipelined levels. Input data every clock cycle. first result appears Abstract: .. ACEX1K -1 1340 40 MHz. APEX20K APEX20K -1 1210 50 MHz. APEX20KE APEX20KE -1 1210 50 MHz. APEX20KC APEX20KC -7 1210 51 MHz. APEX-II -7 1210 67 MHz. MERCURY -5 1290 77 MHz. STRATIX -5 440+8M1 93 MHz. CYCLONE -6 1170 72 MHz. STRATIX-II -3 410 .. Tags: ieee floating point vhdl digital clock vhdl code A1600 IEEE754	99.17 Kb	3 Pages	Original

First line: DINT2FP Integer Floating Point Pipelined Converter 2.32 DINT2FP pipelined integer floating point converter. input output numbers format according IEEE-754 standard. DINT2FP supports double word integers Bytes) single precision real numbers. Convert operation pipelined levels. Input data every clock Abstract: .. ACEX1K -1 570 80 MHz. APEX20K APEX20K -1 470 61 MHz. APEX20KE APEX20KE -1 470 73 MHz. APEX20KC APEX20KC -7 470 87 MHz. APEX-II -7 470 103 MHz. MERCURY -5 570 157 MHz. STRATIX -5 400 150 MHz. CYCLONE -6 385 156 MHz. STRATIX-II -3 330 234 MHz .. Tags: A1600 datasheet abstract..	94.28 Kb	2 Pages	Original

First line: APEX20KC DFPADD Floating Point Pipelined Adder Unit 2.50 DFPADD uses pipelined mathematics algorithm compute arguments. input numbers format according IEEE-754 standard. DFPADD supports single precision real number. operation pipelined levels. Input data every clock cycle. first result appears after Abstract: .. ACEX1K -1 1110 47 MHz. APEX20K APEX20K -1 955 55 MHz. APEX20KE APEX20KE -1 955 52 MHz. APEX20KC APEX20KC -7 955 68 MHz. APEX-II -7 955 88 MHz. MERCURY -5 975 117 MHz. STRATIX -5 845 107 MHz. CYCLONE -6 845 104 MHz. STRATIX-II -3 690 153 MHz .. Tags: APEX20KC ieee floating point vhdl IEEE754	98.86 Kb	3 Pages	Original

First line: DI2CSB Interface Slave Base version 1.15 two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CSB provides interface between passive target device e.g. memory, display, pressure sensors etc. bus. works slave receiver tra Abstract: .. ACEX1K -1 95 99 MHz. FLEX10KE FLEX10KE -1 95 95 MHz. MAX 7000AE 7000AE -4 50 107 MHz. MAX 3000A 3000A -4 50 107 MHz. MAX II -3 75 154 MHz. Core performance in ALTERA � devices. The main features of each Digital Core Design I2C compliant .. Tags: vhdl source code for i2c memory (read and write) vhdl code for i2c verilog code for transmission line DI2CSB	105.74 Kb	4 Pages	Original

First line: DI2CS Interface Slave 3.02 two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CS core provides interface between microprocessor /microcontroller bus. works slave transmitter slave receiver depending working mode determ Abstract: .. ACEX1K -1 170 107 MHz. FLEX10KE FLEX10KE -1 170 107 MHz. MAX 7000AE 7000AE -5 83 96 MHz. MAX 3000A 3000A -5 83 104 MHz. Control Register – Contains five control bits used for performing all types of I2C Bus transmissions. Status .. Tags: verilog code for transmission line DI2CS	109.27 Kb	4 Pages	Original

First line: 8259 D8259 Programmable Interrupt Controller 1.04 D8259 soft Core Programmable Interrupt Controller. fully compatible with 82C59A device. D8259 Core manages 8-vectored priority interrupts processor. Programming cascade allows vectored interrupts. More than vectored interrupts accomplished programmin Abstract: .. ACEX1K -1 413 78 MHz. FLEX10KE FLEX10KE -1 413 76 MHz. Core performance in ALTERA � devices. All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital .. Tags: 8088/8086 processor 8088 MCS-80/85 MCS-80 interrupt controller vhdl code download d8259 D8254 applications of 8259 82C59A 8259 Programmable Interrupt Controller 8259 MCS-80 85	105.42 Kb	4 Pages	Original

First line: DI2CM Interface Master 3.02 two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CM core provides interface between microprocessor microcontroller bus. work master transmitter master receiver depending working mode deter Abstract: .. ACEX1K -1 290 130 MHz. FLEX10KE FLEX10KE -1 290 140 MHz. MAX 7000AE 7000AE -5 149 64 MHz. MAX 3000A 3000A -7 149 47 MHz. Core performance in ALTERA � devices. All trademarks mentioned in this document http://www.DigitalCoreDesign .. Tags: DI2CM DI2CM	142.79 Kb	6 Pages	Original

First line: DI2CMS Interface Master/Slave 1.01 two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CMS core provides interface between microprocessor microcontroller bus. work master slave transmitter/receiver depending working mod Abstract: .. ACEX1K -1 411 107 MHz. FLEX10KE FLEX10KE -1 411 107 MHz. MAX 2 -3 291 187 MHz. MAX 7000AE 7000AE -5 198 67 MHz. MAX 3000A 3000A -7 198 49 MHz. Core performance in ALTERA � devices. DI2CMS implementation in I2C-bus system with Standard .. Tags: DI2CMS	116.97 Kb	6 Pages	Original

First line: DSPIS DSPIS Serial Peripheral Interface -Slave 1.01 DSPIS fully configurable slave device, designated operate with passive devices like memories, drivers etc. DSPIS allows user configure polarity phase serial clock signal SCK. serial clock line (SCK) synchronizes shifting sampling information indepe Abstract: .. ACEX1K -1 87 196 MHz. FLEX10KE FLEX10KE -1 87 204 MHz. MAX2 -3 79 257 MHz. MAX3K -5 57 114 MHz. MAX7K -5 57 114 MHz. Core performance in ALTERA � devices. T r a n s f e r F o r m a t s. Software can select any of four combinations .. Tags: DSPIS APEX20KE datasheet abstract..	113.63 Kb	5 Pages	Original

First line: DI2CM Interface Master 3.08 two-wire, bi-directional serial that provides simple efficient method data transmission over short distance between many devices. DI2CM core provides interface between microprocessor microcontroller bus. work master transmitter master receiver depending working mode deter Abstract: .. ACEX1K -1 287 135 MHz. FLEX10KE FLEX10KE -1 287 140 MHz. MAX 2 -3 241 187 MHz. MAX 7000AE 7000AE -5 137 67 MHz. MAX 3000A 3000A -7 137 49 MHz. Core performance in ALTERA � devices. The main features of each Digital Core Design I2C compliant .. Tags: DI2CM DI2CM	114.55 Kb	5 Pages	Original

First line: uart vhdl fpga D16450 Configurable UART 2.07 D16450 soft Core Universal Asynchronous Receiver/Transmitter (UART) functionally identical TL16C450. D16450 performs serial-to-parallel conversion data characters received from peripheral device MODEM, parallel-to-serial conversion data characters receive Abstract: .. ACEX1K -1 363 99 MHz. FLEX10KE FLEX10KE -1 363 98 MHz. Core performance in ALTERA � devices. D 1 6 X 5 0 U A R T S F A M I L Y O V E R V I E W. The family of DCD D16X50 D16X50 UART IP Cores combine a high–performance, low cost, and small .. Tags: uart vhdl fpga vhdl code for 8 bit ODD parity generator verilog code for uart communication datasheet of 16450 UART D16754 APEX20KE a VHDL description for an 8-bit even/odd parity c TL16C450	129.84 Kb	6 Pages	Original

First line: DSPI Serial Peripheral Interface Master/Slave 2.07 fully configurable master/slave device, which allows user configure polarity phase serial clock signal SCK. allows microcontroller communicate with serial peripheral devices. also capable interprocessor communications multi-master system. serial clo Abstract: .. ACEX1K -1 205 156 MHz. FLEX10KE FLEX10KE -1 205 156 MHz. MAX2 -3 181 209 MHz. MAX3K -5 119 96 MHz. MAX7K -5 119 96 MHz. Core performance in ALTERA � devices. All trademarks mentioned in this document http://www.DigitalCoreDesign .. Tags: DSPI A1600 SS7O SS0O	90.2 Kb	6 Pages	Original

First line: DSPI_FIFO Serial Peripheral Interface Master/Slave with FIFO 1.07 DSPI_FIFO fully configurable master/slave device, which allows user configure polarity phase serial clock signal SCK. DSPI_FIFO allows microcontroller communicate with serial peripheral devices. also capable interprocessor communicati Abstract: .. ACEX1K -1 369 103 MHz. FLEX10KE FLEX10KE -1 369 103 MHz. Core performance in ALTERA � devices. T r a n s f e r F o r m a t s. Software can select any of four combinations of serial clock SCK phase and polarity using two .. Tags: A1600 SS7O SS0O	91.93 Kb	6 Pages	Original

First line: DRPIC1655X High Performance Configurable 8-bit RISC Microcontroller 2.15 DRPIC1655X low-cost, high performance, 8-bit, fully static soft Core, dedicated operation with fast (typically onchip) dual ported memory. core been designed with special concern about power consumption. DRPIC1655X soft core so Abstract: .. ACEX1K -1 1150 64 MHz. FLEX10KE FLEX10KE -1 1150 59 MHz. Core performance in ALTERA � devices. Area utilized by the each unit of DRPIC1655X DRPIC1655X core in vendor specific technologies is summarized in table below. .. Tags: vhdl code for usart PIC16C55X PIC16C554 PIC16C554 PIC16C558	139.88 Kb	8 Pages	Original

First line: DF6811CPU 8-bit FAST Microcontrollers Family 2.17 Document contains brief description DF6811CPU core functionality. DF6811CPU advanced 8-bit Core with highly sophisticated, chip peripheral capabilities. DF6811CPU soft core binarycompatible with industry standard 68HC11 8-bit microcontroller achieve Abstract: .. ACEX1K -1 1785 34 MHz. FLEX10KE FLEX10KE -1 1785 32 MHz. Core performance in ALTERA � devices. I M P R O V E M E N T For user the most important is application speed improvement. The most commonly used arithmetic functions .. Tags: arithmetic instruction for microcontroller 68HC11 DF6811CPU	145.17 Kb	7 Pages	Original

First line: DF6808 8-bit FAST Microcontrollers Family 1.04 Document contains brief description DF6808 core functionality. DF6808 advanced 8-bit Core with highly sophisticated, chip peripheral capabilities. DF6808 soft core binary-compatible with industry standard 68HC08 8-bit microcontroller achieve performance Abstract: .. ACEX1K -1 2536 36 MHz. FLEX10KE FLEX10KE -1 2536 36 MHz. Core performance in ALTERA � devices. Area utilized by the each unit of DF6808 DF6808 core in vendor specific technologies is summarized in table below. Component .. Tags: verilog code for uart communication DF6808 DF6808	158.61 Kb	9 Pages	Original

First line: DFPIC1655X High Performance Configurable 8-bit RISC Microcontroller 2.02 DFPIC1655X low-cost, high performance, 8-bit, fully static soft Core, dedicated operation with fast memory (typically on-chip). core been designed with special concern about power consumption. DFPIC1655X software compatible wit Abstract: .. ACEX1K -1 804 39 MHz. FLEX10KE FLEX10KE -1 804 38 MHz. Core performance in ALTERA � devices. I M P R O V E M E N T Most instruction of DFPIC1655X DFPIC1655X is exe-cuted within 2 CLK cycles. Except the condi-tional program memory .. Tags: vhdl code for usart vhdl code for spi controller implementation on fp verilog HDL program to generate PWM PIC16C55X PIC16C554 free vhdl code download for usart PIC16C554 PIC16C558	133.92 Kb	7 Pages	Original

First line: DP8051CPU Pipelined High Performance 8-bit Microcontroller 4.02 DP8051CPU ultra high performance, speed optimized soft core singlechip 8-bit embedded controller dedicated operation with fast (typically on-chip) slow (off-chip) memories. core been designed with special concern about performance power Abstract: .. ACEX1K -1 56 MHz. APEX20K APEX20K -1 50 MHz. APEX20KE APEX20KE -1 68 MHz. APEX20KC APEX20KC -7 79 MHz. APEX-II -7 74 MHz. MERCURY -5 .. Tags: verilog code for uart communication function of internal data memory microcontroller DP8051CPU DP8051CPU	169.93 Kb	10 Pages	Original

First line: D16750 Configurable UART with FIFO 2.08 D16750 soft Core Universal Asynchronous Receiver/Transmitter (UART) functionally identical TL16C750. D16750 allows serial transmission modes: UART mode FIFO mode. FIFO mode internal FIFOs activated allowing bytes (plus bits error data byte RCVR FIFO) stored bo Abstract: .. ACEX1K -1 5431 93 MHz. FLEX10KE FLEX10KE -1 5431 94 MHz. 1 - FIFOs implemented in EAB’s – 1216 Bits Core performance in ALTERA � devices. All trademarks mentioned in this document are trademarks of their respective .. Tags: verilog code for uart communication D16750 TL16C750	135.41 Kb	7 Pages	Original

First line: D16550 Configurable UART with FIFO 2.08 D16550 soft Core Universal Asynchronous Receiver/Transmitter (UART) functionally identical TL16C550A. D16550 allows serial transmission modes: UART mode FIFO mode. FIFO mode internal FIFOs activated allowing bytes (plus bits error data byte RCVR FIFO) stored b Abstract: .. ACEX1K -1 5001 104 MHz. FLEX10KE FLEX10KE -1 5001 102 MHz. 1 - FIFOs implemented in EAB’s – 304 Bits Core performance in ALTERA � devices. All trademarks mentioned in this document are trademarks of their respective .. Tags: verilog code for uart communication TL16C550A TL16C550A	134.85 Kb	7 Pages	Original

First line: DRPIC166X High Performance Configurable 8-bit RISC Microcontroller 2.15 DRPIC166X low-cost, high performance, 8-bit, fully static soft Core, dedicated operation with fast (typically onchip) dual ported memory. core been designed with special concern about power consumption. DRPIC166X soft core softw Abstract: .. ACEX1K -1 1695 52 MHz. FLEX10KE FLEX10KE -1 1695 54 MHz. Core performance in ALTERA � devices. Area utilized by the each unit of DRPIC166X DRPIC166X core in vendor specific technologies is summarized in table below. Component .. Tags: vhdl code for usart verilog HDL program to generate PWM free vhdl code download for usart PIC16C6X	142.42 Kb	8 Pages	Original

First line: DF6805 8-bit FAST Microcontrollers Family 1.04 Document contains brief description DF6805 core functionality. DF6805 advanced 8-bit Core with highly sophisticated, chip peripheral capabilities. DF6805 soft core binary-compatible with industry standard 68HC05 8-bit microcontroller achieve performance Abstract: .. ACEX1K -1 1739 41 MHz. FLEX10KE FLEX10KE -1 1739 41 MHz. Core performance in ALTERA � devices. Area utilized by the each unit of DF6805 DF6805 core in vendor specific technologies is summarized in table below. Component .. Tags: verilog code for uart communication DF6805 DF6805	154.04 Kb	8 Pages	Original

First line: DFPIC165X High Performance 8-bit RISC Microcontroller 2.01 DFPIC165X low-cost, high performance, 8-bit, fully static soft Core, dedicated operation with fast memory (typically on-chip). core been designed with special concern about power consumption. DFPIC165X software compatible with industry stand Abstract: .. ACEX1K -1 648 50 MHz. FLEX10KE FLEX10KE -1 648 48 MHz. CPU – consisted of ALU, Control Unit, Bus Controller, Hardware Stack, 256 B RAM, 4k of Program memory. Core performance in ALTERA � devices. I M P R O V E M E N T .. Tags:* vhdl code for spi controller implementation on fp PIC16C58 PIC16C54 PIC16C55 PIC16C56 PIC16C57 PIC16C58	128.96 Kb	6 Pages	Original

First line: D16550 D16550 Configurable UART with FIFO 2.03 D16550 soft Core Universal Asynchronous Receiver/Transmitter (UART) functionally identical TL16C550A. D16550 allows serial transmission modes: UART mode FIFO mode. FIFO mode internal FIFOs activated allowing bytes (plus bits error data byte RCVR FIFO) s Abstract: .. ACEX1K -1 5091 88 MHz. FLEX10KE FLEX10KE -1 5091 81 MHz. 1 - FIFOs implemented in EAB’s – 304 Bits Core performance in ALTERA � devices. D 1 6 X 5 0 U A R T S F A M I L Y O V E R V I E W. The family of DCD D16X50 D16X50 UART IP Cores combine .. Tags: D16550 verilog code for uart communication TL16C550A 12 f 5091 TL16C550A	96.65 Kb	6 Pages	Original

First line: Simulating Altera Devices with IBIS Models November 2003, ver. Application Note High-performance systems that involve complex clock trees high-data rates tightly constrain design parameters, creating significant challenge board designers. Also, because short design time high cost, beneficial develop Abstract: .. ■ acex_3_sp_BI = ACEX1K device model with the PCI diode and slew control rate option on. Corner Case Support. Altera IBIS models support all three corner cases: Typ, Min, and Max. Each corner is defined .. Tags: analog cookbook datasheet abstract..	146.67 Kb	24 Pages	Original

First line: DP80C51 Pipelined High Performance 8-bit Microcontroller 4.01 DP80C51 ultra high performance, speed optimized soft core single-chip 8bit embedded controller dedicated operation with fast (typically on-chip) slow (offchip) memories. core been designed with special concern performance power consumptio Abstract: .. ACEX1K -1 57 MHz. APEX20K APEX20K -1 50 MHz. APEX20KE APEX20KE -1 66 MHz. APEX20KC APEX20KC -7 78 MHz. APEX-II -7 76 MHz. MERCURY -5 .. Tags: verilog code for uart communication DP80C51 DP80C51	167.63 Kb	10 Pages	Original

First line: DP8051 Pipelined High Performance 8-bit Microcontroller 4.03 DP8051 ultra high performance, speed optimized soft core single-chip 8bit embedded controller dedicated operation with fast (typically on-chip) slow (offchip) memories. core been designed with special concern about performance power consum Abstract: .. ACEX1K -1 57 MHz. APEX20K APEX20K -1 50 MHz. APEX20KE APEX20KE -1 66 MHz. APEX20KC APEX20KC -7 78 MHz. APEX-II -7 76 MHz. MERCURY -5 .. Tags: vhdl code for rs232 receiver verilog code for uart communication DP8051 DP8051	169.51 Kb	10 Pages	Original

First line: DF6811 8-bit FAST Microcontrollers Family 3.01 Document contains brief description DF6811 core functionality. DF6811 advanced 8-bit Core with highly sophisticated, chip peripheral capabilities. DF6811 soft core binary-compatible with industry standard 68HC11 8-bit microcontroller achieve performance Abstract: .. ACEX1K -1 3023 33 MHz. FLEX10KE FLEX10KE -1 3023 33 MHz. Core performance in ALTERA � devices. Area utilized by the each unit of DF6811 DF6811 core in vendor specific technologies is summarized in table below. Component .. Tags: verilog code for uart communication DF6811	123.21 Kb	9 Pages	Original

First line: DP80390CPU Pipelined High Performance 8-bit Microcontroller 4.02 DP80390CPU ultra high performance, speed optimized soft core singlechip 8-bit embedded controller dedicated operation with fast (typically on-chip) slow (off-chip) memories. supports linear code linear data spaces. core been designed w Abstract: .. ACEX1K -1 56 MHz. APEX20K APEX20K -1 50 MHz. APEX20KE APEX20KE -1 63 MHz. APEX20KC APEX20KC -7 76 MHz. APEX-II -7 74 MHz. MERCURY -5 .. Tags: DP80390CPU DP80390CPU	169.49 Kb	10 Pages	Original

First line: DP80390 Pipelined High Performance 8-bit Microcontroller 4.02 DP80390 ultra high performance, speed optimized soft core single-chip 8bit embedded controller dedicated operation with fast (typically on-chip) slow (offchip) memories. supports linear code linear data spaces. core been designed with spe Abstract: .. ACEX1K -1 57 MHz. APEX20K APEX20K -1 50 MHz. APEX20KE APEX20KE -1 66 MHz. APEX20KC APEX20KC -7 78 MHz. APEX-II -7 76 MHz. MERCURY -5 .. Tags: verilog code for uart communication LIN VHDL source code DP80390 DP80390	174.73 Kb	10 Pages	Original

First line: DP8051XP Pipelined High Performance 8-bit Microcontroller 4.05 DP8051XP ultra high performance, speed optimized soft core single-chip 8bit embedded controller dedicated operation with fast (typically on-chip) slow (offchip) memories. core been designed with special concern about performance power co Abstract: .. ACEX1K -1 50 MHz. APEX20K APEX20K -1 45 MHz. APEX20KE APEX20KE -1 55 MHz. APEX20KC APEX20KC -7 66 MHz. APEX-II -7 72 MHz. MERCURY -5 .. Tags: vhdl code for cordic verilog code for cordic DP8051XP DP8051XP	194.43 Kb	12 Pages	Original

First line: DP80390CPU* DP80390XP Pipelined High Performance 8-bit Microcontroller 4.05 DP80390XP ultra high performance, speed optimized soft core singlechip 8-bit embedded controller dedicated operation with fast (typically on-chip) slow (off-chip) memories. supports linear code linear data spaces. core been Abstract: .. ACEX1K -1 50 MHz. APEX20K APEX20K -1 45 MHz. APEX20KE APEX20KE -1 55 MHz. APEX20KC APEX20KC -7 66 MHz. APEX-II -7 72 MHz. MERCURY -5 .. Tags: DP80390CPU* vhdl code for cordic DP80390XP DP80390XP	196.34 Kb	13 Pages	Original