AC354 ASM51 80C31 AX250-PQ208 PQ208

Core8051s Debugging in Axcelerator and RTAX-S Device Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . .

Application Note AC354 AC354 Core8051s Debugging in Axcelerator and RTAX-S Device Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . Core8051s Debug Configuration . . . . . . . . . . . . . Design Example . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . Appendix A Software and Hardware Tools Requirement Appendix B FS2 and Keil uVision3 Interface . . . . . . Appendix C Running Debugger Using FS2 Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 .1 .2 10 10 10 10 Introduction This application note describes Core8051s debug operation in Axcelerator and RTAX-S devices. Core8051s is a high-performance, 8-bit microcontroller IP Core. It is a fully functional 8-bit embedded controller that executes all ASM51 ASM51 instructions and has the same instruction set as the 80C31 80C31. Core8051s can run programs written for the 8051. It contains only the 8051 core logic without any peripherals. Debug operation for Core8051s can be done using UJTAG macro available in Actel Flash devices or user I/Os. The core configurator in Libero IDE allows you to choose the right option and run debug operation. When the debug option is selected, the on-chip instrumentation (OCI) debug functionality is enabled and you can connect a debugger to the processor via a JTAG connection. In RTAXS or Axcelerator families, you can only run debug operation using user I/O option as these devices do not have UJTAG macro. This application note describes how to perform Core8051s debug operation using the user I/Os option in AX250-PQ208 AX250-PQ208 device with a design example. Core8051s Debug Configuration Core8051s is a processor core and is compatible with the instruction set of the 8051 microcontroller. There are three debug-related configuration options. Refer to the Core8051s Handbook for details. When configuring Core8051s, you can chose from these debug modes. From the Debug drop-down menu, you can choose the following options: · Disabled: It excludes debug functionality. · Enabled using UJTAG: It allows including the debug functionality and to use the dedicated JTAG pins of the device (via the UJTAG macro) for the debug connection. · Enabled using I/Os: It allows including debug functionality and to use general purpose I/O pins for the debug connection. This option should be used if the UJTAG macro is either not present on your device or is already in use and not available for the Core8051s debug connection. When Debug option is enabled using UJTAG or user I/Os, two additional debug options are made available for added control over the debug functionality: · Include trace RAM: It allows including a 256-byte deep trace RAM within Core8051s. Including the trace RAM increases the tile count for the processor and consumes RAM blocks on the device. · Number of hardware triggers/breakpoints: It allows setting the maximum number of hardware triggers/breakpoints available when debugging a Core8051s system. The options are 0, 1, 2, or 4. Increasing the number of hardware triggers/breakpoints increases the tile count of the processor. September 2010 © 2010 Actel Corporation 1 Core8051s Debugging in Axcelerator and RTAX-S Device You should choose the debug option based on the family or design being used. Please note that UJTAG macro is only available for Actel flash-based FPGA families. So you have the choice of using either option in Actel flash-based FPGAs because of the availability of UJTAG macro. However, there is no UJTAG macro available on RTAX-S or Axcelerator devices hence use of the dedicated JTAG interface for soft processor debug is not an option. When implementing Core8051s on RTAX-S or Axcelerator device, you are restricted to "Enabled using I/Os" option for running debugger. In addition, when the normal user I/Os are used for the debug connection, a soft JTAG test access port (TAP) is created in the FPGA fabric, consuming few more tiles. The following sections explain how to run debug mode (OCI Block with user I/O) with a design example in Axcelerator or RTAX-S devices. Design Example The design files referred to in this application note are available for downloading. The design example can be downloaded from the Actel website and it includes complete Libero and Keil project. The design example displays a rotating LED pattern using push-button switch. It uses Core8051s, program and data memory, CoreAPB3, CoreInterrupt, CoreGPIO, and PLL. Figure 1 shows a high level block diagram of the design and Figure 2 on page 3 shows Core8051s configuration setting. Please note that "Enable user I/Os" option is selected for debug. Figure 1 · Design Example Block Diagram 2 Design Example Figure 2 · Core8051s Configuration Settings 3 Core8051s Debugging in Axcelerator and RTAX-S Device Figure 3 shows Core8051s block connected to the program and data memory. It shows read enable and write enable signal polarity and how they are connected to Core8051s block. The memories are 2K deep and 8-bit wide. The program memory is accessed using MEMPSACKI (program store memory acknowledge input) and data memory is accessed using MEMACKI (data memory acknowledge input). The MUX logic block in Figure 2 on page 3 is used to control the correct data being passed to Core8051s. Figure 3 · Core8051s Connection to Program and Data Memory Core8051s is also connected to CoreGPIO and CoreInterrupt via APB3 bus. One of the CoreGPIO blocks is used to drive the LEDs. SW3 is connected to INT0 and SW4 is connected to INT1 of CoreInterrupt. When the program is running, pressing SW3 and SW4 causes the illuminated LED to be shifted one position to the left or right. 4 Design Example Design Implementation The design example is implemented using Libero IDE. Table 1 shows the top level I/O ports: Table 1 · Top Level I/O Ports Name Width Description CLKA 1 40 MHz clock (available in AX starter Kit). It is used as CLKA for PLL used to generate 25 MHz clock for Core8051s block. LED 8 LED outputs. RESETN 1 Reset signal. It is connected to push-button reset input on the starter kit and is logical-ANDed with PLL Lock signal. SW3 1 Switch input. When the program is running, pressing SW3 rotates the LED to left. SW4 1 Switch input. When the program is running, pressing SW4 rotates the LED to right. TCK 1 JTAG test clock, connected to user I/O 132. TDI 1 JTAG test data in, connected to user I/O 138. TDO 1 JTAG test data out, connected to user I/O 141. TMS 1 JTAG test mode select, connected to user I/O 133. TRSTN 1 JTAG test reset, connected to user I/O 140. Please use the following guideline during design implementation in Libero: · Simulation: To run simulation with application code, the program memory block should be loaded with hex file generated for the application from keil. This simulation ensures that the design works as expected with preloaded memory. Please note that axcelerator or RTAX-S devices are one time programmable (OTP), so you should run verify the design in simulation before testing it in the hardware. · Global assignment: Please make sure to use global for the critical signals such as clocks and resets to avoid any clock skew issues. In this design example PCLK, TCLK, TRSTn are promoted to routed clock network (RCLK) using CLKINT macro. This is done to allow flexible I/O assignment which is not possible when CLKBUF is used. · Synopsis Design Constraints (SDC): Please apply the appropriate clock constraints. In this design example, a 40 MHz timing constraint is applied to CLKA. SmartTime automatically creates a 25 MHz generated clock constraint on the PLL output. · Pin assignment: During layout make sure that the pins are connected properly. This includes CLKA, RESETN, LEDs and Switch connections. Also make sure the 5 JTAG pins TCK, TMS, TDI, TDO, and TRSTB are brought to header that are easy to access and connect to FlashPro3/FlashPro4 hardware. Running the Hardware Debug The design example has been targeted for Axcelerator starter Kit. The kit has 40 MHz oscillator, 8 LEDs, several I/O headers and a PQ208 PQ208 socket. The design is implemented in AX250-PQ208 AX250-PQ208 device and debug operation can be run using Keil uVision3 IDE or FS2 ISA-Actel51 debugger. Please make sure that you have FS2 ISA-Actel51 Debugger and Keil uVision3 IDE software installed in your PC before running the design example. Please see "Appendix A Software and Hardware Tools Requirement" section for hardware tools requirement and download link. 5 Core8051s Debugging in Axcelerator and RTAX-S Device The following section explains the hardware debug operation using step by step info (please make sure that the Axcelerator starter kit has the right device and design programmed): Step 1: Connect a USB cable between FlashPro3 and PC. Step 2: Connect the other end of FlashPro3 to the JTAG user I/Os in the Axcelerator starter Kit. Please note that the JTAG pins from Core8051s are connected to the user I/Os under header J10 in the Axcelerator starter kit. Please make sure to connect GND and VJTAG pins also on FlashPro3 to the appropriate signals. Figure 4 · Connection Between PC and AX Starter Kit Step 3: Open the FS2 ISA-Actel51 Debugger console by selecting Program>FS2>ISA-Actel51 console to launch console as shown below. Figure 5 · Launching FS2 ISA-Actel51 Console Step 4: In FS2 console, type 'openport lpt1' to select USB communication in the System Analyzer software. Step 5: Set the TCK frequency to 10Mhz using the command 'config TckRate 10000000'. Step 6: In FS2 console, execute the basic commands like "status", "IR 0x02" and "reset" to make sure the FS2 console is able to interact with Core8051s via Flashpro3 as shown in Figure 6. 6 Design Example Figure 6 · Basic Commands in ISA-Actel51 Console · Status: Read the status info. Please note that the OCI version is 0x60 and Triggers is 4. These numbers match Core8051s configuration settings in Figure 2 on page 3. · IR 0x02: Read the IR register 0x02. Please note that 0x0D is the expected value according to Core8051s handbook. · Reset: Reset the Core8051S controller. Step 7: Close FS2 console. Step 8: Start µVision3 by clicking on its desktop icon. Step 9: Select Project/Open Project from the main menu and open the file led_rotate.Uv2. Step 10: Compile and build the project by clicking on the Rebuild icon. 7 Core8051s Debugging in Axcelerator and RTAX-S Device Figure 7 · Building Design in Kiel Step 11: Right click on Target 1 and choose "Options for Target `Target 1'". The "Option for `Target 1'" dialog box is displayed. Step 12: Click on the Debug tab and make sure the debug setting is as shown in Figure 8 below. Figure 8 · Debug Setting in Kiel 8 Design Example Step 13: Click on Start/Stop debug icon, the debug window is displayed. Figure 9 · Debug Session in Kiel Step 14: Click on 'Run' to run the application. Figure 10 · Run Application in Kiel Step 15: Press SW3 or SW4 on AX starter kit and you can observe the LED rotating. Note: Instead of using Keil, you can also load the hex file from FS2 console and run the program. Refer to "Appendix C Running Debugger Using FS2 Debugger" section for loading and running debugger from FS2 console. 9 Core8051s Debugging in Axcelerator and RTAX-S Device Conclusion Core8051s is a popular 8-bit microcontroller IP Core. It can be implemented both in Antifuse and Flash based FPGA. During design process, you can run your code in debug mode before creating the final code. In Antifuse FPGA like Axcelerator or RTAX-S, you can run the debug using the user I/Os only. This appsnote provide detail info on running debug operation on Core8051s using this mode in AX250-PQ208 AX250-PQ208 device. This same procedure can be followed on other Axcelerator or RTAX-S devices. Appendix A Software and Hardware Tools Requirement The following software and hardware are required to run the design example: Software required: · Libero IDE v9.0 IDE · Keil uVision3 IDE (available from Keil) · FS2 ISA-Actel51 Debugger Hardware required: · AX Starter kit with AX250-PQ208 AX250-PQ208 device · Actel FlashPro3 Programmer Note: FlashPro4 programmer will not work for this demo design. Appendix B FS2 and Keil uVision3 Interface The Actel Core8051 System Analyzer interfaces with Keil uVision3 software by adding a hardware driver and a simulator driver to the list of available tools in Keil's tools.ini file. After initiating the uVision3 software, these drivers can be selected and used to debug code with the FS2 debugger. All Keil source level debug features work with the Actel Core8051 System Analyzer go, step, halt, view/edit registers, and view/edit memory. To start a debug session in Keil: · Select the Debug menu. · Select the Start/Stop Debug Session menu item. Once a session is started, new menu items appear in the Peripherals menu: · Target Settings - Use this dialog to change communications ports. · Trace - Used to view the trace for the last emulation session. · Triggers - Used to set complex triggers and view current settings. · Console Interface - Gives full access to the FS2 debugger with macros. Use the Help menu for details. Memory and register changes in the Console are reflected in the Keil windows, and viceversa. Appendix C Running Debugger Using FS2 Debugger You can load the hex file and run the debugger using the FS2 debugger. · Type "go" to start emulation at the current execution address. · Type "halt" to stop emulation immediately. This displays the next execution address and one instruction disassembly. · 10 Locate the hex file and type "Load hex " to load the hex file. · Type "step" to execute 1 instruction and to display next execution address and one instruction disassembly. Appendix C Running Debugger Using FS2 Debugger Figure 11 · Run Application in Kiel 11 Actel is the leader in low power FPGAs and mixed signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation Actel Europe Ltd. Actel Japan Actel Hong Kong 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 EXOS Ebisu Buillding 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn © 2010 Actel Corporation. All rights reserved. Actel, Actel Fusion, IGLOO, Libero, Pigeon Point, ProASIC, SmartFusion and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. 51900222-0/9.10