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ISL2671286IBZ-T Intersil Corporation 12-Bit, 20kSPS SAR ADC; SOIC8; Temp Range: -40° to 85°C visit Intersil Buy
ISL2671286IBZ Intersil Corporation 12-Bit, 20kSPS SAR ADC; SOIC8; Temp Range: -40° to 85°C visit Intersil Buy
ISL267452IHZ-T7A Intersil Corporation 12-Bit, 555kSPS SAR ADC; SOT8; Temp Range: -40° to 85°C visit Intersil Buy
ISL267452IHZ-T Intersil Corporation 12-Bit, 555kSPS SAR ADC; SOT8; Temp Range: -40° to 85°C visit Intersil Buy
ISL267450AIUZ-T7A Intersil Corporation 12-Bit 1MSPS SAR ADCs; MSOP8, SOT8; Temp Range: -40° to 85°C visit Intersil Buy
ISL267817IBZ Intersil Corporation 12-Bit Differential Input 200kSPS SAR ADC; MSOP8, SOIC8; Temp Range: -40° to 85°C visit Intersil Buy

AAL5 SAR

Catalog Datasheet MFG & Type PDF Document Tags

3G ATM

Abstract: CPU Interface Add LANE AAL5 SAR Port A as MII Port A as POS-PHY Port A as UTOPIA T RTP in HDLC D M HDLC Process UDP/RTP Disassembly Packet Routing AAL5 SAR Remove LANE TxA FIFO Packet Assembly HDLC Process TX Path TxB FIFO AAL5 SAR Port B Port A as MII Port A as POS-PHY Port A as UTOPIA xxPCM B U S RTP Assembly RTP in HDLC AAL5 SAR Port B Figure 1 - MT922x0 Block Diagram 1 , discarded, sent to CPU as AAL0 cell, looped back to Port A or Port B, or reassembled by an AAL5 SAR engine
Zarlink Semiconductor
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pacemaker

Abstract: VSC2400-30 Management and SAR Engine AAL5 SAR 4OC-48 AAL5 SAR supporting 256K sessions 4Enhanced interworking , Overall 4OC-48 throughput 4Enhanced AAL5 SAR improves multiservice interworking 4Manages 256K input , , congestion control, a wire By provisioning for both rate and delay guarantees for packet speed AAL5 SAR , requirements. capabilities for multiservice applications: · AAL5 SAR · Unified Packet and Cell buffer and , VSC2400-30UY OC-48 Traffic Management and SAR Engine UTOPIA/POS PHY Interface OC-48 AAL5 SAR
Vitesse Semiconductor
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VSC2400-30 pacemaker PB-VSC2400-30-001

AAL5 SAR

Abstract: pacemaker cross reference OC-48 Throughput Wire-speed AAL5 SAR Weighted Random Early Detection (WRED) with per-flow , Required AAL5 SAR: A P P L I C AT I O N S : OC-48 AAL5 SAR supporting 256K sessions Part of , classification, policing, as well as wire speed AAL5 SAR functions. OSCAR delivers flexible per-flow policing , complete packet and cell interworking capabilities for multiservice applications: AAL5 SAR: Unified , OSCAR (VSC2401-25) OC-48 SAR Engine F E AT U R E S : Overall: OC-48 throughput Manages up to 256K
Vitesse Semiconductor
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AAL5 SAR pacemaker cross reference OC-12

digital pacemaker

Abstract: pacemaker Management and SAR Engine AAL5 SAR !OC-48 AAL5 SAR supporting 256K sessions !Enhanced interworking , Overall !OC-48 throughput !Enhanced AAL5 SAR improves multiservice interworking !Manages 256K input , , congestion control, a wire By provisioning for both rate and delay guarantees for packet speed AAL5 SAR , requirements. capabilities for multiservice applications: · AAL5 SAR Specifications: · Unified Packet , VSC2400-30UY OC-48 Traffic Management and SAR Engine UTOPIA/POS PHY Interface OC-48 AAL5 SAR
Vitesse Semiconductor
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digital pacemaker

TAAD08JU21BCLS2-DB

Abstract: TR008 Product Brief, Rev. 1 April 2002 TAAD08JU21BCLS2-DB SAR-2K AAL2/AAL5 SAR Engine Features s , .363.2. Provides AAL5 SAR functionality per ITU I.363.5. Provides quality of service (QoS) connection identifier , and AAL5 conversion Description SAR-2K provides a flexible network-interface solution for , whereby AAL5 VCs are routed through to the system interface toward their destinations. SAR-2K provides support for up to 2032 bidirectional AAL5 VCs via an internal context memory. Communication with SAR
Agere Systems
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TR008 2032 oam AF-VTOA-0113 voice control vc 200 RF limited 30L-15P-BA PB02-055ATM-1 PB02-055ATM

pacemaker

Abstract: digital pacemaker Early packet discard/Partial packet discard AAL5 SAR · OC-48 AAL5 SAR supporting 256K sessions , cell classification, policing, wire speed AAL5 SAR, a dual leaky bucket shaper, and an optimum , provides complete packet and cell interworking capabilities for multiservice applications: · AAL5 SAR · , congestion management solution · Wire-speed AAL5 SAR enables Multi-Service applications · Unmatched QoS , PaceMaker 2.5TM (VSC2400-25) OC-48 Traffic Management and SAR Engine Traffic Management Family
Vitesse Semiconductor
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VSC2400-25UY

TAAD08JU2

Abstract: voice control vc 200 RF limited Product Brief May 2003 TAAD08JU21BCLSL3A-DB (SAR-1K) AAL2/AAL5 SAR Engine, Versions 2.1 and , .363.2. s Provides AAL5 SAR functionality per ITU I.363.5. s Provides quality of service (QoS , Agere Systems Inc. 0.16 µm CMOS technology, the chip implements AAL2 and AAL5 SAR functions. Support , 2032 bidirectional AAL5 VCs via an internal context memory. Communication with SAR-1K is accomplished , cross connect s AAL2 and AAL5 conversion SAR-1K provides a complete ATM adaptation layer
Agere Systems
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TAAD08JU2 APC 2020 B PB03-109ATM-1 PB03-109ATM

SAR-500

Abstract: AF-VTOA-0113 Product Brief May 2003 TAAD08JU21BCLSU3A-DB (SAR-500) AAL2/AAL5 SAR Engine, Versions 2.1 and , .363.2. s Provides AAL5 SAR functionality per ITU I.363.5. s Provides quality of service (QoS , AAL2 cross connect s AAL2 and AAL5 conversion Description SAR-500 provides a flexible , implements AAL2 and AAL5 SAR functions. Support for AAL2 is provided via an AAL/CPS function that maps , destinations. SAR-500 provides support for up to 2032 bidirectional AAL5 VCs via an internal context memory
Agere Systems
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SAR-500 PB03-110ATM-1 PB03-110ATM
Abstract: Product Brief May 2003 TAAD08JU21BCLS2-DB (SAR-2K) AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1 , per ITU I.363.2. Provides AAL5 SAR functionality per ITU I.363.5. Provides quality of service (QoS , Inc. 0.16 µm CMOS technology, the chip implements AAL2 and AAL5 SAR functions. Support for AAL2 is , bidirectional AAL5 VCs via an internal context memory. Communication with SAR-2K is accomplished through , to area, power, and function. TAAD08JU21BCLS2-DB (SAR-2K) AAL2/AAL5 SAR Engine, Versions 2.1 and Agere Systems
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PB02-055ATM-2
Abstract: Preliminary Data Sheet April 2002 TAAD08JU21BCLS2-DB SAR-2K AAL2/AAL5 SAR Engine 1 Features s , Agere Systems Inc. 0.16 µm CMOS technology, the chip implements AAL2 and AAL5 SAR functions. Support for , bidirectional AAL5 VCs via an internal context memory. Communication with SAR-2K is accomplished through three , AAL5 SAR functionality per ITU I.363.5. Provides quality of service (QoS) connection identifier (CID , , power, and function. TAAD08JU21BCLS2-DB SAR-2K AAL2/AAL5 SAR Engine Table of Contents Contents Agere Systems
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DS02-128ATM
Abstract: Preliminary Data Sheet May 9, 2003 TAAD08JU21BCLS2-DB SAR-2K AAL2/AAL5 SAR Engine, Versions , data or voice traffic per ITU I.363.2. s Provides AAL5 SAR functionality per ITU I.363.5. s , Systemsâ'™ 0.16 µm CMOS technology, the chip implements AAL2 and AAL5 SAR functions. s â'"40 oC , area, power, and function. TAAD08JU21BCLS2-DB SAR-2K AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1 , /AAL5 SAR Engine, Versions 2.1 and 3.1 Table of Contents (continued) Contents Page 11.4.12 Agere Systems
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DS03-128ATM-3 DS03-128ATM-2
Abstract: Preliminary Data Sheet May 9, 2003 TAAD08JU21BCLSU3A-DB AAL2/AAL5 SAR Engine, Versions 2.1 and , AAL2 and AAL5 SAR functions. Support for AAL2 is provided via an AAL/CPS function that maps/demaps , support of low-speed data or voice traffic per ITU I.363.2. Provides AAL5 SAR functionality per ITU I , area, power, and function. TAAD08JU21BCLSU3A-DB AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1 Table of , /AAL5 SAR Engine, Versions 2.1 and 3.1 Table of Contents (continued) Contents 11.4.12 11.4.13 Agere Systems
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D08JU21BCLSU3A-DB DS03-110ATM

A9KX

Abstract: TAAD08JU21BCLSL3A-DB Preliminary Data Sheet May 9, 2003 TAAD08JU21BCLSL3A-DB AAL2/AAL5 SAR Engine, Versions 2.1 and , AAL2 and AAL5 SAR functions. Support for AAL2 is provided via an AAL/CPS function that maps/demaps , support of low-speed data or voice traffic per ITU I.363.2. Provides AAL5 SAR functionality per ITU I , area, power, and function. TAAD08JU21BCLSL3A-DB AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1 Table of , /AAL5 SAR Engine, Versions 2.1 and 3.1 Table of Contents (continued) Contents 11.4.12 11.4.13
Agere Systems
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A9KX D08JU21BCLSL3A-DB DS03-109ATM

pacemaker

Abstract: AAL5 SAR providing packet and cell classification, policing, wire speed AAL5 SAR, ATM/ Frame Relay network , unrestricted number of multicast leaves, VC merging, and label swapping. · · · · · AAL5 SAR OC-48 AAL5 SAR supporting 256K sessions · FRF-5 Interworking FRF-5 compliant ATM/Frame Relay network , · Features: Frame Relay/ATM interworking AAL5 SAR Unified Packet and Cell buffer and
Vitesse Semiconductor
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traffic heart rate monitor

APP550

Abstract: APP550TM . The APP550TM and APP530TM are standalone processors that provide AAL5 SAR and Traffic Management , through the embedded AAL5 segmentation and reassembly (SAR) functionality in the APP550TM and APP530TM , you build multiservice applications. These include: I Wire-Rate Bidirectional AAL5 SAR (APP550) AAL5 SAR capabilities are embedded in the APP550TM and APP530TM. This enables the flexible hardware , Product Brief Product Brief May 2003 May 2003 ATM SAR and Traffic Manager Processor
Agere Systems
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APP550TM and APP530TM traffic manager APP550TM and APP530TM 266MH PB03-138NP

M27483

Abstract: AAL5 segmentation PortMaker®III AAL5 Firmware TSP3 Traffic Stream Processors AAL5 SAR with ATM-to-MPLS , applications for the TSP3 family of devices. The PortMakerIII AAL5 SAR with ATM-to-MPLS interworking , with CBWFQ > ITU I.363.5 compliant AAL5 SAR > ATM-to-MPLS interworking support based on , CBWFQ access · Ingress policing · ITU I.363.5 AAL5 SAR · Congestion control · Auto-VC , applications. > Independent shaping and policing profiles for up to 256K connections AAL5 Segmentation
Mindspeed Technologies
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M27483 AAL5 segmentation MXAPM3A5-BRF-001-A M03-0778
Abstract: for implementing Multi service Traffic Management, Switching and ATM SAR for the access market. The Porto-100's novel, high performance, scalable chip architecture with its built in ATM AAL5 SAR can , AAL5 SAR and MPLS Switch § Flexible Congestion and Buffer Management Schemes § TM 4.1 Compliant , transparently between them. The built in line rate AAL5 SAR and OAM processor combined with ATM and MPLS , an integrated, wire-speed SAR engine. FEATURES Introduction 1M Simultaneously Queued and Cortina Systems
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CS5331 F5331001204

CS533

Abstract: CS5333 -200's novel, high performance, scalable chip architecture with its built in ATM AAL5 SAR can aggregate, switch , integrated, wire-speed SAR engine. FEATURES Introduction 1M Simultaneously Queued and Scheduled Virtual Connections (VCs) § ATM VC/VP Switching, Queuing and Traffic Management § Integrated ATM AAL5 SAR and MPLS , rate AAL5 SAR and OAM processor combined with ATM and MPLS protocol awareness, makes Porto-200 an ideal , CS5333 Porto-200 ­ OC-48 Multi Service Traffic Manager and SAR OVERVIEW The Porto-200 CS5333, a
Cortina Systems
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CS533 F5333001204

wy28

Abstract: application note utopia , which is shown with less detail below. Transmit AAL5 SAR Secondary UTOPIA Primary Transmit , the bus (such as a second MT90500 or an AAL5 SAR). In this setup it is likely that the PRXEN of the , device via its Primary port. Another device is present on the Primary receive bus, such as an AAL5 SAR , to the output enb of the AAL5 SAR. The MT90500 Primary port is operating in 8-bit ATM mode and the Secondary port is operating in 8-bit PHY mode. Primary Receive AAL5 SAR Secondary UTOPIA Primary
Zarlink Semiconductor
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MT90503 wy28 application note utopia AB29 AE13 AF29 AG29 MSAN-205

AF-VTOA-0113

Abstract: BTS G29 Preliminary Data Sheet July 2002 TAAD08JU21BCLS2-DB SAR-2K AAL2/AAL5 SAR Engine 1 Features s , ) function for support of low-speed data or voice traffic per ITU I.363.2. s Provides AAL5 SAR , implements AAL2 and AAL5 SAR functions. Support for AAL2 is provided via an AAL/CPS function that maps , destinations. SAR-2K provides support for up to 2032 bidirectional AAL5 VCs via an internal context memory , function. TAAD08JU21BCLS2-DB SAR-2K AAL2/AAL5 SAR Engine Preliminary Data Sheet July 2002 Table
Agere Systems
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BTS G29 AG10 AH11 AJ11 transistor w2d 31N40 DS02-128ATM-1
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