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A11/MII

Catalog Datasheet MFG & Type PDF Document Tags

LAN911x

Abstract: SMSC LAN911x LAN9118 and LAN9116 devices support an external MII interface in the LAN9117 and LAN9115 devices. The external MII feature allows the LAN9117 and LAN9115 devices to support an external PHY. It is important to , COMMENT LAN9118 32-/16-bit Selectable LAN9117 16-Bit Only External MII Selectable LAN9116 32-/16-bit Selectable LAN9115 16-bit Only External MII Selectable 3 Configuration options , /10W 1% R24 R26 R31 MII Supported DNP DNP Stuff DNP MII Not Supported
Standard MicroSystems
Original
LAN911x SMSC LAN911x TQFP100 footprint RX-3 -G SS-6488-NF TQFP100

AN1259

Abstract: MCF5235 dedicated DMA controller - Memory-based flexible descriptor rings - Media independent interface (MII) to , the 10/100 Mbps 802.3 media independent interface (MII). It requires an external transceiver (PHY) to , - B9, A10, C10, A11 CS[3:2] PCS[3:2] SD_CS[1:0] - O 132,131 A9, C9 CS1 , A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 17 16 15 , A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 Table 7. MCF5271MCF5271 to SDRAM
Freescale Semiconductor
Original
MCF5271EC MCF5271 MCF5270 AN1259 MCF5235 MCF5235RM 100MH

AN1259

Abstract: MCF5235 dedicated DMA controller - Memory-based flexible descriptor rings - Media independent interface (MII) to , the 10/100 Mbps 802.3 media independent interface (MII). It requires an external transceiver (PHY) to , - B9, A10, C10, A11 CS[3:2] PCS[3:2] SD_CS[1:0] - O 132,131 A9, C9 CS1 , A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 17 16 15 , A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 Table 7. MCF5271MCF5271 to SDRAM
Freescale Semiconductor
Original

AN1259

Abstract: MCF5270 - Media independent interface (MII) to external transceiver (PHY) Three Universal Asynchronous , supports connection and functionality for the 10/100 Mbps 802.3 media independent interface (MII). It , ] PCS[7:4] - - O - B9, A10, C10, A11 CS[3:2] PCS[3:2] SD_CS[1:0] - O , external PHY and the media-access controller. Data is synchronous to EMDC. Applies to MII mode operation , . Applies to MII mode operation. O Transmit Clock ETXCLK Input clock which provides a timing
Motorola
Original
Programmable interval timer chip
Abstract: controller - Memory-based flexible descriptor rings - Media independent interface (MII) to external , and functionality for the 10/100 Mbps 802.3 media independent interface (MII). It requires an external , external PHY and the media-access controller. Data is synchronous to EMDC. Applies to MII mode operation , provides a timing reference to the PHY for data transfers on the EMDIO signal. Applies to MII mode , nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated Motorola
Original
MCF5271EC/D

Boundary Scan JTAG Logic

Abstract: DMA controller - Memory-based flexible descriptor rings - Media independent interface (MII) to , independent interface (MII). It requires an external transceiver (PHY) to complete the interface to the media , media-access controller. Data is synchronous to EMDC. Applies to MII mode operation. This signal is an input , PHY for data transfers on the EMDIO signal. Applies to MII mode operation. This pin can also be , (ETXEN) The transmit enable (ETXEN) output indicates when valid nibbles are present on the MII. This
Motorola
Original
Boundary Scan JTAG Logic

MCF5275

Abstract: 5274L independent interface (MII) USB Device Module - Supports full-speed 12-Mbps and low-speed 1.5-Mbps USB , Support for different Ethernet physical interfaces: - 100Mbps IEEE 802.3 MII - 10Mbps IEEE 802.3 MII , . Applies to MII mode operation. This signal is an input after reset. When the FEC is operated in 10Mbps 7 , on the FECn_MDIO signal. Applies to MII mode operation. O Transmit Clock FECn_TXCLK , the MII. This signal is asserted with the first nibble of a preamble and is negated before the first
Motorola
Original
MCF5275 MCF5274 MCF5274L MCF5272 5274L split core ebi mips tea 1010 MCF5275EC/D MCF5275L 166MH
Abstract: independent interface (MII) · USB Device Module - Supports full-speed 12-Mbps and low-speed 1.5-Mbps USB , different Ethernet physical interfaces: - 100Mbps IEEE 802.3 MII - 10Mbps IEEE 802.3 MII · · · · · · · , valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is , only valid during the assertion of FECn_TXEN. This signal is also used for MII mode data in conjunction , data valid (FECn_RXDV) input indicates that the PHY has valid nibbles present on the MII. FECn_RXDV Motorola
Original
150MH

Coldfire MCF5235

Abstract: MB14 controller - Memory-based flexible descriptor rings - Media independent interface (MII) to external , A10 A10 Chip Selects CS[7:4] PCS[7:4] - - O - B9, A10, C10, A11 C12, A13 , A12 A12 A12 CAN0RX - I 136 D8 A11 A11 A11 PUARTL3 - - I , A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 17 16 , A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 Table 7. MCF523x to SDRAM
Freescale Semiconductor
Original
MCF5235EC MC68332 Coldfire MCF5235 MB14 MB15 MCF5232 MCF5233 MCF523

Coldfire MCF5235

Abstract: MB14 Memory-based flexible descriptor rings - Media independent interface (MII) to external transceiver (PHY , A10 A10 Chip Selects CS[7:4] PCS[7:4] - - O - B9, A10, C10, A11 C12, A13 , A12 A12 A12 CAN0RX - I 136 D8 A11 A11 A11 PUARTL3 - - I , A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row 17 16 , A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 Table 7. MCF523x to SDRAM
Freescale Semiconductor
Original
MCF5234 M523X

MTD213

Abstract: AX88140AP . 14 2.4 MII/SYM/SRL INTERFACE SIGNALS GROUP , ) . 26 4.2.10 Serial ROM and MII Management Register (REG9 , . 36 6.4.4 MII/SYM Timing , . 45 B.4.2 Application for MII Mode : LEVEL ONE LXT970. 45 B.4.3 Application for MII Mode : MYSON MTD972 + MTD971
ASIX Electronics
Original
AX88140A AX88140AQ AX88140AP MTD213 MDT972 MAX11855 100BASE-TX/FX AX140D2 160-PIN

cs415

Abstract: PMSM DMA controller - Memory-based flexible descriptor rings - Media independent interface (MII) to , supports connection and functionality for the 10/100 Mbps 802.3 media independent interface (MII). It , [3:2] PCS1 - - SD_CS[1:0] - - - - - - O O O O - 134,133 130 129 B9, A10, C10, A11 A9, C9 B10 , A11 A12 D10 D11 A11 A12 D10 D11 A11 A12 - 147 148 149 150 B7 A6 C5 B5 A5 B10 D9 B8 C8 D8 B10 D9 B8 C8 , controller. Data is synchronous to EMDC. Applies to MII mode operation. This signal is an input after reset
Motorola
Original
cs415 PMSM
Abstract: rings â'" Media independent interface (MII) to external transceiver (PHY) â'¢ FlexCAN Modules (up , the 10/100 Mbps 802.3 media independent interface (MII). It requires an external transceiver (PHY) to Motorola
Original
MCF5235EC/D
Abstract: descriptor rings - Media independent interface (MII) to external transceiver (PHY) · FlexCAN Modules (up to , supports connection and functionality for the 10/100 Mbps 802.3 media independent interface (MII). It , media-access controller. Data is synchronous to EMDC. Applies to MII mode operation. This signal is an input , data transfers on the EMDIO signal. Applies to MII mode operation. This pin can also be configured as , present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the Motorola
Original

BLM21B102SPT

Abstract: rd22 zener diode ) Data Bus (0-7) Address Bus (A1-A15) Control SMSC 83C180 Media Interface (MII) MII SMSC 91C100 , Data Buffer DMA/Buffer Control 80C300/80C200 10/100 Ethernet Controller MII Media Interface (MII) Bus Transceiver Transformer Host CPU System Memory Competitions 10/100 , No Yes Yes MII MII MII, 10MB ENDEC MII No No Yes Yes No No Yes , . 1.9. PHY Layer Support Both devices support the standard IEEE Phy MII style interface. 1.10
Standard MicroSystems
Original
LAN91C100 LAN91C110 BLM21B102SPT 8SOP150 rd22 zener diode optocoupler HA11 RA13 honda c92 6R19 CZT2000 1/16W TS117

BLM21B102SPT

Abstract: rd22 zener diode ) Data Bus (0-7) Address Bus (A1-A15) Control SMSC 83C180 Media Interface (MII) MII SMSC 91C100 , Data Buffer DMA/Buffer Control 80C300/80C200 10/100 Ethernet Controller MII Media Interface (MII) Bus Transceiver Transformer Host CPU System Memory Competitions 10/100 , No Yes Yes MII MII MII, 10MB ENDEC MII No No Yes Yes No No Yes , . 1.9. PHY Layer Support Both devices support the standard IEEE Phy MII style interface. 1.10
-
Original
lu27xx 56kbps modem rd23 8-SOP-150 RMC-EA16LMY-OM00-A PCMCIA Fast Ethernet P3100SA DO-214AA

30076

Abstract: ITL 9 (including punctuation in each digit) 1 digit of floating minus sign, Memory I (M) and Memory II (MII) load , number displayed in the entry register. Memory I & II Plus Key (M+ & MII+) · Adds the current , MII-) · Subtracts the current display from the memory contents. · It will terminate a , e4 "T" c5 g5 e5 c6 g6 e6 MII c7 g7 e7 COM3 10 · A4 , 14/16-Digit Calculator SEG A8 B8 C8 A9 B9 C9 A10 B10 C10 A11 B11
ELAN Microelectronics
Original
EMPCD200 30076 ITL 9 ats 1 1800 p10 M100 M300 14/1614/16-D 14/16-D

EMPCD100

Abstract: Euro 64 -digit of floating minus sign, memory I (M) & memory II (MII) load symbol, error symbol, 3-digits of commas , register. Memory I & II Plus Key (M+ & MII+) · Adds the current display to the contents of memory. · It will terminate a number entry. Memory I & II Minus Key (M- & MII-) · Subtracts the current , TAX C3 X a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 Cn TAX , d9 d8 d7 d6 d5 d4 d3 d2 d1 Cn RATE X X MII p11 p10 p9
ELAN Microelectronics
Original
EMPCD100 Euro 64 solar calculator

88E1011S

Abstract: ADS8540 Controller) supporting 10/100/1000 Mbps, MII, GMII, RGMII, and TBI interfaces DDR SDRAM memory controller , I-Memory SPI I/Os e500 Coherency Module 10/100/1000 MAC MII/GMII/TBI/ RTBI/RGMII 10 , ENET MIIs PCI-X 64b 133MHz DUART DMA Controller 10/100/1000 MAC MII/GMII/TBI/ RTBI , TRI TSEC1 TRI TSEC2, Eth, MII · · · Local control/default Delay ADS_RESET , MII for 10/100-BaseT or GMII and TBI for 1000Base-T. The 88E1011S transceiver device from Marvell is
Motorola
Original
ADS8540 Marvell Ethernet PHY 88E1011S ATX POWER SUPPLY 400W circuit diagram MPC840 825v hg LT1764 MPC8560/ADS8540/D MPC8560/MPC8540 MPC8560 MPC8540 MPC8540/MPC840

STR912FA

Abstract: XC3S500E interface (MII), external memory interface (EMI), SPITM, GPIOs or by other methods. RT Ethernet , FPGA_Interrupt0 C4 100 nF EMI _P71 EMI _P77 MII _CRS MII _TXD3 MII _TXD1 MII_MDINT_2 MII_COL_2 MII _TXD2_2 MII _TXD0_2 MII_TX_CLK_ 2 MII _RX_ER_2 MII _RX_DV_2 MII _RXD1_2 MII _RXD3_2 MII_MDIO 0 , EMI _P94 SPI_P27_NSS EMI _P96 MII_TX_CLK MII _RXD0 EMI_RD MII _RXD2 MII_RX_CLK MII_MDINT_1 MII _RX_ER_1 MII_TX_CLK_1 MII _TXD0_1 MII _TXD2_1 MII_COL_1 MII_RX_CLK_1 MII _RXD0_1 MII
STMicroelectronics
Original
STEVAL-IFW001V1 XCF04S ST3485EB IEEE1588 STR912FA XC3S500E XC3S500E-4PQ208C XCF04SVO20C XC3S500E 208 STEVAL-IFW002V1 RS485
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