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A0-A15

Catalog Datasheet MFG & Type PDF Document Tags

DSP56F803

Abstract: 64Kx16-bit spaces. IP Phone DSP56F803 Modems GS71116 A0-A15 Security A0-A15 D0-D15 Magnetic , DSP56F803 A0-A15 A0-A15 D0-D15 DQ1-DQ16 RD OE WR WE UB PS CE LB DS DSP56F80X CUSTOMER SUPPORT: GS71116 Technical Support: A0-A15 DQ1-DQ16 OE WE UB CE , authorized distributor Disclaimer: DSP56F803 A0-A15 PS D0-D15 GS71116 A0-A15 A16 DQ1-DQ16 RD
Motorola
Original
64Kx16-bit BR1537/D

CMS210 memory

Abstract: card 60-pin A0-A15 O E / Vpp E DO-D7 A0-A15 O E /V p p E D8-D15 M2t 64K x 8 M1 64K x 8 VC C VCC VSS 59 , Address Decoder 16 A0-A15 16 A16 10 CE 41 HCT139 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 1G 2Y2 2Y3 2G GND VC C 1A 2A 1B 2B O E /V p p DO- D7 E Ml 64K x 8 A0-A15 O E /V p p D8-D15 E M2t 64K x 8 Vcc VS S vcc v Ss 16 A0-A15 16 A0-A15 D0-D7 M3 64K x 8 O E /V p p E O E /V p p , 45 16 A0-A15 A0-A15 58 16 Addreaa Decoder A16 A17 10 12 CE 41 HCT139 1Y0 1A
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OCR Scan
CMS210 memory card 60-pin CMS209 CMS210 CMS212 CMS213 CMS214 CMS216

os1p

Abstract: FUNCTION BG IN MC68000 X:$FF7F). PEREN timing is the same as the A0-A15 address lines; it is asserted and deasserted , qualifies the A0-A15 and PS/DS pins. WR can be connected directly to the WE pin of a static RAM. WR is , DSP. When RD is asserted, it qualifies the A0-A15 and PS/DS pins. RD can be connected directly to , Total 112 ADDRESS AND DATA BUS (32 PINS A0-A15 (Address Bus) - three state, active high outputs. A0A15 change in t0 and specify the address for external program and data memory accesses. If there is
Motorola
Original
DSP56100 DSP56166 os1p FUNCTION BG IN MC68000 PB10 PB12 DSP5616 HREQ/PB13 HACK/PB14 HEN/PB12

PB12

Abstract: PC10 DATA BUS (32 PINS) A0-A15 (Address Bus) - three state, active high outputs. A0-A15 change in t0 , activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset. D0-D15 , referenced. PS/DS timing is the same as the A0-A15 address lines. PS/DS is high for program memory access , PB12 PB13 PB14 EXTAL CLKO SXFC VddS GNDS A0-A15 D0-D15 Vdd Add/Data Vss Add/Data BS , same as the A0A15 address lines; it is asserted and deasserted during t0. PEREN is high for any
Motorola
Original
PC10 16-BIT
Abstract: A0-A15 "A" data input bus. The 16-bit "A" input data bus to the ALU. B0-B15 "B" data input bus , ,OSA,OSB to C16 A0-A15, B0-B15 to P,G ¯ ¯ A0-A15, B0-B15 to OVF, ZERO A0-A15, B0-B15 to C16 , QPL4C381-35 S0-S2,OSA,OSB to P,G ¯ ¯ S0-S2,OSA,OSB to OVF, ZERO S0-S2,OSA,OSB to C16 A0-A15, B0-B15 to F0-F15 A0-A15, B0-B15 to P,G ¯ ¯ A0-A15, B0-B15 to OVF, ZERO 27 FTAB=1, FTF , ns ns ns ns ns ns ns ns ns ns ns ns Unless Otherwise Specified A0-A15, B0-B15 to e2v semiconductors
Original
QPL4C381 L4C381 54S381 QPL4C381KMB45-MIL 5962-8995901YA QPL4C381GMB45-MIL

MC68000 PIO

Abstract: DSP56156 ) A0-A15 (Address Bus) - three state, active high outputs. A0-A15 change in t0 and specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset or when the DSP is not bus master , is referenced. PS/DS timing is the same for the A0-A15 address lines. PS/DS is high for program , . A0-A15 PS/DS R/W WR RD Data In D0-D15 Data Out Bus Operation (Read-Write- 0WT) T0
Freescale Semiconductor
Original
DSP56156 MC68000 PIO SC10

CMGA3-P68

Abstract: L4C381 A0-A15 "A" data input bus. The 16-bit "A" input data bus to the ALU. B0-B15 "B" data input bus , ,OSB to P,G ¯ ¯ S0-S2,OSA,OSB to OVF, ZERO S0-S2,OSA,OSB to C16 A0-A15, B0-B15 to P,G ¯ ¯ A0-A15, B0-B15 to OVF, ZERO A0-A15, B0-B15 to C16 Clock to F0-F15 16 FTAB=0, FTF=1, CL , ,OSA,OSB to OVF, ZERO S0-S2,OSA,OSB to C16 A0-A15, B0-B15 to F0-F15 A0-A15, B0-B15 to P,G ¯ ¯ A0-A15, B0-B15 to OVF, ZERO 27 FTAB=1, FTF=0, QPL4C381-45 QPL4C381-35 FTAB=1, FTF
QP Semiconductor
Original
CMGA3-P68 5962-8995901ZC QPL4C381KMB30-MIL 5962-8995902YA QPL4C381GMB30-MIL 5962-8995902ZA
Abstract: of Pins 32 9 4 3 15 2 10 7 4 9 15 1 1 112 ADDRESS AND DATA BUS (32 PINS) A0-A15 (Address Bus) - three state, active high outputs. A0-A15 change in t0 and specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset or when the DSP is not bus master. D0-D15 , /DS timing is the same for the A0-A15 address lines. PS/DS is high for program memory access and is -
Original

G30-88

Abstract: G38-87 the pins A0-A15, D0-D15, PS, DS, RD, and WR derates linearly at 1.7 ns per 20 pF of additional , , the PS, DS, RD, and WR strobes remain deasserted and A0-A15 do not change from their previous state , Min Max 4 16.6 ns 20 21 CLKO High to A0-A15 Valid 5.2 12.4 ns 22 , D0-D15 Out Tri-state - 15 ns 35 CLKO High to A0-A15 Invalid 2.5 3.5 ns 36 , ) 21 35 A0-A15 (See Note) 36 22 PS, DS 23 WR (Output) 29 24 31 RD (Output) 30
Motorola
Original
G30-88 G38-87 DSP56L811 AA0206 AA0207 AA0208 AA0209 AA0210

8X305

Abstract: 8X360 GND1, GND2 Ground 2 TSCL Address 3-State Control Pin TSCL Action 1 Enable A0-A15 0 Disable (3-State) 3-18 A0-A15 16 3-State Address Output Plris: AO is LSB. 19, 21 -23 RS3 - RSO Register Select Input , Low-level input current Vcc = Max, V|L - 0.5V -500 M Vol Low-level output voltage iv TC A0-A15 Vcc = Min Iol - 16mA Iol - 8mA Iol *= 8mA 0.55 0.55 0.55 V V V Voh High-level output voltage 17 TC A0-A15 Vcc , IV TC A0-A15 Vcc-Max Only 1 output at a time -20 -20 -20 mA mA mA ice Vcc-Max 70 100 mA 'BB
-
OCR Scan
8X360 8X305 146g specifications of ic 1408 1S08 N8X360I 6X360 6X305 TC2017OS

idq10

Abstract: EDH816H64C methods of MIL-STD-883C, Class B. Pin Configuration and Block Diagram BS -A0-A15 â  IT. "w Ã2 W , Noise Immunity Single +5V (±10%) Supply Operation Pin Names A0-A15 E0-E3 W DQ0-DQ15 VCC VSS , Configuration Tâ'" E0 â  A0-A15 â  "Ã'T. "W â  Â£2 E3 -DQ0 "Iâ'"DQ1 "Iâ'"DQ2 m -DQ4 -DQ5 , "Iâ'"DQ15 128Kx8 Configuration DQ0 DQ1 A0-A15_ W VCC - 03b 02b Olb C O0b C - A1b 0 - A0b C -CS1b C VCC C 139 DECODER 3 GND 3 03a 3 02a 3 Ola 3 O0a 3 A1a 3 A0a 3 CS1a E A16 VSS J -E0 - A0-A15 â
-
OCR Scan
EDH816H64C idq10 5S70 EDH816H64C35/45/55/70 1024K- EDH816H64C35/45/5S/70 C-D09
Abstract: Pulse Width High Fall Time, Rise Time A0-A15 Hold Time A0-A15 Setup Time BA0-BA7 Hold Time BA0-BA7 Setup , Time Clock Pulse Width Low Clock Pulse Width High Fall Time, Rise Time A0-A15 Hold Time A0-A15 Setup , THE WESTERN DESIGN CENTER, INC. W65C816S PHI2(IN| R/WB, MLB, VPB, A0-A15, VDA, VPA Read -
OCR Scan

40H245

Abstract: msm5165 722 A0A15 I 39 DIEN I ."H" 38 BUSY O . 40 ADF I , DB0DB7, CS, RD, WR, A0A15, "L" VIL 0.7 V DIEN, ADF, RD0RD7 "H" VIH 4.5 , , RD, WR, A0A15, "L" IIL -1 mA DIEN, ADF, RD0RD7, RES, DIV "H" IIH 25 , WR RD IO/M A1A7 CS AD0AD7 ALE HLDA OC DB0DB7 A0A15 A0A15 MSM6255 Z80 WR RD WR RD IORQ A1A7 CS D0D7 DB0DB7 A0A15 A0A15
OKI Electric Industry
Original
Z80CPU 40H245 msm5165 5299C hp 4552 MA10 MA11 J2B0039-27-Y4 MA0MA15 80QFPQFP80-P-1420-0 80-KMSM6255 80-BKMSM6255

50p06

Abstract: ad015 fFPH ( = x) tFPH 37.0 ns 2 A0-A15 ALE tAL 0.5x - 14 4 ns 3 ALE A0-A15 tLA 0.5x - 16 2 ns 4 ALE High tLL x - 20 17 ns 5 ALE RD , tCLW x - 10 27 ns 8 A0-A15 RD / WR tACL x - 23 14 ns 9 A0-A23 RD , WR A0-A23 tCAW x - 13 24 ns 12 A0-A15 D0-D15 tADL 3.0x - 38 73 ns , A0-A23 WAIT 22 A0-A15 WAIT 1+n WAIT 1+n WAIT 1+n WAIT tAWH 3.5x - 60 69
Toshiba
Original
TMP91CY22IFG LQFP100 50p06 ad015 TLCS-900/L1 TMP91CY22I 900/L1 TLCS-90/900 030519TBP

DSP56166

Abstract: PB10 AND DATA BUS (32 PINS) A0-A15 (Address Bus) - three state, active high outputs. A0-A15 change , external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware , memory is referenced. PS/DS timing is the same as the A0-A15 address lines. PS/DS is high for program , Vdd Vss HA0 HA1 HA2 PB11 PB12 PB13 PB14 EXTAL CLKO SXFC VddS GNDS A0-A15 D0-D15 , :$FF7F). PEREN timing is the same as the A0A15 address lines; it is asserted and deasserted during t0
Freescale Semiconductor
Original

40H245

Abstract: hp 4552 39 38 40 RA0RA3 RD0RD7 FRMB VDD, VSS DIV UD0UD3 LD0LD3 CLP LIP FRP CEf CHf TEST1, TEST2 A0A15 DIEN , L H MA0MA15, RA0RA3 A0A15 (DIEN H L ) ) MA0MA15 .WR (DIEN 4/32 MSM6255l n , -1 V V V V mA mA mA mA DB0DB7, CS, RD, WR, A0A15, DIEN, ADF, RD0RD7, RES, DIV TEST1, TEST2 DB0DB7, CS, RD, WR, A0A15, DIEN, ADF, RD0RD7 RES, DIV, XT VOH2.8V -500 VOL0.4V 2.4 l (VDD5V±5, Ta , MA0MA15 DIEN L A0A15MA0MA15 l DIV H XT (XTOpen) DIV L X' tal l ADF L MA0MA15, RA0RA3 ADF H Normal l
OKI Electric Industry
Original
ma0-MA15 VP80-1 J2B003927Y4 80QFPQFP80P14200 80KMSM6255 80BKMSM6255 80QFP HCT244

M28F102

Abstract: PLCC44 Address Inputs DQ0 - DQ15 A0-A15 Output Enable W Supply Voltage VSS E Program , Cycles Operation A0-A15 2nd Cycle DQ0-DQ15 (2) X 2 Write X xx90h 0020h 0001h 0050h X xx20h Read X Data Output A0-A15 Data Input xx00h Electronic Signature 0000h Write Write Read Write 1 A0-A15 Read Read DQ0-DQ15 (2 , Write A0-A15 xxA0h Write X xx40h Program Program Verify 2 Write X xxC0h
STMicroelectronics
Original
M28F102 PLCC44 TSOP40 AI00627B

M28F102

Abstract: PLCC44 16 A0-A15 W DQ0-DQ15 M28F102 E Table 1. Signal Names A0 - A15 DQ0 - DQ15 Data , 0050h Table 5. Commands (1) Command 1st Cycle Cycles 2nd Cycle Operation A0-A15 , X Data Output A0-A15 Data Input xx00h Electronic Signature Read Write Write DQ0-DQ15 (2) Write 1 A0-A15 Read Read Operation Setup Erase/ 2 Write X xx20h Erase Erase Verify Setup Program/ 2 2 Write A0-A15 xxA0h Write X xx40h
STMicroelectronics
Original

DSP56156

Abstract: MC68000 goes high in t0. R/W is three-stated during hardware reset. Address and Data Bus A0-A15 (Address Bus) - three-state, active high outputs. A0-A15 change in t0 and specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset. D0-D15 (Data Bus) - three-state , A0-A15 address lines. PS/DS is high for program memory access and is low for data memory access. If the
Motorola
Original
MC68000 SC10-11

M28F102

Abstract: PLCC44 (K) TSOP40 (N) 10 x 14mm Figure 1. Logic Diagram VCC VPP 16 16 A0-A15 W , A0-A15 Data Input xx00h Electronic Signature DQ0-DQ15 (2) Write DQ0-DQ15 A0-A15 Write A0-A15 Operation Read Operation Setup Erase/ 2 Write X xx20h Erase Erase Verify Setup Program/ 2 2 Write A0-A15 xxA0h Write X xx40h Program , Figure 5. Read Mode AC Waveforms tAVAV A0-A15 tAVQV tAXQX E tELQV tEHQZ tELQX G tGLQV
STMicroelectronics
Original

TMP93CW46AF

Abstract: TMP93CW46A fFPH ( = x) tFPH 37.0 ns 2 A0-A15 ALE tAL 0.5x - 14 4 ns 3 ALE A0-A15 tLA 0.5x - 16 2 ns 4 ALE High tLL x - 20 17 ns 5 ALE RD , tCLW x - 10 27 ns 8 A0-A15 RD / WR tACL x - 23 14 ns 9 A0-A23 RD , WR A0-A23 tCAW x - 13 24 ns 12 A0-A15 D0-D15 tADL 3.0x - 38 73 ns , A0-A23 WAIT 22 A0-A15 WAIT 1+n WAIT 1+n WAIT 1+n WAIT tAWH 3.5x - 60 69
Toshiba
Original
TMP93CW46A TMP93CW46AF TLCS-90 TMP93PW46A 31-RAS 900/L 030519TBP1 93CW46A-1

TMP93CW46A

Abstract: TMP93PW46A A0-A15 O E / Vpp E DO-D7 A0-A15 O E /V p p E D8-D15 M2t 64K x 8 M1 64K x 8 VC C VCC VSS 59 , Address Decoder 16 A0-A15 16 A16 10 CE 41 HCT139 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 1G 2Y2 2Y3 2G GND VC C 1A 2A 1B 2B O E /V p p DO- D7 E Ml 64K x 8 A0-A15 O E /V p p D8-D15 E M2t 64K x 8 Vcc VS S vcc v Ss 16 A0-A15 16 A0-A15 D0-D7 M3 64K x 8 O E /V p p E O E /V p p , 45 16 A0-A15 A0-A15 58 16 Addreaa Decoder A16 A17 10 12 CE 41 HCT139 1Y0 1A
Toshiba
Original
TMP93PW46AF 000000H 000080H 001080H 008000H 028000H

TMP93CW40

Abstract: TMP93PW40 spaces. IP Phone DSP56F803 Modems GS71116 A0-A15 Security A0-A15 D0-D15 Magnetic , DSP56F803 A0-A15 A0-A15 D0-D15 DQ1-DQ16 RD OE WR WE UB PS CE LB DS DSP56F80X CUSTOMER SUPPORT: GS71116 Technical Support: A0-A15 DQ1-DQ16 OE WE UB CE , authorized distributor Disclaimer: DSP56F803 A0-A15 PS D0-D15 GS71116 A0-A15 A16 DQ1-DQ16 RD
Toshiba
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TMP93PW40 TMP93PW40DF TMP93CW40 TLCS-900/L FFFF00H TMP93CW40/TMP93PW40

TMP93CM40

Abstract: TLCS-90 GND1, GND2 Ground 2 TSCL Address 3-State Control Pin TSCL Action 1 Enable A0-A15 0 Disable (3-State) 3-18 A0-A15 16 3-State Address Output Plris: AO is LSB. 19, 21 -23 RS3 - RSO Register Select Input , Low-level input current Vcc = Max, V|L - 0.5V -500 M Vol Low-level output voltage iv TC A0-A15 Vcc = Min Iol - 16mA Iol - 8mA Iol *= 8mA 0.55 0.55 0.55 V V V Voh High-level output voltage 17 TC A0-A15 Vcc , IV TC A0-A15 Vcc-Max Only 1 output at a time -20 -20 -20 mA mA mA ice Vcc-Max 70 100 mA 'BB
Toshiba
Original
TMP93CM40 TMP93CM40F 93CM40-1 P-QFP100-1414-0 93CM40-2 93CM40-18

TLCS-90

Abstract: TMP93CU44 X:$FF7F). PEREN timing is the same as the A0-A15 address lines; it is asserted and deasserted , qualifies the A0-A15 and PS/DS pins. WR can be connected directly to the WE pin of a static RAM. WR is , DSP. When RD is asserted, it qualifies the A0-A15 and PS/DS pins. RD can be connected directly to , Total 112 ADDRESS AND DATA BUS (32 PINS A0-A15 (Address Bus) - three state, active high outputs. A0A15 change in t0 and specify the address for external program and data memory accesses. If there is
Toshiba
Original
TMP93CU44 TMP93CU44DF TMP93PW44A 93CU44-1 P-QFP80-1420-0 93CU44-2

TMP93CS40F

Abstract: TMP93CS41F 722 A0A15 I 39 DIEN I ."H" 38 BUSY O . 40 ADF I , DB0DB7, CS, RD, WR, A0A15, "L" VIL 0.7 V DIEN, ADF, RD0RD7 "H" VIH 4.5 , , RD, WR, A0A15, "L" IIL -1 mA DIEN, ADF, RD0RD7, RES, DIV "H" IIH 25 , WR RD IO/M A1A7 CS AD0AD7 ALE HLDA OC DB0DB7 A0A15 A0A15 MSM6255 Z80 WR RD WR RD IORQ A1A7 CS D0D7 DB0DB7 A0A15 A0A15
Toshiba
Original
TMP93CS40 TMP93CS41 TMP93CS40F TMP93CS41F TMP93CS40/41 TMP93CS40/CS41 TMP93CS40F/TMP93CS41F TMP93CS40DF/TMP93CS41DF TMP93CS40/S41
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